Semiconductor device with buried gate structure

Abstract

This invention relates to a semiconductor device including a buried gate structure. The semiconductor device includes: a substrate; a first fluorine-containing layer on the substrate; a trench formed in the first fluorine-containing layer and extending into the substrate; a gate dielectric layer formed on the trench; a gate electrode formed on the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed on the gate electrode; and a fluorine passivation layer between the gate dielectric layer and the gate electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a buried gate structure. Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0103235, filed on August 5, 2021, the entire contents of which are incorporated herein by reference. Prior Technology

[0003] Metal gate electrodes are used to achieve high transistor performance. Especially in buried gate transistors, high transistor performance requires threshold voltage control. Furthermore, gate-induced drain leakage (GIDL) characteristics have a significant impact on the performance of buried gate transistors. Summary of the Invention

[0004] Various embodiments of the present invention provide a semiconductor device with improved reliability, including a buried gate structure.

[0005] A semiconductor device according to an embodiment of the present invention includes: a substrate; a first fluorine-containing layer on the substrate; a trench formed in the first fluorine-containing layer and extending into the substrate; a gate dielectric layer formed on the trench; a gate electrode formed on the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed on the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.

[0006] A semiconductor device according to an embodiment of the present invention includes: a substrate including a first doped region and a second doped region; a first SiOF layer on the substrate; a trench formed in the first SiOF layer and extending into the substrate between the first doped region and the second doped region; a gate dielectric layer formed on the trench; a gate electrode filling a portion of the trench on the gate dielectric layer and comprising fluorine-free titanium nitride; a second SiOF layer formed on the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.

[0007] The present invention can improve retention and row hammer characteristics by forming a fluorine-rich coating on the gate electrode. Simple Explanation of the Diagram

[0008] [Figure 1] is a schematic plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0009] [Figure 2A] is a cross-sectional view taken along line AA′ in Figure 1.

[0010] [Figure 2B] is a cross-sectional view taken along line BB′ in Figure 1.

[0011] [Figure 2C] is a cross-sectional view taken along line CC′ in Figure 1.

[0012] [Figure 2D] is an enlarged view of the buried gate structure 100G.

[0013] Figures 3A to 3C are enlarged views showing a buried gate structure according to an embodiment of the present invention.

[0014] Figures 4A to 4D are enlarged views showing a buried gate structure according to an embodiment of the present invention.

[0015] Figures 5A to 5D are enlarged views showing a buried gate structure according to an embodiment of the present invention. Implementation

[0016] The various embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which serve as schematic representations of the invention. Therefore, the structure of the drawings can be modified by manufacturing techniques and / or tolerances. The various embodiments of the invention are not limited to the specific structures shown in the drawings, but include any variations in the structure that may result from the manufacturing process. Furthermore, any regions and their shapes shown in the drawings are schematic and intended to illustrate specific examples of the regional structures of various elements, and are not intended to limit the scope of the invention.

[0017] In the following description, the buried gate structure according to an embodiment of the present invention can be disposed in a trench. The buried gate structure may include a stack of a gate dielectric layer, a gate electrode, and a capping layer. The gate dielectric layer may cover the surface of the trench. The gate electrode may partially fill the trench above the gate dielectric layer. The capping layer may fill the remaining portion of the trench above the gate electrode. Therefore, the gate electrode may be referred to as a "buried gate electrode".

[0018] Gate electrodes can include single-gate or dual-gate electrodes. A single-gate electrode can refer to a gate formed solely of polycrystalline silicon or a metal-based material. A single-gate electrode can include a polycrystalline silicon single-gate electrode or a metal single-gate electrode. A dual-gate electrode can refer to a two-layer stack comprising different gate electrodes. A dual-gate electrode can include a homometallic dual-gate electrode or a heterometallic dual-gate electrode. A homometallic dual-gate electrode includes a stack of two layers made of the same metal, a heterometallic dual-gate electrode includes a stack of two layers made of different metals, or a heterometallic dual-gate electrode can be formed by a stack of one layer made of metal and one layer made of polycrystalline silicon.

[0019] The gate electrode may include a barrier layer and a low-resistivity material. The barrier layer can be used to block impurities diffusing from the low-resistivity material or to prevent interdiffusion and reaction between two different materials. The low-resistivity material can be used to reduce the sheet resistance of the gate electrode.

[0020] Gate electrodes may include materials with engineered work functions. Engineering the work function can refer to materials or methods that can adjust the work function to have a reduced work function (i.e., low work function) or an increased work function (i.e., high work function).

[0021] According to embodiments of the present invention, the gate electrode may include a lower gate and an upper gate. The lower gate may fill the lower portion of the trench, while the upper gate may fill the middle and upper portions of the trench. As described above, the gate electrode may be referred to as a dual-gate, wherein the upper gate is disposed above the lower gate. The lower gate may overlap with the channel. The upper gate may laterally overlap with the first doped region and the second doped region (i.e., the source region and the drain region).

[0022] Figure 1 is a schematic plan view of a semiconductor device illustrating an embodiment of the present invention. Figure 2A is a cross-sectional view taken along line AA′ of Figure 1. Figure 2B is a cross-sectional view taken along line BB′ of Figure 1. Figure 2C is a cross-sectional view taken along line CC′ of Figure 1. Figure 2D is an enlarged view of the buried gate structure 100G.

[0023] Referring to Figures 1A to 2D, the semiconductor device 100 may include a substrate 101, a buried gate structure 100G, a bit line structure 140, and a capacitor 160. The semiconductor device 100 may be part of a memory cell. For example, the semiconductor device 100 may be part of a DRAM memory cell.

[0024] Substrate 101 may be a material suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. Substrate 101 may be formed of a silicon-containing material. Substrate 101 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 101 may include another semiconductor material, such as germanium. Substrate 101 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate such as gallium arsenide (GaAs). Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0025] An isolation layer 102 and an active region 104 can be formed in the substrate 101. The active region 104 can be defined by the isolation layer 102. The isolation layer 102 can be a shallow trench isolation (STI) region formed by trench etching. The isolation layer 102 can be formed by filling shallow trenches (e.g., isolation trench 103) with a dielectric material. The isolation layer 102 can be made of silicon oxide, silicon nitride, or a combination thereof, or include silicon oxide, silicon nitride, or a combination thereof.

[0026] A trench 105 may be formed in the substrate 101. Referring to FIG1, the trench 105 may have a line shape extending in a first direction D1. The trench 105 may have a line shape intersecting the active region 104 and the isolation layer 102. The trench 105 may have a shallower depth than the isolation trench 103. In another embodiment, the trench 105 may be the space in which the buried gate structure 100G is to be formed and may also be referred to as a "gate trench".

[0027] A first doped region 107 and a second doped region 108 can be formed in the active region 104. The first doped region 107 and the second doped region 108 are regions doped with a conductive dopant. For example, the conductive dopant may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first doped region 107 and the second doped region 108 may be doped with the same conductive dopant. The first doped region 107 and the second doped region 108 may be located in the active regions 104 on both sides of the trench 105. The bottom surfaces of the first doped region 107 and the second doped region 108 may be located at a predetermined depth from the top surface of the trench 105. The first doped region 107 and the second doped region 108 may contact the sidewalls of the trench 105. The bottom surfaces of the first doped region 107 and the second doped region 108 may be located at a horizontal plane higher than the bottom surface of the trench 105. The first doped region 107 may be referred to as the "first source / drain region," and the second doped region 108 may be referred to as the "second source / drain region." A channel 106 can be defined between a first doped region 107 and a second doped region 108 by a buried gate structure 100G. The channel 106 can be defined along the contour of the trench 105.

[0028] The functional region 104 may include a fin region 104F. The fin region 104F may be formed below the trench 105. The fin region 104F is formed as an insulating layer 102 disposed below the trench 105 and partially recessed. The sidewalls of the fin region 104F are exposed by the recessed insulating layer 102F. The fin region 104F is a region in which a channel CH can be formed. The fin region 104F is also referred to as a "saddle fin". The fin region 104F can increase the channel width and improve electrical characteristics. In another embodiment, the fin region 104F may be omitted.

[0029] In another embodiment, the active region 104 and the fin region 104F may comprise an oxide semiconductor material such as IGZO (InGaZnO). In this case, the first doped region 107 and the second doped region 108 may also comprise an oxide semiconductor material such as IGZO. The active region 104 and the fin region 104F may be formed of IGZO, and the first doped region 107 and the second doped region 108 may be formed of an oxide semiconductor material having a lower resistivity than IGZO.

[0030] According to Figure 1, the buried gate structure 100G can extend in the first direction D1. The buried gate structure 100G may include a gate dielectric layer 110 covering the bottom surface and sidewalls of the trench 105, a gate electrode 120 partially filling the trench 105 above the gate dielectric layer 110, and a cover layer 130 disposed above the gate electrode 120.

[0031] The gate dielectric layer 110 may be made of silicon oxide, silicon nitride, silicon oxynitride, high-k materials, or combinations thereof, or may include silicon oxide, silicon nitride, silicon oxynitride, high-k materials, or combinations thereof. The high-k material may be a material having a higher dielectric constant than silicon oxide, or may include materials having a higher dielectric constant than silicon oxide. For example, the high-k material may be any suitable material having a dielectric constant greater than, for example, 3.9, or may include any suitable material having a dielectric constant greater than, for example, 3.9. In one embodiment, the high-k material may be a material having a dielectric constant greater than, for example, 10, or may include materials having a dielectric constant greater than, for example, 10. In another embodiment, the high-k material may be a material having a dielectric constant in the range of 10 to 30, or may include materials having a dielectric constant in the range of 10 to 30. The high-k material may be at least one metallic element, or may include at least one metallic element. The high-k material may be a hafnium-containing material, or may include hafnium-containing materials. The hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, or a combination thereof, or may include hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, or a combination thereof. In another embodiment, the high-k material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon nitride, aluminum oxide, or a combination thereof, or may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon nitride, aluminum oxide, or a combination thereof. Other known high-k materials may also be selectively used as high-k materials. The gate dielectric layer 110 may be a metal oxide, or may include a metal oxide.

[0032] Gate electrode 120 can be positioned at a level lower than the upper surface of the active region 104 (i.e., the first doped region 107 and the second doped region 108). Gate electrode 120 may comprise a fluorine-free material. A fluorine-free material can refer to a material that does not contain fluorine. Gate electrode 120 may comprise a fluorine-free metal-based material. Gate electrode 120 may comprise a metal, a metal nitride, or a combination thereof. For example, gate electrode 120 may comprise polycrystalline silicon, tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), ruthenium (Ru), or a combination thereof. Tungsten (W) and tungsten nitride (WN) can be used as gate electrode 120 and formed using a fluorine-free precursor. Gate electrode 120 may be formed solely from fluorine-free titanium nitride. In another embodiment, gate electrode 120 may have a high work function. Here, a high work function refers to a work function higher than the mid-gap work function of silicon. Low work function refers to a work function lower than the intermediate bandgap work function of silicon. In other words, high work function can have a work function higher than 4.5 eV, while low work function can have a work function lower than 4.5 eV. The gate electrode 120 may include p-type polycrystalline silicon or nitrogen-rich TiN.

[0033] In another embodiment, the gate electrode 120 may have an increased high work function. The gate electrode 120 may be made of or comprise metal silicon nitride. The metal silicon nitride may be a silicon-doped metal nitride. The gate electrode 120 may be made of or comprise metal silicon nitride with an adjusted percentage of silicon atoms. For example, the gate electrode 120 may be made of or comprise tantalum silicon nitride (TaSiN) or titanium silicon nitride (TiSiN). Titanium nitride may have a high work function and contain silicon to further increase the work function of the titanium nitride. Titanium silicon nitride may have an adjusted percentage of silicon atoms to have an increased high work function. In another embodiment, the gate electrode 120 may comprise, for example, titanium aluminum nitride (TiAlN).

[0034] The capping layer 130 can be used to protect the gate electrode 120. The capping layer 130 can fill the upper part of the trench 105 and can be formed on the gate electrode 120. The top surface of the capping layer 130 can be at the same level as the top surfaces of the first doped region 107 and the second doped region 108.

[0035] Hard masking layers 109 can be formed on both sides of the cover layer 130. The hard masking layers 109 can be made of a dielectric material, or include a dielectric material. The hard masking layers 109 can be formed on the substrate 101 and cover the active region 104 and the isolation layer 102. The cover layer 130 of the buried gate structure 100G can penetrate the hard masking layers 109. Trench 105 can extend through the hard masking layers 109 into the substrate 101.

[0036] The bitline structure 140 can be connected to the first doped region 107 by passing through the hard masking layer 109. Referring to the plan view of FIG1, the bitline structure 140 can extend in a second direction D2. The bitline structure 140 may include a bitline contact plug 141, a bitline 142, a bitline hard masking layer 143, and a spacer 144. The bitline contact plug 141 can directly contact the first doped region 107, and the bitline 142 can be formed on the bitline contact plug 141. The bitline hard masking layer 143 can be formed on the bitline 142, and the spacer 144 can be formed on two sidewalls of the bitline contact plug 141, the bitline 142, and the bitline hard masking layer 143. The bitline contact plug 141 may include, for example, polycrystalline silicon. The bitline 142 may include, for example, titanium nitride, tungsten, or combinations thereof. The bitline hard masking layer 143 may include, for example, silicon nitride. Spacer 144 may include, for example, nitrides, oxides, low-k materials, or combinations thereof. Low-k materials used as spacer 144 may include SiBN, SiCO, SiCN, SiBCN, or combinations thereof. In one embodiment, spacer 144 may include a stack of insulating materials having air gaps embedded in an insulating material.

[0037] Storage node contact plugs 150 can be connected to second doped regions 108 through hard masking layers 109. Capacitors 160 can be formed on storage node contact plugs 150. Plug isolation layers 151 can be formed between consecutively arranged storage node contact plugs 150. Plug isolation layers 151 can also be placed between consecutively arranged bit line structures 140. Storage node contact plugs 150 can include, for example, polysilicon, metal silicides, metal nitrides, metals, or combinations thereof. In one embodiment, storage node contact plugs 150 can be a stack of sequentially stacked polysilicon, cobalt silicide, titanium nitride, and tungsten. Plug isolation layers 151 can include, for example, silicon nitride, low-k materials, or combinations thereof. Low-k materials as plug isolation layers 151 can include SiBN, SiCN, SiBCN, or combinations thereof.

[0038] The capping layer 130 and the gate dielectric layer 110 can be in direct contact. The capping layer 130 and the gate electrode 120 can also be in direct contact. The capping layer 130 may include a fluorinated material. The capping layer 130 may include a fluorine-rich layer. The hard masking layer 109 may include a fluorinated material. The hard masking layer 109 may include a fluorine-rich layer. The capping layer 130 and the hard masking layer 109 may be made of the same material. The capping layer 130 and the hard masking layer 109 may include fluorinated silicon oxide. The capping layer 130 and the hard masking layer 109 may include fluorine-rich silicon oxide. For example, the capping layer 130 and the hard masking layer 109 may include SiOF, fluorinated silicate glass (FSG), or a combination thereof. The fluorinated capping layer 130 and the fluorinated hard masking layer 109 may not include silicon nitride.

[0039] Referring to Figure 2D, the first fluorine FD1 can diffuse from the capping layer 130. For example, the first fluorine FD1 can diffuse into the interface F1 (hereinafter referred to as the "first interface") between the gate electrode 120 and the gate dielectric layer 110. The first fluorine FD1 can diffuse into the film of the gate dielectric layer 110. The first fluorine FD1 can passivate the traps at the first interface F1, thereby improving retention and hammering characteristics. The first fluorine FD1 can also diffuse into the interface F2 (hereinafter referred to as the "second interface") between the capping layer 130 and the gate dielectric layer 110. The second fluorine FD2 can diffuse into the film of the gate dielectric layer 110.

[0040] The diffusion of the first fluorine FD1 and the second fluorine FD2 can be performed through subsequent heat treatment. Here, after forming the buried gate structure 100G, the subsequent heat treatment can be performed simultaneously with the formation of the bit line structure 140, the storage node contact plug 150, and the capacitor 160. The first fluorine FD1 and the second fluorine FD2 can diffuse into the gate dielectric layer 110 or diffuse into the interface between the gate dielectric layer 110 and the gate electrode 120.

[0041] The first interface F1 and the second interface F2 can be perpendicular and continuous to each other. The first interface F1 can be set at a lower level than the second interface F2. The first interface F1 can be set on the two sidewalls of the gate electrode 120.

[0042] As described above, the first interface F1 and the second interface F2 may include a first fluorine FD1 diffused from the capping layer 130, and the traps of the first interface F1 and the second interface F2 may be passivated by the diffused first fluorine FD1. In another embodiment, the first interface F1 and the second interface F2 may each be referred to as fluorine passivation interfaces.

[0043] In another embodiment, the first interface F1 and the second interface F2 can each be referred to as a fluorinated passivation layer or a fluorinated passivation layer. This is because a portion of the gate dielectric layer 110 may include diffused first fluorine FD1 and second fluorine FD2. In other words, the gate dielectric layer 110 may include a fluorinated gate dielectric layer 110F and a fluorine-free gate dielectric layer 110U. The fluorinated gate dielectric layer 110F may be a layer including the first interface F1 and the second interface F2, while the fluorine-free gate dielectric layer 110U may be a layer excluding the first interface F1 and the second interface F2. When the gate dielectric layer 110 is silicon oxide, the fluorinated gate dielectric layer 110F may be fluorinated silicon oxide, while the fluorine-free gate dielectric layer 110U may be fluorine-free silicon oxide. Fluorine-free silicon oxide may not contain fluorine.

[0044] The second fluorine FD2 can diffuse from the hard masking layer 109 to the second interface F2, and the traps at the second interface F2 can be passivated by the diffused second fluorine FD2. The second fluorine FD2 can diffuse to the first interface F1. Therefore, the first interface F1 and the second interface F2 can be passivated by the first fluorine FD1 and the second fluorine FD2. The first interface F1 may include the first fluorine FD1 diffused from the capping layer 130 and the second fluorine FD2 diffused from the hard masking layer 109.

[0045] As described above, since both the cover layer 130 and the hard shield layer 109 contain fluorine, the retention and impact resistance characteristics can be further improved.

[0046] When the fluorine concentration is high, the capping layer 130 has a dielectric constant that decreases with increasing number of voids. When the capping layer 130 is SiOF and the fluorine concentration in the capping layer 130 is 0 at% (i.e., fluorine-free SiO2), it can have a dielectric constant of about 3.9. When the fluorine concentration in the capping layer 130 is 12 at% (SiOF), the dielectric constant can decrease to about 3.0. The fluorine concentration in the capping layer 130 can range from 1 at% to 25 at%.

[0047] Accordingly, since the fluorine-rich capping layer 130 has a low dielectric constant, the parasitic capacitance between the gate electrode 120 and the bit line contact plug 141 can be reduced. The fluorine-rich capping layer 130 can reduce the parasitic capacitance between the gate electrode 120 and the bit line 142.

[0048] Figures 3A to 3C are enlarged views illustrating a buried gate structure according to another embodiment of the present invention. The buried gate structure 100G of Figures 3A to 3C can be similar to the buried gate structure 100G of Figures 1 to 2D. Detailed descriptions of repeated parts will be omitted below.

[0049] In Figures 3A to 3C, the components other than the gate electrodes 120A, 120B and 120C can be the same as those in the buried gate structure 100G of Figure 2D.

[0050] Referring to Figure 3A, the buried gate structure 100G may include a gate dielectric layer 110, a gate electrode 120A, and a capping layer 130. The capping layer 130 and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120A may include a barrier layer 121, a low resistivity electrode 122, and a low work function electrode 123. For example, the barrier layer 121 may be titanium nitride, the low resistivity electrode 122 may be tungsten, and the low work function electrode 123 may be made, for example, of doped polycrystalline silicon. Doped polycrystalline silicon may refer to polycrystalline silicon doped with n-type impurities.

[0051] Referring to Figure 3B, the buried gate structure 100G may include a gate dielectric layer 110, a gate electrode 120B, and a capping layer 130. The capping layer 130 and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120B may include a barrier layer 121, a low resistivity electrode 122, an interface barrier layer 124, and a low work function electrode 123. The barrier layer 121 and the interface barrier layer 124 may be made of, for example, titanium nitride, the low resistivity electrode 122 may be made of, for example, tungsten, and the low work function electrode 123 may be made of, for example, doped polycrystalline silicon. In another embodiment, the interface barrier layer 124 may be formed by plasma nitriding. For example, the barrier layer 121 and the low resistivity electrode 122 may be nitrides formed by plasma nitriding. In another embodiment, the interface barrier layer 124 may be the oxide portion of the barrier layer 121 and the low resistivity electrode 122.

[0052] Referring to Figure 3C, the buried gate structure 100G may include a gate dielectric layer 110, a gate electrode 120C, and a capping layer 130. The capping layer 130 and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120C may include a low-resistivity electrode 122 and a low work function electrode 123. The low-resistivity electrode 122 may be made of, for example, titanium nitride, and the low work function electrode 123 may be made of, for example, doped polycrystalline silicon. In another embodiment, the low-resistivity electrode 122 may be high-work-function titanium nitride, and the low-work-function electrode 123 may be low-work-function titanium nitride.

[0053] In Figures 3A to 3C, the barrier layer 121, the low resistivity electrode 122, the interface barrier layer 124, and the low work function electrode 123 can be fluorine-free layers. In another embodiment, the low resistivity electrode 122 can be a fluorine-containing layer. The low work function electrode 123 can laterally overlap with the first doped region 107 and the second doped region 108 of Figure 2A. The low work function electrode 123 can suppress gate-induced drain leakage (GIDL).

[0054] The capping layer 130 may include a fluorinated material. The capping layer 130 may include a fluorine-rich layer. The hard masking layer 109 may include a fluorinated material. The hard masking layer 109 may include a fluorine-rich layer. The capping layer 130 and the hard masking layer 109 may be made of the same material. The capping layer 130 and the hard masking layer 109 may include fluorinated silicon oxide. For example, the capping layer 130 and the hard masking layer 109 may include fluorinated silicon oxide (SiOF), fluorinated silicate glass (FSG), or a combination thereof.

[0055] The first fluorine FD1 can diffuse from the capping layer 130. For example, the first fluorine FD1 can diffuse into the first interface F1 between the gate electrodes 120A, 120B, and 120C and the gate dielectric layer 110. The first fluorine FD1 can diffuse into the film of the gate dielectric layer 110. The first fluorine FD1 can passivate the traps at the first interface F1, thereby improving retention and hammering characteristics. The first fluorine FD1 can also diffuse into the second interface F2 between the capping layer 130 and the gate dielectric layer 110. The second fluorine FD2 can diffuse into the film of the gate dielectric layer 110.

[0056] The first interface F1 and the second interface F2 can be perpendicular and continuous to each other. The first interface F1 can be set at a lower level than the second interface F2. The first interface F1 can be set on the two sidewalls of the gate electrode 120.

[0057] As described above, the first interface F1 and the second interface F2 may include a first fluorine FD1 diffused from the capping layer 130, and the traps of the first interface F1 and the second interface F2 may be passivated by the diffused first fluorine FD1.

[0058] The second fluorine FD2 can diffuse from the hard masking layer 109 to the second interface F2, and the traps at the second interface F2 can be passivated by the diffused second fluorine FD2. The second fluorine FD2 can diffuse to the first interface F1. Therefore, the first interface F1 and the second interface F2 can be passivated by the first fluorine FD1 and the second fluorine FD2. The first interface F1 may include the first fluorine FD1 diffused from the capping layer 130 and the second fluorine FD2 diffused from the hard masking layer 109.

[0059] Figures 4A to 4D are enlarged views illustrating buried gate structures according to other embodiments of the present invention. The buried gate structure 200G of Figures 4A to 4D can be similar to the buried gate structure 100G of Figures 1 to 3C. Detailed descriptions of repeated components will be omitted below.

[0060] Referring to Figure 4A, the buried gate structure 200G may include a gate dielectric layer 110, a gate electrode 120, and a capping layer 130A. A hard shielding layer 109 may be formed on the two sidewalls of the capping layer 130A, and the gate dielectric layer 110 may be formed below the hard shielding layer 109.

[0061] The capping layer 130A may include a stack of a fluorinated capping layer 131 and a fluorine-free capping layer 132. The fluorinated capping layer 131 may contact the gate dielectric layer 110 but may not contact the hard masking layer 109. The fluorine-free capping layer 132 may contact both the gate dielectric layer 110 and the hard masking layer 109. The fluorinated capping layer 131 may be thinner than the fluorine-free capping layer 132. The fluorinated capping layer 131 may include SiOF or FSG, while the fluorine-free capping layer 132 may include silicon oxide or silicon nitride.

[0062] The hard masking layer 109 may include a fluorine-containing material. The hard masking layer 109 may include SiOF or FSG.

[0063] Referring to Figure 4A, the first fluorine FD1 can diffuse from the fluorine-containing capping layer 131. For example, the first fluorine FD1 can diffuse into the first interface F1 between the gate electrode 120 and the gate dielectric layer 110. The first fluorine FD1 can diffuse into the film of the gate dielectric layer 110. The first fluorine FD1 can passivate the traps at the first interface F1. The first fluorine FD1 can also diffuse into the second interface F2 between the fluorine-containing capping layer 131 and the gate dielectric layer 110. The second fluorine FD2 can diffuse into the film of the gate dielectric layer 110. The second interface F2 may further include the interface between the fluorine-free capping layer 132 and the gate dielectric layer 110.

[0064] The first interface F1 and the second interface F2 can be perpendicular and continuous to each other. The first interface F1 can be set at a lower level than the second interface F2. The first interface F1 can be set on the two sidewalls of the gate electrode 120.

[0065] As described above, the first interface F1 and the second interface F2 may include a first fluorine FD1 diffused from the fluorine-containing capping layer 131, and the traps of the first interface F1 and the second interface F2 may be passivated by the diffused first fluorine FD1.

[0066] The second fluorine FD2 can diffuse from the hard masking layer 109 to the second interface F2, and the traps at the second interface F2 can be passivated by the diffused second fluorine FD2. The second fluorine FD2 can diffuse to the first interface F1. Therefore, the first interface F1 and the second interface F2 can be passivated by the first fluorine FD1 and the second fluorine FD2. The first interface F1 may include the first fluorine FD1 diffused from the fluorine-containing capping layer 131 and the second fluorine FD2 diffused from the hard masking layer 109.

[0067] In Figures 4B to 4D, the components, except for gate electrodes 120A, 120B, and 120C, can be the same as those in the buried gate structure 200G of Figure 4A. Detailed descriptions of the repeated components will be omitted below.

[0068] Referring to Figure 4B, the buried gate structure 200G may include a gate dielectric layer 110, a gate electrode 120A, and a capping layer 130A. The capping layer 130A and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120A may include a barrier layer 121, a low resistivity electrode 122, and a low work function electrode 123. For example, the barrier layer 121 may be titanium nitride, the low resistivity electrode 122 may be tungsten, and the low work function electrode 123 may be made, for example, of doped polycrystalline silicon. Doped polycrystalline silicon may refer to polycrystalline silicon doped with n-type impurities.

[0069] Referring to Figure 4C, the buried gate structure 200G may include a gate dielectric layer 110, a gate electrode 120B, and a capping layer 130A. The capping layer 130A and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120B may include a barrier layer 121, a low resistivity electrode 122, an interface barrier layer 124, and a low work function electrode 123. The barrier layer 121 and the interface barrier layer 124 may be made of, for example, titanium nitride, the low resistivity electrode 122 may be made of, for example, tungsten, and the low work function electrode 123 may be made of, for example, doped polycrystalline silicon. In another embodiment, the interface barrier layer 124 may be formed by plasma nitriding. For example, the barrier layer 121 and the low resistivity electrode 122 may be nitrides formed by plasma nitriding. In another embodiment, the interface barrier layer 124 may be the oxide portion of the barrier layer 121 and the low resistivity electrode 122.

[0070] Referring to Figure 4D, the buried gate structure 200G may include a gate dielectric layer 110, a gate electrode 120C, and a capping layer 130A. The capping layer 130A and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120C may include a low-resistivity electrode 122 and a low work function electrode 123. The low-resistivity electrode 122 may be made of, for example, titanium nitride, and the low work function electrode 123 may be made of, for example, doped polycrystalline silicon. In another embodiment, the low-resistivity electrode 122 may be high-work-function titanium nitride, and the low-work-function electrode 123 may be low-work-function titanium nitride.

[0071] In Figures 4B to 4D, the barrier layer 121, the low resistivity electrode 122, the interface barrier layer 124, and the low work function electrode 123 can be fluorine-free layers. In another embodiment, the low resistivity electrode 122 can be a fluorine-containing layer. The low work function electrode 123 can suppress gate-induced drain leakage (GIDL).

[0072] Figures 5A to 5D are enlarged views illustrating buried gate structures according to other embodiments of the present invention. The buried gate structure 300G of Figures 5A to 5D can be similar to the buried gate structures 100G and 200G of Figures 1 to 4D. Detailed descriptions of repeated components will be omitted below.

[0073] Referring to Figure 5A, the buried gate structure 300G may include a gate dielectric layer 110, a gate electrode 120, and a capping layer 130B. A hard shielding layer 109 may be formed on the two sidewalls of the capping layer 130B, and the gate dielectric layer 110 may be formed below the hard shielding layer 109.

[0074] The capping layer 130B may include a stack of a fluorinated capping layer 131' and a fluorine-free capping layer 132'. The fluorinated capping layer 131' may be conformally formed, and the fluorine-free capping layer 132' may be formed to be thicker than the fluorinated capping layer 131'. The fluorinated capping layer 131' may contact the gate electrode 120, the gate dielectric layer 110, and the hard masking layer 109. The fluorine-free capping layer 132' may not contact the gate dielectric layer 110 and the hard masking layer 109. The fluorinated capping layer 131' may include SiOF or FSG, while the fluorine-free capping layer 132' may include silicon oxide or silicon nitride.

[0075] The hard masking layer 109 may include a fluorine-containing material. The hard masking layer 109 may include SiOF or FSG.

[0076] Referring to Figure 5A, the first fluorine FD1 can diffuse from the fluorine-containing capping layer 131'. For example, the first fluorine FD1 can diffuse into the first interface F1 between the gate electrode 120 and the gate dielectric layer 110. The first fluorine FD1 can diffuse into the film of the gate dielectric layer 110. The first fluorine FD1 can passivate the traps at the first interface F1. The first fluorine FD1 can also diffuse into the second interface F2 between the fluorine-containing capping layer 131' and the gate dielectric layer 110. The second fluorine FD2 can diffuse into the film of the gate dielectric layer 110.

[0077] The first interface F1 and the second interface F2 can be perpendicular and continuous to each other. The first interface F1 can be set at a lower level than the second interface F2. The first interface F1 can be set on the two sidewalls of the gate electrode 120.

[0078] As described above, the first interface F1 and the second interface F2 may include a first fluorine FD1 diffused from the fluorine-containing capping layer 131′, and the traps of the first interface F1 and the second interface F2 may be passivated by the diffused first fluorine FD1.

[0079] The second fluorine FD2 can diffuse from the hard masking layer 109 to the second interface F2, and the traps at the second interface F2 can be passivated by the diffused second fluorine FD2. The second fluorine FD2 can diffuse to the first interface F1. Therefore, the first interface F1 and the second interface F2 can be passivated by the first fluorine FD1 and the second fluorine FD2. The first interface F1 may include the first fluorine FD1 diffused from the fluorine-containing capping layer 131' and the second fluorine FD2 diffused from the hard masking layer 109.

[0080] In Figures 5B to 5D, the components, except for the gate electrodes 120A, 120B, and 120C, can be the same as those in the buried gate structure 300G of Figure 5A. Detailed descriptions of the repeated components will be omitted below.

[0081] Referring to Figure 5B, the buried gate structure 300G may include a gate dielectric layer 110, a gate electrode 120A, and a capping layer 130B. The capping layer 130B and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120A may include a barrier layer 121, a low resistivity electrode 122, and a low work function electrode 123. The barrier layer 121 may be made of, for example, titanium nitride, the low resistivity electrode 122 may be made of, for example, tungsten, and the low work function electrode 123 may be made of, for example, doped polycrystalline silicon. Doped polycrystalline silicon may refer to polycrystalline silicon doped with n-type impurities.

[0082] Referring to Figure 5C, the buried gate structure 300G may include a gate dielectric layer 110, a gate electrode 120B, and a capping layer 130B. The capping layer 130B and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120B may include a barrier layer 121, a low resistivity electrode 122, an interface barrier layer 124, and a low work function electrode 123. The barrier layer 121 and the interface barrier layer 124 may be made of, for example, titanium nitride, the low resistivity electrode 122 may be made of, for example, tungsten, and the low work function electrode 123 may be made of, for example, doped polycrystalline silicon. In another embodiment, the interface barrier layer 124 may be formed by plasma nitriding. For example, the barrier layer 121 and the low resistivity electrode 122 may be nitrides formed by plasma nitriding. In another embodiment, the interface barrier layer 124 may be the oxide portion of the barrier layer 121 and the low resistivity electrode 122.

[0083] Referring to Figure 5D, the buried gate structure 300G may include a gate dielectric layer 110, a gate electrode 120C, and a capping layer 130B. The capping layer 130B and the gate dielectric layer 110 may contact the hard masking layer 109. The gate electrode 120C may include a low-resistivity electrode 122 and a low work function electrode 123. The low-resistivity electrode 122 may be made of, for example, titanium nitride, and the low work function electrode 123 may be made of, for example, doped polycrystalline silicon. In another embodiment, the low-resistivity electrode 122 may be high-work-function titanium nitride, and the low-work-function electrode 123 may be low-work-function titanium nitride.

[0084] In Figures 5B to 5D, the barrier layer 121, the low resistivity electrode 122, the interface barrier layer 124, and the low work function electrode 123 can be fluorine-free layers. In another embodiment, the low resistivity electrode 122 can be a fluorine-containing layer. The low work function electrode 123 can suppress gate-induced drain leakage (GIDL).

[0085] In Figures 3A, 4B, and 5B, the barrier layer 121, the low resistivity electrode 122, and the low work function electrode 123 may respectively include, for example, titanium nitride, tungsten, and doped polycrystalline silicon.

[0086] In Figures 3B, 4C, and 5C, the barrier layer 121, the low resistivity electrode 122, the interface barrier layer 124, and the low work function electrode 123 may respectively include, for example, a first titanium nitride, tungsten, a second titanium nitride, and doped polycrystalline silicon.

[0087] In Figures 3C, 4D, and 5D, the low resistivity electrode 122 and the low work function electrode 123 may respectively comprise, for example, titanium nitride and doped polycrystalline silicon. In another embodiment, the low resistivity electrode 122 may comprise high work function titanium nitride, while the low work function electrode 123 may comprise low work function titanium nitride. The high work function titanium nitride may be titanium-rich titanium nitride, while the low work function titanium nitride may be nitrogen-rich titanium nitride. In another embodiment, the low resistivity electrode 122 may comprise stoichiometric titanium nitride, and the low work function electrode 123 may comprise low work function titanium nitride. The stoichiometric ratio of titanium to nitrogen required for the synthesis of titanium nitride is 1:1.

[0088] The present invention is not limited to the above embodiments and drawings, and it will be apparent to those skilled in the art that various substitutions, modifications and changes can be made to it without departing from the spirit and scope of the present invention.

[0089] 100: Semiconductor devices 100G: Buried gate structure 101:Substrate 102: Isolation layer 102F: Isolation Layer 103: Isolation trench 104: Area of ​​Effect 104F: Fin-like region 105: Trench 106: Channel 107: First doped region 108: Second doped region 109: Hard mask layer 110: Gate dielectric layer 110F: Fluorine-containing gate dielectric layer 110U: Fluorine-free gate dielectric layer 120: Gate electrode 120A: Gate electrode 120B: Gate electrode 120C: Gate electrode 121: Barrier Layer 122: Low resistivity electrode 123: Low work function electrode 124: Interface barrier layer 130: Overlay 130A: Covering layer 130B: Covering layer 131: Fluorine-containing coating 131′: Fluorine-containing coating 132: Fluorine-free coating 132′: Fluorine-free coating 140: Bitline Structure 141: Bit line contact plug 142: Bitline 143: Bitline Hard Mask Layer 144: Spacer 150: Storage node contact plug 151: Insertion isolation layer 160: Capacitor 200G: Buried gate structure 300G: Buried gate structure AA′: line BB′:line CC′: Line D1: First Direction D2: Second Direction F1: Interface / First Interface F2: Interface / Second Interface FD1: First Fluorine FD2: Second Fluorine

Claims

1. A semiconductor device, comprising: substrate; A first fluorine-containing layer is placed on the substrate; A trench formed in the first fluorine-containing layer and extending into the substrate; A gate dielectric layer is formed on the trench; a gate electrode is formed on the gate dielectric layer and fills a portion of the trench. A second fluorine-containing layer is formed on the gate electrode to directly contact the gate electrode; And a fluorinated passivation layer, the fluorinated passivation layer being between the gate dielectric layer and the gate electrode, wherein the bottom surface of the first fluorinated layer covers the top surface of the gate dielectric layer and the top surface of the fluorinated passivation layer.

2. The semiconductor device as claimed in claim 1, wherein, The fluorine-containing passivation layer includes fluorine diffused from the first fluorine-containing layer and the second fluorine-containing layer.

3. The semiconductor device as claimed in claim 1, wherein, The gate dielectric layer comprises silicon oxide, and the fluorinated passivation layer comprises fluorinated silicon oxide.

4. The semiconductor device as claimed in claim 1, wherein, The fluorine-containing passivation layer is in direct contact with the sidewall of the gate electrode.

5. The semiconductor device as claimed in claim 1, wherein, The first fluorinated layer and the second fluorinated layer comprise fluorinated silica, fluorosilicate glass, or a combination thereof.

6. The semiconductor device of claim 1, further comprising a fluorine-free layer above the second fluorine-containing layer, wherein, The fluorine-free layer comprises a material having a higher dielectric constant than the second fluorine-containing layer.

7. The semiconductor device as claimed in claim 6, wherein, The fluorine-free layer comprises silicon nitride.

8. The semiconductor device as claimed in claim 1, further comprising: A first doped region and a second doped region are formed in the substrate on both sides of the trench; Bit line contact plug, the bit line contact plug being formed on the first doped region; bit line, the bit line being formed on the bit line contact plug; A storage node contact plug formed on the second doped region; and a capacitor formed on the storage node contact plug.

9. The semiconductor device as claimed in claim 1, wherein, The gate electrode includes a fluorine-free conductive layer, a fluorine-containing conductive layer, or a combination thereof.

10. The semiconductor device as claimed in claim 1, wherein, The gate electrode comprises polycrystalline silicon, metal, metal nitride, or a combination thereof.

11. The semiconductor device as claimed in claim 1, wherein, The gate electrode is formed solely of titanium nitride.

12. The semiconductor device as claimed in claim 1, wherein, The gate electrode comprises a stack of titanium nitride, tungsten, and doped polycrystalline silicon.

13. The semiconductor device as claimed in claim 1, wherein, The gate electrode comprises a stack of first titanium nitride, tungsten, second titanium nitride, and doped polycrystalline silicon.

14. The semiconductor device as claimed in claim 1, wherein, The gate electrode comprises a stack of titanium nitride and doped polycrystalline silicon.

15. A semiconductor device, comprising: A substrate, the substrate comprising a first doped region and a second doped region; A first fluorinated silicon oxide layer is formed on the substrate. A trench formed in the first fluorinated silicon oxide layer and extending into the substrate between the first doped region and the second doped region; A gate dielectric layer formed on the trench; a gate electrode filling a portion of the trench on the gate dielectric layer and comprising fluorine-free titanium nitride; a second fluorinated silicon oxide layer formed on the gate electrode to directly contact the gate electrode; and a fluorinated passivation layer between the gate dielectric layer and the gate electrode, wherein the top surface of the first fluorinated silicon oxide layer covers the top surface of the gate dielectric layer and the top surface of the fluorinated passivation layer.

16. The semiconductor device as claimed in claim 15, wherein, The fluorinated passivation layer includes fluorine diffused from the first fluorinated silicon oxide layer and the second fluorinated silicon oxide layer.

17. The semiconductor device as claimed in claim 15, wherein, The gate dielectric layer comprises silicon oxide, and the fluorinated passivation layer comprises fluorinated silicon oxide.

18. The semiconductor device as claimed in claim 15, wherein, The gate electrode further includes a low work function material on top of the fluorine-free titanium nitride, and the low work function material horizontally overlaps with the first doped region and the second doped region.

19. The semiconductor device as claimed in claim 18, wherein, The low work function material includes doped polycrystalline silicon.

20. The semiconductor device as claimed in claim 15, further comprising: Bit line contact plugs are formed on the first doped region; Bit lines are formed on the bit line contact plug; A storage node contact plug, the storage node contact plug being formed on the second doped region; And a capacitor formed on the storage node contact plug.

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