Semiconductor die employing repurposed seed layer for forming additional signal paths to back end-of-line (BEOL) structure, and related integrated circuit (IC) packages and fabrication methods

Abstract

A semiconductor die ("die") employs a seed layer to form an additional signal path to a back-end process (BEOL) structure, and related integrated circuit (IC) packaging and manufacturing methods. A seed layer disposed adjacent to the BEOL interconnect structure is repurposed to couple an under-bump metallization (UBM) interconnect without coupled interconnect bumps, forming a non-bumped interconnect bump, to a UBM interconnect with bumped interconnect bumps. To couple the non-bumped interconnect bump to the bumped interconnect bump, the seed layer is selectively removed during manufacturing to leave a repurposed portion that couples the UBM interconnect without interconnect bumps to the UBM interconnect with bumped interconnect bumps. By coupling the UBM interconnect to the non-bumped interconnect bump, an additional routing path can be provided between the bumped interconnect bump and the BEOL interconnect structure.

Description

Semiconductor dies employing additional signal paths formed from seed layers to back-end processes (BEOL) structures, and related integrated circuit (IC) packaging and manufacturing methods. This disclosure relates to integrated circuit (IC) packages comprising one or more semiconductor dies attached to a package substrate, and more particularly to interconnect bump designs in IC packages for electrically coupling the dies to the package substrate. Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are typically packaged in IC packages (also known as "semiconductor packages" or "chip packages"). IC packages can be included in handheld, battery-powered electronic devices, where reduced package size and lower power consumption are particularly important. A typical IC package includes a package substrate and one or more IC chips or other electronic modules mounted to that package substrate to provide connectivity to the IC chip. For example, the IC chip in an IC package can be a system-on-a-chip (SoC), an application processor, or a power management IC. The semiconductor die ("die") of the IC chip is electrically coupled to the package substrate via metal interconnects (such as in the form of solder bumps or copper pillars, also known as "interconnect bumps" or simply "bumps"). Metal traces or wires in the metallization layer of the package substrate are coupled to the interconnect bumps to route electrical signals to the outside of the IC package and to other coupled dies within the IC package. Some metal traces in the package substrate are dedicated to delivering power as part of the power distribution network (PDN) in the IC package. The spacing of interconnect bumps that couple the die to the package substrate affects the performance of the circuitry within the die. Larger interconnect bump spacing can lead to inefficient power delivery when close to the circuitry within the IC package die, increasing signal resistance and current resistance (IR) drop. Therefore, reducing interconnect bump spacing to provide power delivery as close as possible to the circuitry within the IC package die is desirable for improving circuit performance. However, reducing interconnect bump spacing can be challenging in IC package design. Interconnect bump spacing affects many parameters in the package substrate, including trace width and vertical interconnect (via) pad size. Reducing interconnect bump spacing in an IC package is sometimes impossible given packaging manufacturing constraints. Even when reduced interconnect bump spacing can be implemented in an IC package within manufacturing constraints, it can lead to lower yields and increased assembly costs. The various embodiments disclosed in the detailed description include a semiconductor die ("die") that employs a seed layer to form additional signal paths to the back-end process (BEOL) structure of the die. Related integrated circuit (IC) packaging and manufacturing methods are also disclosed. The die includes a BEOL interconnect structure comprising one or more metallization layers. Each metallization layer includes metal interconnects that provide signal routing paths to devices formed in the active semiconductor layer of the die. The die also includes a plurality of under-bump metallization (UBM) interconnects, also referred to as UBM-only. The UBM interconnects are coupled to metal interconnects in the upper metallization layer of the BEOL interconnect structure to facilitate the formation of bump interconnect bumps (e.g., solder bumps, metal pillars). The bump interconnect bumps provide an electrical interconnect interface for signal routing between the die and the package substrate of the IC package. The UBM interconnect is formed by a metal seed layer (also known as a "bump distribution layer" (BDL)) disposed in a groove formed in a passivation layer on the BEOL interconnect structure, which exposes the metal interconnects in the upper metallization layer of the BEOL interconnect structure. The bump interconnect is formed in contact with the UBM interconnect ground. Reducing the bump interconnect spacing to increase die connectivity density may be desirable. The bump interconnect spacing affects the signal routing distance between the die and the package substrate, which can increase routing resistance and inductance. For example, this can increase the current resistance (IR) drop of power signals routed via the bump interconnect. Multiple bump interconnects can be consumed as a node and coupled together to reduce the resistance of a specific die interconnect, but this consumes additional interconnect bumps that could otherwise be used for other signal routing. Even consuming multiple bump interconnects may not provide the desired resistance reduction. The manufacturing method allows the recesses in the BEOL interconnect structure forming the UBM interconnect to have a smaller pitch than the minimum pitch of the raised interconnect bumps. Forming these recesses is not subject to the same manufacturing limitations associated with the formation and minimum pitch of the raised interconnect bumps. Therefore, in various exemplary embodiments, to provide an additional signal path to the die that would otherwise be limited by the minimum raised interconnect bump pitch of its IC package, the seed layer disposed in the recess to form the UBM interconnect is reused. Portions of the seed layer disposed in the recess to form the UBM interconnect are reused to extend beyond the recess and couple to another UBM interconnect in which no raised interconnect bumps are formed. The UBM interconnect in which no raised interconnect bumps are formed is considered an "invisible" or "non-raised" interconnect bump because it lacks formed raised interconnect bumps. The UBM interconnect still has an interconnect path to the BEOL interconnect structure even without coupled interconnect bumps. Therefore, a UBM interconnect without interconnect bumps forming non-raised interconnect bumps still provides an additional signal path to the BEOL interconnect structure. This allows for the provision of such non-bump interconnect bumps in the IC package, and these non-bump interconnect bumps are coupled to the bump interconnect bumps via a seed layer to provide additional signal paths for the bump interconnect bumps. This also allows for providing additional signal routing paths for the bump interconnect bumps without consuming additional bump interconnect bumps and without attempting to further reduce the bump interconnect bump spacing in the BEOL interconnect structure. In one exemplary embodiment, an IC package is disclosed. The IC package includes a die. The die includes a BEOL interconnect structure. The die also includes a plurality of UBM interconnects, each UBM interconnect coupled to the BEOL interconnect structure. The plurality of UBM interconnects includes a first UBM interconnect and a second UBM interconnect, the second UBM interconnect not having a coupled interconnect bump. The die further includes a seed layer that couples the first UBM interconnect to the second UBM interconnect to couple the bump interconnect bump to the second UBM interconnect. In another exemplary embodiment, a method for manufacturing a semiconductor wafer is disclosed. The method includes: forming a BEOL interconnect structure on a semiconductor layer. The method also includes: forming a plurality of UBM interconnects, each UBM interconnect coupled to the BEOL interconnect structure. Forming the plurality of UBM interconnects includes: forming a first UBM interconnect coupled to the BEOL interconnect structure. Forming the plurality of UBM interconnects also includes: forming a second UBM interconnect coupled to the BEOL interconnect structure, wherein the second UBM interconnect does not have coupled interconnect bumps. The method also includes: forming a seed layer that couples the first UBM interconnect to the second UBM interconnect. The method also includes: forming a raised interconnect bump coupled to the first UBM interconnect, the first UBM interconnect coupling the raised interconnect bump to the second UBM interconnect. Several exemplary forms of this case are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any form described herein as "exemplary" is not necessarily to be construed as superior to or better than the other forms. The various embodiments disclosed in the detailed description include a semiconductor die ("die") that employs a seed layer to form additional signal paths to the back-end process (BEOL) structure of the die. Related integrated circuit (IC) packaging and manufacturing methods are also disclosed. The die includes a BEOL interconnect structure comprising one or more metallization layers. Each metallization layer includes metal interconnects that provide signal routing paths to devices formed in the active semiconductor layer of the die. The die also includes a plurality of under-bump metallization (UBM) interconnects, also referred to simply as UBMs. The UBM interconnects are coupled to metal interconnects in the upper metallization layer of the BEOL interconnect structure to facilitate the formation of bump interconnects (e.g., solder bumps, metal pillars). The bump interconnects provide an electrical interconnect interface for signal routing between the die and the package substrate of the IC package. The UBM interconnect is formed by a metal seed layer (also known as a "bump distribution layer" (BDL)) disposed in a groove formed in a passivation layer on top of the BEOL interconnect structure, which exposes the metal interconnects in the upper metallization layer of the BEOL interconnect structure. The bump interconnect is formed in contact with the UBM interconnect ground. Reducing the bump interconnect spacing to increase die connectivity density may be desirable. The bump interconnect spacing affects the signal routing distance between the die and the package substrate, which can increase routing resistance and inductance. For example, this can increase the current resistance (IR) drop of power signals routed via the bump interconnect. Multiple bump interconnects can be consumed as a node and coupled together to reduce the resistance of a specific die interconnect, but this consumes additional interconnect bumps that could otherwise be used for other signal routing. Even consuming multiple bump interconnects may not provide the desired resistance reduction. The manufacturing method allows the recesses in the BEOL interconnect structure forming the UBM interconnect to have a smaller pitch than the minimum pitch of the raised interconnect bumps. Forming these recesses is not subject to the same manufacturing limitations associated with the formation and minimum pitch of the raised interconnect bumps. Therefore, in various exemplary embodiments, to provide an additional signal path to the die that would otherwise be limited by the minimum raised interconnect bump pitch of its IC package, the seed layer disposed in the recess to form the UBM interconnect is reused. Portions of the seed layer disposed in the recess to form the UBM interconnect are reused to extend beyond the recess and couple to another UBM interconnect that does not have a raised interconnect bump. The UBM interconnect that does not have a raised interconnect bump is considered an "invisible" or "non-raised" interconnect bump because it lacks a formed raised interconnect bump. Even without coupled interconnect bumps, the UBM interconnect still has an interconnect path to the BEOL interconnect structure. Therefore, a UBM interconnect without interconnect bumps forming non-raised interconnect bumps still provides an additional signal path to the BEOL interconnect structure. This allows for the provision of such non-bump interconnect bumps in the IC package, and the non-bump interconnect bumps are coupled to the bump interconnect bumps via a seed layer to provide additional signal paths for the bump interconnect bumps(s). This also allows for providing additional signal routing paths for the bump interconnect bumps without consuming additional bump interconnect bumps and without attempting to further reduce the bump interconnect bump spacing in the BEOL interconnect structure. Before discussing the exemplary die that employs a seed layer to form an additional signal path to the die in the BEOL interconnect structure, starting from Figures 3A and 3B, an exemplary integrated circuit IC package 100 including dies 104(1)-104(3) coupled to the package substrate 106 via interconnect bumps is first described with reference to Figures 1 and 2. In this regard, Figure 1 illustrates an IC package 100 including a die module 102 comprising a plurality of dies 104(1)-104(3) coupled to a package substrate 106 in a stacked configuration in the vertical direction (Z-axis direction). Three dies 104(1)-104(3) are illustrated, but note that the IC package 100 is not limited to any particular number of dies. The die module 102 includes raised interconnect bumps 108 coupled to the dies 104(1) to facilitate coupling between the dies 104(1) and the package substrate 106. The raised interconnect bumps 108 are formed on the die module 102 with a desired interconnect bump pitch, depending on the signal transmission density required for the application of the IC package 100 and manufacturing process limitations. The raised interconnect bumps 108 are die interconnects formed of a metallic material, such as copper. Solder joints can also be formed on the metal material of the bump interconnect 108 to facilitate solder coupling to the package substrate 106. In this example, dies 104(1)-104(3) include vertical interconnect vias (vias) 110 (such as through-silicon vias (TSVs)) to provide stacked coupling between dies 104(1)-104(3) to the bump interconnect 108 so that dies 104(2) and 104(3) can be coupled to the package substrate 106 via intermediary dies 104(1) and 104(2), respectively. The package substrate 106 includes metallization layers 112, each metallization layer 112 including metal interconnects 114. The metal interconnects 114 can be coupled to the bump interconnect 108 to provide signal routing paths between dies 104(1)-104(3) and the package substrate 106. Metal interconnects 114 may also be coupled to external interconnect bumps 116 (e.g., solder bumps, ball grid arrays (BGAs), pad gate arrays (LGAs)) outside the IC package 100 to facilitate coupling of the IC package 100 to the circuit board 118. In this way, the package substrate 106 and the raised interconnect bumps 108 provide a signal routing path to the circuit board 118 between the dies 104(1)-104(3) and the external interconnect bumps 116. Furthermore, some metal interconnects 114 may be coupled to each other to reduce the resistance of such connections and / or provide die-to-die (D2D) interconnects. Moreover, some raised interconnect bumps 108 may be coupled to the same metal interconnects 114 to further reduce resistance. For example, this reduction in current resistance (IR) drop for power signal routing paths may be desirable. Figure 2 illustrates a top view of the IC package 100 in Figure 1, showing a die 104(1) disposed on a package substrate 106. Interconnect bumps 108 coupling the die 104(1) to the package substrate 106 have an interconnect bump pitch P. 1. It may be desirable to reduce the interconnect bump spacing P of the bump interconnect 108 of the die module 102. 1. To increase the die interconnect density in IC package 100. The spacing P of the bump interconnect 108. 1. The routing distance of the signal path between the dies 104(1)-104(3) and the package substrate 106 is affected. An increased routing distance in the signal routing path can increase the resistance of the signal carried on the signal path. If the signal carried is a power signal, the increase in resistance in the signal routing path will also increase the IR drop, thereby affecting the performance of the dies 104(1)-104(3). In the die module 102, multiple interconnect bumps 108 can be consumed and electrically coupled together to reduce the resistance of a specific die interconnect, but this consumes additional bump interconnect bumps 108 that could otherwise be used for other signal routing. In this regard, to provide more interconnect bump structures to provide additional signal routing paths to the bumped interconnect bumps coupling the die to the package substrate, and without reducing the bumped interconnect bump spacing, a seed layer (e.g., a bump distribution layer) can form additional UBM interconnects that do not have interconnect bumps (e.g., bumped interconnect bumps) formed thereon. UBM interconnects that do not have, for example, interconnect bumps coupled thereon are considered "non-bumped" interconnect bumps. A seed layer deposited adjacent to the outer metallization layer of the die's BEOL interconnect structure can be reused to form additional non-bumped interconnect bumps. In this regard, the seed layer is selectively removed during manufacturing to leave at least a portion of the seed layer that will be formed in the UBM interconnect and electrically coupled to the bumped metal interconnect of the BEOL interconnect structure to one or more other UBM interconnects in which no interconnect bumps (e.g., bumped interconnect bumps) are formed. The other UBM interconnects that do not have interconnect bumps are considered "invisible" or "non-bumped" interconnect bumps because, although no UBM interconnect bumps are formed in this type of UBM interconnect, the seed layer in this type of UBM interconnect is also electrically coupled to the BEOL interconnect structure. By having a seed layer that couples the bumped interconnect bumps to the non-bumped interconnect bumps, an additional signal routing path can be provided between the bumped interconnect bumps and the BEOL interconnect structure. This also allows for providing additional signal routing paths for the bumped interconnect bumps by coupling them to(the) non-bumped interconnect bumps via a seed layer, without consuming additional bumped interconnect bumps and without attempting to further reduce the interconnect bump spacing. This is illustrated by examples in Figures 3A and 3B discussed below. In this regard, Figure 3A is a cross-sectional side view of an exemplary IC package 300 including a die 302 and a non-bump interconnect bump 306 coupled to a package substrate 304, and the non-bump interconnect bump 306 serving to provide an additional signal path between the die 302 and the package substrate 304. The package substrate 304 is illustrated in Figure 3A as being above the die 302 in the vertical Z-axis direction, with the die 302 flipped over. In this example, the non-bump interconnect bump 306 is disposed between bump interconnect bumps 308(2), 308(3). The term "non-bump" interconnect bump means that the UBM interconnect formed in the BEOL interconnect structure 310 (discussed in more detail in Figure 3B) does not have interconnect bumps with coupling similar to the bump interconnect bumps 308(1)-308(3) (e.g., bump interconnect bumps formed on the UBM interconnect). Bumps 308(1)-308(3) couple the BEOL interconnect structure 310 of the die 302 to the package substrate 304 to provide a signal routing path between the die 302 and the package substrate 304, including a signal routing path to the external interconnect bumps 311 (e.g., solder bumps, ball grid arrays (BGAs), pad gate arrays (LGAs). In this example, the BEOL interconnect structure 310 includes an external BEOL metallization layer 312(1) and also includes a plurality of BEOL metallization layers. Interconnection structures 312(2)-312(X). Figure 3A illustrates BEOL metallization layers 312(1)-312(3) including corresponding metal interconnects 314(1)-314(X), which provide signal routing paths between the active semiconductor layers 316 in die 302 and the BEOL interconnect structure 310. The active semiconductor layers 316 are front-end process (FEOL) structures 317 including semiconductor devices (such as transistors). As discussed in more detail below, the non-protruding interconnect bump 306 does not include protruding metal pillars or structures similar to those of the protruding interconnect bumps 308(1)-308(3). Therefore, forming the non-protruding interconnect bump 306 is not limited by the same pitch manufacturing process as forming the protruding interconnect bumps 308(1)-308(3). The protruding interconnect bumps 308(1)-308(3) in Figure 3A have an interconnect bump pitch P. 2. The interconnect bump spacing P 2. This limits the number and density of interconnect bumps formed to couple the die 302 to the package substrate 304 in the IC package 300. In this example, non-bump interconnect bumps 306 can be formed at a distance from adjacent bump interconnect bumps 308(2), 308(3) relative to the interconnect bump spacing P. 2. At a shorter distance. As will be discussed in more detail below, in this example, the non-bump interconnect 306 is coupled to the bump interconnects 308(1)-308(2) via a seed layer 318 (also referred to as a bump distribution layer (BDL)). The bump interconnect 308(2) is coupled to the adjacent bump interconnect 308(1) via the seed layer 318 to couple both interconnects 308(1)-308(2) together with the non-bump interconnect 306 via the seed layer 318. In this example, the non-bump interconnect 306 is also coupled to a metal interconnect in the form of a redistribution layer (RDL) interconnect 320 (for example, a metal pad, such as an aluminum pad), which is in the RDL 322 formed on the BEOL metallization layer 312(1) of the BEOL interconnect structure 310 of the die 302. In this manner, the non-bump interconnect bump 306 provides a signal routing path to the BEOL interconnect structure 310. RDL 322 is a type of metallization layer that can be provided in the BEOL interconnect structure 310. RDL 322 includes a metal interconnect in the form of an RDL interconnect 320. The RDL interconnect 320 is a metal interconnect formed of a metallic material. Because the non-bump interconnect bump 306 is coupled to the bump interconnect bumps 308(1), 308(2) via a seed layer 318, the non-bump interconnect bump 306 provides an additional signal routing path for signals carried on the coupled bump interconnect bumps 308(1), 308(2). In this manner, an additional signal routing path to the BEOL interconnect structure 310 can be provided for the bump interconnect bumps 308(1), 308(2) via the coupling between the bump interconnect bumps 308(1), 308(2) and the non-bump interconnect bump 306. Figure 3B is a cross-sectional view of die 302 in Figure 3A, to facilitate further discussion and additional exemplary details of non-bump interconnect bump 306 coupled to bump interconnect bumps 308(1), 308(2). As shown in Figure 3B, in this example, die 302 includes a UBM layer 324 disposed on passivation layers 334, 336 and in contact with RDL interconnect 320 of RDL 322. The UBM layer 324 with respect to UBM interconnects 326(1), 326(2) and the second UBM interconnect 326(4) is shown only in the cross-sectional side view of IC package 300 in Figure 3B. The UBM layer formed beneath bump interconnect bump 308(3) is hidden in the cross-sectional view of Figure 3. In this example, UBM layer 324 is a thin metal layer disposed (e.g., sputtered on) passivation layers 334, 336, which is disposed on BEOL interconnect structure 310. In this example, passivation layers 334 and 336 are electrical dielectric materials (e.g., polyimide, silicon nitride, silicon oxide) disposed on RDL 322 and formed on the outer BEOL metallization layer 312(1). Passivation layer 334 protects the RDL interconnects 320 in RDL 322 from oxidation and / or corrosion. A second passivation layer 336 may also be disposed on the first passivation layer 334. Passivation layer 334 (and optionally passivation layer 336) are selectively removed (e.g., etched) during manufacturing to form grooves 328(1)-328(4). Grooves 328(1)-328(4) extend downward to and expose the RDL interconnects 320(1)-320(4) of RDL 322. This provides interconnect paths for UBM layer 324, which is formed within corresponding recesses 328(1)-328(2), 328(4) to form UBM interconnects 326(1)-326(2) and a second UBM interconnect 326(4) coupled to RDL interconnects 320(1)-320(2), 320(4), thereby providing signal paths to BEOL interconnect structure 310. UBM interconnect 326(3) (not shown in Figure 3B) is formed in recess 328(3) and coupled to RDL interconnect 320(3) to provide signal paths to BEOL interconnect structure 310. UBM interconnects 326(1)-326(3) facilitate the formation of raised interconnect bumps 308(1)-308(3). As will be discussed below, raised interconnect bumps are not formed on the second UBM interconnect 326(4), so that the second UBM interconnect 326(4) forms a non-raised interconnect bump 306. In this example, the grooves 328(1)-328(3) can be formed such that the distance between them in the horizontal direction (X-axis or Y-axis direction) is greater than the raised interconnect bump spacing P. 2 is shorter. Referring again to Figure 3B, the seed layer 318 is disposed above the UBM layer 324 and contacts the corresponding RDL interconnects 320(1)-320(2) and 320(4) in the grooves 328(1)-328(2) and 328(4). A portion of the seed layer 318 disposed and residing in the grooves 328(1)-328(2) and 328(4) contacts the UBM layer 324 coupled to the RDL interconnects 320(1)-320(2) and 320(4). The UBM layer 324 also forms part of the UBM interconnects 326(1)-326(2) and 324(4) (sometimes simply referred to as UBM). UBM interconnects 326(1)-326(3) and the second UBM interconnect 326(4) contact and are electrically coupled to the corresponding RDL interconnects 320(1)-320(3) formed in RDL 322 to provide an electrical connection between the UBM interconnects 326(1)-326(3) and the second UBM interconnect 326(4) and the BEOL interconnect structure 310. Grooves 328(1)-328(3) are formed to prepare raised interconnect bumps 308(1)-308(3) which are to be formed in contact with the corresponding UBM interconnects 326(1)-326(3) and thus in contact with the BEOL interconnect structure 310. In this manner, in this example, UBM interconnects 326(1)-326(3) are each coupled to metal interconnects 314(1) in the external BEOL metallization layer 312(1) via RDL interconnects 320(1)-320(3) in RDL 322. Bump interconnects 308(1)-308(3) are formed in contact with UBM interconnects 326(1)-326(3) to provide a signal routing path between the bump interconnects 308(1)-308(3) (and the coupled package substrate 304 as shown in Figure 3A) and the BEOL interconnect structure 310. In this example, the bump interconnects 308(1)-308(3) include corresponding metal pillars 330(1)-330(3). The metal pillars 330(1)-330(3) are formed of a metallic material (e.g., copper) in corresponding recesses 328(1)-328(3) that are disposed in contact with the corresponding UBM interconnects 326(1)-326(3). Solder joints 332(1)-332(3) may be coupled to the metal pillars 330(1)-330(3) to provide coupling of the die 302 to the package substrate 304 (Figure 3A) during the solder reflow process. The UBM interconnects 326(1)-326(3) that facilitate the formation of the corresponding bump interconnects 308(1)-308(3) have a UBM interconnect bump pitch that can be the smallest due to the process limitations of the BEOL interconnect structure 310 (which is the interconnect pitch P). 2). The spacing of the bump interconnects 308(1)-308(3) need not be the same. Such signal routing paths can then be coupled to semiconductor elements formed in the active semiconductor layer 316 (Figure 3A) to provide signal routing paths between the bump interconnects 308(1)-308(3) and the active semiconductor layer 316. Referring again to Figure 3B, the seed layer 318 remains resident (i.e., repurposed) to couple the raised interconnect bumps 308(1), 308(2) to the second UBM interconnect 326(4) forming the non-raised interconnect bump 306 in the recess 328(4). In this example, the second UBM interconnect 326(4) forms the non-raised interconnect bump 306 because interconnect bumps (e.g., raised interconnect bumps) are not formed on the second UBM interconnect 326(4). The portion of the seed layer 318 extending into the recess 328(4) constitutes the second UBM interconnect 326(4) forming the non-raised interconnect bump 306. As discussed above, the second UBM interconnect 326(4) forming the non-raised interconnect bump 306 is coupled via RDL 322 to the metal interconnect 314(1) in the external BEOL metallization layer 312(1) to provide an additional signal routing path to the raised interconnect bump 308(2). This is because the seed layer 318 remains resident (i.e., reused) during manufacturing to continuously extend outside the grooves 328(1), 328(2), and 328(4) in contact with the UBM interconnects 326(1)-326(2), the second UBM interconnect 326(4), the raised interconnect bumps 308(1), 308(2), and the non-raised interconnect bump 306. The UBM layer 324 and the seed layer 318 are selectively removed only during the manufacturing of the die 302 so that the raised interconnect bumps 308(1), 308(2) are coupled to the non-raised interconnect bump 306. Note that additional passivation layers may also be provided on the seed layer 318 exposed outside the raised interconnect bumps 308(1)-308(3) to protect the seed layer 318. Referring again to Figure 3B, as an example, a non-bump interconnect bump 306 can be used to provide additional signal paths for bump interconnect bumps 308(1), 308(2), which are part of the power distribution network (PDN) of IC package 300, to reduce resistance and IR drop. The non-bump interconnect bump 306 can be used to provide signal paths for input / output (I / O) signal nodes of die 302, which provide I / O signals from the I / O circuitry in die 302. The non-bump interconnect bump 306 and the coupled bump interconnect bumps 308(1), 308(2) can be coupled to a ground plane formed by coupled metal interconnects 314(1)-314(X) in the BEOL metallization layers 312(1)-312(X) of IC package 300 (see also Figure 3A). In this example, the seed layer 318 will be coupled to a ground plane that is part of the PDN to provide an additional signal path between the package substrate 304 and ground. Alternatively, the non-bump interconnect bump 306 can provide an additional signal path for the bump interconnect bumps 308(1), 308(2) that are part of the positive power rail of the PDN of the IC package 300. Furthermore, the non-bump interconnect bump 306 can be provided to provide an additional or alternative signal path for the bump interconnect bumps 308(1), 308(2) that are part of the signal path (e.g., I / O signal path) between the package substrate 304 and the die 302, which is not part of the PDN used to distribute power in the IC package 300. Figure 4 illustrates a top view of the IC package 300 shown in Figures 3A and 3B, illustrating a die 302 disposed on a package substrate 304. Interconnect bumps 308 coupling the die 302 to the package substrate 304 have an interconnect bump pitch P. 2. Non-bump interconnect bumps 306 are formed on die 302 between and adjacent to bump interconnect bumps 308 to provide additional signal routing paths to package substrate 304. Note, for example, the distance D between non-bump interconnect bumps 306(1) and bump interconnect bumps 308(1) is... 1 is less than the interconnect bump pitch P 2. In this manner, additional non-bump interconnect bumps 306 may be provided between and adjacent to bump interconnect bumps 308 and coupled to one or more interconnect bumps 308 to provide additional signal routing paths and / or reduce the resistance of certain signal routing paths between die 302 and package substrate 304. As an example, bump interconnect bumps 308(2) are coupled to non-bump interconnect bumps 306(2) via seed layer 318(2). It may also be desirable to provide certain non-bump interconnect bumps 306 that are coupled to bump interconnect bumps 308 that are not directly adjacent to each other. For example, it may be desirable to never be directly adjacent to a non-bump interconnect bump 306 and to be located at a distance greater than the interconnect bump pitch P from the desired bump interconnect bump 308 to be coupled. The convex interconnect bump 308 routes the signal at a distance of 2. This is illustrated by an example in Figure 4, where the non-convex interconnect bump 306(1) is coupled to the convex interconnect bump 308(3) via the seed layer 318(3). Figure 5 is a cross-sectional side view of another IC package 500 including a die 502, which includes a seed layer 518 coupling raised interconnect bumps 508(1) to non-raised interconnect bumps 506 that are not directly adjacent to each other. The non-raised interconnect bumps 506 are coupled to the raised interconnect bumps 508(1), which are located at an interconnect bump spacing P greater than that between the raised interconnect bumps 508(1) and 508(3). A distance of 3. In this example, non-bump interconnect bump 506 is disposed between bump interconnect bumps 508(2) and 508(3). Bump interconnect bumps 508(1)-508(3) couple the BEOL interconnect structure 510 of die 502 to a package substrate (not shown) to provide a signal routing path between die 502 and package substrate. In this example, the BEOL interconnect structure 510 is an interconnect structure including an external BEOL metallization layer 512(1) and also including a plurality of BEOL metallization layers 512(2)-512(X). BEOL metallization layers 512(1)-512(X) include corresponding metal interconnects 514(1)-514(X) which provide a signal routing path between the active semiconductor layers 516 in die 502 and the BEOL interconnect structure 510. (Various) Active semiconductor layer 516 is a front-end process (FEOL) structure 517 that includes semiconductor devices (such as transistors). Similar to the non-bump interconnect bumps 306 in die 302 of Figures 3A and 3B, the non-bump interconnect bumps 506 in die 502 of Figure 5 do not include bump-like interconnect bumps 508(1)-508(3) provided as bump interconnect bumps. Therefore, forming the non-bump interconnect bumps 506 is not limited by the same pitch manufacturing process as forming the bump interconnect bumps 508(1)-508(3). The bump interconnect bumps 508(1)-508(3) in Figure 5 have an interconnect bump pitch P. 3. The interconnect bump spacing P 3. This limits the number and density of interconnect bumps coupled to the die 502 in the IC package 500. In this example, non-bump interconnect bumps 506 can be formed at a distance from adjacent bump interconnect bumps 508(2), 508(3) relative to the interconnect bump spacing P. 3. At a shorter distance. In this example, the non-bump interconnect 506 is coupled to the bump interconnect 508(1) via a seed layer 518, which is located at a distance from the non-bump interconnect 506 greater than the interconnect bump spacing P. A distance of 3. In this example, the non-bump interconnect 506 is also coupled to the RDL interconnect 520(4) (e.g., a metal pad, such as an aluminum metal pad), which is in the RDL 522 formed on the outer BEOL metallization layer 512(1) of the die 502 on the BEOL interconnect structure 510. The RDL 522 may be another metallization layer that can be included in the BEOL interconnect structure 510. The RDL interconnects 520(1)-520(4) are metal interconnects formed of a metal material. The non-bump interconnect 506 provides a signal routing path to the BEOL interconnect structure 510. And because the non-bump interconnect 506 is coupled to the bump interconnect 508(1) via the seed layer 518, the non-bump interconnect 508 provides an additional or alternative signal routing path for the signals carried on the coupled bump interconnect 508(1). In this way, an additional or alternative signal routing path to the BEOL interconnect structure 510 can be provided to the raised interconnect bump 508(1) via coupling to the non-raised interconnect bump 506, without consuming additional raised interconnect bumps and without attempting to further reduce the interconnect bump spacing P. 3. Referring again to Figure 5, in this example, die 502 includes a UBM layer 524. The UBM layer 524 extends between recesses 528(1) and 528(4), but appears to extend below the raised interconnect bumps 508(2), as Figure 5 is a cross-sectional view where the raised interconnect bumps 508(2) are located behind the recesses 528(1), 528(4). The UBM layer 524 is disposed on passivation layers 534, 536 and is disposed in recesses 528(1), 524(4) on RDL 522 in contact with the corresponding RDL interconnects 520(1), 520(4). The UBM layer 524 is a thin metal layer partially disposed on the passivation layers 534, 536, which are disposed on the BEOL interconnect structure 510. In this example, passivation layers 534 and 536 are disposed on RDL 522 and formed on an external BEOL metallization layer 512(1) with an electrical dielectric material (e.g., polyimide, silicon nitride, silicon oxide). Passivation layer 534 protects the RDL interconnects 520 in RDL 522 from oxidation and / or corrosion. A second passivation layer 536 may also be disposed on the first passivation layer 534. Passivation layer 534 (and optionally passivation layer 536) are selectively removed (e.g., etched) during manufacturing to form grooves 528(1)-528(4). Grooves 528(2) are not shown directly in the cross-sectional view of Figure 5 because the cross-sectional position in Figure 5 is in front of the raised interconnect bumps 508(2) outside the figure in the Y-axis direction. Referring again to Figure 5, recesses 528(1)-528(4) extend downward to RDL interconnects 520(1)-520(4) to expose the RDL interconnects 520(1)-520(4) of RDL 522. This provides interconnect paths for UBM layers 524 within the corresponding recesses 528(1), 528(4) to form UBM interconnects 526(1) and second UBM interconnects 526(4) (each coupled to the corresponding RDL interconnects 520(1), 520(4)) to provide signal paths to the BEOL interconnect structure 510. UBM interconnects 526(2), 526(3) are formed by UBM layers and seed layers (not shown in the cross-sectional view of IC package 500 in Figure 5). UBM interconnects 526(1)-526(3) facilitate the formation of bump interconnects 508(1)-508(3). As will be discussed below, raised interconnect bumps are not formed on the second UBM interconnect 526(4), so that the second UBM interconnect 526(4) forms a non-raised interconnect bump 506. In this example, the grooves 528(1)-528(4) may be spaced apart in the horizontal direction (X-axis or Y-axis direction) at a distance greater than the raised interconnect bump spacing P. 2. Formed over a shorter distance. Referring again to Figure 5, a seed layer 518 is disposed above a UBM layer 524, which contacts the corresponding RDL interconnects 520(1) and 520(4) in the recesses 528(1) and 528(4). The UBM layer 524 forms part of the UBM interconnect 526(1) and the second UBM interconnect 526(4) (sometimes simply referred to as UBM). Therefore, the UBM interconnect 526(1) and the second UBM interconnect 526(4) are in contact with and electrically coupled to the corresponding RDL interconnects 520(1) and 520(4) formed in the RDL 522 to provide electrical connection between the UBM interconnects 526(1) and the second UBM interconnect 526(4) and the BEOL interconnect structure 510. The UBM interconnects 526(2) and 326(3) are also in contact with the corresponding RDL interconnects 520(2) and 520(3), but this is hidden in the cross-sectional view of Figure 5. Grooves 528(1)-528(3) are formed to prepare raised interconnect bumps 508(1)-508(3), which are to be formed in contact with the corresponding UBM interconnects 526(1)-526(3) and thus in contact with the BEOL interconnect structure 310. In this way, in this example, the UBM interconnects 526(1)-526(3) are each coupled to the metal interconnects 514(1) in the outer BEOL metallization layer 512(1) via RDL interconnects 520(1)-520(3) in RDL 522. The raised interconnect bumps 508(1)-508(3) are formed in contact with the UBM interconnects 526(1)-526(3) to provide a signal routing path between the raised interconnect bumps 508(1)-508(3) and the BEOL interconnect structure 510. In this example, the bump interconnects 508(1)-508(3) include corresponding metal pillars 530(1)-530(3). The metal pillars 530(1)-530(3) are formed of a metallic material (e.g., copper) disposed in corresponding recesses 528(1)-528(3) in contact with the corresponding UBM interconnects 526(1)-526(3). Solder joints 532(1)-532(3) may be coupled to the metal pillars 530(1)-530(3) to provide coupling of the die 502 to the package substrate 304 (Figure 3A) during the solder reflow process. The UBM interconnects 526(1)-526(3) that facilitate the formation of the corresponding bump interconnects 508(1)-508(3) have a UBM interconnect bump pitch that can be the smallest due to the process limitations of the BEOL interconnect structure 510 (which is the interconnect pitch P). 3) The spacing of the bump interconnects 508(1)-508(3) need not be the same. Such signal routing paths can then be coupled to a semiconductor device formed in the active semiconductor layer 516 to provide a signal routing path between the bump interconnects 508(1)-508(3) and the active semiconductor layer 516. Referring again to Figure 5, the seed layer 518 remains resident (i.e., repurposed) to couple the raised interconnect bump 508(1) to the second UBM interconnect 526(4) forming the non-raised interconnect bump 506 in the recess 528(4). In this example, the second UBM interconnect 526(4) forms the non-raised interconnect bump 506 because the interconnect bump (e.g., the raised interconnect bump) is not formed on the second UBM interconnect 526(4). The portion of the seed layer 518 extending into the recess 528(4) constitutes the second UBM interconnect 526(4) forming the non-raised interconnect bump 506. As discussed above, the second UBM interconnect 526(4) forming the non-raised interconnect bump 506 is coupled via RDL 522 to the metal interconnect 514(1) in the external BEOL metallization layer 512(1) to provide an additional signal routing path to the raised interconnect bump 508(1). This is because the seed layer 518 remains resident (i.e., repurposed) during manufacturing to continuously extend over the recess 528(1) and extend into the recess 528(1) in contact with the UBM interconnect 526(1) and the raised interconnect bump 508(1) formed in the recess 528(1). The UBM layer 524 and the seed layer 518 are selectively removed only during the manufacturing of the die 502 so that the raised interconnect bump 508(1) couples to the non-raised interconnect bump 506. Note that additional passivation layers may also be disposed on the seed layer 518 to protect the seed layer 518. This is desirable because the seed layer 518 is repurposed and remains resident outside the recesses 528(1)-528(4) to couple the raised interconnect bump 508(1) to the non-raised interconnect bump 506. For example, continuing to refer to Figure 5, a non-bump interconnect bump 506 can be provided to provide an additional signal path for the bump interconnect bump 508(1), which is part of the PDN of the IC package 500, to reduce resistance and IR drop. The non-bump interconnect bump 506 can be used to provide a signal path for the I / O signal node of the die 502, which provides I / O signals from the I / O circuitry in the die 502. The non-bump interconnect bump 506 and the coupled bump interconnect bump 508(1) can be coupled to a ground plane formed by coupled metal interconnects 514(1)-514(X) in the BEOL metallization layers 512(1)-512(X) of the IC package 500. In this example, the seed layer 518 will be coupled to the ground plane, which is part of the PDN, to provide an additional signal path between the package substrate and ground. Alternatively, the non-bump interconnect bump 506 can provide an additional signal path for the bump interconnect bump 508(1), which is part of the positive power rail of the PDN of the IC package 500. Furthermore, the non-bump interconnect bump 506 can provide an additional or alternative signal path for the bump interconnect bump 508(1), which is part of a signal path (e.g., an I / O signal path) to the die 502, and this additional or alternative signal path is not part of the PDN used to distribute power in the IC package 500. To further illustrate the benefits of a die with non-bump interconnect bumps, Figures 6 and 7 are provided. Figure 6 is a top view of an exemplary IC package 600 including a die 602, which includes bump interconnect bumps 608 coupling the die 602 to a package substrate 604. The die 602 does not include non-bump interconnect bumps. The bump interconnect bumps 608 are spaced at interconnect bump pitch P. 4 is formed in die 602. Other larger bump interconnects 610 (for example, for power signal distribution) are formed at interconnect bump pitch P. 5 is formed in die 602. Figure 7 is a top view of another exemplary IC package 700 including die 702, which includes raised interconnect bumps 708 coupling die 702 to package substrate 704. The raised interconnect bumps 708 are at interconnect bump pitch P. 6 is formed in grain 702, and the interconnect bump spacing P The interconnect bump spacing P in grain 602 in Figure 6 is compared to that in Figure 6. 4. Larger and more spacious. Other larger bump interconnects 710 are located in a segment of die 702 with interconnect bump spacing P. 7 is formed, the interconnecting bump spacing P 7 is greater than the interconnect bump spacing P in grain 602 in Figure 6. 5. As an example, raised interconnect bumps 710 can be used for power signal distribution in the PDN of die 702. Die 702 in Figure 7 includes non-raised interconnect bumps 706 formed by a seed layer between adjacent raised interconnect bumps 708. Die 702 in Figure 7 also includes non-raised interconnect bumps 712 formed by a seed layer between adjacent raised interconnect bumps 710. The ability to provide non-raised interconnect bumps 712 in die 702 provides additional signal routing paths in die 702. This can allow for a reduction in the number of interconnect bumps 708, 710 and / or the corresponding interconnect bump spacing P in die 702 of Figure 7. 6. P 7. Increase and loosen. Figure 8A illustrates a top view of another IC package 800 including a die 802 disposed on a package substrate 804, wherein the die 802 includes regions 810(1)-810(7), which include non-bump interconnect bumps 806(1)-806(7) of corresponding clusters of bump interconnect bumps 808(1)-808(7) that can be coupled to the bump interconnect bumps 808(1)-808(7) in the respective regions 810(1)-810(7). For example, a large number of bump interconnect bumps 808(1)-808(7) in a given region 810(1)-810(7) can be coupled together to ground the die 802 to a ground plane in the package substrate 804. Figure 8B is a close-up bottom view of region 810 in the exemplary die 802 in Figure 8A. As shown herein, a plurality of bump interconnect bumps 808 are coupled together. Non-bump interconnect bumps 806 are formed between adjacent interconnect bumps 808 and coupled to bump interconnect bumps 808 to form an additional signal routing path between die 802 and package substrate 804. Figure 9 is a flowchart illustrating an exemplary manufacturing process 900 for manufacturing a die for an IC package, wherein the die includes a seed layer forming non-bump interconnect bumps coupled to bump interconnect bumps. For example, the manufacturing process 900 in Figure 9 can be used to manufacture dies 302 and 502 in Figures 3A-3B and Figure 5, respectively. The manufacturing process 900 in Figure 9 will be described in conjunction with exemplary dies 302 and 502 in Figures 3A-3B and Figure 5. In this regard, as illustrated in Figure 9, the first step in manufacturing process 900 may include forming BEOL interconnect structures 310 and 510 on active semiconductor layers 316 and 516. BEOL interconnect structures 310 and 510 include BEOL metallization layers 312(1) and 512(1), which include a plurality of metal interconnects 314(1) and 514(1) (block 902). The next step in manufacturing process 900 may include forming a plurality of UBM interconnects 326(1)-326(3) and 526(1)-526(3), each UBM interconnect coupled to metal interconnects 314(1) and 514(1) in BEOL interconnect structures 310 and 510 (block 904 in Figure 9). The next step in manufacturing process 900 may include: forming first UBM interconnects 326(1)-326(3) and 526(1)-526(3) in a plurality of UBM interconnects 326(1)-326(3) and 526(1)-526(3), the first UBM interconnects 326(1)-326(3) and 526(1)-526(3) coupled to metal interconnects 314(1) and 514(1) in BEOL interconnect structures 310 and 510 (block 906 in Figure 9). The next step in manufacturing process 900 may include: forming second UBM interconnects 326(4) and 526(4) coupled to metal interconnects 314(1) and 514(1) in BEOL interconnect structures 310 and 510, wherein the second UBM interconnects 326(4) and 526(4) do not have coupled interconnect bumps (block 908 in Figure 9). The manufacturing process 900 may also include: forming seed layers 318 and 518, which are coupled to first UBM interconnects 326(1)-326(3) and 526(1)-526(3) and to second UBM interconnects 326(4) and 526(4), wherein the seed layers 318 and 518 couple the first UBM interconnects 326(1)-326(3) and 526(1)-526(3) to the second UBM interconnect bumps 326(4) and 526(4) (block 910 in Figure 9). The manufacturing process 900 may also include: forming raised interconnect bumps 308 and 508 coupled to the first UBM interconnects 326(1)-326(3) and 526(1)-526(3), and the first UBM interconnects 326(1)-326(3) and 526(1)-526(3) couple the raised interconnect bumps 308 and 508 to the second UBM interconnects 326(4) and 526(4) (block 912 in Figure 9). Dies including seed layers forming non-bump interconnect bumps coupled to bump interconnect bumps (such as dies 302 and 502 in Figures 3A-3B and 5, respectively) can be manufactured according to other processes. In this regard, Figures 10A-10C are flowcharts illustrating another exemplary manufacturing process 1000 for manufacturing dies for IC packages, wherein the die includes seed layers forming non-bump interconnect bumps coupled to bump interconnect bumps, and the die includes, but is not limited to, dies 302, 502, 602, 702, and 802 in Figures 3A-8B. Figures 11A-11I illustrate exemplary manufacturing stages 1100A-1100I of manufacturing dies according to the exemplary manufacturing process 1000 in Figures 10A-10C, wherein the die includes seed layers forming non-bump interconnect bumps coupled to bump interconnect bumps. Manufacturing process 1000 in Figures 10A to 10C will be discussed in conjunction with exemplary manufacturing stages 1100A-1100I in Figures 11A to 11I. Manufacturing process 1000 and manufacturing stages 1100A-1100I are illustrated with reference to grain 302 in Figures 3A and 3B. However, it should be noted that manufacturing process 1000 and manufacturing stages 1100A-1100I can also be applied to the manufacture of grains 502, 602, 702, and 802 in Figures 5 to 8B. In this regard, as shown in the exemplary manufacturing stage 1100A in Figure 11A, the first step of the manufacturing process 1000 may be to provide a BEOL interconnect structure 310, which includes a metallization layer 312 and an RDL 322 (block 1002 in Figure 10A) formed in the BEOL interconnect structure 310. As shown in the exemplary manufacturing stage 1100B in Figure 11B, the next step in the manufacturing process 1000 may be to form a passivation layer 334 and a second passivation layer 336 on the RDL 322 and to pattern the passivation layers 334, 336 to form grooves 328(2)-328(4) (block 1004 in Figure 10A) in the passivation layers 334, 336 over the corresponding RDL interconnects 320(2)-320(3) in the RDL 322. As shown in the exemplary manufacturing stage 1100C in Figure 11C, the next step in the manufacturing process 1000 may be to form a UBM layer 324 over the passivation layers 334, 336 to prepare UBM interconnects 326(2)-326(3) (not shown) and a second UBM interconnect 326(4) (not shown), which are to be formed in corresponding recesses 328(2)-328(4) to form raised interconnect bumps 308(2), 308(3) and non-raised interconnect bumps 306 (block 1006 in Figure 10A). As shown in the exemplary manufacturing stage 1100D in Figure 11D, the next step in manufacturing process 1000 may be to form a seed layer 318 on UBM layer 324 and in grooves 328(2)-328(4) to form UBM interconnects 326(2), 326(3) and a second UBM interconnect 326(4) in contact with RDL interconnects 320(2)-320(4) in grooves 328(2)-328(4) (block 1008 in Figure 10B). As shown in the exemplary manufacturing stage 1100E in Figure 11E, the next step in manufacturing process 1000 may be to form a photoresist layer 1102 on seed layer 318 and pattern openings 1104(2), 1104(3) in photoresist layer 1102 to prepare for the formation of raised metal interconnects 308(2), 308(3) (Figure 11F) (block 1010 in Figure 10B). In this example, openings 1104(2), 1104(3) are formed only above the seed layer 318 for UBM interconnects 326(2), 326(3), because the raised interconnect bumps will not be formed in contact with the second UBM interconnect 326(4) to which the non-raised interconnect bump 306 will be formed. The photoresist layer 1102 can be patterned in a photolithography process to form openings 1104(2), 1104(3), each opening being disposed in the vertical direction (Z-axis direction) to expose the seed layer 318 disposed in the recesses 328(2), 328(3). As illustrated in the exemplary manufacturing stage 1100F in Figure 11F, the next step in manufacturing process 1000 is to deposit a metal material 1106 in a plurality of openings 1104(2), 1104(3) in the photoresist layer 1102 to form raised interconnect bumps 308(2), 308(3) (blocks 1012 in Figure 10B) coupled to the corresponding UBM interconnects 326(2), 326(3). A portion of the seed layer 318 and UBM layer 324 disposed in the recesses 328(2)-328(3) form UBM interconnects 326(2), 326(3). A portion of the seed layer 318 and UBM layer 324 disposed in the recess 328(4) form a second UBM interconnect 326(4). As illustrated in the exemplary manufacturing stage 1100G in Figure 11G, the next step of manufacturing process 1000 is to remove the photoresist layer 1102 and place a second photoresist layer 1108 on the seed layer 318 exposed from the bump interconnect bumps 308(2), 308(3) to prepare selected portions of the UBM layer 324 and seed layer 318 to be removed (e.g., etched) (block 1014 in Figure 10C). This is to prepare the UBM layer 324 and seed layer 318 to be etched outside the recesses 328(2)-328(4). In this example, portions of the UBM layer 324 and the seed layer 318 within the grooves 328(2)-328(4) will not be etched and will remain in the grooves 328(2)-328(4) to form UBM interconnects 326(2), 326(3) and the second UBM interconnect 326(4). The UBM layer 324 and the seed layer 318 are etched to be used to couple the second UBM interconnect 326(4) to the UBM interconnect 326(2), the second UBM interconnect 326(4) being formed by the seed layer 318 in the groove 328(4) and not having a coupled interconnect bump (block 1014 in Figure 10C). This couples the second UBM interconnect 326(4) without a coupled interconnect bump to the raised interconnect bump 308(2). As shown in the exemplary manufacturing stage 1100G in Figure 11G, patterned openings 1110 are formed in the second photoresist layer 1108 disposed above the seed layer 318, in which portions of the seed layer 318 are removed. In this manner, as shown in the exemplary manufacturing stage 1100H in Figure 11H, portions of the UBM layer 324 and the seed layer 318 in the openings 1110 are removed (e.g., etched) to provide an open circuit (block 1016 in Figure 10C) between the second UBM interconnect 326(4) forming the non-bump interconnect bump 306 and the bump interconnect bump 308(3). Due to etching into the openings 1110, the UBM layer 324 is split into three (3) separate UBM layers 324(1)-324(3). As etched into the opening 1110, the seed layer 318 is also split into three (3) separate seed layers 318(1)-318(3). The portion of the seed layer 318(1) that couples the non-bump interconnect 306 to the bump interconnect 308(2) remains resident by being blocked by the second photoresist layer 1108. Therefore, this portion of the seed layer 318(1) is used to couple the non-bump interconnect 306 to the bump interconnect 308(2).Subsequently, as shown in the exemplary manufacturing stage 1100I in Figure 11I, the entire structure of the BEOL interconnect structure 310 of manufacturing stage 1100F, including the raised interconnect bumps 308(2), 308(3) and the non-raised interconnect bumps 306, can then be reflowed to form solder joints 332(2), 332(3) (block 1018 in Figure 10C) on the metal pillars 330(2), 330(3) of the raised interconnect bumps 308(2), 308(3). It may also be desirable to provide a seed layer to provide non-bump interconnect bumps in the stacked dies of the IC package to facilitate an increase in interconnect density between stacked dies and / or between stacked dies and the package substrate. In this regard, Figure 12 is a side view of an exemplary stacked die IC package 1200 including a plurality of stacked first and second dies 1202(1), 1202(2), wherein each of the first die 1202(1) and the second die 1202(2) includes a seed layer 1218(1), 1218(2) similar to the seed layers 318, 518 in dies 302, 502 in Figures 3A to 3B and Figure 5 to form a non-bump interconnect bump coupled to one or more bump interconnect bumps. In this regard, as illustrated in Figure 12, the stacked die IC package 1200 includes a package substrate 1204. The first die 1202(1) is disposed above the package substrate 1204 in the vertical direction (Z-axis direction) and coupled to the package substrate 1204 via the raised interconnect bump 1208(1). The second die 1202(2) is disposed above the first die 1202(1) in the vertical direction (Z-axis direction) and coupled to the first die 1202(1) via the raised interconnect bump 1208(2). The first die 1202(1) includes a first BEOL interconnect structure 1210(1), which includes a first RDL layer 1224(1) and a UBM interconnect 1226(1). The BEOL interconnect structure 1210(1) is adjacent to the first active side 1240(1) of the first die 1202(1). An active semiconductor layer 1216(1) is coupled to the first BEOL interconnect structure 1210(1). The active semiconductor layer 1216(1) is adjacent to the first passive side 1242(1) of the first die 1202(1). Note that the first passive side 1242(1) of the first die 1202(1) may be facing down in the vertical direction (Z-axis direction) of Figure 12, rather than facing up as shown. A raised interconnect bump 1208(1) is formed in contact with the first die 1202(1). Non-bump interconnect 1206(1) is formed by a seed layer 1218(1) and coupled to other bump interconnects 1208(1). A second die 1202(2) includes a second BEOL interconnect structure 1210(2) adjacent to a second active side 1240(2) of the second die 1202(2). The second BEOL interconnect structure 1210(2) includes a second RDL layer 1224(2), which includes a UBM interconnect 1226(2). An active semiconductor layer 1216(2) is coupled to the second BEOL interconnect structure 1210(2). The active semiconductor layer 1216(2) is adjacent to a second passive side 1242(2) of the second die 1202(2). Bump interconnects 1208(2) are formed in contact with corresponding UBM interconnects 1226(2). Non-bump interconnect bump 1206(2) is formed by a seed layer 1218(2) and coupled to other bump interconnect bumps 1208(2). Through-hole 1244 (such as through silicon via (TSV)) can be used to provide a direct connection from the second die 1202(2) to the package substrate 1204 via the first die 1202(1). Through-hole 1244 can be used, for example, to couple the PDN of the first and second dies 1202(1), 1202(2) to their respective bump interconnect bumps 1208(1), 1208(2) dedicated to carrying signals and coupled non-bump interconnect bumps 1206(1), 1206(2). As an example, if the raised interconnect bumps 1208(1) and 1208(2) used for power delivery are not directly above each other in the vertical direction (z-axis direction), then the non-bump interconnect bumps 1206(1) and 1206(2) may be useful in the stacked die IC package 1200 in Figure 12. The non-bump interconnect bumps 1206(1) and 1206(2) can be used to provide flexibility for rerouting signals in the horizontal direction (X-axis or Y-axis direction).As another example, if the top die 1202(2) extends beyond the bottom die 1202(1) in the horizontal direction (X-axis or Y-axis direction), it would be impossible to directly couple the raised interconnect bump 1208(2) on the edge of the BEOL interconnect structure 1210(2) to the raised interconnect bump 1208(1) of the BEOL interconnect structure 1210(1) directly below. Therefore, the non-raised interconnect bump 1206(2) in the top BEOL interconnect structure 1210(1) can be used to horizontally reroute signals to other raised interconnect bumps 1208(2) adjacent to the top BEOL interconnect structure 1210(2), so that they can subsequently be routed downwards in the vertical direction (Z-axis direction) to the raised interconnect bump 1208(1) adjacent to the bottom BEOL interconnect structure 1210(1). Dies, including seed layers for forming non-bump interconnects, can also be placed in split-die IC packages that include split dies. In this regard, Figure 13 is a top view of an exemplary split-die IC package 1300, which includes split dies 1302(1) and 1302(2) coupled to a package substrate 1304. The first die 1302(1) and the second die 1302(2) each include corresponding D2D bump interconnect regions 1346(1) and 1346(2), which include corresponding interconnect bumps 1308(1) and 1308(2). The interconnect bumps 1308(1) and 1308(2) are coupled to each other via the package substrate 1304 to provide D2D connectivity between the first and second dies 1302(1) and 1302(2). Each die 1302(1), 1302(2) may include UBM interconnects 1326(1), 1326(2) in the corresponding BEOL interconnect structures 1310(1), 1310(2), the BEOL interconnect structures 1310(1), 1310(2) supporting the formation of raised interconnect bumps 1308(1), 1308(2) and non-raised interconnect bumps 1306(1), 1306(2) formed by the seed layers 1318(1), 1318(2), as shown by dies 302, 502 in Figures 3A to 3B and Figure 5, as examples. The raised interconnect bumps 1308(1) and 1308(2) in the corresponding D2D bump interconnect regions 1346(1) and 1346(2) can be coupled to the non-raised interconnect bumps 1306(1) and 1306(2) via seed layers 1318(1) and 1318(2), as shown by dies 302 and 502 in Figures 3A to 3B and Figure 5, as an example. The non-raised interconnect bumps 1306(1) and 1306(2) in the corresponding D2D bump interconnect regions 1346(1) and 1346(2) can be coupled to each other via the package substrate 1304 to provide D2D connectivity. Note that the terms "top" and "bottom" used herein are relative terms and do not imply a restriction or implication that an element referenced "top" must always be strictly oriented above an element referenced "bottom," or vice versa. Furthermore, note that the terms "above" and "below" used herein are relative terms and do not imply a restriction or implication that an element referenced "above" another reference element must always be strictly oriented relative to that other reference element above the ground, or that an element referenced "below" another reference element must always be strictly oriented relative to that other reference element below the ground. An IC package employing dies coupled to a package substrate can be provided in any processor-based device or the IC package can be integrated into the processor-based device, wherein the dies may include a seed layer for non-bump interconnect bumps in a UBM layer of the die, wherein the dies include, but are not limited to, the exemplary dies in Figures 3A to 8B and Figures 11A to 13 and the exemplary manufacturing process according to Figures 9 to 11F. Examples not limited to these include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft. In this regard, Figure 14 illustrates an example of a processor-based system 1400 including circuitry that may be provided in one or more IC packages 1402(1)-1402(5), each IC package employing dies coupled to a package substrate, wherein the dies may include seed layers of non-bump interconnect bumps coupling bumps to a UBM layer of the die, the dies including but not limited to the exemplary dies in Figures 3A to 8B and Figures 11A to 13 and the exemplary manufacturing process according to Figures 9 to 11F. In this example, the processor-based system 1400 may be formed as an IC 1404 in IC package 1402 and as a system-on-a-chip (SoC) 1406. The processor-based system 1400 includes a central processing unit (CPU) 1408, which includes one or more processors 1410, which may also be referred to as CPU cores or processor cores. CPU 1408 may have cached memory 1412 coupled to CPU 1408 for fast access to temporarily stored data. CPU 1408 is coupled to system bus 1414 and may be coupled to master and slave devices included in processor-based system 1400. As is well known, CPU 1408 communicates with these other devices by exchanging address, control, and data information on system bus 1414. For example, CPU 1408 may communicate bus transaction requests to memory controller 1416, which is an instance of a slave device. Although not shown in Figure 14, multiple system buses 1414 may be provided, each forming a different texture. Other master and slave devices may be connected to system bus 1414. As illustrated in Figure 14, such devices may, as an example, include a memory system 1418 comprising a memory controller 1420 and memory arrays 1416, one or more input devices 1422, one or more output devices 1424, one or more network peripheral devices 1426, and one or more display controllers 1428. Each of the memory system 1420, the one or more input devices 1422, the one or more output devices 1424, the one or more network peripheral devices 1426, and the one or more display controllers 1428 may be provided in the same IC package or different IC packages 1402(3), 1402(4). The input devices 1422 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 1424 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. (All) network peripheral devices 1426 may be any device configured to allow data exchange to and from network 1430. Network 1430 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth™ networks, and the Internet. (All) network peripheral devices 1426 may be configured to support any type of communication protocol desired. CPU 1408 can also be configured to access display controllers 1428 via system bus 1414 to control information sent to one or more displays 1432. Display controllers 1428 send information to be displayed to displays 1432 via one or more video processors 1434, which process the information to be displayed into a format suitable for displays 1432. As an example, display controllers 1428 and video processors 1434 can be included as ICs in the same IC package 1402(5) and in the same or different IC packages 1402, 1402(1) containing CPU 1402. Displays 1432 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc. Figure 15 illustrates an exemplary wireless communication device 1500 including radio frequency (RF) components formed of one or more ICs 1502, wherein any IC 1502 may be included in an IC package 1503 employing dies coupled to a package substrate, wherein the dies may include a seed layer of non-bump interconnect bumps coupling bumps to a UBM layer of the dies, the dies including but not limited to the exemplary dies in Figures 3A to 8B and Figures 11A to 13 and the exemplary manufacturing process according to Figures 9 to 11F. As an example, the wireless communication device 1500 may be included in or provided in any of the above-described devices. As shown in Figure 15, the wireless communication device 1500 includes a transceiver 1504 and a data processor 1506. The data processor 1506 may include memory for storing data and code. The transceiver 1504 includes a transmitter 1508 and a receiver 1510 supporting bidirectional communication. Generally, the wireless communication device 1500 may include any number of transmitters 1508 and / or receivers 1510 for any number of communication systems and frequency bands. All or part of the transceiver 1504 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc. Transmitter 1508 or receiver 1510 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted in multiple stages between the RF and baseband frequencies; for example, for receiver 1510, it is converted from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between the RF and baseband frequencies in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 1500 of Figure 15, transmitter 1508 and receiver 1410 are implemented using a direct conversion architecture. In the transmission path, data processor 1506 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1508. In the exemplary wireless communication device 1500, data processor 1506 includes digital-to-analog converters (DACs) 1512(1) and 1512(2) to convert digital signals generated by data processor 1506 into I and Q analog output signals (e.g., I and Q output currents) for further processing. Within transmitter 1508, low-pass filters 1514(1) and 1514(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1516(1) and 1516(2) amplify the signals from low-pass filters 1514(1) and 1514(2), respectively, and provide I and Q baseband signals. Upconverter 1518 upconverts the I and Q baseband signals via mixers 1520(1) and 1520(2) using the I and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 1522 to provide upconverted signal 1524. Filter 1526 filters upconverted signal 1524 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1528 amplifies the up-converted signal 1524 from filter 1526 to obtain the desired output power level and provide a transmit RF signal. This transmit RF signal is routed through duplexer or switch 1530 and transmitted via antenna 1532. In the receiving path, antenna 1532 receives signals transmitted from the base station and provides a received RF signal, which is routed through duplexer or switch 1530 and provided to low-noise amplifier (LNA) 1534. Duplexer or switch 1530 is designed to operate with specific receive (RX) and TX duplexer frequencies separated, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1534 and filtered by filter 1536 to obtain the desired RF input signal. Down-conversion mixers 1538(1) and 1538(2) mix the output of filter 1536 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1540 to generate I and Q baseband signals. The I and Q fundamental frequency signals are amplified by AMPs 1542(1) and 1542(2) and further filtered by low-pass filters 1544(1) and 1544(2) to obtain I and Q analog input signals, which are provided to data processor 1506. In this example, data processor 1506 includes analog-to-digital converters (ADCs) 1546(1) and 1546(2) to convert the analog input signals into digital signals to be further processed by data processor 1506. In the wireless communication device 1500 of Figure 15, a TX LO signal generator 1522 generates I and Q TX LO signals for up-conversion, while an RX LO signal generator 1540 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1548 receives timing information from a data processor 1506 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1522. Similarly, an RX PLL circuit 1550 receives timing information from a data processor 1506 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1540. Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the forms disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As examples, the master and slave devices described herein can be used in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in their functional form. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this document. The various illustrative logic blocks, modules, and circuits described in conjunction with the various states disclosed herein may be implemented or executed using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, individual gate or transistor logic, individual hardware components, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any general-purpose processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors coordinated with a DSP core, or any other such configuration). The various forms disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. Exemplary storage media are coupled to a processor so that the processor can read and write information to / from the storage media. In alternatives, the storage media can be integrated into the processor. The processor and storage media can reside in an ASIC. The ASIC can reside in a remote station. In alternatives, the processor and storage media can reside as separate components in a remote station, base station, or server. It should also be noted that the operational steps described in any of the exemplary embodiments herein are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders besides the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. The prior description of this application is provided to enable anyone skilled in the art to make or use it. Various modifications to this application will be apparent to those skilled in the art, and the universal principles defined herein can be applied to other variations. Therefore, this application is not intended to be limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein. Each embodiment is described in the following numbered clauses. 1. An integrated circuit (IC) package comprising: a die including: a back-end process (BEOL) interconnect structure; a plurality of under-bump metallization (UBM) interconnects, each UBM interconnect coupled to the BEOL interconnect structure, the plurality of UBM interconnects including: a first UBM interconnect; and a second UBM interconnect having uncoupled interconnect bumps; and a raised interconnect bump coupled to the first UBM interconnect; wherein the die further includes: a seed layer that couples the first UBM interconnect to the second UBM interconnect to couple the raised interconnect bump to the second UBM interconnect. 2. The IC package of clause 1, wherein the seed layer further includes the first UBM interconnect and the second UBM interconnect. 3. An IC package as described in any of Clauses 1-2, wherein the BEOL interconnect structure includes a metallization layer comprising: a plurality of first metal interconnects, each first metal interconnect coupled to a UBM interconnect among the plurality of UBM interconnects; and a second metal interconnect coupled to a second UBM interconnect. 4. An IC package as described in Clause 3, wherein the metallization layer includes a redistribution layer (RDL), the RDL comprising a plurality of first RDL interconnects and a second RDL interconnect; the plurality of first metal interconnects comprising the plurality of first RDL interconnects, each first RDL interconnect coupled to a UBM interconnect among the plurality of UBM interconnects; and the second metal interconnect comprising a second RDL interconnect. 5. An IC package as described in Clause 3, wherein the plurality of first metal interconnects comprises a plurality of metal pads. 6. An IC package as described in any of claims 1-5, wherein the plurality of UBM interconnects further includes a third UBM interconnect; and further includes a second bump interconnect coupled to the second UBM interconnect; wherein the seed layer couples the third UBM interconnect to the second UBM interconnect to couple the second bump interconnect to the second UBM interconnect and the bump interconnect. 7. An IC package as described in any of claims 1-6, wherein: the plurality of UBM interconnects have interconnect bump spacing; and the second UBM interconnect is located in the horizontal direction at a distance from the coupled bump interconnect less than the interconnect bump spacing. 8. An IC package as described in any of claims 1-6, wherein: the plurality of UBM interconnects have interconnect bump spacing; and the second UBM interconnect is located in the horizontal direction at a distance from the coupled bump interconnect greater than the interconnect bump spacing. 9. The IC package of clauses 1-8, wherein the die further includes a power distribution network, the power distribution network including: a ground plane in the BEOL interconnect structure; and a positive power rail in the BEOL interconnect structure. 10. The IC package of clause 9, wherein a second UBM interconnect is coupled to the ground plane of the power distribution network to couple the second UBM interconnect to the ground plane.11. An IC package as described in Clause 9, wherein a second UBM interconnect is coupled to the positive power rail of the power distribution network to couple the second UBM interconnect to the positive power rail. 12. An IC package as described in Clause 9, wherein the die further includes an I / O signal node configured to carry input / output (I / O) signals; and a second UBM interconnect is coupled to the I / O signal node. 13. An IC package as described in any of Clauses 1-12, wherein the die further includes a front-end process (FEOL) structure including a semiconductor device; and a second UBM interconnect is coupled to the semiconductor device via the BEOL interconnect structure. 14. An IC package as described in any of clauses 1-13, further comprising: a package substrate; the die coupled to the package substrate; and a second die comprising: a second BEOL interconnect structure; a plurality of second UBM interconnects, each second UBM interconnect coupled to the second BEOL interconnect structure, the plurality of second UBM interconnects comprising: a third UBM interconnect; and a fourth UBM interconnect, without coupled interconnect bumps; a second raised interconnect bump coupled to the third UBM interconnect; and a second seed layer, the second seed layer coupling the fourth UBM interconnect to the third UBM interconnect to couple the second raised interconnect bump to the fourth UBM interconnect; and a second UBM interconnect coupled to the fourth UBM interconnect. 15. An IC package as described in clause 14, wherein: the die further comprises a first active side and a first passive side; the second die further comprises a second active side and a second passive side; the first active side of the die is coupled to the package substrate; and the second active side of the second die is coupled to the first passive side of the die. 16. The IC package of Clause 15, wherein: the die further includes a vertical interconnect via (through-hole); a second UBM interconnect coupled to the through-hole; and a fourth UBM interconnect coupled to the through-hole. 17. The IC package of Clause 14, wherein: the die is horizontally coupled adjacent to the package substrate to the second die; the die includes a first die-to-die (D2D) bump interconnect region comprising a UBM layer; and the second die includes a second D2D bump interconnect region comprising a second UBM layer.18. An IC package as described in any of Clauses 1-17, which is integrated into a device selected from the group consisting of: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, SIP phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, unmanned aerial vehicles, and multi-rotor aircraft. 19. A method of manufacturing a semiconductor wafer, the method comprising: forming a back-end process (BEOL) interconnect structure on a semiconductor layer; forming a plurality of under-bump metallization (UBM) interconnects, each UBM interconnect coupled to the BEOL interconnect structure, the forming comprising: forming a first under-bump metallization (UBM) interconnect coupled to the BEOL interconnect structure; and forming a second UBM interconnect coupled to the BEOL interconnect structure, wherein the second UBM interconnect does not have coupled interconnect bumps; forming a seed layer coupling the first UBM interconnect to the second UBM interconnect; and forming a raised interconnect bump coupled to the first UBM interconnect, the first UBM interconnect coupling the raised interconnect bump to the second UBM interconnect. 20. The method of claim 19, further comprising: forming the plurality of UBM interconnects at an interconnect bump pitch; and forming the second UBM interconnect at a horizontal distance from the coupled raised interconnect bumps at a distance less than the interconnect bump pitch. 21. The method of claim 19, comprising: forming the plurality of UBM interconnects with interconnect bump spacing; and forming a second UBM interconnect at a horizontal distance from the coupled raised interconnect bumps greater than the interconnect bump spacing. 22. The method of any of claims 19-21, wherein: forming the BEOL interconnect structure comprises: forming at least one BEOL metallization layer, each BEOL metallization layer comprising a plurality of metal interconnects; forming the plurality of UBM interconnects further comprises: coupling each of the plurality of UBM interconnects to a metal interconnect among the plurality of metal interconnects in a BEOL metallization layer of the at least one BEOL metallization layer; and forming the second UBM interconnect further comprises: coupling the second UBM interconnect to a second metal interconnect among the plurality of metal interconnects in the BEOL metallization layer.23. The method of claim 22, wherein the BEOL interconnect structure includes a redistribution layer (RDL), the RDL including a plurality of RDL interconnects; wherein: coupling each of the plurality of UBM interconnects includes: coupling each of the plurality of UBM interconnects to one of the plurality of RDL interconnects in the RDL; and coupling a second UBM interconnect includes: coupling a second UBM interconnect to a second RDL interconnect in the plurality of RDL interconnects. 24. The method of any one of claims 22-23, further comprising: forming a passivation layer adjacent to the BEOL interconnect structure. 25. The method of claim 24, further comprising: forming a plurality of recesses in the passivation layer, each recess adjacent to one of the plurality of metal interconnects in the BEOL metallization layer. 26. The method of Clause 25 further comprises: disposing a UBM layer on the passivation layer and within each of the plurality of recesses such that the UBM layer is coupled to the plurality of metal interconnects adjacent to the plurality of recesses; wherein: a portion of the UBM layer within a first recess of the plurality of recesses forms at least a portion of a first UBM interconnect; and a portion of the UBM layer within a second recess of the plurality of recesses forms at least a portion of a second UBM interconnect. 27. The method of any one of clauses 25-26, further comprising: disposing a seed layer adjacent to the passivation layer and in each of the plurality of grooves such that the seed layer is coupled to the plurality of metal interconnects adjacent to the plurality of grooves; wherein: portions of the seed layer in a first plurality of grooves of the plurality of grooves form at least a portion of the plurality of UBM interconnects; a portion of the seed layer in a first groove of the plurality of grooves forms at least a portion of a first UBM interconnect; and a portion of the seed layer in a second groove of the plurality of grooves forms at least a portion of a second UBM interconnect. 28. The method of claim 27, further comprising: forming a photoresist layer on the seed layer; patterning the photoresist layer to form a plurality of openings, each opening being disposed vertically above a corresponding recess among the plurality of recesses; disposing a metal material in one of the openings in the photoresist layer to form a raised interconnect bump coupled to the seed layer in a first recess among the plurality of recesses; and removing the photoresist layer. 29. The method of claim 28, further comprising: forming a second photoresist layer on the seed layer and the raised interconnect bump; patterning the second photoresist layer to form a second opening in a horizontal direction adjacent to the second recess and not between the first recess and the second recess; removing the seed layer in the second opening; not removing the seed layer coupled to the first UBM interconnect in the first recess and the second UBM interconnect in the second recess; and removing the second photoresist layer.30. The method of Clause 29 further includes: reflowing the BEOL interconnect structure to form solder bumps on the raised interconnect bumps. 100: Integrated Circuit IC Package 102: Die Module 104(1): Die 104(2): Die 104(3): Die 106: Package Substrate 108: Bumped Interconnect Bump 110: Vertical Interconnect Path 112: Metallization Layer 114: Metal Interconnect 116: External Interconnect Bump 118: Circuit Board 300: IC Package 302: Die 304: Package Substrate 306: Non-Bumped Interconnect Bump 308(1): Bumped Interconnect Bump 308(2): Bumped Interconnect Bump 308(3): Bumped Interconnect Bump 310: BEOL Interconnect Structure 311: External Interconnect Bump 312(1): External BEOL Metallization Layer 2(2): BEOL metallization layer 312(3): BEOL metallization layer 312(X): BEOL metallization layer 314(1): Metal interconnect 314(2): Metal interconnect 314(3): Metal interconnect 314(X): Metal interconnect 316: Active semiconductor layer 317: Front-end process (FEOL) structure 318: Seed layer 318(1): Seed layer 318(2): Seed layer 318(3): Seed layer 320: Redistribution layer (RDL) interconnect 320(1): RDL interconnect 320(2): RDL interconnect 320(3): RDL interconnect 320(4): RDL interconnect 322: RDL 324: UBM layer 324(1): UBM layer 324(2): UBM layer 324(3): UBM layer 326(1): UBM interconnect 326(2): UBM interconnect 326(3): UBM interconnect 326(4): Second UBM interconnect 328(1): Groove 328(2): Groove 328(3): Groove 328(4): Groove 330(1): Metal pillar 330(2): Metal pillar 330(3): Metal pillar 332(1): Solder joint 332(2): Solder joint 332(3): Solder joint 334: Passivation layer 336: Second passivation layer 500: IC package 502: Die 506 : Non-bump interconnect bump 508(1): Bump interconnect bump 508(2): Bump interconnect bump 508(3): Bump interconnect bump 510: BEOL interconnect structure 512(1): External BEOL metallization layer 512(2): BEOL metallization layer 512(X): BEOL metallization layer 514(1): Metal interconnect 514(X): Metal interconnect 516: Active semiconductor layer 517: Front-end process (FEOL) structure 518: Seed layer 520(1): RDL interconnect 520(2): RDL interconnect 520(3): RDL interconnect 520(4): RDL interconnect 522: RDL 524: UBM layer 526(1): UBM interconnect 526(2): UBM interconnect526(3): UBM Interconnect 526(4): Second UBM Interconnect 528(1): Groove 528(2): Groove 528(3): Groove 528(4): Groove 530(1): Metal Pillar 530(2): Metal Pillar 530(3): Metal Pillar 532(1): Solder Joint 532(2): Solder Joint 532(3): Solder Joint 534: Passivation Layer 536: Passivation Layer 600: IC Package 602: Die 604: Package Substrate 608: Bump Interconnect Bump 610: Bump Interconnect Bump 700: IC Package 702: Die 704: Package Substrate 706: Non-Bump Interconnect Bump 708: Bump Interconnect Bump 710: Bump Interconnect Bump Block 712: Non-bump interconnect bump 800: IC package 802: Die 804: Package substrate 806: Non-bump interconnect bump 806(1): Non-bump interconnect bump 806(2): Non-bump interconnect bump 806(3): Non-bump interconnect bump 806(4): Non-bump interconnect bump 806(5): Non-bump interconnect bump 806(6): Non-bump interconnect bump 806(7): Non-bump interconnect bump 808: Bump interconnect bump 808(1): Bump interconnect bump 808(2): Bump interconnect bump 808(3): Bump interconnect bump 808(4): Bump interconnect bump 808(5): Bump interconnect bump 808(6): Bump Interconnect bump 808(7): bump Interconnect bump 810: region 810(1): region 810(2): region 810(3): region 810(4): region 810(5): region 810(6): region 810(7): region 900: manufacturing process 902: block 904: block 906: block 908: block 910: block 912: block 1000: manufacturing process 1002: block 1004: block 1006: block 1008: block 1010: block 1012: block 1014: block 1016: block 1018: block 1100A: manufacturing stage 1100B: manufacturing stage 1100C : Manufacturing stage 1100D: Manufacturing stage 1100E: Manufacturing stage 1100F: Manufacturing stage 1100G: Manufacturing stage 1100H: Manufacturing stage 1100I: Manufacturing stage 1102: Photoresist layer 1104(2): Patterned opening 1104(3): Patterned opening 1108: Second photoresist layer 1110: Patterned opening 1200: Stacked die IC package 1202(1): First die 1202(2): Second die 1204: Package substrate 1206(1): Non-bump interconnect bump 1206(2): Non-bump interconnect bump 1208(1): Bump interconnect bump 1208(2): Bump interconnect bump1210(1): BEOL interconnect structure 1210(2): BEOL interconnect structure 1216(1): Active semiconductor layer 1216(2): Active semiconductor layer 1218(1): Seed layer 1218(2): Seed layer 1224(1): First RDL layer 1224(2): Second RDL layer 1226(1): UBM interconnect 1226(2): UBM interconnect 1240(1): First active side 1240(2): Second active side 1242(1): First passive side 1242(2): Second passive side 1244: Through-hole 1300: Split die IC package 1302(1): Split die / first die 1302(2): Split die / second die 1304: Package substrate 1306(1): Non-bump interconnect bump 1306(2): Non-bump interconnect bump 1308(1): Bump interconnect bump 1308(2): Bump interconnect bump 1310(1): BEOL interconnect structure 1310(2): BEOL interconnect structure 1318(1): Seed layer 1318(2): Seed layer 1326(1): UBM interconnect 1326(2): UBM interconnect 1346(1): D2D bump interconnect region 1346(2): D2D bump interconnect region 1400: System 1402: IC package 1402(1): IC package 1402(2): IC package 1402(3): IC package 1402(4): IC package 1402(5): IC package 1404: IC 1406: System-on-a-Chip (SoC) 1408: Central Processing Unit (CPU) 1410: Processor 1412: Cache Memory 1414: System Bus 1416: Memory Controller 1418: Memory System 1420: Memory Controller 1422: Input Device 1424: Output Device 1426: Network Peripheral Device 1428: Display Controller 1430: Network 1432: Display 1434: Video Processor 1500: Wireless Communication Device 1502: IC 1503: IC Package 1504: Transceiver 1506: Data Processor 1508: Transmitter 1510: Receiver 1512(1): Digital-to-Analog Converter 1512(2): Digital-to-Analog Converter (DAC) 1514(1): Low-Pass Filter 1514(2): Low-Pass Filter 1516(1): Amplifier (AMP) 1516(2): Amplifier (AMP) 1518: Up-converter; 1520(1): Mixer; 1520(2): Mixer; 1522: Transmit (TX) Local Oscillator (LO) Signal Generator; 1524: Up-converted signal; 1526: Filter; 1528: Power Amplifier (PA)1530: Duplexer / Switch 1532: Antenna 1534: Low Noise Amplifier (LNA) 1536: Filter 1538(1): Down-conversion Mixer 1538(2): Down-conversion Mixer 1540: RX LO Signal Generator 1542(1): AMP 1542(2): AMP 1544(1): Low-pass Filter 1544(2): Low-pass Filter 1546(1): Analog-to-Digital Converter (ADC) 1546(2): Analog-to-Digital Converter (ADC) 1548: TX Phase-Locked Loop (PLL) Circuit 1550: RX PLL Circuit D1: Distance P 1: Interconnect bump spacing P 2: Interconnect bump spacing P 3: Interconnect bump spacing P 4: Interconnect bump spacing P 5: Interconnect bump spacing P 6: Interconnect bump spacing P 7: Interconnect bump spacing Figure 1 is a cross-sectional side view of an exemplary integrated circuit (IC) package including a semiconductor die ("die") module, wherein stacked dies are coupled to a package substrate via interconnect bumps formed on the dies. Figure 2 is a top view of the bottom die of the IC package die module in Figure 1; Figures 3A and 3B are cross-sectional side views of an exemplary IC package including a die that includes bumped interconnect bumps coupled to non-bumped interconnect bumps to provide additional signal paths between the bumped interconnect bumps and the back-end process (BEOL) interconnect structure of the die. Figure 4 is a top view of an exemplary IC package including bumped interconnect bumps that couple the die in Figures 3A and 3B to the package substrate, wherein the die includes a seed layer that couples the bumped interconnect bumps to the non-bumped interconnect bumps to provide an additional signal path between the bumped interconnect bumps and the BEOL interconnect structure of the die; Figure 5 is a cross-sectional side view of another exemplary IC package including a die, which includes a seed layer that couples raised interconnect bumps to non-raised interconnect bumps to provide an additional signal path between the raised interconnect bumps and the BEOL interconnect structure of the die, wherein the non-raised interconnect bumps are located at a distance from the interconnect bumps greater than the interconnect bump pitch. Figure 6 is a top view of an exemplary IC package including a die, the die including raised interconnect bumps that couple the die to the package substrate and the die not including non-raised interconnect bumps. Figure 7 is a top view of another exemplary IC package including a die, the die including raised interconnect bumps coupling the die to the package substrate, and wherein the die includes a seed layer coupling the raised interconnect bumps to the non-raised interconnect bumps to provide an additional signal path between the raised interconnect bumps and the BEOL interconnect structure of the die. Figure 8A is a top view of another exemplary IC package including raised interconnect bumps that couple a die to a package substrate, wherein the die includes a plurality of regions containing non-raised interconnect bumps coupled to the raised interconnect bumps; Figure 8B is a close-up bottom view of a region in an exemplary grain in Figure 8A; Figure 9 is a flowchart illustrating an exemplary process for manufacturing a die for IC packaging, wherein the die includes a seed layer for coupling bumped interconnects to non-bumped interconnects, and the die includes, but is not limited to, the dies in Figures 3A to 8B. Figures 10A to 10C are flowcharts illustrating another exemplary process for manufacturing a die for an IC package, wherein the die includes a seed layer forming non-bump interconnect bumps coupled to bump interconnect bumps, and the die includes, but is not limited to, the dies in Figures 3A to 8B. Figures 11A to 11I illustrate exemplary manufacturing stages of the processes shown in Figures 10A to 10C; Figure 12 is a side view of an exemplary stacked die IC package including multiple stacked dies, wherein the die includes a seed layer that couples bumped interconnects to non-bumped interconnects, and the die includes, but is not limited to, the dies in Figures 3A to 8B and Figures 11A to 11I. Figure 13 is a top view of an exemplary split die IC package including a split die coupled to a package substrate, wherein the die includes a seed layer of non-bump interconnect bumps that couple bump interconnect bumps to the die’s UBM layer, and the die includes, but is not limited to, the dies in Figures 3A to 8B and Figures 11A to 11I. Figure 14 is a block diagram of an exemplary processor-based system that may be provided in one or more IC packages, each IC package employing dies coupled to a package substrate, wherein the dies may include a seed layer coupling bumped interconnects to non-bumped interconnects, the dies including but not limited to the exemplary dies in Figures 3A to 8B and Figures 11A to 13 and the exemplary manufacturing process according to Figures 9 to 11I; and Figure 15 is a block diagram of an exemplary wireless communication device including radio frequency (RF) components provided in one or more IC packages, each IC package employing dies coupled to a package substrate, wherein the dies may include a seed layer for coupling raised interconnect bumps to non-raised interconnect bumps, the dies including but not limited to the exemplary dies in Figures 3A to 8B and Figures 11A to 13 and the exemplary manufacturing process according to Figures 9 to 11I. Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None. 300: IC package 302: Grain 306: Non-protruding interconnect bump 308(1): Bump Interconnect Bump 308(2): Bump Interconnect Bump 308(3): Bump Interconnect Bump 310: BEOL interconnect structure 312(1): External BEOL metallization layer 314(1): Metal interconnect 318: Use of seed layer 320: Redistribution Layer (RDL) Interconnect 320(1): RDL Interconnection 320(2): RDL Interconnection 320(3): RDL Interconnection 322:RDL 324: UBM layer 326(1): UBM Interconnect 326(2): UBM Interconnect 326(3): UBM Interconnect 326(4): Second UBM Interconnect 328(1): Groove 328(2): Groove 328(3): Groove 328(4): Groove 330(1): Metal column 330(2): Metal column 330(3): Metal column 332(1): Solder joint 332(2): Solder joint 332(3): Solder joint 334: Passivation layer 336: Second passivation layer

Claims

1. An integrated circuit (IC) package, comprising: A die comprising: a back-end process interconnect (BEOL) structure; a plurality of under-bump metallization (UBM) interconnects, each UBM interconnect coupled to the BEOL interconnect structure, the plurality of UBM interconnects comprising: a first UBM interconnect; and a second UBM interconnect without a coupled interconnect bump; and a raised interconnect bump coupled to the first UBM interconnect; wherein the die further comprises: a seed layer that couples the first UBM interconnect to the second UBM interconnect to couple the raised interconnect bump to the second UBM interconnect; wherein the BEOL interconnect structure comprises a metallization layer comprising: a plurality of first metal interconnects, the plurality of first metal interconnects comprising a plurality of metal pads, each first metal interconnect coupled to one of the plurality of UBM interconnects; and a second metal interconnect coupled to the second UBM interconnect.

2. The IC package as described in claim 1, wherein the seed layer further includes the first UBM interconnect and the second UBM interconnect.

3. The IC package as claimed in claim 1, wherein the metallization layer includes a redistribution layer (RDL), the RDL including a plurality of first RDL interconnects and a second RDL interconnect; the plurality of first metal interconnects including the plurality of first RDL interconnects, each first RDL interconnect coupled to a UBM interconnect in the plurality of UBM interconnects; and the second metal interconnect including the second RDL interconnect.

4. The IC package as claimed in claim 1, wherein the plurality of UBM interconnects further includes a third UBM interconnect; and further includes a second bump interconnect coupled to the second UBM interconnect; wherein the seed layer couples the third UBM interconnect to the second UBM interconnect to couple the second bump interconnect to the second UBM interconnect and the bump interconnect.

5. The IC package as described in claim 1, wherein: The plurality of UBM interconnects have an interconnect bump pitch; and the second UBM interconnect is located in a horizontal direction at a distance from the coupled protruding interconnect bumps that is smaller than the interconnect bump pitch.

6. The IC package as described in claim 1, wherein: The plurality of UBM interconnects have an interconnect bump pitch; and the second UBM interconnect is located in a horizontal direction at a distance from the coupled protruding interconnect bumps that is greater than the interconnect bump pitch.

7. The IC package as described in claim 1, wherein the die further includes a power distribution network, the power distribution network comprising: A ground plane is present in this BEOL interconnect structure; And a positive power rail in this BEOL interconnect structure.

8. The IC package as described in claim 7, wherein the second UBM interconnect is coupled to the ground plane of the power distribution network to couple the second UBM interconnect to the ground plane.

9. The IC package as described in claim 7, wherein the second UBM interconnect is coupled to the positive power rail of the power distribution network to couple the second UBM interconnect to the positive power rail.

10. The IC package as claimed in claim 7, wherein the die further includes an I / O signal node configured to carry an input / output (I / O) signal; the second UBM interconnect is coupled to an I / O signal node.

11. The IC package as claimed in claim 1, wherein the die further includes a front-end process (FEOL) structure, the FEOL structure including a semiconductor device; the second UBM interconnect is coupled to the semiconductor device via the BEOL interconnect structure.

12. The IC package as described in claim 1, further comprising: One packaging substrate; The die is coupled to the packaging substrate; The second die includes: a second BEOL interconnect structure; a plurality of second UBM interconnects, each second UBM interconnect coupled to the second BEOL interconnect structure, the plurality of second UBM interconnects including: a third UBM interconnect; and a fourth UBM interconnect without a coupled interconnect bump; a second raised interconnect bump coupled to the third UBM interconnect; and a second seed layer that couples the fourth UBM interconnect to the third UBM interconnect to couple the second raised interconnect bump to the fourth UBM interconnect; the second UBM interconnect coupled to the fourth UBM interconnect.

13. The IC package as described in claim 12, wherein: The die further includes a first active side and a first passive side; the second die further includes a second active side and a second passive side; the first active side of the die is coupled to the packaging substrate; and the second active side of the second die is coupled to the first passive side of the die.

14. The IC package as described in claim 13, wherein: The die further includes a vertical interconnect via (via); the second UBM interconnect is coupled to the via; and the fourth UBM interconnect is coupled to the via.

15. The IC package as described in claim 12, wherein: The die is coupled to the package substrate adjacent to the second die in a horizontal direction; the die includes a first die-to-die (D2D) bump interconnect region containing a UBM layer; and the second die includes a second D2D bump interconnect region containing a second UBM layer.

16. The IC package as described in claim 1, wherein the IC package is integrated into a device selected from the group consisting of: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a Global Positioning System (GPS) device, a mobile phone, a cellular phone, a smartphone, a SIP phone, a tablet device, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multi-rotor aircraft.

17. A method for manufacturing a semiconductor wafer, the method comprising the following steps: A back-end process interconnect (BEOL) structure is formed on a semiconductor layer; Forming a plurality of under-bump metallization (UBM) interconnects, each UBM interconnect coupled to the BEOL interconnect structure, the formation comprising: forming a first under-bump metallization (UBM) interconnect coupled to the BEOL interconnect structure; and forming a second UBM interconnect coupled to the BEOL interconnect structure, wherein the second UBM interconnect does not have a coupled interconnect bump; forming a seed layer that couples the first UBM interconnect to the second UBM interconnect; and forming a raised interconnect bump coupled to the first UBM interconnect, the first UBM interconnect coupling the raised interconnect bump to the second UBM interconnect; wherein the BEOL interconnect structure includes a metallization layer, the metallization layer including: a plurality of first metal interconnects, the plurality of first metal interconnects including a plurality of metal pads, each first metal interconnect coupled to one of the plurality of UBM interconnects; and a second metal interconnect coupled to the second UBM interconnect.

18. The method as claimed in claim 17, comprising the steps of: forming the plurality of UBM interconnects with an interconnect bump pitch; and forming the second UBM interconnect at a distance in a horizontal direction from the coupled raised interconnect bumps less than the interconnect bump pitch.

19. The method as claimed in claim 17, comprising the steps of: forming the plurality of UBM interconnects with an interconnect bump pitch; and forming the second UBM interconnect at a distance in a horizontal direction from the coupled raised interconnect bumps greater than the interconnect bump pitch.

20. The method as described in claim 17, wherein the BEOL interconnect structure includes a redistribution layer (RDL), the RDL including a plurality of RDL interconnects; wherein: Coupling each of the plurality of UBM interconnects includes: coupling each of the plurality of UBM interconnects to an RDL interconnect among the plurality of RDL interconnects in the RDL; and coupling the second UBM interconnect includes: coupling the second UBM interconnect to a second RDL interconnect among the plurality of RDL interconnects.

21. The method as described in claim 17 further includes the step of forming a passivation layer adjacent to the BEOL interconnect structure.

22. The method as claimed in claim 21 further includes the step of forming a plurality of grooves in the passivation layer, each groove being adjacent to one of the plurality of metal interconnects in the BEOL metallization layer.

23. The method of claim 22, further comprising the step of: providing a UBM layer on the passivation layer and within each of the plurality of recesses such that the UBM layer is coupled to the plurality of metal interconnects adjacent to the plurality of recesses; wherein: The UBM layer forms at least a portion of the first UBM interconnect within a first groove among the plurality of grooves; and the UBM layer forms at least a portion of the second UBM interconnect within a second groove among the plurality of grooves.

24. The method of claim 22, further comprising the step of: disposing a seed layer adjacent to the passivation layer and in each of the plurality of grooves such that the seed layer is coupled to the plurality of metal interconnects adjacent to the plurality of grooves; wherein: The portion of the seed layer within a first plurality of grooves forms at least a portion of the plurality of UBM interconnects; a portion of the seed layer within a first groove within the plurality of grooves forms at least a portion of the first UBM interconnect; and a portion of the seed layer within a second groove within the plurality of grooves forms at least a portion of the second UBM interconnect.

25. The method of claim 24, further comprising the steps of: forming a photoresist layer on the seed layer; patterning the photoresist layer to form a plurality of openings, each opening being disposed in a vertical direction above a corresponding groove among the plurality of grooves; disposing a metal material in one of the openings in the photoresist layer to form a raised interconnect bump coupled to the seed layer in a first groove among the plurality of grooves; and removing the photoresist layer.

26. The method of claim 25, further comprising the steps of: forming a second photoresist layer on the seed layer and the bump interconnect; patterning the second photoresist layer to form a second opening in a horizontal direction adjacent to the second groove and not between the first groove and the second groove; removing the seed layer in the second opening; not removing the seed layer coupling the first UBM interconnect in the first groove and the second UBM interconnect in the second groove; and removing the second photoresist layer.

27. The method as described in claim 26, further comprising: The BEOL interconnect structure is reflowed to form a solder bump on the raised interconnect bump.

28. An integrated circuit (IC) package, comprising: A die comprising: a metallization layer comprising: a plurality of first metal interconnects, the plurality of first metal interconnects including a plurality of metal pads, each first metal interconnect coupled to a UBM interconnect in a plurality of under-bump metallization (UBM) interconnects; and a second metal interconnect coupled to a second UBM interconnect; the plurality of UBM interconnects, each UBM interconnect coupled to the metallization layer, the plurality of UBM interconnects including: a first UBM interconnect; and the second UBM interconnect, not having a coupled interconnect bump; and a raised interconnect bump coupled to the first UBM interconnect; wherein the die further comprises: a seed layer, the seed layer coupling the first UBM interconnect to the second UBM interconnect to couple the raised interconnect bump to the second UBM interconnect.

29. The IC package as described in claim 28, wherein: The plurality of UBM interconnects have an interconnect bump pitch; and the second UBM interconnect is located in a horizontal direction at a distance from the coupled protruding interconnect bumps that is greater than the interconnect bump pitch.

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