Apparatus for memory module, apparatus comprising memory module and method for operating memory module

Abstract

In one embodiment, an apparatus including a memory module is described. The memory module may include a plurality of memory layers and a register clock driver (RCD) coupled to one of the plurality of memory layers. The RCD may include a receiver configured to receive a chip select signal for selecting one or more memory layers. The RCD may further include logic circuitry coupled to the receiver and an output driver coupled to the logic circuitry. The RCD may further include a feedback circuitry configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuitry and a second sampling point between the logic circuitry and the output driver.

Description

[Previous Technology]

[0001] This invention relates to memory devices. More specifically, in some embodiments, this invention relates to a register clock driver for a dual data rate (DDR) random access memory (RAM) module.

[0002] Power consumption and efficiency are becoming increasingly important in both stationary and portable computing devices to reduce electricity costs and ensure longer battery life. Portable computing devices, such as laptops, notebooks, portable e-wizards, or other computing devices that may rely on battery power, typically have stringent requirements for power consumption and efficiency. In such devices, it is typical to optimize each component to reduce power consumption. In one application, dual data rate generation 5 (DDR5) memory modules can be used in these computing devices. Compared to its predecessors (such as DDR3 and DDR4 memory modules), DDR5 memory modules reduce power consumption, increase bandwidth, and improve efficiency (e.g., faster speeds). In another application, DDR5 memory modules can be coupled with onboard voltage regulators to achieve even higher speeds. [Summary of the Invention]

[0003] In this embodiment, a device in a memory module is generally described. The device may include a receiver configured to receive a chip select signal for selecting one or more memory layers of the memory module. The device may further include logic circuitry coupled to the receiver. The device may further include an output driver coupled to the logic circuitry. The logic circuitry may be configured to decode the chip select signal to generate an output signal for selecting one or more memory layers of the memory module. The output driver may be configured to use the output signal to select one or more memory layers. The device may further include feedback circuitry configured to sample the chip select signal at one or more of a first sampling point between the receiver and the logic circuitry and a second sampling point between the logic circuitry and the output driver.

[0004] In another embodiment, a device including a memory module is generally described. The memory module may include a plurality of memory layers and a register clock driver (RCD). The RCD may be coupled to the plurality of memory layers. The RCD may include a receiver configured to receive a chip select signal for selecting one or more memory layers among the plurality of memory layers. The RCD may further include logic circuitry coupled to the receiver. The RCD may further include an output driver coupled to the logic circuitry. The logic circuitry may be configured to decode the chip select signal to generate an output signal for selecting one or more memory layers of the memory module. The output driver may be configured to use the output signal to select one or more memory layers. The RCD may further include feedback circuitry configured to sample the chip select signal at one or more of a first sampling point between the receiver and the logic circuitry and a second sampling point between the logic circuitry and the output driver.

[0005] In another embodiment, a method for operating a memory module is generally described. The method may include receiving a chip select signal for selecting one or more memory layers of the memory module by a register clock driver (RCD) of the memory module. The method may include sampling the chip select signal from one or more of the following: a first sampling point between the RCD's receiver and the RCD's logic circuitry, and a second sampling point between the RCD's logic circuitry and the RCD's output driver.

[0006] The foregoing overview is illustrative only and is not intended to be limiting in any way. In addition to the illustrative examples, embodiments, and features described above, other examples, embodiments, and features will become apparent from the accompanying drawings and the following detailed description. In the drawings, the same reference numerals indicate the same or functionally similar elements.

Implementation Method

[0013] A register clock driver (RCD) is a device used on memory modules such as DDR5 memory modules. The RCD buffers the command address (CA) bus, chip select signal, and clock signal between the host controller and the DDR5 memory module. When the RCD is used to reduce the load of a dual-row memory module (LRDIMM), it can also establish a buffer communication (BCOM) bus to control the LRDIMM's data buffer. LRDIMMs can support relatively higher densities than other memory modules and include memory buffer chips. In one case, LRDIMMs can be used, for example, in servers, and the memory buffer chips of the LRDIMM can reduce and minimize the load on the server's memory bus. For example, LRDIMMs can use memory buffer chips to combine the electrical load of layers on the LRDIMM into a single electrical load, thereby allowing them to have up to, for example, eight layers on a single DIMM module. Therefore, using LRDIMMs allows the system configuration to have the maximum possible memory footprint.

[0014] However, the use of memory buffer chips in LRDIMMs, instead of temporary registers like those in other DIMMs, can negatively impact signal integrity, especially as the speed of DDR5 memory modules increases (e.g., higher speeds result in worse signal integrity). In one example, the disclosed embodiments may integrate feedback circuitry with hardware components to form a feedback path for the chip select signal of the RCD. This feedback path can drive the chip select signal of the RCD back to the host controller for debugging, testing, or training. Furthermore, in one embodiment, the feedback path for the chip select signal may utilize a portion of another existing feedback path reserved for other internal signals of the RCD that can be fed back to the host controller. Additionally, the feedback circuitry integrated into the RCD can sample the chip select signal from different locations within the RCD, allowing the host controller to determine which component or processing stage of the RCD might be causing a problem. Furthermore, integrating the feedback circuitry into the RCD allows the RCD to undergo chip select signal testing at any time (including during normal operation of the memory module). By being able to test the chip select signal at any time, the signal integrity of the chip select signal can be maintained, thereby improving the functionality of the memory module.

[0015] Figures 1 and 2 illustrate an example embodiment of the memory system 10. The memory system 10 includes memory modules 201, 202...20N, connector 70, and memory controller 80. The memory modules are also collectively referred to herein or individually as memory module 20.

[0016] Referring to FIG1, in one example embodiment, memory module 20 may include dual-row memory modules (DIMMs). In some embodiments, memory module 20 may be implemented as a dual data rate generation 5 (DDR5) SDRAM module. Although described and illustrated herein as components having a particular type, configuration, and number, in other embodiments, memory module 20 may include any other type, configuration, or number of components.

[0017] Example memory module 20 includes circuit blocks 301, 302, 303, 304, 305...30P-4, 30P-3, 30P-2, 30P-1 and 30P, circuit blocks 401, 402,...40M-1 and 40M, a register clock driver (RCD) 50, a PMIC 60, a connector 70, and any other blocks, circuits, pins, connectors, traces or other components typically found in a memory module. In some embodiments, circuit blocks 301, 302, 303, 304, 305...30P-4, 30P-3, 30P-2, 30P-1 and 30P may be configured as data buffers and will also be collectively or individually referred to herein as data buffer 30. In some embodiments, circuit blocks 401, 402, ... 40M-1 and 40M may be configured as memory devices and will also be collectively or individually referred to herein as memory device 40. Although described herein as data buffer 30 and memory device 40, circuit blocks 30 and 40 may also be used by memory module 20 for any other purpose.

[0018] In some embodiments, the data buffer 30 and memory device 40 include a synchronous dynamic random access memory (SDRAM) device, a chip, or a module. In some embodiments, the data buffer 30 and memory device 40 may also include, or alternatively include, any other type of memory device, such as SRAM, DRAM, MROM, PROM, EPROM, and EEPROM. The data buffer 30, memory device 40, or both may be physically located on one or both sides (e.g., the front and back) of the memory module 20.

[0019] The PMIC 60 is configured to perform power management on the memory module 20. For example, the PMIC 60 may be configured to scale up or down voltage, perform DC-DC conversion, or perform other similar power management operations. In some embodiments, the PMIC 60 may include a low dropout regulator (LDO), a DC-DC converter such as a buck or boost converter, pulse frequency modulation (PFM), pulse width modulation (PWM), a power MOSFET, an instantaneous clock (RTC), or any other circuitry typically found in a PMIC.

[0020] Connector 70 may include pins, traces, or other connections configured to connect memory module 20 to other components of the computing system, such as memory controller 80, motherboard, or other components. In some embodiments, connector 70 may include, for example, a 288-pin configuration or any other pin configuration.

[0021] In some embodiments, the memory module 20 includes a connector 70. In other embodiments, the motherboard of the computing device, the memory controller 80, or any other component includes the connector 70. In another embodiment, one or more of the connectors 70 may be part of the memory module 20, and one or more of the connectors 70 may be part of the motherboard of the computing device, the memory controller 80, or other components.

[0022] The memory module 20 may be connected, for example, to the motherboard of a computing device, the memory controller 80, or other components via a connector 70 to transfer data between components of the computing device and the memory module 20. For example, in an embodiment implementing UDIMM, the connector 70 may include a 64-bit bus, a 72-bit bus, or a bus containing any other number of bits.

[0023] Memory module 20 is shown as a memory controller 80 connected to a computing device. In an exemplary embodiment, the memory controller 80 may be implemented as a component of the computer motherboard or motherboard of the computing device, for example, on the northbridge of the motherboard. In another embodiment, the memory controller 80 may be implemented as a component of the microprocessor of the computing device. In yet another embodiment, the memory controller 80 may be implemented as a component of the central processing unit (CPU) of the computing device. In other embodiments, the memory controller 80 may be implemented as part of any other component of the computing device.

[0024] In some embodiments, the memory module 20 is implemented as a DDR5 SDRAM memory module. As an example, the memory module 20 may contain a memory module density of 128 gigabits (GB), 512 GB, 1 terabyte (TB), or higher per module. The memory module 20 may operate at a frequency of about 1.2 to about 3.2 GHz and a data rate range of about 3.2 GT / s to about 4.6 GT / s, and in some cases, at a data rate of up to about 8 GT / s or higher. In some embodiments, the memory module 20 may alternatively contain smaller or larger densities, operate at lower or higher frequencies, and operate at lower or higher data rates.

[0025] Referring now to FIG. 2, a block diagram of the example memory module 20 of FIG. 1 is shown. Memory module 20 may represent memory modules 20A to 20N. Memory module 20 is shown communicating with memory controller 80. Memory controller 80 is shown as part of circuitry 90, such as a motherboard, mainboard, or other component of a computing device communicating with memory module 20.

[0026] The memory module 20 includes one or more groups of circuits 221, 222, 223, 224, 225...22Q-4, 22Q-3, 22Q-2, 22Q-1, and 22Q, which are also collectively referred to herein or individually as data paths 22 of the memory module 20. In the illustrated example, the memory module 20 may include five data paths 22 (e.g., data paths 221, 222, 223, 224, and 225) on one side of the RCD 50 and five data paths 22 (e.g., data paths 22Q-4, 22Q-3, 22Q-2, 22Q-1, and 22Q) on the other side of the RCD 50. In other embodiments, the memory module 20 may include other configurations with more or fewer data paths 22 on each side of the RCD 50.

[0027] Data path 22 may each contain individual memory channels 421, 422, 423, 424, 425...42R-4, 42R-3, 42R-2, 42R-1 and 42R, which are also collectively referred to herein and individually as memory channels 42. Each memory channel 42 may contain one or more of the memory devices 40. For example, memory channel 421 may contain memory devices 401 to 40S, while memory channel 42R may contain memory devices 40T to 40M.

[0028] The memory controller 80 is configured to generate various signals, including clock signals (CLK), control signals (ADDR and CMD), and command signals. One or more of the CLK, ADDR, and CMD signals can be provided to the RCD 50, for example, via one or more buses 23.

[0029] Signals from the memory controller 80 can also be transmitted from the memory controller 80 to the PMIC 60 via bus 24, which is also referred to herein as the host interface bus 24. In some embodiments, the host interface bus 24 is bidirectional and configured to communicate commands or other data between the PMIC 60 and the memory controller 80 or other components of the memory module 20. The host interface bus 24 may implement the I2C protocol, the I3C protocol, or any other protocol.

[0030] The data bus 72 may be connected between the memory controller 80 and the data path 22 (e.g., having a data buffer 30), and may be included in the connector 70 between the memory controller 80 and the data path 22, such as traces, pins and other connectors.

[0031] The memory controller 80 may generate or receive data signals (e.g., DQa to DQn) and data strobe signals (e.g., DQSa to DQSn), which may be presented to or received from the data bus 72. A portion of the signals DQa to DQn and DQSa to DQSn may be presented to or received from the respective data path 22. In the illustrated example, each of the signals DQa to DQn may have a corresponding signal DQSa to DQSn. In some embodiments, one DQS signal may strobe multiple DQ signals; for example, in some embodiments, one DQS signal is used for four DQ signals.

[0032] RCD 50 is configured to communicate with memory controller 80, data buffer 30, memory channel 42, and PMIC 60. RCD 50 is configured to decode instructions, such as control words, received from memory controller 80. For example, RCD 50 may be configured to receive and decode register command words (RCW). In another example, RCD 50 may be configured to receive and decode buffer control words (BCW). RCD 50 is configured to train one or more of the command and address lines between data buffer 30, memory device 40, and RCD 50 and memory controller 80. For example, RCW may flow from memory controller 80 to RCD 50 and be used to configure RCD 50.

[0033] In some embodiments, RCD 50 may implement a command / address register, such as a 32-bit 1:2 command / address register. RCD 50 may support full-speed buses, such as a one-way buffered communication (BCOM) bus between RCD 50 and data buffer 30. In some embodiments, RCD 50 may implement automatic impedance calibration, command / address parity checking, control register RCW readback, or one or more serial buses such as a 1 MHz internal integrated circuit (I2C) bus and a 12.5 MHz internal integrated circuit (I3C) bus. The inputs of RCD 50 may be pseudo-differential using external and internal voltages. The clock output, command / address output, control output, and data buffer control output of RCD 50 may be enabled in groups and driven independently at different intensities.

[0034] RCD 50 is configured to receive CLK, ADDR, and CMD signals or other signals (such as RCW and BCW) from memory controller 80, and is configured to generate corresponding output signals based on the CLK, ADDR, and CMD signals using various digital logic components. For example, RCD 50 is configured to generate corresponding signals, such as CLK', ADDR', and CMD' signals, based on the received CLK, ADDR, and CMD signals. The CLK', ADDR', and CMD' signals can be presented to memory channel 42. For example, the CLK' signal can be transmitted from RCD 50 to memory channel 42 on common bus 25, and the ADDR' and CMD' signals can be transmitted from RCD 50 to memory channel 42 on common bus 26. RCD 50 is also configured to generate one or more data buffer control (DBC) signals, such signals being transmitted, for example, on common bus 27 to data buffer 30, which is also referred to herein as data buffer control bus 27.

[0035] Data buffer 30 is configured to receive commands and data from data buffer control bus 27, and to generate data, receive data from data bus 72, or transmit data to data bus 72. Each data path 22 also includes a bus 28 between its data buffer 30 and memory channel 42, which is configured to carry data between the data buffer 30 and memory channel 42. For example, as shown in FIG2, data path 22 1 includes a bus 28 between data buffer 30 1 and memory channel 42 1.

[0036] The data buffer 30 is configured to buffer the data on buses 72 and 28 for write operations (e.g., data transfer from memory controller 80 to the corresponding memory channel 42) and read operations (e.g., data transfer from the corresponding memory channel 42 to memory controller 80).

[0037] In some embodiments, data buffer 30 exchanges data with memory device 40 via bus 28 in small units (e.g., 4-bit halves). In other embodiments, larger or smaller data transfers may be used instead. In some cases, memory device 40 may be configured as multiple sets, such as two sets. For example, in a two-set / two-memory-device embodiment, such as memory devices 40 1 and 40 2, each set may contain a single memory device 40 (e.g., 40 1 or 40 2), wherein each memory device 40 is connected to a respective data buffer 30 by a top half-byte and a bottom half-byte. In a two-set / four-memory-device embodiment, each set may contain two memory devices 40. A first set may be connected to a respective data buffer 30 by a top half-byte, and a second set may be connected to a respective data buffer 30 by a bottom half-byte. In a two-set / eight-memory-device embodiment, each set may contain four memory devices 40. A first set of four memory devices 40 can be connected to individual data buffers 30 via upper halves, and a second set of four memory devices can be connected to individual data buffers 30 via lower halves. Alternatively, other numbers of sets, other numbers of memory devices per set, and other data unit sizes can be used.

[0038] The memory module 20 may also include an interface 29 configured to enable communication between the RCD 50 and the PMIC 60. For example, the interface 29 may be used as part of a temporary register clock driver / power management integrated circuit interface, such as an RCD-PMIC interface. The interface 29 is configured to support one or more signals or connections that may be bidirectional or unidirectional.

[0039] FIG3 is a block diagram of an example 300 of a register clock driver with a chip select feedback circuit according to an embodiment of the present invention. System 300 may include a host device 302 and a memory module 304. Memory module 304 may be one of memory modules 20, and host device 302 may be the memory controller 80 shown in FIG1 and FIG2. In one or more embodiments, host device 302 may be, for example, a part of a circuit, a motherboard, a motherboard, a processor or processor core, a central processing unit (CPU), or other components of a computing device that communicates with memory module 304. System 300 may be implemented in a computing device such as a desktop computer, a laptop computer, a server, a benchmark device, etc. In an embodiment, memory module 304 may be, for example, a dual-row memory module (DIMM). In some embodiments, memory module 304 may be implemented as a dual data rate fifth generation (DDR5) load-reduced dual row memory module (LRDIMM) including synchronous dynamic random access memory (SDRAM) devices.

[0040] Memory module 304 may include a register clock driver (RCD) 306 and a plurality of memory levels. In the example shown in FIG3, memory module 304 may include four memory levels labeled as level 0, level 1, level 2, and level 3. In one or more embodiments, memory module 304 may include fewer than four levels or more than four levels up to, for example, eight levels. In some embodiments, RCD 306 may implement a command / address register and may support a one-way buffer communication (BCOM) bus between RCD 306 and data buffers in memory module 304.

[0041] RCD 306 can be configured to receive a plurality of input signals 308 from host device 302. Input signals 308 may include control signals, such as address signals (e.g., memory bank address signals, column address signals, row address signals, gated row address strobe signals, chip select signals, and peer signals), command signals (e.g., recharge, precharge, etc.), and data signals (e.g., data to be written to the memory device in memory module 304).

[0042] The RCD 306 can be configured to operate in both loopback and pass-through modes. The pass-through mode allows the RCD 306 to decode the input signal 308 and, based on the input signal 308, continue reading and / or writing to memory levels within the memory module 304. In one embodiment, the RCD 306 may include one or more logic circuits configured to receive the input signal 308 and generate a set of output control signals that can be transmitted to appropriate memory devices within the memory module 304. Furthermore, the RCD 306 can be configured to decode instructions from the input signal 308. For example, the RCD 306 can be configured to receive and decode register command words (RCWs) and buffer control words (BCWs) received from the host device 302. The pass-through mode allows the input signal 308 to be processed by the logic circuitry of the RCD 306 and output to one or more memory levels within the memory module 304.

[0043] The loopback mode allows the RCD 306 to feed back samples of one or more signals from the input signal 308 or other internal signals within the RCD 306 (e.g., signals exchanged between components within the RCD 306) to the host device 302, or another device, for testing, debugging, and training purposes. In one embodiment, the loopback mode of the RCD 306 can be activated by enabling the loopback circuitry 310 within the RCD 306. The loopback circuitry 310 can be configured to sample signals from the input signal 308 or internal signals of the RCD 306 and transmit the sampled signals to the host device 302. In one or more embodiments, the pass-through mode and the loopback mode can be activated individually or simultaneously.

[0044] In one state, sampling external signals (e.g., signals provided to RCD 306 by another device outside RCD 306, or signals provided to another device by RCD 306) and sampling the output signal of RCD 306 allow host device 302 to determine whether an error exists or does not exist within RCD 306. However, such sampling techniques may not allow host device 302 to determine which part, processing stage, or component of RCD 306 is causing the error. Integration of feedback circuitry 310 within RCD 306 allows feedback circuitry 310 to sample internal signals within RCD 306 from one or more sampling points within RCD 306. Sampled signals from one or more sampling points within RCD 306 allow host device 302 to identify specific processing stages or components within RCD 306 that may be causing the error. In one embodiment, in response to processing by different processing stages in RCD 306, the chip select signal in the input signal 308 can be sampled at multiple sampling points in RCD 306 to determine if any errors related to the chip select signal exist (e.g., an incorrect chip select signal, or a bad delay, etc.). In another embodiment, the feedback circuit 310 can use existing internal feedback lines in RCD 306 to sample the chip select signal to reduce the number of hardware or traces available for integrating chip select signal feedback features.

[0045] FIG4 is a schematic diagram illustrating details of the example register clock driver (RCD) 306 of FIG3 according to an embodiment of the present invention. In the example shown in FIG4, RCD 306 may include a feedback circuit 310, a receiver 404, logic circuitry 406, and an output driver 408. Receiver 404 may be configured to receive an input signal 308 (see FIG3) from a host device 302. In one embodiment, receiver 404 may include hardware or circuit components such as buffers and amplifiers. Input signal 308 may pass through these components in receiver 404 and may be output as an intermediate signal 407. In one embodiment, due to variations in the manufacturing process and temperature of components such as those in receiver 404, intermediate signal 407 may deviate from the expected output from receiver 404. Receiver 404 may buffer intermediate signal 407 and send it to logic circuitry 406.

[0046] Logic circuitry 406 may be configured to decode intermediate signal 407 to generate another set of intermediate signals 409, and send intermediate signals 409 to output driver 408. In an embodiment, input signal 308 may include chip select signal 412 for selecting one or more memory levels in memory module 304 (see FIG. 3). Intermediate signal 407 may include a processed version of chip select signal 412 (e.g., buffered, amplified, etc.). Logic circuitry 406 may decode intermediate signal 407 including processed chip select signal 412 and generate intermediate signal 409, which indicates a voltage that can be applied to memory module 304 to activate the selected memory level. Logic circuitry 406 may send intermediate signal 409 to output driver 408. Output driver 408 may output voltage 430 to activate the memory level selected in chip select signal 412.

[0047] The feedback circuit 310 can be configured to sample the chip select signal 412 at different sampling points within the RCD 306. For example, the feedback circuit 310 can obtain a replica of the sampled chip select signal 412, labeled as intermediate signal 407, from sampling point 414 between the receiver 404 and the logic circuit 406. The feedback circuit 310 can also obtain a replica of the sampled chip select signal 412, labeled as intermediate signal 409, from another sampling point 416 between the logic circuit 406 and the output driver 408. The feedback circuit 310 can transmit the sampled signals 422 and 424 to the host device 302.

[0048] In one embodiment, the host device 302 may store a copy of the chip select signal 412. The host device 302 may compare the chip select signal 412 with the sampled signals 422, 424 to determine the difference between the chip select signal 412 and the sampled signals 422, 424. In one embodiment, the host device 302 may simulate the operation of the receiver 404 and the logic circuit 406. Simulation may result in the generation of simulated signals 434, 436, which may be simulated versions of intermediate signals 407, 409, respectively. The host device 302 may compare the intermediate signal 407 with the simulated signal 434 to identify whether there is a difference between the intermediate signal 407 and the simulated signal 434. If the difference between the intermediate signal 407 and the simulated signal 434 exceeds a predefined difference (which may be stored in the host device 302), the host device 302 may determine that there may be an error in the receiver 404. The host device 302 may generate a flag and output the flag on a user interface, such as a display connected to the host device 302, to notify the user that there may be an error in the receiver 404 and / or indicate that the receiver 404 may need to be reconfigured to maintain the signal integrity of the chip select signal 412 and / or future chip select signals.

[0049] If the difference between the intermediate signal 409 and the analog signal 436 exceeds a predefined difference (which may be stored in the host device 302), the host device 302 may determine that there may be an error in the logic circuit 406. The host device 302 may generate a flag and output the flag on a user interface, such as a display connected to the host device 302, to notify the user that there may be an error in the logic circuit 406 and / or indicate that the logic circuit 406 may need to be reconfigured to maintain the signal integrity of the chip select signal 412 and / or future chip select signals.

[0050] In one embodiment, the host device 302 may sample voltage 430 at the output of RCD 306. The host device 302 may simulate voltage 430 and compare the sampled voltage with the simulated voltage. If there is no difference between intermediate signals 407, 409 and simulated signals 434, 436, or if the difference does not exceed a predefined difference stored in the host device 302, but there is a difference between the sampled version and the simulated version of voltage 430, then the host device 302 may determine that there may be an error in the output driver 408 and the output driver 408 may need to be reconfigured to maintain the signal integrity of chip select signal 412 and / or future chip select signals.

[0051] In one embodiment, if there is no difference between the intermediate signal 407 and the analog signal 434, or if the difference between the intermediate signal 407 and the analog signal 434 does not exceed a predefined difference stored in the host device 302, but there is a difference between the intermediate signal 409 and the analog signal 436, then the host device 302 may determine that there may be an error in the logic circuit 406, but there is no error in the receiver 404.

[0052] In one embodiment, if there is no difference between the intermediate signal 409 and the analog signal 436, or if the difference between the intermediate signal 409 and the analog signal 436 does not exceed a predefined difference stored in the host device 302, but there is a difference between the intermediate signal 407 and the analog signal 434, then the host device 302 may determine that there may be an error in the receiver 404, but there is no error in the logic circuit 406.

[0053] Furthermore, in one embodiment, the host device 302 may send an enable signal 440 to the feedback circuit 310 to enable or disable the feedback circuit 310. The enable signal 440 may be, for example, a binary signal, such that a binary zero disables the feedback circuit 310, and a binary one enables the feedback circuit 310 (or vice versa). In response to disabling the feedback circuit 310, the RCD 306 may operate in normal or pass-through mode, wherein the RCD may buffer and decode the input signal 308 for controlling the memory hierarchy of the memory module 304, reading and / or writing to the memory hierarchy of the memory module 304. It should be noted that when the feedback circuit 310 is disabled, the connection between sampling point 414 and the feedback circuit 310 and between sampling point 416 and the feedback circuit 310 may be cut off or disconnected, so that the signal is not sampled from sampling points 414, 416. In response to enabling the feedback circuit 310, the connections between sampling point 414 and the feedback circuit 310, and between sampling point 416 and the feedback circuit 310, can be closed or connected, allowing the feedback circuit 310 to sample signals from sampling points 414 and 416. In one embodiment, a pass-through mode and a feedback mode can be activated simultaneously, allowing the feedback circuit 310 to sample signals during normal operation of the RCD 306.

[0054] By integrating the feedback circuit 310 into the RCD 306, one or more test points can be inserted into the RCD 306 to maintain signal integrity. For example, the chip selection signal can be sampled from more than one sampling point inside the RCD 306 as shown in Figure 4. Different sampling points in the RCD 306 can provide information about which specific parts or stages of the RCD 306 may be faulty and may require attention. In addition, the integration of the feedback circuit 310 allows dedicated ports of the RCD 306 to be assigned to sampling points (e.g., 414, 416), enabling periodic testing to improve and maintain signal integrity during normal operation.

[0055] FIG5 is a block diagram of a feedback circuit 310 according to an embodiment of the present invention. The feedback circuit 310 may include a plurality of circuit components to facilitate sampling and selection of sampled signals that can be fed back to the host device 302 (see FIG4). In the example shown in FIG5, the feedback circuit 310 may include a plurality of multiplexers 502, 504, 506, 508 and 510. Multiplexer 502 may be configured to receive a plurality of command / address signals (DCA0_A to DCA6_A) and a parity signal or parity bit (DPAR_A) sampled from one or more sampling points in RCD 306 (see FIG3, FIG4). The sampled signals DPAR_A and DCA0_A to DCA6_A may correspond to a first channel ("Channel A") of memory module 304 and RCD 306. Multiplexer 504 can be configured to receive a plurality of command / address signals (DCA0_B to DCA6_B), and a parity signal or parity bit (DPAR_B) sampled from one or more sampling points in RCD 306. The sampled signals DPAR_B and DCA0_B to DCA6_B may correspond to a second channel ("Channel B") of memory module 304 and RCD 306. A selection signal 520 labeled RX_LOOPBACK_SEL can be provided by RCD 306 and / or host device 302 (see Figures 3 and 4) to select one of the sampled signals received by multiplexers 502 and 504 for output to multiplexer 510. In one embodiment, selection signal 520 may be a three-bit signal having a first bit, a second bit, and a third bit.

[0056] Multiplexer 506 can be configured to receive a sampled chip select signal (DCS0_A) from a sampling point in RCD 306, wherein the sampled chip select signal DCS0_A corresponds to channel A. Multiplexer 508 can be configured to receive a sampled chip select signal (DCS0_B) from a sampling point in RCD 306, wherein the sampled chip select signal DCS0_B corresponds to channel B. The sampled chip select signals received by multiplexers 502 and 504 can be one or more of the signals sampled from sampling points 414 and 416 shown in FIG. 4. In one embodiment, a bit in selection signal 520 can be used to select one of the input sampled signals received by multiplexers 506 and 508 for output to multiplexer 510.

[0057] Multiplexer 510 can be configured to receive outputs from multiplexers 502, 504, 506, and 508. Multiplexer 510 can also receive sampled external signals, such as DLBD_A and DLBD_B, which can be sampled externally, such as at sampling points outside RCD 306, at sampling points between RCD 306 and host device 302, and / or at sampling points between RCD 306 and memory layers of memory module 304 (see Figure 3). Multiplexer 510 can also receive sampled clock signals that can be inside or outside RCD 306 (e.g., the internal clock signal marked as internal QCK in Figure 5). A selection signal 522, labeled RX_LOOPBACK_CTRL, can be provided by RCD 306 and / or host device 302 to select one of the sampled signals received by multiplexer 510 as the sampled signals 422 and 424 shown in FIG. 4. In one embodiment, the selection signal 522 may be a three-bit signal having a first bit, a second bit, and a third bit.

[0058] In one embodiment, the selection signal 522 can control the selection of the sampled chip selection signal output by the multiplexer 510. For example, the third bit (or least significant bit) of the selection signal 520 can be used to select the sampled signal in multiplexers 506 and 508. Thus, selection signals 520 being "000", "010", "100", or "110" can cause a binary "0" to be transmitted to the selection pins of multiplexers 506 and 508. In an example, selection signal 520 being "000" can cause multiplexer 502 to select DCA0_A, multiplexer 504 to select DCA0_B, and a binary "0" can cause multiplexers 506 and 508 to select chip selection signals DCS0_A and DCS0_B, respectively. Therefore, selecting signal 520 as "000" enables multiplexers 502, 504, 506, and 508 to output DCA0_A, DCA0_B, DCS0_A, and DCS0_B respectively. Select signal 522 can select one of DCA0_A, DCA0_B, DCS0_A, and DCS0_B, ensuring that even if the third bit of select signal 520 is shared by multiple multiplexers, multiplexer 510 can still output the desired sampled signal. By using existing bits in the select signal for other sampled internal signals, feedback circuit 310 can internally provide sampling of the chip select signal without needing to design and assign new control word bits for chip select sampling and feedback.

[0059] In one embodiment, multiplexers 502, 504, 506, 508, and 510 can be considered as a group of feedback blocks within feedback circuitry 310. Feedback circuitry 310 may include more than one feedback block, similar to the example shown in FIG. 5, which may receive different types of sampled signals to feed back to host device 302. For example, multiplexers 502, 504, 506, 508, and 510 shown in FIG. 5 may be configured to sample command / address signals, local signals, chip select signals, and external data signals DLBD_A and DLBD_B from within RCD 306. The feedback circuit 310 may include another feedback block having a similar configuration of multiplexers 502, 504, 506, 508, and 510. Multiplexers 502, 504, 506, 508, and 510 may be configured to sample command / address signals, local signals, chip select signals, and external clock signals from inside the RCD 306 (e.g., instead of DLBD_A and DLBD_B, multiplexer 510 may receive external clock signals).

[0060] FIG6 is a flowchart of an example program 600 of a register clock driver with a chip select feedback circuit according to an embodiment of the present invention. Program 600 may include one or more operations, actions, or functions shown in one or more of blocks 602, 604, and / or 606. Although shown as discrete blocks, the blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or in parallel, depending on the desired implementation.

[0061] Program 600 may be implemented by a register clock driver (RCD) of the memory module. Program 600 may begin at block 602. At block 602, the RCD may receive a chip select signal for selecting one or more memory layers of the memory module. In one embodiment, the memory module may be a DDR5 load-reduced dual-row memory module (LRDIMM) including a synchronous dynamic random access memory (SDRAM) device.

[0062] Program 600 may proceed from block 602 to block 604. At block 604, the RCD may sample the chip selection signal from a first sampling point between the RCD's receiver and the RCD's logic circuitry. Program 600 may proceed from block 604 to block 606. At block 606, the RCD may sample the chip selection signal from a second sampling point between the RCD's logic circuitry and the RCD's output driver. Program 600 may proceed from block 606 to block 608. At block 608, the RCD may send the sampled chip selection signal to the memory controller. In one embodiment, the RCD may perform the operations in either block 604 or block 606. In another embodiment, the RCD may perform operations in both blocks 604 and 606, individually or simultaneously.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. It will be further understood that the terms "comprises and / or comprising," when used in this specification, designate the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0064] The corresponding structures, materials, actions, and equivalents of all components or steps plus functional elements (if any) in the following claims are intended to include any structure, material, or action used to perform functions in conjunction with other claimed elements specifically claimed. The disclosed embodiments of the invention have been presented for illustrative and descriptive purposes, but are not intended to be exhaustive or limiting of the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Embodiments were chosen and described to best explain the principles of the invention and its practical application, and to enable others skilled in the art to understand the invention through various embodiments and modifications as suited to the intended particular use. Cross-Reference to Related Applications

[0065] This application is a continuation-to-file of PCT International Application No. PCT / CN2021 / 130922, filed on November 16, 2021. The entire contents of PCT International Application No. PCT / CN2021 / 130922 are incorporated herein by reference. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a diagram of an example memory system according to an embodiment of the present invention.

[0008] FIG2 is a block diagram illustrating an example memory module of the memory system of FIG1 according to an embodiment of the present invention.

[0009] Figure 3 is a block diagram of an example memory module including a register clock driver with a chip select feedback circuit according to an embodiment of the present invention.

[0010] Figure 4 is a diagram illustrating details of a register clock driver with a chip select feedback circuit according to an embodiment of the present invention.

[0011] Figure 5 is a circuit diagram of the feedback circuit according to an embodiment of the present invention.

[0012] FIG6 is a flowchart of an example program 600 of a temporary register clock driver with chip select feedback according to an embodiment of the present invention.

Claims

1. An apparatus for a memory module, comprising: a receiver configured to receive a chip select signal for selecting one or more memory layers of the memory module; a logic circuit coupled to the receiver; and an output driver coupled to the logic circuit, wherein: The logic circuit is configured to decode the chip select signal to generate an output signal for selecting one or more memory levels of the memory module; the output driver is configured to use the output signal to select one or more memory levels; and a feedback circuit is configured to sample the chip select signal from one or more of the following: a first sampling point between the receiver and the logic circuit; and a second sampling point between the logic circuit and the output driver.

2. The device of claim 1, wherein the feedback circuit is configured to provide one or more samples of the chip select signal to a memory controller.

3. The device as requested in item 1, wherein: In response to disabling the feedback circuit, the device operates in a continuous mode; and in response to enabling the feedback circuit, the device operates in a feedback mode, and the feedback circuit is configured to sample the chip select signal in response to enabling the feedback circuit.

4. The device of claim 1, wherein the feedback circuitry comprises: a first multiplexer configured to sample the chip select signal from a first channel of the device; and a second multiplexer configured to sample the chip select signal from a second channel of the device.

5. The device of claim 1, wherein the feedback circuitry comprises: a first portion configured to a plurality of address and command signals; a second portion configured to sample a plurality of co-location signals; and a third portion configured to sample the chip select signal.

6. The device of claim 5, wherein the first and second portions of the feedback circuit are controlled by a selection signal including a first bit, a second bit and a third bit, and the third portion of the feedback circuit is controlled by one of the first bit, the second bit and the third bit.

7. The device as requested in item 1, wherein the memory module is a dual data rate fifth generation (DDR5) memory module.

8. The device of claim 1, wherein the receiver, the logic circuit, the output driver and the feedback circuit are part of a register clock driver (RCD) of a DDR5 memory module.

9. The device as claimed in claim 1, wherein the memory module includes a DDR5 load-reduced dual-row memory module (LRDIMM) of the synchronous dynamic random access memory (SDRAM) device.

10. A device comprising a memory module, wherein the memory module includes: Multiple memory levels; and a register clock driver (RCD) coupled to the plurality of memory levels, the RCD being configured to receive a chip select signal for selecting one or more memory levels among the plurality of memory levels; and the RCD including a feedback circuit configured to sample the chip select signal from one or more of the following: a first sampling point between a receiver of the RCD and a logic circuit of the RCD; and a second sampling point between the logic circuit of the RCD and an output driver of the RCD.

11. The device of claim 10, wherein the feedback circuit is configured to provide a sample of the chip select signal to a memory controller coupled to the RCD.

12. The equipment as requested in item 10, wherein: In response to disabling the feedback circuit, the RCD operates in a continuous mode; and in response to enabling the feedback circuit, the RCD operates in a feedback mode, wherein the feedback circuit is configured to sample the chip select signal in response to enabling the feedback circuit.

13. The device of claim 10, wherein the feedback circuitry comprises: a first multiplexer configured to sample the chip select signal from a first channel of the device; and a second multiplexer configured to sample the chip select signal from a second channel of the device.

14. The device of claim 10, wherein the feedback circuitry comprises: a first portion configured to a plurality of address and command signals; a second portion configured to sample a plurality of co-location signals; and a third portion configured to sample the chip select signal.

15. The device of claim 14, wherein the first and second portions of the feedback circuit are controlled by a selection signal including a first bit, a second bit and a third bit, and the third portion of the feedback circuit is controlled by one of the first bit, the second bit and the third bit.

16. The device as requested in item 10, wherein the memory module is a dual data rate fifth generation (DDR5) memory module.

17. The device of claim 10, wherein the memory module includes a DDR5 load-reduced dual-row memory module (LRDIMM) of a synchronous dynamic random access memory (SDRAM) device.

18. A method for operating a memory module, the method comprising: receiving a chip select signal for selecting one or more memory layers of the memory module by a register clock driver (RCD) of a memory module; and sampling the chip select signal by the RCD from one or more of the following: a first sampling point between a receiver of the RCD and a logic circuit of the RCD; and a second sampling point between the logic circuit of the RCD and an output driver of the RCD.

19. The method of claim 18 further includes sending the sampled chip select signal from the RCD to a memory controller of the memory module.

20. The method of claim 18, wherein the memory module includes a DDR5 load-reduced dual-row memory module (LRDIMM) of a synchronous dynamic random access memory (SDRAM) device.

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