Memory system and operating method of controller of the memory system

Abstract

The controller of the memory system includes memory, a temperature increment estimation unit, and a reordering unit. The memory includes a request queue configured to queue operation requests provided from the host device. The temperature increment estimation unit estimates the temperature increment corresponding to each operation request. The reordering unit performs a reordering operation based on the temperature increment to rearrange the operation requests queued in the request queue.

Description

[Technical Field]

[0001] Various embodiments of the present invention relate to memory systems, and more specifically, to memory systems including non-volatile memory devices. [Previous Technology]

[0002] The memory system can be configured to store data provided by the host device in response to a write request from the host device. Furthermore, the memory system can be configured to provide the stored data to the host device in response to a read request from the host device. The host device is an electronic device capable of processing data and may include a computer, a digital camera, or a mobile phone. For operation, the memory system can be installed in the host device or can be manufactured to be connected to and separate from the host device.

[0003] An electronic device includes many electronic components, and a computer system, as an electronic device, includes many semiconductor devices, each configured by semiconductors. In the semiconductor devices configuring a computer system, a host (such as a processor or memory controller) performs data communication with the memory devices. The memory devices include multiple memory cells, each memory cell being identified and configured with stored data via word lines and bit lines. [Summary of the Invention]

[0004] Cross-reference to related applications: This application claims priority to Korean Patent Application No. 10-2021-0143459, filed on October 26, 2021, which is incorporated herein by reference in its entirety as stated herein.

[0005] In an embodiment of the present invention, the controller of the memory system includes memory, a temperature increment estimation unit, and a reordering unit. The memory may include a request queue configured to queue operation requests provided from a host device. The temperature increment estimation unit may be configured to estimate temperature increments corresponding to the operation requests. The reordering unit may be configured to perform a reordering operation based on the temperature increments to rearrange the operation requests queued in the request queue.

[0006] In an embodiment, the operation method of the controller of the memory system may include estimating the temperature increment corresponding to the operation request provided from the host device and performing a reordering operation based on the temperature increment to rearrange the operation requests queued in the request queue.

[0007] In embodiments of the present invention, the controller of the memory system may include memory, a temperature increment estimation unit, a reordering unit, and a performance tuning unit. The memory may include a request queue configured to queue operation requests provided from a host device. The temperature increment estimation unit may be configured to estimate temperature increments corresponding to the operation requests. The reordering unit may be configured to reorder the operation requests queued in the request queue based on the temperature increment when the temperature of the memory system becomes higher than a reordering trigger temperature, thereby delaying the temperature rise of the memory system. The performance tuning unit may be configured to compare the temperature of the memory system with one or more performance tuning trigger temperatures to change the performance mode of the memory system.

[0008] In embodiments of the present invention, the controller operation method may include reducing the performance of the memory device in a stepped manner as the temperature of the memory device increases; and dequeuing queued requests to control the memory device to sequentially execute operations for dequeuing the requests, each operation causing a temperature increment in the memory device. The queued requests may be dequeued in ascending order of temperature increments.

Implementation Method

[0010] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be exhaustive and complete, and will fully convey the scope of the invention to those skilled in the art to which it pertains.

[0011] The drawings are not necessarily to scale, but in some instances the scale may have been exaggerated in order to clearly illustrate the features of the embodiments. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0012] As used herein, the term “and / or” includes at least one of the associated listed items. It will be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be one or more intermediate elements. As used herein, the singular form is intended to include the plural form, and vice versa, unless the context clearly indicates otherwise. It should be further understood that when the terms “comprising,” “including,” “including,” and “comprises” are used in this specification, they expressly indicate the presence of the stated element and do not exclude the presence or enlargement of more than one or more other elements.

[0013] In the following, various embodiments of the present invention will be described with reference to the drawings.

[0014] According to an embodiment, a controller for a memory system and a method of operating the controller may be provided, the controller being able to delay the temperature rise of the memory system to provide improved responsiveness to a host device.

[0015] FIG1 is a block diagram illustrating a memory system 100 according to an embodiment of the present invention.

[0016] The memory system 100 can be configured to store data provided from the host device in response to a write request from the external host device. The memory system 100 can be configured to provide the data stored therein to the host device in response to a read request from the host device.

[0017] The memory system 100 can be configured as a PCMCIA card, a micro flash (CF) card, a smart media card, a memory stick, a variety of multimedia cards (e.g., MMC, eMMC, RS-MMC and MMC-Micro), a secure digital (SD) card (e.g., SD, mini SD and micro SD), a universal flash (UFS) or a solid-state drive (SSD).

[0018] The memory system 100 may include a controller 110 and a non-volatile memory device 120.

[0019] The controller 110 can control the overall operation of the memory system 100. The controller 110 can control the non-volatile memory device 120 to perform foreground operations in response to instructions from the host device. Foreground operations may include the following operations: writing data to the non-volatile memory device 120 and reading data from the non-volatile memory device 120 in response to instructions from the host device, namely, write requests and read requests.

[0020] Furthermore, the controller 110 can control the non-volatile memory device 120 to perform necessary internal background operations, independent of the host device. Background operations may include at least one of the following for the non-volatile memory device 120: wear leveling, useless cell collection, erasure, read / reclaim, and refresh operations. Similar to foreground operations, background operations may include writing data to the non-volatile memory device 120 and reading data from the non-volatile memory device 120.

[0021] The controller 110 may include a memory 111, a temperature increment estimation unit 112, a performance adjustment unit 113, and a reordering unit 114.

[0022] Memory 111 can operate as an operable memory, buffer memory, or cache memory for controller 110. As operable memory, memory 111 can store various software programs and various program data that run through controller 110. As buffer memory, memory 111 can buffer data to be transferred between host device and non-volatile memory device 120. As cache memory, memory 111 can temporarily store cached data. Memory 111 may include a request queue RQQ. The request queue RQQ can queue and dequeue operation requests provided from the host device. Operation requests can be queued sequentially in the request queue RQQ according to the order in which operation requests are provided from the host device. However, as described later, queued operation requests can be rearranged in the request queue RQQ through a reordering operation of reordering unit 114.

[0023] The temperature increment estimation unit 112 can estimate the temperature increments corresponding to the operation requests queued in the request queue RQQ. The temperature increment corresponding to the operation request can be the temperature of the memory system 100, which is estimated to increase as the corresponding operation request is processed. According to an embodiment, whenever a corresponding operation request is received from the host device, the temperature increment estimation unit 112 can estimate or calculate the temperature increment corresponding to the operation request. According to an embodiment, when the reordering unit 114 determines to perform a reordering operation (described later), the temperature increment estimation unit 112 can calculate the temperature increments corresponding to the operation requests queued in the request queue RQQ.

[0024] The performance tuning unit 113 can compare the temperature of the memory system 100 with one or more performance tuning trigger temperatures to perform a performance tuning operation for adjusting the performance of the memory system 100. The performance tuning unit 113 can perform the performance tuning operation by selecting one of a plurality of performance modes and controlling the memory system 100 to operate in the selected performance mode. The temperature of the memory system 100 can be measured by a temperature sensor (not shown) provided inside the memory system 100.

[0025] The reordering unit 114 can perform a reordering operation for rearranging the queued operation requests based on the temperature increments corresponding to the operation requests queued in the request queue RQQ, wherein the temperature increments are estimated by the temperature increment estimation unit 112. The reordering unit 114 can perform a reordering operation by rearranging the operation requests queued in the request queue RQQ, such that the operation request corresponding to the smallest temperature increment is rearranged to be dequeued from the request queue RQQ first. The reordering unit 114 can also perform a reordering operation by rearranging the operation requests queued in the request queue RQQ in ascending order of temperature increments, such that the operation requests corresponding to smaller temperature increments are rearranged to be dequeued from the request queue RQQ earlier than the operation requests corresponding to larger temperature increments. The reordering unit 114 can perform a reordering operation on operation requests queued in the request queue RQQ, such that random requests (i.e., random read requests and / or random write requests) are rearranged to be dequeued from the request queue RQQ earlier than sequential requests (i.e., sequential read requests and / or sequential write requests). Typically, the user experiences more response latency for random requests than for sequential requests. The reordering unit 114 can perform a reordering operation when the temperature increments corresponding to random and sequential requests in the operation requests queued in the request queue RQQ have the same value, such that random requests are rearranged to be dequeued from the request queue RQQ earlier than sequential requests. The reordering unit 114 can perform a reordering operation to allow the temperature of the memory system 100 to rise slowly. The reordering unit 114 can perform a reordering operation to allow as many queued operation requests as possible to be processed before performance tuning operations are performed to change the performance mode of the memory system 100 to a lower mode.

[0026] According to an embodiment, the reordering unit 114 can perform a reordering operation when a predetermined reordering trigger condition is met. The reordering trigger condition may include when the temperature of the memory system 100 becomes higher than the reordering trigger temperature. As long as the reordering trigger condition remains met, the reordering unit 114 can perform a reordering operation whenever an operation request is provided from the host device.

[0027] According to an embodiment, the reordering trigger temperature may be a first performance tuning trigger temperature having the lowest value among performance tuning trigger temperatures, which is mentioned during the performance tuning operation. According to an embodiment, the reordering trigger temperature may be lower than the first performance tuning trigger temperature. According to an embodiment, the reordering trigger temperature may be one of the performance tuning trigger temperatures mentioned during the performance tuning operation.

[0028] According to the control of the controller 110, the non-volatile memory device 120 can store data provided by the controller 110 therein and can read the data stored therein and provide the read data to the controller 110.

[0029] The non-volatile memory device 120 may include flash memory devices (e.g., NAND flash or NOR flash), ferroelectric random access memory (FeRAM), phase change random access memory (PCRAM), magnetic random access memory (MRAM), and resistive random access memory (ReRAM), etc.

[0030] The non-volatile memory device 120 may include one or more planes, one or more memory chips, one or more memory dies, or one or more memory packages.

[0031] FIG2 is a schematic diagram showing the operation of the temperature increment estimation unit 112 of FIG1 according to an embodiment of the present invention.

[0032] Referring to FIG2, the temperature increment estimation unit 112 can calculate the temperature increment corresponding to the operation request provided from the host device based on the power consumption information and operation request information corresponding to the operation request.

[0033] The temperature increment estimation unit 112 can refer to the power consumption information table PIT to obtain power consumption information corresponding to the operation request. The power consumption information table PIT may include power consumption information segments corresponding to the corresponding operation type. For example, the operation type may include sequential read operation, sequential write operation, random read operation, and random write operation. The power consumption information segment corresponding to each operation type may include information on the average power consumption and / or peak power consumption to be consumed when performing an operation on the processing unit (e.g., a predetermined data size). The power consumption information table PIT may be managed in memory 111 and / or in non-volatile memory device 120. The power consumption information table PIT may be predetermined through testing.

[0034] The operation request information corresponding to the operation request may include information about the size of the data to be processed through the operation request.

[0035] For example, when the operation request is a sequential read request, the power consumption information corresponding to the operation request may include information on the average power consumption of the sequential read operation, and the operation request information corresponding to the operation request may include information on the size of the data to be read from the non-volatile memory device 120 through the sequential read operation.

[0036] In order to calculate the temperature increment corresponding to the operation request, the temperature increment estimation unit 112 can refer to a predetermined formula EQ related to the power consumption information and the operation request information. The formula EQ can be predetermined through testing.

[0037] FIG3 is a schematic diagram illustrating the operation of the performance adjustment unit 113 of FIG1 according to an embodiment of the present invention.

[0038] Referring to Figure 3, the performance adjustment unit 113 can determine the performance mode of the memory system 100 based on the temperature of the memory system 100. The performance adjustment unit 113 can compare the temperature of the memory system 100 with a first performance adjustment trigger temperature TT1 to a third performance adjustment trigger temperature TT3 to select one of a high-performance mode (HP), an intermediate performance mode (MP), and a low-performance mode (LP), and can control the memory system 100 to operate in the selected performance mode. For example, the first performance adjustment trigger temperature TT1 to the third performance adjustment trigger temperature TT3 can be 85°C, 95°C, and 105°C, respectively. For example, in the high-performance mode (HP), intermediate performance mode (MP), and low-performance mode (LP), the memory system 100 can operate based on 100%, 50%, and 5% of the total performance of the memory system 100, respectively.

[0039] More specifically, the memory system 100 can operate in high-performance mode HP until the temperature of the memory system 100 rises to 95°C. When the temperature of the memory system 100 rises to 95°C, the performance mode of the memory system 100 can change from high-performance mode HP to intermediate performance mode MP. After the performance mode of the memory system 100 changes to intermediate performance mode MP, the memory system 100 can remain in intermediate performance mode MP while the temperature of the memory system 100 remains between 85°C and 105°C. When the temperature of the memory system 100 reaches 85°C in intermediate performance mode MP, the performance mode of the memory system 100 can change to high-performance mode HP. When the temperature of the memory system 100 reaches 105°C in intermediate performance mode MP, the performance mode of the memory system 100 can change to low-performance mode LP. After the performance mode of the memory system 100 changes to low-performance mode LP, the memory system 100 can remain in low-performance mode LP until the temperature of the memory system 100 drops to 85°C. When the temperature of the memory system 100 reaches 85°C in low performance mode LP, the performance mode of the memory system 100 can be changed to high performance mode HP.

[0040] In order to adjust the performance of the memory system 100, the performance adjustment unit 113 can control the operating frequency and number of allowed resources. For example, as the operating frequency and / or number of allowed resources become smaller, the memory system 100 can operate in a lower performance mode.

[0041] According to an embodiment, the number of performance modes and the number of performance adjustment trigger temperatures can be determined differently from those shown in Figure 3.

[0042] FIG4 is a schematic diagram illustrating the operation of the reordering unit 114 of FIG1 according to an embodiment of the present invention. Referring to FIG4, case 41 represents the case in which no reordering operation is performed, and case 42 represents the case in which a reordering operation is performed.

[0043] Referring to case 41, the controller 110 can sequentially receive a first sequential read request SEQ_RD1, a second sequential read request SEQ_RD2, a sequential write request SEQ_WT, and a random read request RAN_RD from the thermal device. The first sequential read request SEQ_RD1, the second sequential read request SEQ_RD2, the sequential write request SEQ_WT, and the random read request RAN_RD can be sequentially queued in the request queue RQQ according to the order in which the controller 110 receives them. Figure 4 shows the amount of processing time required for the memory system 100 to process the corresponding operation request in high-performance mode HP. In the following text, as shown in Figure 3, the memory system 100 can operate at 100% and 50% of its full performance in high-performance mode HP and intermediate performance mode MP, respectively.

[0044] The temperature increment estimation unit 112 can estimate the temperature increment corresponding to each operation request. For example, the temperature increment estimation unit 112 can estimate a temperature increase of 4°C in the memory system 100 due to the processing of the first sequential read request SEQ_RD1. Furthermore, the temperature increment estimation unit 112 can estimate a temperature increase of 4°C in the memory system 100 due to the processing of the second sequential read request SEQ_RD2. Furthermore, the temperature increment estimation unit 112 can estimate a temperature increase of 2°C in the memory system 100 due to the processing of the sequential write request SEQ_WT. Furthermore, the temperature increment estimation unit 112 can estimate a temperature increase of 1°C in the memory system 100 due to the processing of the random read request RAN_RD.

[0045] When the reordering unit 114 does not perform a reordering operation, the first sequential read request SEQ_RD1, the second sequential read request SEQ_RD2, and the sequential write request SEQ_WT can be processed in the order of transmission. During processing, the temperature of the memory system 100 may not rise to the second performance adjustment trigger temperature TT2, i.e., 95°C, and therefore the first sequential read request SEQ_RD1, the second sequential read request SEQ_RD2, and the sequential write request SEQ_WT can be processed in high-performance mode HP. When the temperature of the memory system 100 rises to 95°C after the processing of the sequential write request SEQ_WT is completed, the performance mode of the memory system 100 can change from high-performance mode HP to intermediate performance mode MP. Therefore, up to 100% of the random read requests RAN_RD can be processed in intermediate performance mode MP. The processing time spent by the memory system 100 in high-performance mode HP to process up to 100% of the random read requests RAN_RD can be 5 seconds (sec). However, due to performance tuning operations, up to 100% of random read requests RAN_RD can be processed in intermediate performance mode MP, and therefore the amount of time that memory system 100 takes to process up to 100% of random read requests RAN_RD can be 10 seconds. That is, when the performance of memory system 100 is reduced to 50% of its full performance, the processing time that memory system 100 takes to process up to 100% of random read requests RAN_RD can double.

[0046] To clearly describe situation 42, the temperature of the memory system 100 increases proportionally to the progress rate of the processed operation requests (i.e., the progress rate of operations performed in response to operation requests). For example, when up to 50% of the operation requests are processed, the temperature of the memory system 100 may increase by 50% corresponding to the temperature increment of the operation requests.

[0047] The reordering unit 114 operates as follows. When the temperature of the memory system 100 becomes higher than the reordering trigger temperature, the reordering unit 114 can perform a reordering operation. For example, the reordering trigger temperature can be a first performance adjustment trigger temperature TT1, i.e., 85°C. Therefore, when the temperature of the memory system 100 rises from 85°C to 89°C as the first sequential read request SEQ_RD1 is processed, the reordering unit 114 can perform a reordering operation. Specifically, the reordering unit 114 can perform a reordering operation by changing the order of the random read request RAN_RD and the second sequential read request SEQ_RD2. That is, the reordering unit 114 can perform a reordering operation such that among the second sequential read request SEQ_RD2, the sequential write request SEQ_WT, and the random read request RAN_RD queued in the request queue RQQ, the random read request RAN_RD corresponding to the smallest temperature increment is rearranged so that it is dequeued from the request queue RQQ first. The reordered order in Case 42 could be the result of rearranging the second sequential read request SEQ_RD2, sequential write request SEQ_WT, and random read request RAN_RD, which are queued in the request queue RQQ and arranged in the order of Case 41, in ascending order of temperature increments. This would result in the random read request RAN_RD, corresponding to a smaller temperature increment, being rearranged from the request queue RQQ earlier than each sequential write request SEQ_WT and second sequential read request SEQ_RD2 corresponding to a larger temperature increment.

[0048] After the reordering operation, random read requests RAN_RD and sequential write requests SEQ_WT can be processed sequentially. During processing, the temperature of the memory system 100 can rise to 92°C (not yet the second performance tuning trigger temperature TT2, i.e., 95°C), and therefore the memory system 100 can remain in high-performance mode HP. When up to 75% of the second sequential read requests SEQ_RD2 are processed, the temperature of the memory system 100 can rise to 95°C. Therefore, the performance mode of the memory system 100 can change from high-performance mode HP to intermediate performance mode MP, and up to 25% of the second sequential read requests SEQ_RD2 can be processed in intermediate performance mode MP. In high-performance mode HP, the amount of processing time spent by the memory system 100 to process up to 100% of the second sequential read requests SEQ_RD2 can be 10 seconds. However, due to performance tuning operations, up to 75% of the second sequential read requests SEQ_RD2 can be processed in high-performance mode HP and up to the remaining 25% can be processed in intermediate performance mode MP, and therefore the amount of processing time spent by memory system 100 to process the second sequential read requests SEQ_RD2 can be 12.5 seconds.

[0049] When comparing cases 41 and 42, the temperature rise of the memory system 100 can be delayed through a reordering operation. That is, through the reordering operation, as many operation requests as possible can be processed before the performance tuning operation used to change the performance mode of the memory system 100 to a lower mode. Furthermore, as a result of the reordering operation, the total processing time for operation requests queued in the request queue RQQ can be reduced, and thus the response performance to the host device can be improved.

[0050] FIG5 is a flowchart illustrating the operation of the controller 110 according to an embodiment of the present invention.

[0051] Referring to FIG5, in operation S110, the temperature increment estimation unit 112 can estimate the temperature increment corresponding to the operation request provided from the host device. The temperature increment corresponding to the operation request can be the temperature of the memory system 100, which is estimated to increase as the corresponding operation request is processed.

[0052] In operation S120, the reordering unit 114 may perform a reordering operation to rearrange the queued operation requests based on the temperature increments corresponding to the operation requests queued in the request queue RQQ, wherein the temperature increments are estimated by the temperature increment estimation unit 112. According to an embodiment, the reordering unit 114 may perform the reordering operation when a reordering trigger condition is met.

[0053] FIG6 is a schematic diagram illustrating a data processing system 1000 including a solid-state drive (SSD) 1200 according to an embodiment of the present invention. Referring to FIG6, the data processing system 1000 may include a host device 1100 and an SSD 1200.

[0054] The SSD 1200 may include a controller 1210, a buffer memory device 1220, multiple non-volatile memory devices 1231 to 123n, a power supply 1240, a signal connector 1250, and a power connector 1260.

[0055] The controller 1210 can control the overall operation of the SSD 1200. The controller 1210 may include a host interface unit 1211, a control unit 1212, a random access memory 1213, an error correction code (ECC) unit 1214, and a memory interface unit 1215.

[0056] The host interface unit 1211 can exchange signals SGL with the host device 1100 through the signal connector 1250. The signal SGL may include commands, addresses, and data. The host interface unit 1211 can interface with the host device 1100 and the SSD 1200 according to the protocol of the host device 1100. For example, the host interface unit 1211 can communicate with the host device 1100 through any standard communication interface or protocol, such as Secure Digital, Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), PCMCIA, Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCI-e or PCIe), and Universal Flash Storage (UFS).

[0057] The control unit 1212 can analyze and process the signal SGL received from the host device 1100. The control unit 1212 can control the operation of internal functional blocks according to the solid-state or software control used to drive the SSD 1200. Random access memory 1213 can serve as working memory for driving such solid-state or software. The control unit 1212 may include a temperature increment estimation unit 112, a performance adjustment unit 113, and a reordering unit 114 shown in FIG. 1.

[0058] The ECC unit 1214 can generate parity data for data to be transferred to at least one of the non-volatile memory devices 1231 to 123n. The generated parity data can be stored together with the data in the non-volatile memory devices 1231 to 123n. The ECC unit 1214 can detect errors in data read from at least one of the non-volatile memory devices 1231 to 123n based on the parity data. If the detected error is within a correctable range, the ECC unit 1214 can correct the detected error.

[0059] The memory interface unit 1215 may provide control signals (such as commands and addresses) to at least one of the non-volatile memory devices 1231 to 123n under the control of the control unit 1212. Additionally, the memory interface unit 1215 may exchange data with at least one of the non-volatile memory devices 1231 to 123n under the control of the control unit 1212. For example, the memory interface unit 1215 may provide data stored in the buffer memory device 1220 to at least one of the non-volatile memory devices 1231 to 123n, or provide data read from at least one of the non-volatile memory devices 1231 to 123n to the buffer memory device 1220.

[0060] The buffer memory device 1220 can temporarily store data to be stored in at least one of the non-volatile memory devices 1231 to 123n. Furthermore, the buffer memory device 1220 can temporarily store data read from at least one of the non-volatile memory devices 1231 to 123n. The data temporarily stored in the buffer memory device 1220 can be transferred to the host device 1100 or at least one of the non-volatile memory devices 1231 to 123n under the control of the controller 1210.

[0061] Non-volatile memory devices 1231 to 123n can serve as storage media for the SSD 1200. Non-volatile memory devices 1231 to 123n can be coupled to the controller 1210 via multiple channels CH1 to CHn. One or more non-volatile memory devices can be coupled to a single channel. Non-volatile memory devices coupled to each channel can be coupled to the same signal bus and data bus.

[0062] Power supply 1240 can provide power PWR input through power connector 1260 to the interior of SSD 1200. Power supply 1240 may include auxiliary power supply 1241. Auxiliary power supply 1241 can supply power to allow SSD 1200 to shut down normally in the event of a sudden power outage. Auxiliary power supply 1241 may include a large-capacity capacitor.

[0063] The signal connector 1250 can be configured with various types of connectors depending on the interface scheme between the host device 1100 and the SSD 1200.

[0064] The power connector 1260 can be configured with various types of connectors depending on the power supply scheme of the host device 1100.

[0065] FIG7 is a schematic diagram illustrating a data processing system 2000 including a memory system 2200 according to an embodiment of the present invention. Referring to FIG7, the data processing system 2000 may include a host device 2100 and a memory system 2200.

[0066] The host device 2100 may be configured in the form of a board (such as a printed circuit board). Although not shown, the host device 2100 may include internal function blocks for performing the functions of the host device.

[0067] The host device 2100 may include a connection terminal 2110, such as a socket, slot, or connector. The memory system 2200 may be mounted on the connection terminal 2110.

[0068] The memory system 2200 may be configured in the form of a board (such as a printed circuit board). The memory system 2200 may be referred to as a storage module or a memory card. The memory system 2200 may include a controller 2210, a buffer memory device 2220, a non-volatile memory device 2231 and a non-volatile memory device 2232, a power management integrated circuit (PMIC) 2240, and a connection terminal 2250.

[0069] Controller 2210 can control the overall operation of memory system 2200. Controller 2210 can be configured in the same manner as controller 1210 shown in FIG. 6.

[0070] The buffer memory device 2220 can temporarily store data to be stored in the non-volatile memory device 2231 and the non-volatile memory device 2232. Furthermore, the buffer memory device 2220 can temporarily store data read from the non-volatile memory device 2231 and the non-volatile memory device 2232. Data temporarily stored in the buffer memory device 2220 can be transferred to the host device 2100 or the non-volatile memory device 2231 and the non-volatile memory device 2232 under the control of the controller 2210.

[0071] The non-volatile memory device 2231 and the non-volatile memory device 2232 can serve as storage media for the memory system 2200.

[0072] The PMIC 2240 can provide power to the memory system 2200 through the connection terminal 2250. The PMIC 2240 can manage the power of the memory system 2200 according to the control of the controller 2210.

[0073] Connection terminal 2250 can be coupled to connection terminal 2110 of host device 2100. Through connection terminal 2250, signals (such as commands, addresses, and data) and power can be transmitted between host device 2100 and memory system 2200. Connection terminal 2250 can be configured in various types depending on the interface scheme between host device 2100 and memory system 2200. Connection terminal 2250 can be located on either side of memory system 2200.

[0074] FIG8 is a schematic diagram illustrating a data processing system 3000 including a memory system 3200 according to an embodiment of the present invention. Referring to FIG8, the data processing system 3000 may include a host device 3100 and a memory system 3200.

[0075] The host device 3100 may be configured in the form of a board (such as a printed circuit board). Although not shown, the host device 3100 may include internal function blocks for performing the functions of the host device.

[0076] The memory system 3200 can be configured in a surface-mount package. The memory system 3200 can be mounted onto the host device 3100 via solder balls 3250. The memory system 3200 may include a controller 3210, a buffer memory device 3220, and a non-volatile memory device 3230.

[0077] The controller 3210 can control the overall operation of the memory system 3200. The controller 3210 can be configured in the same way as the controller 1210 shown in FIG. 6.

[0078] The buffer memory device 3220 can temporarily store data to be stored in the non-volatile memory device 3230. Furthermore, the buffer memory device 3220 can temporarily store data read from the non-volatile memory device 3230. Data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the non-volatile memory device 3230 under the control of the controller 3210.

[0079] The non-volatile memory device 3230 can serve as a storage medium for the memory system 3200.

[0080] FIG9 is a schematic diagram illustrating a network system 4000 including a memory system 4200 according to an embodiment of the present invention. Referring to FIG9, the network system 4000 may include a server system 4300 coupled through a network 4500 and a plurality of client systems 4410 to 4430.

[0081] Server system 4300 can provide data services in response to requests from multiple client systems 4410 to 4430. For example, server system 4300 can store data provided from multiple client systems 4410 to 4430. As another example, server system 4300 can provide data to multiple client systems 4410 to 4430.

[0082] The server system 4300 may include a host device 4100 and a memory system 4200. The memory system 4200 may be configured via the memory system 100 shown in FIG1, the SSD 1200 shown in FIG6, the memory system 2200 shown in FIG7, or the memory system 3200 shown in FIG8.

[0083] FIG10 is a block diagram illustrating a non-volatile memory device 300 included in a memory system according to an embodiment of the present invention. Referring to FIG10, the non-volatile memory device 300 may include a memory cell array 310, a column decoder 320, a data read / write block 330, a row decoder 340, a voltage generator 350, and control logic 360.

[0084] The memory cell array 310 may include memory cells MC arranged in the region where word lines WL1 to WLm and bit lines BL1 to BLn intersect each other.

[0085] The column decoder 320 can be coupled to the memory cell array 310 via word lines WL1 to WLm. The column decoder 320 can operate under the control of control logic 360. The column decoder 320 can decode addresses provided from external devices (not shown). The column decoder 320 can select and drive word lines WL1 to WLm based on the decoding result. For example, the column decoder 320 can provide word line voltages provided by voltage generator 350 to word lines WL1 to WLm.

[0086] The data read / write block 330 can be coupled to the memory cell array 310 via bit lines BL1 to BLn. The data read / write block 330 may include read / write circuits RW1 to RWn corresponding to bit lines BL1 to BLn respectively. The data read / write block 330 can be operated under the control of the control logic 360. The data read / write block 330 can operate as a write driver or a sense amplifier depending on the operating mode. For example, the data read / write block 330 can operate as a write driver, storing data provided from an external device into the memory cell array 310 during a write operation. As another example, the data read / write block 330 can operate as a sense amplifier, reading data from the memory cell array 310 during a read operation.

[0087] The line decoder 340 can operate under the control of the control logic 360. The line decoder 340 can decode addresses provided from external devices. Based on the decoding result, the line decoder 340 can couple the read / write circuits RW1 to RWn of the data read / write block 330, which correspond to bit lines BL1 to BLn respectively, to the data input / output lines or the data input / output buffer.

[0088] Voltage generator 350 can generate voltages to be used in the internal operation of non-volatile memory device 300. The voltage generated by voltage generator 350 can be applied to the memory cells of memory cell array 310. For example, a program voltage generated during a program operation can be applied to the word line of the memory cell to which the program operation will be performed. As another example, an erase voltage generated during an erase operation can be applied to the well region of the memory cell to which the erase operation will be performed. As yet another example, a read voltage generated during a read operation can be applied to the word line of the memory cell to which the read operation will be performed.

[0089] The control logic 360 can control the overall operation of the non-volatile memory device 300 based on control signals provided from an external device. For example, the control logic 360 can control the operation of the non-volatile memory device 300, such as read, write and erase operations of the non-volatile memory device 300.

[0090] According to an embodiment, the controller of the memory system and the method of operation thereof can delay the temperature rise of the memory system to provide improved responsiveness to the host device.

[0091] Although certain embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the controller and operating methods of the memory system should not be limited based on the described embodiments. Specifically, the controller and operating methods of the memory system described herein should only be limited according to the appended claims when combined with the foregoing description and drawings. Furthermore, embodiments may be combined to form other embodiments. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the present invention. Figure 2 is a schematic diagram illustrating the operation of the temperature increment estimation unit of Figure 1 according to an embodiment of the present invention. Figure 3 is a schematic diagram illustrating the operation of the performance adjustment unit of Figure 1 according to an embodiment of the present invention. Figure 4 is a schematic diagram illustrating the operation of the reordering unit of Figure 1 according to an embodiment of the present invention. Figure 5 is a flowchart illustrating the operation of the controller according to an embodiment of the present invention. Figure 6 is a schematic diagram illustrating a data processing system including a solid-state drive (SSD) according to an embodiment of the present invention. Figure 7 is a schematic diagram illustrating a data processing system including a memory system according to an embodiment of the present invention. Figure 8 is a schematic diagram illustrating a data processing system including a memory system according to an embodiment of the present invention. Figure 9 is a schematic diagram illustrating a network system including a memory system according to an embodiment of the present invention. Figure 10 is a block diagram illustrating a non-volatile memory device included in a memory system according to an embodiment of the present invention.

Claims

1. A memory system, comprising: Memory devices; The controller queues operation requests from the host device into a request queue and controls the memory device according to the operation requests. The controller estimates temperature increments corresponding to the operation requests and performs a reordering operation based on the temperature increments to rearrange the operation requests queued in the request queue. The controller performs the reordering operation by rearranging random and sequential requests among the operation requests such that when the temperature increments corresponding to the random and sequential requests have the same value, the random request is rearranged to be dequeued from the request queue earlier than the sequential request.

2. The memory system as described in claim 1, wherein, The controller estimates the temperature increment by calculating the temperature of the memory system as one of the temperature increments corresponding to one of the operation requests, the temperature being estimated to increase as the corresponding operation request is processed.

3. The memory system as described in claim 1, wherein, The controller estimates the temperature increment by calculating one of the temperature increments corresponding to one of the operation requests based on power consumption information and operation request information corresponding to the operation request, wherein the power consumption information includes information on at least one of average power consumption and peak power consumption corresponding to the operation request, and the operation request information includes information on the data size corresponding to the operation request.

4. The memory system as described in claim 1, wherein, The controller performs the reordering operation by rearranging the operation requests, such that the operation request corresponding to the smallest temperature increment is rearranged to be the first to be dequeued from the request queue.

5. The memory system as described in claim 1, wherein, The controller performs the reordering operation by rearranging the operation requests in ascending order of the temperature increments, such that operation requests corresponding to smaller temperature increments are rearranged and dequeued from the request queue earlier than operation requests corresponding to larger temperature increments.

6. The memory system as described in claim 1, wherein, The controller performs the reordering operation when the temperature of the memory system becomes higher than the reordering trigger temperature.

7. The memory system as described in claim 6, wherein, The controller compares the temperature of the memory system with one or more performance adjustment trigger temperatures to perform a performance adjustment operation to adjust the performance of the memory system.

8. The memory system as described in claim 7, wherein, The reordering trigger temperature is the first performance adjustment trigger temperature with the lowest value among the one or more performance adjustment trigger temperatures.

9. A method for operating a controller for a memory system, the method comprising: The estimates correspond to the temperature increments of the operation requests provided by the host device. And perform a reordering operation based on the temperature increment to rearrange the operation requests queued in the request queue, wherein performing the reordering operation includes: rearranging random requests and sequential requests among the operation requests such that: when the temperature increments corresponding to the random requests and the sequential requests have the same value, the random requests are rearranged to be dequeued from the request queue earlier than the sequential requests.

10. The operating method as described in claim 9, wherein, Estimating the temperature increment includes calculating the temperature of the memory system as one of the temperature increments corresponding to one of the operation requests, the temperature being estimated to increase as the corresponding operation request is processed.

11. The operating method as described in claim 9, wherein, Estimating the temperature increment includes calculating one of the temperature increments corresponding to one of the operation requests based on power consumption information and operation request information corresponding to the operation request, wherein the power consumption information includes information on at least one of average power consumption and peak power consumption corresponding to the operation request, and the operation request information includes information on the data size corresponding to the operation request.

12. The operating method as described in claim 9, wherein, Performing the reordering operation includes rearranging the operation requests such that the operation request corresponding to the smallest temperature increment is rearranged to be the first to be dequeued from the request queue.

13. The operating method as described in claim 9, wherein, Performing the reordering operation includes rearranging the operation requests in ascending order of the temperature increment, such that operation requests corresponding to smaller temperature increments are reordered to be dequeued from the request queue earlier than operation requests corresponding to larger temperature increments.

14. The operating method as described in claim 9, wherein, Performing the reordering operation includes performing the reordering operation when the temperature of the memory system becomes higher than the reordering trigger temperature.

15. The method of operation as described in claim 14 further includes comparing the temperature of the memory system with one or more performance tuning trigger temperatures to perform a performance tuning operation for adjusting the performance of the memory system.

16. The operating method as described in claim 15, wherein, The reordering trigger temperature is the first performance adjustment trigger temperature that has the lowest value among the one or more performance adjustment trigger temperatures.

17. A memory system, comprising: Memory devices; The controller queues operation requests from the host device into a request queue and controls the memory device according to the operation requests. The controller estimates temperature increments corresponding to the operation requests, and when the temperature of the memory system becomes higher than a reordering trigger temperature, reorders the operation requests queued in the request queue based on the temperature increments, such that the temperature rise of the memory system is delayed. The controller also compares the temperature of the memory system with one or more performance adjustment trigger temperatures to change the performance mode of the memory system. Furthermore, the controller performs a reordering operation by reordering random and sequential requests among the operation requests, such that when the temperature increments corresponding to the random and sequential requests have the same value, the random request is reordered to be dequeued from the request queue earlier than the sequential request.

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