Integrated circuit device and electronic device including the same

Abstract

This invention provides an integrated circuit device comprising a substrate and a unit cell on the substrate. The unit cell defines a unit cell region comprising at least two discrete devices. The unit cell includes: a wiring layer configured to route signals and voltages to the at least two discrete devices, the wiring layer including signal lines and voltage lines extending in a first direction and spaced apart from each other in a second direction; and a metal wire stack including metal wires stacked between the unit cell region and the wiring layer in the first direction. A plurality of contact vias are each configured to connect the signal lines, voltage lines, metal wires, and at least two adjacent of the at least two discrete devices in a third direction.

Description

Technical Field

[0001] Some example embodiments of the inventive concept described herein relate to integrated circuit devices, electronic devices including integrated circuit devices, integrated circuit devices capable of high-speed operation, and / or electronic devices including integrated circuit devices. Cross-reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10-2022-0058845, filed on May 13, 2022, and Korean Patent Application No. 10-2021-0155150, filed on November 11, 2021, with the Korean Intellectual Property Office, and the disclosures of each of the applications are incorporated herein by reference in their entireties.

Background Art

[0003] The operating speed required or desired for integrated circuit devices is increasing rapidly. In this case, due to the influence of parasitic components of the integrated circuit device, a voltage drop depending on high-speed operation may occur. Alternatively, the performance of the integrated circuit device may be degraded due to an increase in current density depending on high-speed operation. In addition, in this case, errors may occur in the operation of an electronic device including the integrated circuit device.

Summary of the Invention

[0004] Some example embodiments of the inventive concept provide an integrated circuit device and an electronic device including the integrated circuit device that can operate stably even in high-speed operation.

[0005] According to an example embodiment, an integrated circuit device includes a substrate and unit cells on the substrate, wherein the unit cells define a unit cell region including at least two discrete devices. The unit cells include: a wiring layer configured to route signals and voltages to at least two discrete devices, the wiring layer including signal lines and voltage lines extending in a first direction, and the signal lines and voltage lines being spaced apart from each other in a second direction; a metal wire stack including metal wires stacked in the first direction between the unit cell region and the wiring layer; and a plurality of contact vias, each configured to connect at least two adjacent ones of the signal lines, voltage lines, metal wires, and at least two discrete devices in a third direction.

[0006] The wiring layer may include at least two layers.

[0007] At least one of the signal lines and voltage lines may include two or more than two lines, and signal lines or voltage lines positioned adjacent to each other among the signal lines and voltage lines may be evenly spaced apart from each other by a first separation distance.

[0008] For each of the discrete device, signal line, voltage line, and metal line, the same number of contact VIAs can be formed.

[0009] The metal line stack can be formed separately for the signal line and the voltage line.

[0010] In the unit cell, the routing of signals and voltages for at least two discrete devices can be performed in a third direction.

[0011] Among the metal lines, the metal lines positioned adjacent to the unit cell region can have a higher resistance value than the metal lines positioned adjacent to the wiring layer, and among the metal lines, the signal line and the voltage line can have a lower resistance value than the metal lines positioned adjacent to the signal line and the voltage line.

[0012] m*n unit cells (where m and n are integers of 1 or greater than 1) can form a unit cell array. m unit cells can be arranged in a first direction to form n columns of the unit cell array, and the unit cells positioned adjacent to each other in the first direction can be electrically isolated by a device isolation film.

[0013] The signal lines, voltage lines, and metal lines positioned adjacent to each other in the first direction can be connected respectively, and the unit cells positioned adjacent to each other in the first direction can be routed by the connected signal lines and the connected voltage lines.

[0014] The integrated circuit device can further include an array signal line connecting the signal lines of n columns, and an array voltage line connecting the voltage lines of n columns.

[0015] Among the n columns, the columns positioned adjacent to each other in a second direction can be separated by a second separation distance.

[0016] The signal lines and the voltage lines can be arranged in the same sequence in the second direction for each of the n columns.

[0017] When the driving strength of a unit cell is 1, the driving strength of the unit cell array can be m*n.

[0018] p*q unit cells (where p and q are integers of 1 or greater than 1) can further form a second unit cell array, and the first unit cell array and the second unit cell array can be electrically connected.

[0019] The signal lines may include input signal lines and output signal lines for routing input signals and output signals for at least two discrete devices. The voltage lines may include a power voltage line and a ground voltage line for applying a power voltage and a ground voltage to at least two discrete devices. The at least two discrete devices may include an NMOS transistor and a PMOS transistor, wherein an input signal is applied to the gate, an output signal is output from the source-drain region, and a power voltage or a ground voltage is applied to the source-drain region.

[0020] Each of the NMOS transistor and the PMOS transistor may be a planar field effect transistor (planar FET), a fin FET, a gate all around FET (GAAFET), or a multi-bridge channel FET (MBCFET), but the example embodiments are not limited thereto.

[0021] According to an example embodiment, an integrated circuit device including a unit inverter, wherein the unit inverter includes: an NMOS transistor and a PMOS transistor located in a unit cell region of a substrate; an input signal line, an output signal line, a power voltage line, and a ground voltage line extending in a first direction and configured to route an input signal, an output signal, a power voltage, and a ground voltage to the NMOS transistor and the PMOS transistor; and a metal wire stack including metal wires extending in the first direction and stacked one above the other, wherein the metal wires include at least one individual metal wire corresponding to each of the input signal line, the output signal line, the power voltage line, and the ground voltage line, and wherein the metal wires connect the NMOS transistor and the PMOS transistor to the corresponding ones of the input signal line, the output signal line, the power voltage line, and the ground voltage line via contact vias.

[0022] Signal lines or voltage lines that are positioned adjacent to each other among the input signal line, the output signal line, the power voltage line, and the ground voltage line may be spaced apart from each other in a second direction by a first separation distance.

[0023] When a metal wire positioned adjacent to an NMOS transistor or a PMOS transistor in a third direction among the metal wires of a metal wire stack is referred to as a first metal wire, and a metal wire positioned adjacent to an input signal line, an output signal line, a power supply voltage line, or a ground voltage line in the third direction is referred to as a k-th metal wire (k is an integer of 2 or greater than 2), at least two vias can be formed between the NMOS transistor or the PMOS transistor and the first metal wire, between the metal wires positioned adjacent to each other in the third direction among the metal wires of the metal wire stack, and between the k-th metal wire and the input signal line, the output signal line, the power supply voltage line, or the ground voltage line.

[0024] When a metal wire positioned adjacent to an NMOS transistor or a PMOS transistor in a third direction among the metal wires of a metal wire stack is referred to as a first metal wire, and a metal wire positioned adjacent to an input signal line, an output signal line, a power supply voltage line, or a ground voltage line in the third direction is referred to as a k-th metal wire (k is an integer of 2 or greater than 2), the k-th metal wire can have a lower resistance value than the first metal wire, and the input signal line, the output signal line, the power supply voltage line, or the ground voltage line can have a lower resistance value than the k-th metal wire.

[0025] m * n unit inverters can form a unit inverter array. m unit inverters can be arranged in a first direction to form n columns of the unit inverter array, and the unit inverters positioned adjacent to each other in the first direction can be electrically isolated by a device isolation film.

[0026] The input signal line, the output signal line, the power supply voltage line, and the ground voltage line can be connected in the first direction. The integrated circuit device can further include: an array input line connecting the input signal lines of n columns; an array output line connecting the output signal lines of n columns; an array power line connecting the power supply voltage lines of n columns; and an array ground line connecting the ground voltage lines of n columns.

[0027] The columns positioned adjacent to each other in a second direction among the n columns can be separated from each other by a second separation distance.

[0028] The input signal line, the output signal line, the power supply voltage line, and the ground voltage line can be arranged in the same sequence in the second direction for each of the n columns.

[0029] When the driving strength of a unit inverter is 1, the driving strength of the unit inverter array can be m * n.

[0030] The integrated circuit device may further include a ring oscillator, where an odd number of driving inverters greater than or equal to three are disposed between a first end and a second end, and each of the driving inverters includes one or more unit inverter arrays. Among the driving inverters positioned adjacent to each other in a first direction, the output of the driving inverter positioned adjacent to the first end may be applied as the input of the driving inverter positioned adjacent to the second end, and the output of the driving inverter closest to the second end may be fed back to the driving inverter closest to the first end.

[0031] The integrated circuit device may further include a clock driver, where at least two driving inverters are disposed between a first end and a second end, each of the at least two driving inverters includes one or more unit inverter arrays, and among the driving inverters positioned adjacent to each other in a first direction, the output of the driving inverter positioned adjacent to the first end may be applied as the input of the driving inverter positioned adjacent to the second end.

[0032] According to an example embodiment, an electronic device includes an integrated circuit device and a functional block that operates in response to a clock or a signal generated or controlled by the integrated circuit device.

Embodiments

[0034] Hereinafter, some embodiments of the inventive concept will be described clearly and in detail.

[0035] FIG. 1 is a view showing an integrated circuit device including a unit cell according to an example embodiment of the inventive concept.

[0036] Referring to FIG. 1, an integrated circuit device 100 according to an example embodiment of the present disclosure may include a substrate 110 and at least one unit cell UC formed on the substrate 110.

[0037] The substrate 110 may contain one or more semiconductor materials, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or silicon germanium carbon (SiGeC), but the example embodiment is not limited thereto. The substrate 110 may be a bulk silicon substrate or a semiconductor on insulator (SOI) substrate.

[0038] The unit cell UC may refer to a circuit in which at least two discrete devices DD1 and discrete device DD2 are electrically connected to perform a unit operation. The unit operation may refer to, for example, the logical product, logical sum, logical complement, logical inversion, storage, or delay of a unit input or unit data. The discrete device DD1 and the discrete device DD2 may refer to, for example, transistors, diodes, light-emitting diodes (LEDs), photodiodes, inductors, resistors, or capacitors, but the example embodiments are not limited thereto.

[0039] The unit cell UC may include a unit cell region 120, a wiring layer 130, a metal wire stack 140, and a plurality of contacts VIA 150.

[0040] The unit cell region 120 may be formed on a local region of the substrate 110. The unit cell region 120 may be isolated from another region of the substrate 110 adjacent to the unit cell region 120 in a first direction (e.g., the x-axis direction) or a second direction (e.g., the y-axis direction) by a device isolation membrane (not shown). The device isolation membrane may contain an insulating material such as silicon oxide.

[0041] At least two discrete devices DD1 and discrete device DD2 may be formed in the unit cell region 120. As described above, the discrete devices DD1 and DD2 may be transistors.

[0042] The wiring layer 130 may route signals and voltages for the discrete devices DD1 and discrete device DD2. The wiring layer 130 may include signal lines XL for routing signals for the discrete devices DD1 and discrete device DD2 and voltage lines VL for routing voltages for the discrete devices DD1 and discrete device DD2. The signal lines XL and the voltage lines VL may be connected to an external control logic (not shown) or a power supply (not shown), and may transmit and receive signals or voltages.

[0043] The signal lines XL and the voltage lines VL may be formed in the x-axis direction and may be spaced apart from each other in the y-axis direction.

[0044] The metal wire stack 140 may be formed between the unit cell region 120 and the wiring layer 130. For example, the metal wire stack 140 may be formed between the discrete devices DD1 and discrete device DD2 in the unit cell region 120 and the signal lines XL and the voltage lines VL of the wiring layer 130.

[0045] The metal wire stack 140 can be provided separately for the signal line XL and the voltage line VL. For example, two metal wire stacks 140 can be provided for one signal line XL and one voltage line VL. In some exemplary embodiments, when the signal line XL and the voltage line VL are spaced apart from each other in the y-axis direction, the two metal wire stacks 140 can also be spaced apart from each other in the y-axis direction.

[0046] The metal wire stack 140 can be formed by stacking metal wires ML in multiple layers. The metal wire ML can be formed of aluminum (Al), tungsten (W), titanium (Ti), or copper (Cu), but the exemplary embodiments are not limited thereto. The insulating layer 160 can be formed between the metal wires ML. Similar to the signal line XL or the voltage line VL, the metal wire ML can be formed in the x-axis direction.

[0047] The metal wire ML constituting the metal wire stack 140 can have a higher resistance value when positioned adjacent to the unit cell region 120 in the third direction (e.g., the z-axis direction) than when positioned adjacent to the wiring layer 130 in the third direction. The resistance value can refer to the resistance value per unit area and per unit length of the metal wire ML. Hereinafter, it is the same. In addition, the resistance value of the metal wire ML constituting the metal wire stack 140 can decrease as the separation distance from the unit cell region 120 in the z-axis direction increases.

[0048] Similar to the metal wire ML, the signal line XL and the voltage line VL can be formed of metal components. Among the metal wires ML constituting the metal wire stack 140, the signal line XL and the voltage line VL can have a lower resistance value than the metal wires ML positioned adjacent to the signal line XL and the voltage line VL.

[0049] Multiple vias VIA 150 can connect the discrete devices DD1 and DD2, the signal line XL or the voltage line VL, and the corresponding devices or lines among the multiple metal wires ML. The multiple vias VIA 150 can connect the discrete devices DD1 and DD2 and the metal wire ML positioned adjacent to the multiple vias VIA 150 in the z-axis direction, can connect the metal wires ML positioned adjacent to each other in the z-axis direction, can connect the metal wires ML and the signal line XL positioned adjacent to each other in the z-axis direction, or can connect the metal wires ML and the voltage line VL positioned adjacent to each other in the z-axis direction. The multiple vias VIA 150 can be provided by forming holes in the insulating layer 160 and then filling the holes with a conductive material, and the holes are formed between the discrete devices DD1 and DD2 and the metal wire ML adjacent to each other in the z-axis direction, between the metal wires ML adjacent to each other in the z-axis direction, between the metal wires ML and the signal line XL adjacent to each other in the z-axis direction, or between the metal wires ML and the voltage line VL adjacent to each other in the z-axis direction.

[0050] In the unit cell UC of the integrated circuit device 100 having the above structure, routing can be performed between the signal line XL or the voltage line VL of the wiring layer 130 and the discrete devices DD1 and DD2 only in one direction (i.e., the z-axis direction). That is, signals or voltages can be transmitted in the z-axis direction to adjacent devices or lines via the contact VIA 150 only, and thus the length of the wiring required or needed for routing can be reduced or minimized. In addition, when routing is performed via the metal wire stack 140 composed of multiple metal wires ML in the unit cell UC, the resistance components of the metal wires ML in each layer can be processed in parallel, and thus the influence of the resistance on the routing of signals or voltages in the unit cell UC can be reduced or minimized.

[0051] Therefore, the integrated circuit device 100 according to some exemplary embodiments of the present inventive concept can reduce or minimize the influence of resistance on routing in the unit cell UC. Therefore, the integrated circuit device 100 according to some exemplary embodiments of the present inventive concept can reduce the parasitic resistance that resists routing to suppress or prevent voltage drops caused by the parasitic resistance, thereby stably performing high-speed operations.

[0052] Regarding the matters of the first direction, the second direction, and the third direction defined in FIG. 1, such as the x-axis direction, the y-axis direction, and the z-axis direction, can be applied in the same way to the diagrams to be described below.

[0053] FIG. 2 is a view showing signal lines and voltage lines according to an exemplary embodiment of the present disclosure.

[0054] Referring to FIGS. 1 and 2, the number and type of the signal line XL and the voltage line VL of the wiring layer 130 according to an exemplary embodiment of the present inventive concept can correspond to the number and type of the discrete devices DD1 and DD2. For example, as many signal lines XL as the signals applied to or output from the discrete devices DD1 and DD2 can be provided. For example, as many voltage lines VL as the types of voltages applied to the discrete devices DD1 and DD2 can be provided.

[0055] When multiple signal lines XL or voltage lines VL are arranged as described above, the lines adjacent to each other among the signal lines XL and the voltage lines VL can be evenly spaced apart from each other by a first separation distance d1 in the y-axis direction. Although FIG. 2 shows an example of alternatively arranging the signal lines XL and the voltage lines VL, the present disclosure is not limited thereto.

[0056] FIG. 3 is a view showing a contact VIA according to an exemplary embodiment of the present inventive concept.

[0057] Referring to FIGS. 2 and 3, in an exemplary embodiment according to the concept of the present invention, the contact VIA 150 may be disposed between the layers of the unit cell UC, that is, between the discrete device DD1 and the discrete device DD2 and the metal line ML, between the metal lines ML of the metal line stack 140, and between the metal line ML and the signal line XL or the voltage line VL. In addition, the same or substantially the same number of contact VIAs 150 may be disposed between the layers. However, without being limited thereto, the number of contact VIAs formed between some layers of the unit cell UC may be different from the number of contact VIAs formed between other layers of the unit cell UC.

[0058] The number of contact VIAs 150 formed in the unit cell region 120 may be limited by the design rules applied in the design of the unit cell UC. In the unit cell UC of an exemplary embodiment according to the concept of the present invention, the signal lines XL or the voltage lines VL may be evenly spaced apart from each other by a first separation distance d1, and thus an increased or maximum number of contact VIAs 150 may be provided while conforming to the design rules. Therefore, the resistance components of the contact VIAs 150 can be processed in parallel, and thus the influence of the resistance routed in the unit cell UC can be reduced or minimized.

[0059] FIG. 4 is a view showing a wiring layer according to an exemplary embodiment of the present disclosure.

[0060] Referring to FIG. 4, the wiring layer 130 of an exemplary embodiment according to the concept of the present invention may include two or more than two layers. For example, the wiring layer 130 may be disposed in multiple layers depending on the magnitude of the signal or voltage required for the signal line XL or the voltage line VL, the width of the wiring, the separation distance between the lines, and the like. In each of the multiple wiring layers 130, the signal lines XL and the voltage lines VL may be disposed in the same or different manners.

[0061] FIG. 5 is a view showing an integrated circuit device including an array of unit cells according to an exemplary embodiment of the concept of the present invention.

[0062] Referring to FIGS. 1 and 5, the integrated circuit device 100 of an exemplary embodiment according to the concept of the present invention may include m*n unit cells UC in an array form. That is, the integrated circuit device 100 of an exemplary embodiment according to the concept of the present invention may include a unit cell array UCA having m unit cells UC in the x-axis direction and n unit cells UC in the y-axis direction. m and n may be integers of 1 or greater. In the unit cell array UCA, the m unit cells UC in the x-axis direction may be referred to as a row RW, and the n unit cells UC in the y-axis direction may be referred to as a column CL.

[0063] In the unit cell array UCA, each of the m unit cells UC that make up a row RW can be formed to contact a unit cell UC positioned adjacent to each of the m unit cells UC in the x-axis direction on the base 110. That is, each of the m unit cells UC can be formed to contact the unit cell region 120 of the unit cell UC positioned adjacent to each of the m unit cells UC in the x-axis direction on the base 110. The adjacent unit cell regions 120 can be electrically isolated by a device isolation film (not shown).

[0064] As described above, a merged or shared region (e.g., a drain region between adjacent unit cells) does not exist between unit cells UC positioned adjacent to each other in the x-axis direction. Therefore, the integrated circuit device 100 according to some exemplary embodiments of the present inventive concept can prevent current in the merged region from concentrating on one side of unit cells UC positioned adjacent to each other to cause a voltage drop.

[0065] The signal line XL, voltage line VL, and metal line ML in FIG. 1 can together provide each of the unit cells UC that make up the row RW of the unit cell array UCA. That is, the signal line XL, voltage line VL, and metal line ML in FIG. 1 can extend or be connected in the x-axis direction and can be connected to each of the unit cells UC that make up the row RW of the unit cell array UCA.

[0066] Since routing is performed only in the z-axis direction within one unit cell UC as described above, routing between unit cells UC positioned adjacent to each other in the x-axis direction can be performed only by the signal line XL and voltage line VL. That is, the metal line ML of the metal line stack 140 is not involved in routing between unit cells UC positioned adjacent to each other in the x-axis direction.

[0067] As described above, when routing a signal or voltage between unit cells UC positioned adjacent to each other in the x-axis direction, the integrated circuit device 100 according to some exemplary embodiments of the present inventive concept can perform routing by the signal line XL and voltage line VL of the wiring layer 130 having a relatively low resistance value, thereby reducing or minimizing the influence of the resistance of the routing and stably performing high-speed operations.

[0068] FIG. 6 is a view showing the configuration of signal lines and voltage lines in a unit cell array according to an exemplary embodiment of the present inventive concept.

[0069] Referring to FIGS. 5 and 6, each of the n rows RW1 to RWn of the unit cell array UCA can be formed to be separated from a row RW adjacent to each of the n rows RW1 to RWn in the y-axis direction on the substrate 110 by a second separation distance d2 in the y-axis direction. For example, the first row RW1 and the second row RW2 can be formed to be separated from each other by the second separation distance d2. That is, each of the n unit cells UC constituting a row CL can be formed to be separated from a unit cell UC located adjacent to each of the n unit cells UC in the y-axis direction on the substrate 110. The second separation distance d2 can correspond to the width of the power rail connected to the row RW.

[0070] In each of the n rows RW1 to RWn of the unit cell array UCA, the sequence of the signal lines XL or the voltage lines VL in the y-axis direction can be the same or substantially the same. For example, when the signal line XL and the voltage line VL are sequentially arranged in the y-axis direction for the first row RW1, the signal line XL and the voltage line VL can even be sequentially arranged in the y-axis direction in the second row RW2. Although not shown, the same applies to the case where multiple signal lines XL and multiple voltage lines VL are provided as in FIG. 2.

[0071] As described above, the unit cell array UCA according to an embodiment of the present disclosure can prevent the following problem: when the distance between the rows RW is shorter than the second separation distance d2 or the rows RW are in contact with each other, the signal lines XL or the voltage lines VL are combined or shared to increase the current density.

[0072] FIG. 7 is a view showing an integrated circuit device including an array signal line and an array voltage line according to an embodiment of the present disclosure.

[0073] Referring to FIGS. 1 and 7, the integrated circuit device 100 according to an exemplary embodiment of the present inventive concept can further include an array signal line AXL and an array voltage line VAL connecting the signal lines XL and the voltage lines VL of the unit cell array UCA. When the metal wire stack 140 is formed below the wiring layer 130 of each unit cell UC in the z-axis direction, the array signal line AXL and the array voltage line AVL can be formed above the wiring layer 130 of each unit cell UC. In addition, the array signal line AXL and the array voltage line AVL can be formed in the y-axis direction.

[0074] The array signal line AXL can be connected to the signal lines XL of rows RW1 to RWn of the unit cell array UCA. The array signal line AXL can receive a main input from the outside and can apply the main input to the discrete devices DD1 and DD2, or can receive the signals applied to the signal line XL from the discrete devices DD1 and DD2 and can transfer the signals to the outside as the main output. The array voltage line AVL can be connected to the voltage lines VL of rows RW1 to RWn of the unit cell array UCA and can apply a voltage from the outside to the discrete devices DD1 and DD2. Although not shown, when a plurality of signal lines XL and a plurality of voltage lines VL are provided as in FIG. 2, the same or substantially the same number of array signal lines AXL and array voltage lines AVL as the signal lines XL and voltage lines VL can be provided.

[0075] FIGS. 8 and 9 are views showing an integrated circuit device including a plurality of unit cell arrays according to an exemplary embodiment of the concept of the present invention.

[0076] Referring to FIGS. 5 and 8, an integrated circuit device 100 according to an exemplary embodiment of the concept of the present invention may include a plurality of unit cell arrays UCA. Each of the unit cell arrays UCA may include the same number of unit cells UC or a different number of unit cells UC. For example, the first unit cell array UCA1 may include m*n unit cells UC, and the second unit cell array UCA2 may include p*q unit cells UC. m*n may be equal to or different from p*q.

[0077] The number of unit cells UC included in each unit cell array UCA may correspond to the driving strength required for the unit cell array UCA. For example, when the driving strength of the unit cell UC of the integrated circuit device 100 according to an exemplary embodiment of the concept of the present invention is "1", the driving strength of the first unit cell array UCA1 including m*n unit cells UC may be "m*n", and the driving strength of the second unit cell array UCA2 including p*q unit cells UC may be "p*q". p and q may be 1 or integers greater than 1. The required or maximum number of unit cells UC included in each unit cell array UCA may be set to correspond to the power consumption of the unit cell array UCA or the allowable power consumption of the entire integrated circuit device 100.

[0078] In addition, although not shown, a plurality of unit cell arrays UCA may be electrically connected. For example, the main output of the first unit cell array UCA1 may be input to the second unit cell array UCA2 as the main input of the second unit cell array UCA2.

[0079] The number of unit cells UC in each of the unit cell arrays UCA included in the unit cell array UCA and the connection relationship between the unit cell arrays UCA can correspond to the operations required or desired by the integrated circuit device 100. For example, the number of unit cells UC in each of the unit cell arrays UCA included in the unit cell array UCA and the connection relationship between the unit cell arrays UCA can be set to correspond to the oscillation, buffering, and driving required by the integrated circuit device 100.

[0080] Referring to FIGS. 5 and 9, the integrated circuit device 100 according to an exemplary embodiment of the present invention concept may include a plurality of unit cell arrays UCA stacked one above the other. The number of unit cells UC in the unit cell arrays UCA included in each layer and the connection relationship between the unit cell arrays UCA of the respective layers are the same as or substantially the same as those described with reference to FIG. 8.

[0081] FIGS. 10 to 12 are perspective views, plan views, and side views of a unit inverter according to an exemplary embodiment of the present invention concept.

[0082] Referring to FIGS. 1 and 10 to 12, the unit inverter UI may be provided as a unit cell UC in the integrated circuit device 100 according to an exemplary embodiment of the present invention concept. In some exemplary embodiments, the discrete device DD1 and the discrete device DD2 may be a PMOS transistor PT and an NMOS transistor NT, the signal line XL may include an input signal line IXL and an output signal line OXL, and the voltage line VL may include a power supply voltage line DVL and a ground voltage line SVL.

[0083] Although FIGS. 10 to 12 show an example in which the ground voltage line SVL, the output signal line OXL, the input signal line IXL, and the power supply voltage line DVL are arranged in sequence in the y-axis direction, the present invention concept is not limited thereto and the sequence may be changed. The ground voltage line SVL, the output signal line OXL, the input signal line IXL, and the power supply voltage line DVL may be evenly spaced apart from each other by a first separation distance d1 in the y-axis direction.

[0084] The metal wire stack 140 may be formed separately for the input signal line IXL, the output signal line OXL, the power supply voltage line DVL, and the ground voltage line SVL. The metal wires ML of the metal wire stack 140 and the input signal line IXL, the output signal line OXL, the power supply voltage line DVL, and the ground voltage line SVL of the wiring layer 130 may all be formed in the x-axis direction.

[0085] In the metal wire stack 140, the resistance value of the metal wire adjacent to the unit cell region 120 in the z-axis direction (i.e., the resistance value of the first metal wire ML) can be higher than the resistance value of the metal wire ML adjacent to the wiring layer 130 (i.e., the resistance value of the fourth metal wire ML). The resistance value of the second metal wire ML can be less than or equal to the resistance value of the first metal wire ML and can be higher than the resistance value of the third metal wire ML. Similarly, the resistance value of the third metal wire ML can be less than or equal to the resistance value of the second metal wire ML and can be higher than the resistance value of the fourth metal wire ML. The resistance values of the input signal line IXL, the output signal line OXL, the power supply voltage line DVL, and the ground voltage line SVL can be less than the resistance value of the fourth metal wire ML. Although FIGS. 10 to 12 show an example in which the metal wire stack 140 includes a total of four metal wires ML, the inventive concept is not limited thereto.

[0086] In an example where the metal wire stack 140 includes a total of four metal wires ML, at least two contacts VIA 150 can be disposed between the PMOS transistor PT or the NMOS transistor NT and the first metal wire ML, between the first metal wire ML and the second metal wire ML, between the second metal wire ML and the third metal wire ML, between the third metal wire ML and the fourth metal wire ML, and between the fourth metal wire ML and the input signal line IXL, the output signal line OXL, the power supply voltage line DVL, or the ground voltage line SVL.

[0087] For example, since the ground voltage line SVL, the output signal line OXL, the input signal line IXL, and the power supply voltage line DVL are evenly spaced apart from each other by a first separation distance d1 in the y-axis direction as described above, one or at most two contacts VIA 150 can be formed between the layers of the unit inverter UI (i.e., between the PMOS transistor PT or the NMOS transistor NT and the first metal wire ML, between the first metal wire ML and the second metal wire ML, between the second metal wire ML and the third metal wire ML, between the third metal wire ML and the fourth metal wire ML, and between the fourth metal wire ML and the input signal line IXL, the output signal line OXL, the power supply voltage line DVL, or the ground voltage line SVL) under the condition of conforming to the design rules of the unit inverter UI.

[0088] However, the inventive concept is not limited thereto. Depending on changes in the design rules or changes in the materials of the transistors or metal wires, three or more than three contacts VIA 150 can be disposed between the layers of the unit inverter UI. Alternatively, the number of contacts VIA 150 formed between one or more layers can be different from the number of contacts VIA 150 formed between other layers.

[0089] As described above, in the integrated circuit device 100 according to some example embodiments of the present invention concept, the unit inverter UI has the above structure, and thus the routing of signals or voltages in the unit inverter UI can be performed in one direction (e.g., the z-axis direction). Therefore, the influence of resistance on routing can be reduced or minimized. In addition, in the integrated circuit device 100 according to some example embodiments of the present invention concept, the unit inverter UI includes the desired or maximum number of vias VIA, and thus the influence of resistance on routing can be reduced or minimized.

[0090] FIG. 13 is a view showing the structure of a unit inverter according to an example embodiment of the present invention concept.

[0091] Referring to FIGS. 10 and 13, the unit inverter UI according to an example embodiment of the present invention concept may include an NMOS transistor NT and a PMOS transistor PT that are positioned adjacent to each other in the y-axis direction in the unit cell region 120.

[0092] The input signal line IXL may be electrically connected to the contact CT1 of the gate GT shared by the NMOS transistor NT and the PMOS transistor PT. The output signal line OXL may be electrically connected to the contact CT2 connecting the source-drain regions SD of the NMOS transistor NT and the PMOS transistor PT. The power supply voltage line DVL may be electrically connected to the contact CT3 connecting the source-drain region SD of the PMOS transistor PT and the first doped region DA1. The ground voltage line SVL may be electrically connected to the contact CT4 connecting the source-drain region SD of the NMOS transistor NT and the second doped region DA2. The first doped region DA1 and the second doped region DA2 may be doped with n+ and p+, respectively.

[0093] The positions and numbers of the contacts CT1 to CT4 in FIG. 13 may vary depending on the contact VIA 150 in FIG. 10.

[0094] The NMOS transistor NT and the PMOS transistor PT according to some example embodiments of the present invention concept may be implemented by a planar field effect transistor (planar FET), a fin FET, a gate-all-around FET (GAAFET), or a multi-bridge channel FET (MBCFET), but the example embodiments are not limited thereto.

[0095] FIGS. 14 and 15 are perspective views and plan views of a unit inverter array including a unit inverter according to an example embodiment of the present invention concept.

[0096] Referring to FIGS. 14 and 15, an integrated circuit device 100 according to an exemplary embodiment of the present invention concept may include a unit inverter array UIA in which unit inverters UI are arranged in an array. For example, a unit inverter array UIA according to an exemplary embodiment of the present invention concept may include three rows RW, and each of the three rows RW is formed of 10 unit inverters UI that are continuously located in the x-axis direction. In each of the rows RW, the unit inverters UI that are positioned adjacent to each other in the x-axis direction may be electrically isolated by a device isolation film (not shown). Therefore, the influence of the voltage drop in the merged region of the unit inverters UI that are positioned adjacent to each other in the x-axis direction can be reduced or eliminated.

[0097] When the driving strength of one unit inverter UI is “1X”, the driving strength of a unit inverter array UIA including 30 unit inverters UI may be “30X”.

[0098] Input signal lines IXL, output signal lines OXL, power supply voltage lines DVL, ground voltage lines SVL, and metal lines ML may jointly provide the unit inverters UI that constitute the rows RW of the unit inverter array UIA. Since routing is only performed in the z-axis direction within only one unit inverter UI as described above, routing between the unit inverters UI that are positioned adjacent to each other in the x-axis direction may be performed only by the input signal lines IXL, output signal lines OXL, power supply voltage lines DVL, and ground voltage lines SVL. That is, the metal lines ML of the metal line stack 140 may not be involved in routing between the unit inverters UI that are positioned adjacent to each other in the x-axis direction.

[0099] As described above, when routing signals or voltages between the unit inverters UI, the integrated circuit device 100 according to some exemplary embodiments of the present invention concept may perform routing by the input signal lines IXL, output signal lines OXL, power supply voltage lines DVL, and ground voltage lines SVL having relatively low electrical resistances, thereby minimizing the influence of the resistance of the routing and stably performing high-speed operations.

[0100] Referring to FIGS. 14 and 15, the three columns RW of the unit inverter array UIA can be spaced apart from each other by a second separation distance d2. In each of the three columns RW of the unit inverter array UIA, the sequence of the input signal line IXL, the output signal line OXL, the power supply voltage line DVL, and the ground voltage line SVL can be the same in the y-axis direction. For example, in all three columns RW, the ground voltage line SVL, the output signal line OXL, the input signal line IXL, and the power supply voltage line DVL can be arranged in sequence in the y-axis direction. Therefore, in the unit inverter array UIA of an exemplary embodiment according to the concept of the present invention, the input signal line IXL, the output signal line OXL, the power supply voltage line DVL, or the ground voltage line SVL may not be combined or shared between columns RW that are not located adjacent to each other, and thus the influence of the voltage drop of routing can be reduced or minimized.

[0101] The unit inverter array UIA may further include: an array input line AIXL connecting the input signal lines IXL of the columns RW; an array output line AOXL connecting the output signal lines OXL of the columns RW; an array power supply line ADVL connecting the power supply voltage lines DVL of the columns RW; and an array ground line ASVL connecting the ground voltage lines SVL of the columns RW.

[0102] The array input line AIXL can receive an input signal from the outside and apply the input signal to each of the unit inverters UI via the input signal line IXL. The array output line AOXL can receive the output signal applied to the output signal line OXL from each of the unit inverters UI and transfer the output signal to the outside. The array power supply line ADVL and the array ground line ASVL can supply the power supply voltage and the ground voltage applied to each of the unit inverters UI from the outside through the power supply voltage line DVL and the ground voltage line SVL. The array input line AIXL, the array output line AOXL, the array power supply line ADVL, and the array ground line ASVL can be connected to the input signal line IXL, the output signal line OXL, the power supply voltage line DVL, and the ground voltage line SVL of each column RW of the unit inverter array UIA via contacts VIA (not shown).

[0103] One, two, or more than two unit inverter arrays UIA according to an exemplary embodiment of the concept of the present invention can be provided to serve as basic units for the operation of the integrated circuit device 100. One, two, or more than two unit inverter arrays UIA serving as basic units for the operation of the integrated circuit device 100 can be referred to as driving inverters. Two or more than two unit inverter arrays UIA constituting one driving inverter can be located adjacent to each other in the x-axis direction or the y-axis direction.

[0104] FIG. 16A and FIG. 16B are views showing a ring oscillator according to an exemplary embodiment of the concept of the present invention.

[0105] Referring to FIGS. 16A and 16B, an integrated circuit device 100 according to an exemplary embodiment of the concept of the present invention may include a ring oscillator RO. FIG. 16A shows the logic circuit of a ring oscillator RO according to an exemplary embodiment of the concept of the present invention, and FIG. 16B shows the layout of a ring oscillator RO according to an exemplary embodiment of the concept of the present invention.

[0106] A ring oscillator RO according to an exemplary embodiment of the concept of the present invention may include a first drive inverter DI1, a second drive inverter DI2, and a third drive inverter DI3 connected between a first end T1 and a second end T2.

[0107] Each of the first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may include 60 unit inverters UI, each of which has a drive strength of "1X". However, without being limited thereto, a ring oscillator RO according to some exemplary embodiments of the concept of the present invention may include an odd number of drive inverters greater than or equal to five, and each of the drive inverters may include various numbers of unit inverters, such as 30 unit inverters or 120 unit inverters.

[0108] The unit inverters UI included in the first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may be the same as or substantially the same as the unit inverter UI of FIG. 10. The unit inverter array UIA included in the first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may be the same as or substantially the same as the unit inverter array UIA of FIG. 14. Each of the first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may include two unit inverter arrays UIA adjacent to each other in the y-axis direction. Therefore, the first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may have a drive strength of "60X".

[0109] The ring oscillator RO may perform an oscillation operation by applying the output A of the first drive inverter DI1 as the input of the second drive inverter DI2, applying the output B of the second drive inverter DI2 as the input of the third drive inverter DI3, and feeding back the output C of the third drive inverter DI3 to the first drive inverter DI1.

[0110] The outputs A of the first drive inverter DI1, the outputs B of the second drive inverter DI2, and the outputs C of the third drive inverter DI3 can be output from the array output line AOXL of the unit inverter array UIA included in the drive inverter DI1, the drive inverter DI2, and the drive inverter DI3. Similarly, the inputs C of the first drive inverter DI1, the inputs A of the second drive inverter DI2, and the inputs B of the third drive inverter DI3 can be input to the array input line AIXL of the unit inverter array UIA included in the drive inverter DI1, the drive inverter DI2, and the drive inverter DI3.

[0111] The ring oscillator RO according to an exemplary embodiment of the inventive concept may further include a connection line CL for connecting the array output line AOXL and the array input line AIXL of the drive inverters DI1, DI2, and DI3 positioned adjacent to each other in the x-axis direction. For example, the ring oscillator RO according to an exemplary embodiment of the inventive concept may include a connection line CL connecting the array output line AOXL of the first drive inverter DI1 and the array input line AIXL of the second drive inverter DI2, a connection line CL connecting the array output line AOXL of the second drive inverter DI2 and the array input line AIXL of the third drive inverter DI3, and a connection line CL connecting the array output line AOXL of the third drive inverter DI3 and the array input line AIXL of the first drive inverter DI1. The array output line AOXL or the array input line AIXL of the drive inverter corresponding to the connection line CL may be electrically connected via a contact VIA (not shown).

[0112] As described above, the ring oscillator RO according to some exemplary embodiments of the inventive concept may be implemented by the unit inverter UI and the unit inverter array UIA, in which the influence of the resistance on the routing of the signal or voltage is reduced or minimized, thereby stably performing high-speed operations. The ring oscillator RO according to some exemplary embodiments of the inventive concept may be included in a high-speed phased locked loop (PLL) such as a memory or a communication chip.

[0113] FIG. 17A, FIG. 17B, and FIG. 18 are views showing a clock driver according to an exemplary embodiment of the inventive concept.

[0114] Referring to FIGS. 17A and 17B, the integrated circuit device 100 according to an exemplary embodiment of the inventive concept may include a clock driver CD. FIG. 17A shows the logic circuit of the clock driver CD according to an exemplary embodiment of the inventive concept, and FIG. 17B shows the layout of the clock driver CD according to an exemplary embodiment of the inventive concept.

[0115] The clock driver CD according to an exemplary embodiment of the inventive concept may include a first drive inverter DI1, a second drive inverter DI2, and a third drive inverter DI3 connected between a first end T1 and a second end T2. The first drive inverter DI1 may include 30 unit inverters UI, each having a drive strength of "1X". The second drive inverter DI2 may include 60 unit inverters UI, each having a drive strength of "1X". The third drive inverter DI3 may include 120 unit inverters UI, each having a drive strength of "1X".

[0116] The unit inverters UI included in the first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may be the same as or substantially the same as the unit inverter UI of FIG. 10. The unit inverter array UIA included in the first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may be the same as or substantially the same as the unit inverter array UIA of FIG. 14.

[0117] The first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may respectively include one unit inverter array UIA, two unit inverter arrays UIA, and four unit inverter arrays UIA. The two unit inverter arrays UIA of the second drive inverter DI2 and the four unit inverter arrays UIA of the third drive inverter DI3 may be formed adjacent to each other in the y-axis direction. Accordingly, the drive strengths of the first drive inverter DI1, the second drive inverter DI2, and the third drive inverter DI3 may be "30X", "60X", and "120X", respectively. However, without being limited thereto, the clock driver CD according to some exemplary embodiments of the inventive concept may include two or less than two unit inverter arrays UIA or four or more than four unit inverter arrays UIA, and each of the unit inverter arrays UIA may include a different number of unit inverters UI from each unit inverter array UIA of FIGS. 17A and 17B.

[0118] In the clock driver CD according to an exemplary embodiment of the inventive concept, the signal O of the first end T1 may be applied as an input to the first drive inverter DI1, the output A of the first drive inverter DI1 may be applied as an input to the second drive inverter DI2, the output B of the second drive inverter DI2 may be applied as an input to the third drive inverter DI3, and the output C of the third drive inverter DI3 may be transferred to the second end T2.

[0119] The input O of the first driving inverter DI1, the input A of the second driving inverter DI2, and the input B of the third driving inverter DI3 can be input to the array input line AIXL of the unit inverter array UIA included in the driving inverter DI1, the driving inverter DI2, and the driving inverter DI3. Similarly, the output A of the first driving inverter DI1, the output B of the second driving inverter DI2, and the output C of the third driving inverter DI3 can be output from the array output line AOXL of the unit inverter array UIA included in the driving inverter DI1, the driving inverter DI2, and the driving inverter DI3.

[0120] The clock driver CD according to an example embodiment of the concept of the present invention may further include a connection line CL for connecting the array output line AOXL and the array input line AIXL of the driving inverters DI1, DI2, and DI3 that are positioned adjacent to each other in the x-axis direction. For example, the clock driver CD according to an example embodiment of the concept of the present invention may include a connection line CL connecting the first end T1 and the array input line AIXL of the second driving inverter DI2, a connection line CL connecting the array output line AOXL of the first driving inverter DI1 and the array input line AIXL of the second driving inverter DI2, a connection line CL connecting the array output line AOXL of the second driving inverter DI2 and the array input line AIXL of the third driving inverter DI3, and a connection line CL connecting the array output line AOXL of the third driving inverter DI3 and the second end T2. The array output line AOXL or the array input line AIXL of the driving inverter corresponding to the connection line CL may be electrically connected via a contact VIA (not shown).

[0121] Referring to FIG. 18, the integrated circuit device 100 according to an example embodiment of the concept of the present invention may include two clock drivers CD. The two clock drivers CD may be disposed adjacent to each other in the y-axis direction. The two clock drivers CD may have points that are symmetric with respect to any point P between the two clock drivers CD, and thus the area may be reduced or minimized. Different from FIG. 18, the integrated circuit device 100 according to an example embodiment of the concept of the present invention may include three or more than three clock drivers CD, and the clock drivers adjacent to each other in the y-axis direction may be configured as shown in FIG. 18.

[0122] As described above, the clock driver CD according to some example embodiments of the concept of the present invention may be implemented by the unit inverter UI and the unit inverter array UIA, wherein the influence of the resistance on the routing of the signal or voltage is reduced or minimized, thereby stably performing high-speed operations. The clock driver CD according to some example embodiments of the concept of the present invention may be included in a high-speed PLL such as a memory or a communication chip.

[0123] FIG. 19 is a view showing an electronic device according to an exemplary embodiment of the concept of the present invention.

[0124] Referring to FIG. 19, an electronic device 1000 according to an exemplary embodiment of the concept of the present invention may include the integrated circuit device 100 of FIG. 1 and the like described above. The electronic device 1000 according to an exemplary embodiment of the concept of the present invention may be a memory device or a communication device, and the electronic device 1000 includes a functional block 200 that operates in response to a signal such as a clock, and the signal is generated or controlled by the integrated circuit device 100.

[0125] The integrated circuit device 100 according to an exemplary embodiment of the concept of the present invention may be the ring oscillator RO of FIGS. 16A and 16B or the clock driver CD of FIGS. 17A and 17B included in the electronic device 1000 or the PLL of the electronic device 1000. Alternatively, the integrated circuit device 100 according to an exemplary embodiment of the concept of the present invention may be implemented by a current controlled oscillator CCO (not shown) included in the electronic device 1000 or the PLL of the electronic device 1000. Although not shown, the CCO according to some exemplary embodiments of the concept of the present invention may be implemented by the unit inverter UI of FIG. 10 and the unit inverter array UIA of FIG. 14, where the influence of resistance on the routing of signals or voltages is reduced or minimized.

[0126] In the integrated circuit device 100 according to some exemplary embodiments of the concept of the present invention, the influence of resistance on the routing of signals and voltages may be reduced or minimized, and thus the electronic device 1000 according to some exemplary embodiments of the concept of the present invention may stably perform the operations required by the electronic device 1000 even in high-speed operations (for example, high-speed operations of about 30 gigahertz).

[0127] According to the concept of the present invention, by reducing or minimizing the influence of resistance or voltage drop on the routing of signals or voltages in the integrated circuit device and the influence of electromigration (EM) which depends on the increase of current density, the integrated circuit device and the electronic device including the integrated circuit device may stably operate even in high-speed operations.

[0128] The above is an exemplary embodiment for implementing the concept of the present invention. The concept of the present invention not only includes the above exemplary embodiments but also includes exemplary embodiments that can be carried out by simple design changes or can be easily modified. In addition, the concept of the present invention includes techniques that can be carried out by easily modifying some exemplary embodiments. Therefore, the scope of the concept of the present invention should not be determined by the above exemplary embodiments.

[0129] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. It should be further understood that when an element is referred to as being "over" another element, it can be above or below or adjacent to (e.g., horizontally adjacent to) the other element.

[0130] It will be understood that elements and / or their properties described herein as being "substantially" the same and / or consistent encompass elements and / or their properties having a relative difference equal to or less than 10% in magnitude. In addition, whether or not the elements and / or their properties are modified as "substantially", it will be understood that such elements and / or their properties should be interpreted to include manufacturing or operating tolerances (e.g., ±10%) with respect to the stated elements and / or their properties.

[0131] One or more of the elements disclosed above may include or be implemented in one or more processing circuits, such as: hardware, including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, a processing circuit system more specifically may include but is not limited to: a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0132] Although the inventive concept has been described with reference to some exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the scope of the inventive concept.

Brief Description of the Drawings

[0033] The above and other objects and features of the inventive concept will become more apparent by referring to some example embodiments described in detail with reference to the accompanying drawings. FIG. 1 is a view of an integrated circuit device including a unit cell according to an example embodiment of the inventive concept. FIG. 2 is a view of signal lines and voltage lines according to an example embodiment of the inventive concept. FIG. 3 is a view of contact vias according to an example embodiment of the inventive concept. FIG. 4 is a view of a wiring layer according to an example embodiment of the inventive concept. FIG. 5 is a view of an integrated circuit device including an array of unit cells according to an example embodiment of the inventive concept. FIG. 6 is a view of the configuration of signal lines and voltage lines in an array of unit cells according to an example embodiment of the inventive concept. FIG. 7 is a view of an integrated circuit device including array signal lines and array voltage lines according to an example embodiment of the inventive concept. FIGS. 8 and 9 are views of an integrated circuit device including a plurality of arrays of unit cells according to an example embodiment of the inventive concept. FIGS. 10, 11, and 12 are a perspective view, a plan view, and a side view of a unit inverter according to an example embodiment of the inventive concept. FIG. 13 is a view of the structure of a unit inverter according to an example embodiment of the inventive concept. FIGS. 14 and 15 are a perspective view and a plan view of an array of unit inverters including a unit inverter according to an example embodiment of the inventive concept. FIGS. 16A and 16B are views of a ring oscillator according to an example embodiment of the inventive concept. FIGS. 17A, 17B, and 18 are views of a clock driver according to an example embodiment of the inventive concept. FIG. 19 is a view of an electronic device according to an example embodiment of the inventive concept.

Claims

1. An integrated circuit device, comprising: Base; and a unit cell, located on the substrate, wherein the unit cell comprises: a unit cell region comprising at least two discrete devices; A wiring layer configured to route signals and voltages to the at least two discrete devices, the wiring layer comprising signal lines and voltage lines extending in a first direction and spaced apart from each other in a second direction; a metal wire stack comprising metal lines stacked between the unit cell region and the wiring layer in the first direction; and a plurality of contact vias, each configured to connect the signal lines, the voltage lines, the metal lines, and two adjacent devices in a third direction, wherein at least one of the metal lines adjacent to the unit cell region has a higher resistance value than at least one of the metal lines adjacent to the wiring layer, and the signal lines and the voltage lines have a lower resistance value than at least one of the metal lines adjacent to the signal lines and the voltage lines.

2. The integrated circuit arrangement as claimed in claim 1, wherein the wiring layer comprises at least two layers.

3. The integrated circuit device as claimed in claim 1, wherein at least one of the signal line and the voltage line comprises two or more lines, and adjacent signal lines or voltage lines are uniformly spaced apart from each other by a first separation distance.

4. The integrated circuit device as claimed in claim 3, wherein the same number of contact vias are present for each of the discrete device, the signal line, the voltage line, and the metal line.

5. The integrated circuit arrangement as claimed in claim 1, wherein the metal lines of the metal line stack corresponding to the signal lines are separated from the metal lines of the metal line stack corresponding to the voltage lines.

6. The integrated circuit arrangement as claimed in claim 5, wherein in the unit cell, the wiring layer is configured to route the signals and voltages for the at least two discrete devices upwards.

7. The integrated circuit device as claimed in claim 1, wherein m*n unit cells define a unit cell array, and m and n are each integers greater than or equal to one, the m unit cells define n columns of the unit cell array in the first direction, and the unit cells adjacent to each other in the first direction are electrically isolated by a device isolation membrane.

8. The integrated circuit arrangement of claim 7, wherein the signal lines, the voltage lines, and the metal lines connected adjacent to each other in the first direction, and the wiring layer is configured to route the unit cells adjacent to each other in the first direction via the signal lines connected in the first direction and the voltage lines connected in the first direction.

9. The integrated circuit device as claimed in claim 8, further comprising: An array of signal lines, configured to connect the signal lines of the n columns; And array voltage lines, configured to connect the voltage lines of the n columns.

10. The integrated circuit arrangement as claimed in claim 7, wherein the columns of the n columns that are adjacent to each other in the second direction are spaced apart by a second separation distance.

11. The integrated circuit arrangement of claim 10, wherein the signal lines and the voltage lines are in the same sequence in the second direction for each of the n columns.

12. The integrated circuit arrangement as claimed in claim 7, wherein the driving strength of the unit cell array is m*n when the driving strength of the unit cell is 1.

13. The integrated circuit arrangement of claim 1, wherein the signal lines include input signal lines and output signal lines configured to route input signals and output signals for the at least two discrete devices, the voltage lines include power supply voltage lines and ground voltage lines configured to apply a power supply voltage and a ground voltage to the at least two discrete devices, and the at least two discrete devices include an NMOS transistor and a PMOS transistor, each of the NMOS transistor and PMOS transistor being configured to receive the input signal at its gate, output the output signal from its source-drain region, and receive the power supply voltage or the ground voltage at its source-drain region.

14. An integrated circuit arrangement comprising a unit inverter, wherein the unit inverter includes: an NMOS transistor and a PMOS transistor located in a unit cell region of a substrate; an input signal line, an output signal line, a power supply voltage line, and a ground voltage line extending in a first direction and configured to route an input signal, an output signal, a power supply voltage, and a ground voltage to the NMOS transistor and the PMOS transistor; and a metal line stack comprising metal lines extending in the first direction and stacked one on top of the other, wherein the metal lines include at least one individual metal line corresponding to each of the input signal line, the output signal line, the power supply voltage line, and the ground voltage line, and wherein the metal lines connect the NMOS transistor and the PMOS transistor to their corresponding counterparts among the input signal line, the output signal line, the power supply voltage line, and the ground voltage line via contact vias. At least one of the metal lines adjacent to the unit cell region has a higher resistance value than at least one of the metal lines adjacent to the wiring layer, and the input signal line, the output signal line, the power supply voltage line, and the ground voltage line have a lower resistance value than at least one of the metal lines adjacent to the input signal line, the output signal line, the power supply voltage line, and the ground voltage line.

15. The integrated circuit arrangement of claim 14, wherein the adjacent of the input signal line, the output signal line, the power supply voltage line, and the ground voltage line are spaced apart from each other by a first separation distance in a second direction.

16. The integrated circuit device as claimed in claim 14, wherein m*n unit inverters define a unit inverter array, m unit inverters extend in the first direction to define n columns of the unit inverter array, and the unit inverters adjacent to each other in the first direction are electrically isolated by a device isolation film.

17. The integrated circuit device as claimed in claim 16, further comprising: A ring oscillator comprising an odd number of drive inverters, greater than or equal to three, each drive inverter comprising one or more of the unit inverter arrays, and the drive inverters being located between a first end and a second end, wherein at least one of the drive inverters adjacent to each other in the first direction is configured to supply an output as an input to a drive inverter adjacent to the second end, the drive inverter being configured to supply an output adjacent to the first end, and the drive inverter closest to the second end being configured to feed back an output to the drive inverter closest to the first end.

18. The integrated circuit device as claimed in claim 16, further comprising: A clock driver comprising at least two drive inverters, each drive inverter comprising one or more of the unit inverter arrays, and the at least two drive inverters being located between a first end and a second end, wherein at least one of the drive inverters adjacent to each other in the first direction is configured to supply an output as an input to at least one of the drive inverters adjacent to the second end.

19. An electronic device comprising: The integrated circuit device as described in claim 1; And functional blocks configured to operate in response to clock or signal generated or controlled by the integrated circuit device.

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