Memory, data processing device including memory

Abstract

This application relates to a memory and a data processing apparatus including the memory. According to one embodiment of the present invention, the data processing apparatus includes: a memory comprising at least one cell block, the at least one cell block consisting of a setting message block configured to store setting information required for processing an image signal and a header configured to store basic information about the setting information; and a setting controller configured to receive setting information from the memory, wherein the setting controller includes: a memory mapper configured to store the setting information received from the memory; a memory controller configured to sequentially request the basic information and setting information stored in the at least one cell block; and a setting message signal output unit configured to generate and output a setting message signal and an enable signal corresponding to each cell block using the basic information and setting information received through the memory controller.

Description

[Technical Field]

[0001] This specification relates to a memory, a data processing apparatus including the memory, and a display driver apparatus including the data processing apparatus. [Previous Technology]

[0002] Liquid crystal displays (LCDs) that use liquid crystals and organic light-emitting diode (OLED) displays that use organic light-emitting diodes are representative display devices for displaying images.

[0003] Recently, with the development of semiconductor manufacturing technology and image processing technology, the commercialization and supply expansion of display elements that can easily reduce the weight and thickness of display devices and achieve high definition are proceeding rapidly. [Summary of the Invention]

[0004] The present invention aims to provide a data processing apparatus for reducing the time required to read a memory, and a display driving device including the data processing apparatus.

[0005] A data processing apparatus according to an embodiment of the present invention includes: a memory comprising at least one cell block, the at least one cell block comprising a setting message block configured to store setting messages required for processing image signals and a header configured to store basic messages about the setting messages; and a setting controller configured to receive setting messages from the memory, wherein the setting controller includes: a memory mapper configured to store setting messages received from the memory; a memory controller configured to sequentially request basic messages and setting messages stored in at least one cell block; and a setting message signal output unit configured to generate and output a setting message signal and an enable signal corresponding to each cell block using the basic messages and setting messages received through the memory controller.

Implementation Method

[0007] In this specification, it should be noted that the same reference numerals used to denote the same elements in other figures are used to denote elements wherever possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are not related to the basic configuration of the invention will be omitted. The terminology described in this specification should be understood as follows.

[0008] The advantages and features of the present invention and its implementation methods will be illustrated by the following description of embodiments with reference to the accompanying drawings. However, the present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, the present invention is limited only by the scope of the claims.

[0009] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of the present invention are merely examples, and therefore the invention is not limited to the details shown. The same reference numerals always denote the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted when determined to unnecessarily obscure the essential points of the invention.

[0010] When using the terms “comprising,” “having,” and “including” as described in this specification, an additional part may be added unless “only” is used. Unless otherwise indicated, singular terms may include plural forms.

[0011] When interpreting a component, although there is no explicit description, the component is also interpreted as including the error range.

[0012] For example, when describing time relationships, when the time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “exactly” or “immediately following” is used.

[0013] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0014] The term “at least one” should be understood to include any and all combinations of one or more of the related listed items. For example, “at least one of the first, second and third items” means a combination of all items drawn from two or more of the first, second and third items, as well as the first, second or third item.

[0015] As those skilled in the art will fully understand, the features of various embodiments of the present invention can be partially or entirely linked or combined with each other, and can interoperate with each other in various ways and be technically driven. Embodiments of the present invention can be implemented independently of each other, or can be implemented together in an interdependent relationship.

[0016] In the following, a display device including a data processing apparatus according to an embodiment of the present invention will be described in detail with reference to FIG1.

[0017] FIG1 is a configuration diagram of a display device including a display driving device according to an embodiment of the present invention.

[0018] Referring to FIG1, a display device 1000 according to an embodiment of the present invention includes a display panel 100 and a display driving device 200. Although not shown in the drawings, the display device 1000 according to an embodiment of the present invention may further include a touch driving device.

[0019] The display device 1000 is configured to perform a display function and can be implemented as a flat panel display, such as a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display.

[0020] The display panel 100 includes multiple gate lines GL1 to GLn, multiple data lines DL1 to DLm, and multiple pixels P.

[0021] Each of the multiple gate lines GL1 to GLn receives a gate pulse (or scan pulse). Each of the multiple data lines DL1 to DLm receives a data signal. The multiple gate lines GL1 to GLn and the multiple data lines DL1 to DLm are configured to intersect on the substrate to define a plurality of pixels P. Although not shown in the figures, each of the plurality of pixels P may include a thin-film transistor (not shown) connected to the adjacent gate line GL1 and data line DLj, a pixel electrode (not shown) connected to the thin-film transistor, a storage capacitor (not shown) connected to the pixel electrode, and a parasitic capacitor (not shown) formed between the gate line GL1 and the data line DLj.

[0022] The display driving device 200 includes a data processing device 210, a gating driver 220, and a data driver 230. According to one embodiment of the present invention, the data processing device 210 includes a timing controller. Although the data processing device 210 is shown as independent of the gating driver 220 and the data driver 230, the data processing device 210 may include at least one of the timing controller, the gating driver 220, and the data driver. Furthermore, the data processing device 210 may be a SoC (System-on-a-Chip) that may include at least one of the timing controller, the gating driver 220, and the data driver.

[0023] The data processing device 210 receives various timing signals (including vertical synchronization signals, horizontal synchronization signals, data enable signals, clock signals, etc.) from an external host system (not shown) to generate a gating control signal GCS for controlling the gating driver 220 and a data control signal DCS for controlling the data driver 230. Furthermore, the data processing device 210 receives image signals from the external system, converts the image signals into an image signal that can be processed by the data driver 230, and outputs the converted image signal.

[0024] At the same time, the data processing device 210 can generate an internal data enable signal by compressing the external data enable signal sent from the host system within a preset period.

[0025] According to one embodiment of the present invention, the data processing device 210 may include a setting controller that stores setting information required for outputting a strobe control signal GCS, a data control signal DCS, and an image signal.

[0026] In this case, the external host system converts the digital image data into a format suitable for display on the display panel 100 and sends the digital image data along with a timing signal to the data processing device 210. The host system can be any of a television system, set-top box, navigation system, digital optical disc (DVD) player, Blu-ray player, personal computer (PC), home theater system, and telephone system to receive the input image.

[0027] The gating driver 220 receives a gating control signal GCS from the data processing device 210. The gating control signal GCS may include a gating start pulse, a gating shift clock, a gating output enable signal, etc. The gating driver 220 generates gating pulses synchronized with the data signal through the received gating control signal, and shifts the generated gating pulses to sequentially provide the gating pulses to the gating lines GL1 to GLn. For this purpose, the gating driver 220 may include multiple gating driver ICs (not shown). Under the control of the data processing device 210, the gating driver ICs sequentially provide the gating pulses synchronized with the data signal to the gating lines GL1 to GLn to select the data lines for writing data signals. The gating pulses oscillate between gating high voltage and gating low voltage.

[0028] The data driver 230 receives a data control signal (DCS) and an image signal from the data processing device 210. The data control signal (DCS) may include a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the n source driver ICs (not shown) constituting the data driver 230. The source sampling clock is a clock signal that controls the data sampling timing of each of the source driver ICs. The source output enable signal controls the output timing of each source driver IC.

[0029] In the following, a data processing apparatus according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 5.

[0030] FIG2 is a configuration diagram of a data processing apparatus according to an embodiment of the present invention, and FIG3 is a block diagram of a setting controller including a memory according to an embodiment of the present invention. FIG4 is a view showing the structure of a memory according to an embodiment of the present invention, and FIG5 is a view showing the signals transmitted between the setting controller including the memory and the functional blocks of the data processing apparatus according to an embodiment of the present invention.

[0031] Referring to FIG2, a data processing apparatus 210 according to an embodiment of the present invention includes a receiving unit 211, a data processing unit 212, a sending unit 213, a clock generation unit 214, and a setting controller 215.

[0032] As described above, the receiving unit 211 receives data signal RGB, vertical synchronization signal Vsync / horizontal synchronization signal Hsync, data enable signal DE, and clock signal clk from an external host system, and provides these signals to the data processing unit 212 and the clock generation unit 214. Specifically, the receiving unit 211 provides data signal RGB to the data processing unit 212 and clock signal clk to the clock generation unit 214.

[0033] The data processing unit 212 can use the received data signal RGB to convert the format into one corresponding to the data channel configuration and data signal protocol. For example, the data processing unit 212 can correct the received data signal RGB and convert the format of the corrected data signal in frames into the format to be displayed on the display panel 100, so as to output the converted image signal RGB'.

[0034] In addition, the data processing unit 212 can generate a data control signal DCS and a strobe control signal GCS based on the vertical synchronization signal Vsync / horizontal synchronization signal Hsync, the data enable signal DE and the clock signal clk.

[0035] The transmitting unit 213 outputs the image signal RGB', the gating control signal GCS and the data control signal DCS generated by the data processing unit 212.

[0036] Although not shown in the figure, the transmitting unit 213 is connected to n source driver ICs. In this case, the transmitting unit 213 and the source driver ICs can transmit signals using a single-ended signaling method using one line or a differential signaling method using two lines (where the signal is displayed through the voltage difference between the two lines).

[0037] The clock generation unit 214 uses the input clock signal clk to provide the data processing unit 212 with a clock signal of the required frequency. In this case, the clock generation unit 214 fixes the phase of the clock signal so that the clock signal is output at a predetermined period. For this purpose, the clock generation unit 214 may include a phase-locked loop (PLL) circuit.

[0038] The setting controller 215 sends setting message signals to the corresponding function blocks. Specifically, the setting controller 215 can send the corresponding setting message signals to the receiving unit 211, the data processing unit 212, the sending unit 213, or the clock generation unit 214. For this purpose, the setting controller 215 includes a memory map 215a, a memory controller 215b, and a setting message signal output unit 215c. In addition, the setting controller 215 may also include a memory 216.

[0039] When powered on, the memory mapper 215a receives setting information from the memory 216. This setting information can be stored in the memory mapper 215a of the setting controller 215, and the setting information stored in the memory mapper 215a can be provided to the functional blocks of the receiving unit 211, the data processing unit 212, the sending unit 213, and the clock generation unit 214.

[0040] The memory 216 can store setting information required by the data processing device 210 to process image signals, and can provide the stored setting information to the data processing device 210.

[0041] As described above, the memory 216 may be included in the setting controller 215 of the data processing device 210. However, the present invention is not limited thereto, and the memory 216 may be located in a region of the data processing device 210 other than the setting controller 215, or it may be located in a region of the display driving device 200 other than the data processing device 210.

[0042] Memory 216 may include (but is not limited to) random access memory (RAM), such as synchronous dynamic random access memory (SDRAM), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc. Memory 216 may also store instructions and program code executed by a processor as part of performing the various techniques described herein.

[0043] As shown in Figure 4, the memory 216 includes multiple cell blocks blk1 to blkn.

[0044] The unit block blk may include setting information required for each functional block of the device including the setting controller 215 to perform its function and basic information about the setting information. Specifically, the unit block blk may include setting information for each functional block that receives setting information signals from the setting controller 215 and basic information about the setting information. For example, each unit block blk may store the setting information required for each of the drive receiving unit 211, data processing unit 212, transmitting unit 213 and clock generation unit 214.

[0045] According to one embodiment of the present invention, the unit block blk can be classified according to the function block that receives setting message signals from the setting controller 215. For example, the first unit block blk1 stores basic information about the first unit block blk1 and setting information required to drive the receiving unit 211, the second unit block blk2 stores basic information about the second unit block blk2 and setting information required to drive the data processing unit 212, the third unit block blk3 stores basic information about the third unit block blk3 and setting information required to drive the transmitting unit 213, and the nth unit block blkn stores basic information about the nth unit block blkn and setting information required to drive the clock generation unit 214.

[0046] As described above, the unit block blk can be divided into different sizes. Since the unit block blk according to one embodiment of the present invention is divided based on the size of the setting information required to drive the function blocks corresponding to each unit block, the time and memory required to read the area of ​​setting information included in the unstored memory 216 can be optimized.

[0047] Each cell block blk includes headers Header1 to Headern and setting message blocks CFG1 to CFGn. In this case, since the header is located at the beginning of the setting message block CFG in each cell block blk, the memory controller 215b, which will be described below, can receive the message stored in the header before receiving the message stored in the setting message block CFG.

[0048] According to one embodiment of the present invention, the header includes basic information about the corresponding unit block blk. Specifically, the basic information may include function block information (which is information about the function block corresponding to the setting information included in the corresponding unit block blk), output size information (which is the size information of the setting information to be output in the information stored in the setting information block CFG), and last unit block information (which indicates whether the corresponding unit block blk is the last unit block). That is, the header may include information about the function block corresponding to the setting information included in the corresponding unit block blk, output size information (which is the size information of the setting information to be output in the information stored in the setting information block CFG), and last unit block information (which indicates whether the corresponding unit block blk is the last unit block). In this case, the header header n of the nth unit block blk n, which is the last unit block, may include information indicating that the corresponding unit block is the last unit block as the last unit block information.

[0049] Because the header includes output size information (which is the size information of the setting message to be output in the message stored in the setting message block CFG), unlike conventional memory structures composed of cell blocks having a size initially set at design time, in a memory according to an embodiment of the present invention, the size of the cell block can be changed to store setting messages having a size smaller or larger than the size initially set at design time. For example, when storing setting messages having a size smaller than the size of the setting messages initially set at design time, in a conventional memory structure, it is also necessary to read the area that does not contain the setting messages. However, according to an embodiment of the present invention, since the cell block has a size corresponding to the size of the setting messages, it does not include the area where the setting messages are not stored, thereby optimizing the time and memory required to read the area where the setting messages are not stored.

[0050] The setting message block CFG stores the setting information required for the function block corresponding to the corresponding unit block blk to perform its function. For example, as described above, the first unit block blk1 stores basic information about the first unit block blk1 in the first header 1, and stores the setting information required for the receiving unit 211 to perform its function in the first setting message block CFG1; the second unit block blk2 stores basic information about the second unit block blk2 in the second header 2, and stores the setting information required for the data processing unit 212 to perform its function in the second setting message block CFG2; the third unit block blk3 stores basic information about the third unit block blk3 in the third header 3, and stores the setting information required for the sending unit 213 to perform its function in the third setting message block CFG3; and the nth unit block blkn stores basic information about the nth unit block blkn in the nth header n, and stores the setting information required for the clock generation unit 214 to perform its function in the nth setting message block CFGn.

[0051] The memory controller 215b sequentially receives messages stored in the cell block blk of the memory 216 by requesting the setting messages stored in the memory 216.

[0052] According to one embodiment of the present invention, the memory controller 215b uses the basic information of the corresponding unit block blk included in the header to determine whether to terminate the request for setting information stored in the memory. That is, after receiving the setting information of the corresponding unit block blk using the basic information of the corresponding unit block blk included in the header, the memory controller 215b determines whether to terminate the request for setting information. Specifically, the memory controller 215b analyzes the last unit block information included in the header to receive the setting information stored in the corresponding unit block blk, and then determines whether to request the information stored in the unit block blk corresponding to the next unit block blk. For example, when the header header 1 of the first unit block blk1 includes a message indicating that the corresponding block is not the last block as the last unit block information, the memory controller 215b receives the information stored in the first unit block blk1, and then requests the information stored in the second unit block blk2, which is the next unit block. At the same time, when the memory controller 215b analyzes the message indicating that the corresponding cell block is the last block and includes it as the last cell block message in the header Header n of the nth cell block blk n, which is the last cell block, it can request the setting message of the corresponding cell block, and then it can terminate the request for the setting message.

[0053] Furthermore, according to one embodiment of the present invention, the memory controller 215b uses the basic information of the corresponding cell block blk included in the header to determine the size of the message to be requested from the setting message block CFG of the corresponding cell block blk. Specifically, the memory controller 215b can request as many messages as the output size message, which is the size of the setting message required for the corresponding function block to perform its function, stored in the setting message block CFG, starting from the beginning of the corresponding cell block blk, using the output size message included in the header. For example, as shown in FIG4, when the header header 1 of the first cell block blk1 includes "150" as the output size message, the memory controller 215b can request the setting messages from 0 to 149 of the first setting message block CFG1 based on the relative address of the first setting message block CFG1. Therefore, since only the setting messages required for the function to perform its function stored in the setting message block CFG of the corresponding cell block blk can be requested and read, the time required to read areas where setting messages are not stored can be reduced.

[0054] The setting message output unit 215c receives setting messages stored in the memory 216 through the memory controller 215b, and uses the received messages to generate and output enable signals blk_en1 to blk_enn and setting message signals CFG_s for each block. Specifically, the setting message output unit 215c receives messages stored in the header of the cell block blk to analyze the basic information of the corresponding cell block blk. That is, the setting message output unit 215c obtains function block information (which is information about the function block corresponding to the setting messages included in the corresponding cell block blk), output size information (which is the size information of the message to be requested in the setting messages stored in the setting message block CFG), and last cell block information (which indicates whether the corresponding cell block blk is the last cell block). The setting message output unit 215c uses the obtained function block information, output size information, and last cell block information to generate an enable signal and a setting message signal CFG_s corresponding to each function block. For example, as shown in Figure 5, when the header 1 of the first unit block blk1 includes information about the receiving unit 211 as information about the function block, includes "150" as output size information, and includes information indicating the second unit block blk2 as next unit block information, the setting message signal output unit 215c sends the setting message stored in the first unit block blk1 from relative addresses "0" to "149" as a setting message signal CFG_s along with the enable signal blk_en1 of the first unit block blk1. Therefore, when the receiving unit 211 receives the first enable signal blk_en1 corresponding to the first unit block blk1 and the receiving unit 211, the receiving unit 211 receives the setting message signal CFG_s received along with the first enable signal blk_en1, and is thus driven using the received setting message signal CFG_s.

[0055] When the header 1 of the first unit block blk1 includes a message indicating that the corresponding block is not the last unit block message as the last unit block message, the memory controller 215b receives the message stored in the first unit block blk1 and then requests the message stored in the second unit block blk2, which is the next unit block. Therefore, as shown in FIG5, when the header 2 of the second unit block blk2 includes a message about the data processing unit 212 as a message about the function block, includes "40" as an output size message, and includes a message indicating that the corresponding block is not the last unit block as the last unit block message, the setting message signal output unit 215c sends the setting message stored from relative addresses "0" to "39" of the second unit block blk2 as the setting message signal CFG_s together with the enable signal blk_en2 of the second unit block blk2. Therefore, when the enable signal blk_en2 corresponding to the second unit block blk2 and the data processing unit 212 is received, the data processing unit 212 receives the setting message signal CFG_s along with the enable signal blk_en2, and is thus driven using the received setting message signal CFG_s. That is, the enable signal blk_en2 and the setting message signal CFG_s are synchronized and output, and the setting message signal CFG_s received simultaneously with the enable signal blk_en2 is used to drive the data processing unit 212, which is a function block.

[0056] According to one embodiment of the present invention, the memory 216 may be divided according to the size of the setting information to be stored, and may include a header containing basic information about the stored setting information, so as to optimize the reading time by requesting the setting information required by the drive data processing device 210 and the display drive device 200 from the memory 216.

[0057] The memory, the data processing apparatus including the memory, and the display driving apparatus including the data processing apparatus according to the present invention can optimize the time required to read the setting information of the data processing apparatus and the display driving apparatus.

[0058] It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.

[0059] Furthermore, at least a portion of the methods described herein may be implemented using one or more computer programs or components. These components may be provided as a series of computer instructions via a computer-readable or machine-readable medium including volatile and non-volatile memory. The instructions may be provided as software or firmware and may be implemented, wholly or partially, in a hardware configuration such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or other similar device. The instructions may be configured to be executed by one or more processors or other hardware components, and when one or more processors or other hardware components execute the series of computer instructions, one or more processors or other hardware components may perform, wholly or partially, the methods and processes disclosed herein.

[0060] Therefore, it should be understood that the above embodiments are not limiting but illustrative in all respects. The scope of the invention is defined by the appended claims rather than by the specific description, and it should be understood that all changes or modifications derived from the meaning and scope of the appended claims and their equivalents fall within the scope of the invention. [Simplified Explanation of the Diagram]

[0006] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the invention and, together with the text description, serve to explain the principles of the invention. In the drawings: FIG1 is a configuration diagram of a display device including a display driving device according to an embodiment of the invention; FIG2 is a configuration diagram of a data processing device according to an embodiment of the invention; FIG3 is a block diagram of a setting controller including a memory according to an embodiment of the invention; FIG4 is a view showing the structure of a memory according to an embodiment of the invention; and FIG5 is a view showing signals transmitted between a setting controller including a memory and a functional block of a data processing device according to an embodiment of the invention.

Claims

1. A data processing apparatus, the data processing apparatus comprising: The memory includes at least one cell block, the at least one cell block consisting of a setting message block configured to store setting messages required for processing image signals and a header configured to store basic messages about the setting messages; The system also includes a setting controller configured to receive setting messages from the memory, wherein the setting controller comprises: a memory mapper configured to store the setting messages received from the memory; a memory controller configured to sequentially request the basic messages and the setting messages stored in the at least one cell block; and a setting message signal output unit configured to generate and output a setting message signal and an enable signal corresponding to the at least one cell block using the basic messages and the setting messages received through the memory controller.

2. The data processing apparatus as described in claim 1, wherein, The basic message includes a last cell block message indicating whether the corresponding cell block is the last cell block.

3. The data processing apparatus as described in claim 2, wherein, The at least one cell block, excluding the last cell block, includes a message indicating that the corresponding cell block is not the last cell block.

4. The data processing apparatus as described in claim 2, wherein, The memory includes a first cell block and a second cell block, and when the last cell block message of the first cell block includes a message indicating that the corresponding cell block is not the last cell block, the memory controller receives the message stored in the first cell block and then requests the message stored in the second cell block.

5. The data processing apparatus as described in claim 2, wherein, The memory includes a first cell block, and when the last cell block message of the first cell block includes a message indicating that the corresponding cell block is the last cell block, the memory controller receives the message stored in the first cell block and then terminates the request for the setting message.

6. The data processing apparatus as claimed in claim 1, wherein, The basic information includes output size information, which is the size information of the message to be output stored in the set message block.

7. The data processing apparatus as described in claim 6, wherein, The memory includes a first cell block, the output size message of the first cell block includes a message indicating x, where x is a positive integer, and the memory controller requests a message stored in 0 or greater and x-1 or less based on the relative address of the first set message block.

8. The data processing apparatus as claimed in claim 1, wherein, The basic information includes function block information, which is information about the function block corresponding to the setting information included in the corresponding unit block.

9. The data processing apparatus as claimed in claim 8, further comprising a first functional block and a second functional block, wherein, The memory includes a first unit block and a second unit block. The first unit block includes setting messages for driving the first functional block, and the second unit block includes setting messages for driving the second functional block. The setting message signal output unit generates an enable signal corresponding to each functional block and a setting message signal synchronized with the enable signal, so as to output the enable signal and the setting message signal to each functional block.

10. The data processing apparatus as claimed in claim 8, further comprising a first functional block and a second functional block, wherein, The memory includes a first unit block and a second unit block. The first unit block includes setting messages for driving the first functional block, and the second unit block includes setting messages for driving the second functional block. When the first unit block includes a message indicating information about the first functional block as the functional block message, the setting message signal output unit generates a setting message signal to output the setting message signal to the first functional block. The setting message signal includes a first enable signal corresponding to the first unit block and the first functional block, and a first setting message signal synchronized with the first enable signal. When the second unit block includes a message indicating information about the second functional block as the functional block message, the setting message signal output unit generates a setting message signal to output the setting message signal to the second functional block. The setting message signal includes a second enable signal corresponding to the second unit block and the second functional block, and a second setting message signal synchronized with the second enable signal.

11. The data processing apparatus as claimed in claim 10, wherein, When the first enable signal is received, the first functional block simultaneously receives the first enable signal and the first setting message signal, and when the second enable signal is received, the second functional block simultaneously receives the second enable signal and the second setting message signal.

12. A memory comprising at least one cell block, the at least one cell block consisting of a setting message block configured to store setting messages and a header configured to store basic messages about the setting messages, wherein, The header includes: a function block message, which is a message about a function block corresponding to the setting message included in the corresponding cell block; an output size message, which is a size message of the message to be output stored in the setting message block; and a last cell block message, which indicates whether the corresponding cell block is the last cell block.

13. The memory as claimed in claim 12, wherein, The at least one cell block, excluding the last cell block, includes a message indicating that the corresponding cell block is not the last cell block.

14. The memory as claimed in claim 12, wherein, The cell block includes a first cell block, and the output size message of the first cell block includes a message indicating x, where x is a positive integer.

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