Image sensor

Abstract

This invention relates to an image sensor and / or a method of manufacturing it. The image sensor may include: a substrate, including a first surface, a second surface opposite to the first surface, and a plurality of unit pixel regions in the substrate; a pixel defining pattern; and a microlens. Each of the plurality of unit pixel regions may include a photoelectric conversion layer. The pixel defining pattern may extend through the substrate in a first direction to define each of the unit pixel regions. The microlens may be located on the second surface of the substrate and correspond to a unit pixel region. The pixel defining pattern may include a first conductive layer and a second conductive layer spaced apart from the first conductive layer.

Description

Technical Field

[0001] This disclosure relates to an image sensor and / or a method of manufacturing the same.

Prior Art

[0002] An image sensing device is a semiconductor component that converts optical information into an electrical signal. The image sensing device may include a charge-coupled device (CCD) image sensing device and a complementary metal-oxide semiconductor (CMOS) image sensing device.

[0003] A CMOS image sensor may be abbreviated as a CMOS image sensor (CIS). The CIS may include a plurality of pixels arranged in a two-dimensional manner. Each of the pixels may include, for example, a photodiode (PD). The photodiode can be used to convert incident light thereon into an electrical signal.

[0004] Recently, with the development of the computer industry and the communication industry, the demand for miniaturized image sensing devices with improved performance is increasing in various fields such as digital cameras, camcorders, smartphones, gaming devices, security cameras, medical microcameras, and robots. Therefore, research on highly scaled and highly integrated semiconductor components in image sensing devices is underway. The patterns of the semiconductor components may have a fine width and may be spaced apart by a fine pitch.

Summary of the Invention

[0005] Aspects of this disclosure relate to an image sensor with improved performance and / or reliability.

[0006] Another aspect of this disclosure relates to a method for manufacturing an image sensor with improved performance and / or reliability.

[0007] Aspects and features of the embodiments in this disclosure are not limited to the aspects and features discussed above. Other aspects and features not mentioned in the embodiments of this disclosure can be understood based on the following description and can be more clearly understood based on the embodiments according to this disclosure. In addition, it will be readily understood that the objects, effects, and advantages according to this disclosure can be achieved using the components and their combinations illustrated in the claims.

[0008] According to an exemplary embodiment of the present disclosure, an image sensor may include: a substrate including a first surface and a second surface opposite to each other, the substrate including a plurality of unit pixel regions in the substrate, each of the plurality of unit pixel regions including a photoelectric conversion layer; a pixel defining pattern extending through the substrate in a first direction, the pixel defining pattern defining each of the plurality of unit pixel regions; and a microlens located on the second surface of the substrate and corresponding to the plurality of unit pixel regions. The pixel defining pattern may include a first conductive layer and a second conductive layer spaced apart from the first conductive layer.

[0009] According to an exemplary embodiment of the present disclosure, an image sensor may include: a substrate including a first region, a second region, a first surface, and a second surface opposite to the first surface, the substrate including a plurality of unit pixel regions in the substrate, each of the plurality of unit pixel regions including a photoelectric conversion layer; a pixel defining pattern extending through the substrate in a first direction, the pixel defining pattern defining each of the plurality of unit pixel regions, the pixel defining pattern including a first defining pattern and a second defining pattern aligned with each other in the first direction; a microlens located on the second surface of the substrate in the first region of the substrate, the microlens corresponding to the plurality of unit pixel regions; a first pad pattern located on the second surface of the substrate in the second region of the substrate, the first pad pattern being electrically connected to the first defining pattern; and a second pad pattern located on the second surface of the substrate in the second region of the substrate, the second pad pattern being electrically connected to the second defining pattern. The second defining pattern may be in contact with the substrate.

[0010] According to an exemplary embodiment of the present disclosure, an image sensor may include a substrate, a pixel definition pattern extending through the substrate, a microlens, a first pad pattern, and a second pad pattern. The substrate may include a first region, a second region, a first surface, a second surface opposite the first surface, a first trench, and a second trench. The substrate may include a plurality of unit pixel regions in the substrate, and each of the plurality of unit pixel regions may include a photoelectric conversion layer. The second region of the substrate may include dummy unit pixel regions in the substrate. The dummy unit pixel regions may include a grounded region and may not include a photoelectric conversion layer. The pixel definition pattern may extend through the substrate. The pixel definition pattern may define each of the plurality of unit pixel regions and the dummy unit pixel regions. The pixel definition pattern may include a first definition pattern in the first trench and a second definition pattern in the second trench. The first definition pattern may include an inner lining film and a first conductive layer on the inner lining film. The inner lining film may be disposed along sidewalls and a bottom surface of the first trench and on the sidewalls and the bottom surface. The second definition pattern may include a second conductive layer. The microlens may be located on the second surface of the substrate in the first region of the substrate. The microlens may correspond to the plurality of unit pixel regions. The first pad pattern may be located on the second surface of the substrate in the second region of the substrate. The first pad pattern may be connected to the first conductive layer. The second pad pattern may be located on the second surface of the substrate in the second region of the substrate. The second pad pattern may be electrically connected to the second conductive layer. The image sensor may be configured to apply a first voltage to the first conductive layer via the first pad pattern. The image sensor may be configured to apply a second voltage to the second conductive layer via the second pad pattern. The image sensor may be configured to apply the second voltage to the grounded region of the dummy unit pixel region.

[0011] According to an exemplary embodiment of the present disclosure, a method for manufacturing an image sensor may include: providing a substrate having a first surface and a second surface opposite each other; forming a first trench in the substrate by etching a first region of the substrate starting from the first surface of the substrate; forming a first definition pattern in the first trench; forming a second trench in the substrate by etching a second region of the substrate starting from the second surface of the substrate, the second trench exposing the first definition pattern; and forming a second definition pattern in the second trench. The first definition pattern may include a first conductive layer. The second definition pattern may include a second conductive layer spaced apart from the first conductive layer. The image sensor may be configured to apply a first voltage to the first conductive layer. The image sensor may be configured to apply a second voltage to the second conductive layer. The second voltage may be different from the first voltage.

Embodiments

[0013] Hereinafter, the present disclosure will be described in more detail with reference to the accompanying drawings according to some embodiments of the present disclosure. Referring to FIGS. 1 to 16, an image sensor according to some embodiments will be described.

[0014] FIG. 1 is an example block diagram of an image sensor according to some embodiments.

[0015] Referring to FIG. 1, an image sensor according to some embodiments may include a first semiconductor wafer 100 and a second semiconductor wafer 200. The first semiconductor wafer 100 and the second semiconductor wafer 200 may be arranged to overlap each other in a plan view. The first semiconductor wafer 100 and the second semiconductor wafer 200 may be stacked in a vertical direction.

[0016] Alternatively, an image sensor according to some embodiments may further include a third semiconductor wafer. In one example, the third semiconductor wafer may include a memory cell array. However, the inventive concept of the present disclosure is not limited thereto. The first semiconductor wafer to the third semiconductor wafer may be sequentially stacked in a vertical direction.

[0017] The first semiconductor wafer 100 may include a pixel array 10. The second semiconductor wafer 200 may include a logic circuit 20 and an analog-to-digital converter (ADC) 25. The pixel array 10 may generate charges proportional to the amount of light entering the pixel array 10. In addition, the pixel array 10 may convert an optical signal into an electrical signal, that is, an analog signal under the control of the control circuit 20. The pixel array 10 may output the analog signal to the ADC 25. The ADC 25 may convert the analog signal into a digital signal. The ADC 25 may provide data based on the digital signal.

[0018] Although not shown, an image sensor according to some embodiments may further include a memory cell array in the second semiconductor wafer 200. The memory cell array may store data therein based on the digital signal.

[0019] The data may be image data generated on a frame basis. The number of bits of the data may be determined based on the resolution of the ADC 25. The number of bits of the data may be determined based on the high dynamic range (HDR) supported by the image sensor. In addition, the bits of the data may further include at least one extended bit indicating the data generation position, information about the data, and the like.

[0020] In some embodiments, the second semiconductor wafer 200 may further include a built-in processor for processing data output from the pixel array 10, such as an image signal processor (ISP), a digital signal processor (DSP), or the like. The processor may reduce noise in the image data, correct the image, or perform subsequent operations related to the image output from the pixel array 10.

[0021] FIG. 2 is a block diagram showing the pixel array, the logic circuit, and the ADC of FIG. 1.

[0022] Referring to FIG. 2, the pixel array 10 may be implemented in the first semiconductor wafer 100. The logic circuit (20 in FIG. 1) may be implemented in the second semiconductor wafer 200.

[0023] The pixel array 10 may convert incident light thereon into an electrical signal. The pixel array 10 may include unit pixel regions arranged in a matrix form along the column direction and the row direction. The pixel array 10 may operate under the control of the logic circuit 20. Specifically, the logic circuit 20 may control a plurality of transistors included in the pixel array 10.

[0024] The logic circuit 20 may effectively receive data from the pixel array 10 and generate an image frame. For example, the logic circuit 20 may use a global shutter scheme in which all unit pixel regions are sensed simultaneously, a rolling shutter scheme in which the exposure time for simultaneously sensing all unit pixel regions is adjusted, and a rolling shutter or coded rolling shutter scheme in which the unit pixel regions are controlled on a column basis. The logic circuit 20 may include a column driver 21, a timing controller, and an ADC 25.

[0025] The column driver 21 may control the pixel array 10 on a column basis under the control of the timing controller 22. The column driver 21 may select at least one column from among the columns of the pixel array 10 based on a column address. The column driver 21 may decode the column address and may be connected to a selection transistor AX, a reset transistor RX, and a source follower transistor SX. The pixel array 10 may operate based on a plurality of driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal received from the column driver 21.

[0026] The ADC 25 may be connected to the pixel array 10 via a row line COL. The ADC 25 may convert an analog signal received from the pixel array 10 into a digital signal via the row line COL. The number of ADCs 25 may be determined based on the number of row lines COL and the number of unit pixel regions arranged along one column. The number of ADCs 25 may be at least one. However, the inventive concept of the present disclosure is not limited thereto.

[0027] For example, the ADC 25 may include a reference signal generator REF, a comparator CMP, a counter CNT, and a buffer BUF. The reference signal generator REF may generate a ramp signal having a specific slope and provide the ramp signal as a reference signal for the comparator. The comparator CMP may compare the analog signal and the ramp signal of the reference signal generator REF with each other and may output a comparison signal having respective transition times based on the valid signal component. The counter CNT may perform a counting operation to generate a count signal and may provide the count signal to the buffer BUF. The buffer BUF may include a latch circuit respectively connected to the row line COL, and may latch the count signal output from the counter CNT in response to a transition of the comparison signal on a row basis, and may output the latched count signal as data.

[0028] In some embodiments, the logic circuit 20 may further include a correlated double sampling (CDS) circuit, which obtains the difference between a reference voltage representing the reset state of each of the unit pixel regions and an output voltage representing the signal component corresponding to the incident light to perform correlated double sampling, and outputs an analog sampling signal corresponding to the valid signal component. The correlated double sampling circuit may be connected to the row line COL.

[0029] The timing controller 22 may control the operation timings of each of the column driver 21 and the ADC 25. The timing controller 22 may provide timing signals and control signals to each of the column driver 21 and the ADC 25. More specifically, the timing controller 22 may control the ADC 25. The ADC 25 may provide data to the logic circuit 20 under the control of the timing controller 22. In addition, the timing controller 22 may further include a circuit that provides a request, a command, or an address to the logic circuit 20 to store the data of the ADC 25 in the memory cell array.

[0030] FIG. 3 is a circuit diagram showing a unit pixel region of the pixel array of FIG. 1. For reference, FIG. 3 may be based on a 4T structure of each of the unit pixel regions constituting the pixel array.

[0031] Referring to FIG. 3, the pixel array may include a photoelectric conversion layer PD1 and a photoelectric conversion layer PD2, a transfer transistor TX, a floating diffusion region FD, a reset transistor RX, a source follower transistor SX, and a selection transistor AX.

[0032] The photoelectric conversion layers PD1 and PD2 can generate charges proportional to the amount of light incident thereon from the outside. Each of the photoelectric conversion layers PD1 and PD2 can be embodied as a photodiode, which includes an n-type impurity region and a p-type impurity region. Each of the photoelectric conversion layers PD1 and PD2 can be coupled to respective transfer transistors TX that transfer the charges generated and accumulated in each of the photoelectric conversion layers PD1 and PD2 to the floating diffusion region FD. The floating diffusion region FD can refer to a region that converts charges into a voltage. Since the floating diffusion region FD has a parasitic capacitance, charges can be stored in the floating diffusion region FD in an accumulated manner.

[0033] One end of each transfer transistor TX can be connected to each of the photoelectric conversion layers PD1 and PD2, and the other end of each transfer transistor TX can be connected to the floating diffusion region FD. The transfer transistor TX can be embodied as a transistor that operates based on a desired and / or alternative predefined bias (e.g., a transfer signal). The transfer signal can be applied thereto via each of the transfer gates TG1 and TG2. That is, each transfer transistor TX can transfer the charges generated from each of the photoelectric conversion layers PD1 and PD2 to the floating diffusion region FD based on each of the transfer signals.

[0034] The source follower transistor SX can amplify the change in the potential of the floating diffusion region FD when receiving charges from the photoelectric conversion layers PD1 and PD2, and output the amplified change to the output line V OUT. When the source follower transistor SX is turned on, a desired and / or alternative predefined potential, such as the power supply voltage V DD provided to the drain of the source follower transistor SX, can be delivered to the drain region of the selection transistor AX. The source follower gate SF of the source follower transistor SX can be connected to the floating diffusion region FD.

[0035] The selection transistor AX can select a unit pixel region to be read on a column basis. The selection transistor AX can be embodied as a transistor driven by a selection line that applies a desired and / or alternative predefined bias (e.g., a column selection signal). The column selection signal can be applied thereto via the selection gate SEL.

[0036] The reset transistor RX can periodically reset the floating diffusion region FD. The reset transistor RX can be embodied as a transistor driven by a reset line that applies a desired and / or alternative predefined bias (e.g., a reset signal). The reset signal can be applied thereto via the reset gate RG. When the reset transistor RX is turned on based on the reset signal, a desired and / or alternative predefined potential, such as the power supply voltage V DD provided to the drain of the reset transistor RX, can be transferred to the floating diffusion region FD.

[0037] In FIG. 3, a structure is shown in which the photoelectric conversion layer PD1 and the photoelectric conversion layer PD2 electrically share a floating diffusion region FD. However, the inventive concept disclosed herein is not limited thereto. For example, a unit pixel region may include the photoelectric conversion layer PD1 and the photoelectric conversion layer PD2, the floating diffusion region FD, and one of four transistors TX, transistor RX, transistor AX, and transistor SX, and the reset transistor RX, the source follower transistor SX, or the selection transistor AX may be shared by an adjacent unit pixel region. In addition, the number of the photoelectric conversion layer PD1 and the photoelectric conversion layer PD2 that electrically share a floating diffusion region FD is not limited thereto. Therefore, the integration of the image sensor according to some embodiments can be improved.

[0038] Different from the illustrated example, since the size of the unit pixel region becomes smaller, the photoelectric conversion layer PD and the transfer transistor TX may be formed in one semiconductor wafer, while the reset transistor RX, the source follower transistor SX, and the selection transistor AX may be formed in the other semiconductor wafer. The semiconductor wafers may be aligned with each other to form a unit pixel region.

[0039] FIG. 4 is a plan view example of an image sensor according to some embodiments. FIG. 5 is a cross-sectional view taken along line A-A of FIG. 4.

[0040] Referring to FIGS. 4 and 5, an image sensor according to some embodiments may include a first semiconductor wafer 100 and a second semiconductor wafer 200. The first semiconductor wafer 100 may serve as a sensor wafer, and the second semiconductor wafer 200 may serve as a logic wafer.

[0041] The first semiconductor wafer 100 may include a light receiving region APS, a light blocking region OB, and a pad region PAD. In the light receiving region APS and the light blocking region OB, a plurality of unit pixel regions PX may be arranged in a two-dimensional manner, for example, in a matrix form. The unit pixel regions PX may be arranged in a matrix form in a plane, and a first direction D1 and a second direction D2 extend across the plane. The first direction D1 and the second direction D2 may intersect with each other. The first direction D1 and the second direction D2 may be substantially perpendicular to each other. A third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2.

[0042] In the light receiving region APS, active pixels that can receive light and generate active signals can be configured. Optical black pixels that block light to generate optical black signals can be configured in the light blocking region OB. The light blocking region OB can be arranged, for example, along the perimeter of the light receiving region APS. However, this is only an example. In some embodiments, dummy unit pixel regions DPX can be configured in the light blocking region OB. The dummy unit pixel regions DPX can refer to regions of pixels that do not generate active signals.

[0043] The pad region PAD can be arranged around the light blocking region OB. The pad region PAD can be arranged adjacent to the edge of the image sensor according to some embodiments. However, this is only an example. The pad region PAD can be configured to connect to an external device and the like to transmit / receive electrical signals between the image sensor according to some embodiments and the external device. For example, the third pad pattern 455 can be arranged on the first substrate 110 of the pad region PAD. The third pad pattern 455 can be connected to an external device or the like.

[0044] An image sensor according to some embodiments can include a first substrate 110, a pixel defining pattern 120, a surface insulating film 150, a first color filter 170, a grating pattern 160, a microlens 180, a second substrate 210, a first pad pattern 365, a second pad pattern 355, and a third pad pattern 455.

[0045] The first substrate 110 can be embodied as a semiconductor substrate. For example, the first substrate 110 can be made of bulk silicon or silicon-on-insulator (SOI). The first substrate 110 can be a silicon substrate, or can be made of a material other than silicon, such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate 110 can include a base substrate and an epitaxial layer formed on the base substrate.

[0046] The first substrate 110 can include a first surface 110a and a second surface 110b that face each other. In some embodiments, the second surface 110b of the first substrate 110 can be the light receiving surface on which light is incident. That is, an image sensor according to some embodiments can be embodied as a backside-illuminated (BSI) image sensor.

[0047] A plurality of unit pixel regions PX may be formed in the first substrate 110 and in the light receiving region APS and the light blocking region OB. Each unit pixel region PX may include a photoelectric conversion layer PD. A dummy unit pixel region DPX that does not include the photoelectric conversion layer PD may be included in the first substrate 110 and in the light blocking region OB. However, the inventive concept of the present disclosure is not limited thereto. The signal generated from the dummy unit pixel region DPX can be used as information for removing process noise later.

[0048] Each unit pixel region PX may include a photoelectric conversion layer PD, a floating diffusion region FD, and a transfer transistor TX. The photoelectric conversion layer PD may be formed in the first substrate 110 and in each of the light receiving region APS and the light blocking region OB. The photoelectric conversion layer PD may generate charges proportional to the amount of light incident thereon from the outside. The photoelectric conversion layer PD may transfer the charges generated and accumulated therein to the floating diffusion region FD.

[0049] The floating diffusion region FD may be formed in the first substrate 110 and in each of the light receiving region APS and the light blocking region OB. The floating diffusion region FD may be formed in the first surface 110a of the first substrate 110. The charges transferred to the floating diffusion region FD may be applied to the source follower gate SF in FIG. 3.

[0050] The transfer transistor TX may be embedded in the first substrate 110. One end of the transfer transistor TX may be connected to the photoelectric conversion layer PD, and the other end of the transfer transistor TX may be connected to the floating diffusion region FD. The transfer transistor TX may transfer the charges generated from the photoelectric conversion layer PD to the floating diffusion region FD.

[0051] The transfer transistor TX may include a transfer gate, a gate insulating film, and a gate spacer. The transfer gate may include a portion embedded in the first substrate 110. The gate insulating film may be disposed between the transfer gate and the first substrate 110. The gate spacer may be disposed on each of two opposite sidewalls of the transfer gate.

[0052] The pixel defining pattern 120 may be formed in the first substrate 110. The pixel defining pattern 120 may be formed by filling an insulating material in a deep trench formed by patterning the first substrate 110. The pixel defining pattern 120 may extend through the first substrate 110 in the third direction D3. For example, the pixel defining pattern 120 may extend from the first surface 110a to the second surface 110b. The pixel defining pattern 120 may be embodied as a front deep trench isolation (FDTI).

[0053] The pixel-defining pattern 120 can define each of the plurality of unit pixel regions PX and the dummy unit pixel region DPX. The pixel-defining pattern 120 can be arranged in a grid pattern in a planar view so that the plurality of unit pixel regions PX and the dummy unit pixel region DPX are spaced apart from each other.

[0054] In some embodiments, an element isolation pattern 105 can be provided. The element isolation pattern 105 can be disposed within the first substrate 110. For example, the element isolation pattern 105 can be received in a trench that recesses a portion of the first substrate 110. The trench can be recessed from the first surface 110a of the first substrate 110. The element isolation pattern 105 can be embodied as a shallow trench isolation (STI) film. The element isolation pattern 105 can define each of the active regions (ACT in FIG. 6A).

[0055] The width of the element isolation pattern 105 in the second direction D2 can gradually decrease as the pattern 105 extends from the first surface 110a of the first substrate 110 toward its second surface 110b. The element isolation pattern 105 can overlap the pixel-defining pattern 120 in the second direction D2 or the first direction D1. The pixel-defining pattern 120 can extend through the element isolation pattern 105 in the third direction D3. The element isolation pattern 105 can include an insulating material. The element isolation pattern 105 can include at least one of, for example, silicon nitride, silicon oxide, and silicon oxynitride.

[0056] An image sensor according to some embodiments can further include a first line insulating film 131, a first line insulating film 132, a first line insulating film 133, a first line insulating film 134, and a first line insulating film 135. The first line insulating film 131, the first line insulating film 132, the first line insulating film 133, the first line insulating film 134, and the first line insulating film 135 can be formed on the first surface 110a of the first substrate 110. For example, the first line insulating film 131, the first line insulating film 132, the first line insulating film 133, the first line insulating film 134, and the first line insulating film 135 can cover the first surface 110a of the first substrate 110. The first substrate 110 and the first line insulating film 131, the first line insulating film 132, the first line insulating film 133, the first line insulating film 134, and the first line insulating film 135 can constitute the first semiconductor wafer 100. In FIG. 5, the number of the first line insulating film 131, the first line insulating film 132, the first line insulating film 133, the first line insulating film 134, and the first line insulating film 135 is five. However, the present disclosure is not limited thereto. The number of the first line insulating film 131, the first line insulating film 132, the first line insulating film 133, the first line insulating film 134, and the first line insulating film 135 is only an example.

[0057] Each of the first line insulating films 131, 132, 133, 134, and 135 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a dielectric constant lower than that of silicon oxide. However, the inventive concept of the present disclosure is not limited thereto.

[0058] A plurality of first contacts 141 and 143 and a plurality of first line patterns 142, 144, 145, 146, and 147 may be disposed in the first line insulating films 131, 132, 133, 134, and 135. The plurality of first contacts 141 and 143 may electrically connect the floating diffusion region FD to the plurality of first line patterns 142, 144, 145, 146, and 147. Some of the plurality of first line patterns 142, 144, 145, 146, and 147 may be connected to the first connection structure 360. However, the inventive concept of the present disclosure is not limited thereto.

[0059] Each of the first contacts 141 and 143 and the first line patterns 142, 144, 145, 146, and 147 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, the inventive concept of the present disclosure is not limited thereto.

[0060] The second substrate 210 may be made of bulk silicon or silicon-on-insulator (SOI). The second substrate 210 may be embodied as a silicon substrate or may be made of a material other than silicon, such as silicon germanium, indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate 210 may include a base substrate and an epitaxial layer formed on the base substrate.

[0061] The second substrate 210 may include an upper surface and a bottom surface. The upper surface of the second substrate 210 may be the surface facing the first semiconductor wafer 100. The bottom surface of the second substrate 210 may be the surface opposite to the upper surface of the second substrate 210.

[0062] Multiple transistors TR may be formed on the upper surface of the second substrate 210. The transistors TR may be, for example, logic circuits. The transistors TR may control the transfer transistor TX, the reset transistor (RX in FIG. 3), the selection transistor (AX in FIG. 3), and the source follower transistor (SX in FIG. 3).

[0063] The second line insulating film 230 may be formed on the second substrate 210. For example, the second line insulating film 230 may cover the upper surface of the second substrate 210. The second substrate 210 and the second line insulating film 230 may constitute the second semiconductor wafer 200. The second line insulating film 230 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material having a dielectric constant lower than that of silicon oxide. However, the inventive concept of the present disclosure is not limited thereto.

[0064] Multiple second line patterns 241 and second line patterns 242 may be disposed in the second line insulating film 230. The multiple second line patterns 241 and second line patterns 242 may be respectively connected to the transistors TR and may be connected to the floating diffusion region FD of the first semiconductor wafer 100. Some of the multiple second line patterns 241 and second line patterns 242 may be connected to the first connection structure 360. In addition, some of the multiple second line patterns 241 and second line patterns 242 may be connected to the third connection structure 450. However, the inventive concept is not limited thereto.

[0065] Each of the second line patterns 241 and second line patterns 242 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and their alloys. However, the inventive concept of the present disclosure is not limited thereto.

[0066] The surface insulating film 150 may be formed on the second surface 110b of the first substrate 110. The surface insulating film 150 may extend along the second surface 110b of the first substrate 110. In some embodiments, at least a portion of the surface insulating film 150 may contact the pixel defining pattern 120.

[0067] The surface insulating film 150 may include an insulating material. For example, the surface insulating film 150 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof. However, the inventive concept of the present disclosure is not limited thereto.

[0068] The surface insulating film 150 serves as an antireflection film to limit and / or prevent the reflection of light incident on the first substrate 110, thereby improving the light reception of the photoelectric conversion layer PD. In addition, the surface insulating film 150 serves as a planarizing film, such that the first color filter 170 and the microlens 180, which will be described later, can be formed at a uniform vertical level.

[0069] The first color filter 170 can be formed on the surface insulating film 150 and in the light reception area APS. In some embodiments, the first color filter 170 can be arranged to correspond to each unit pixel region PX. For example, multiple first color filters 170 can be arranged in a two-dimensional manner, such as in a matrix form.

[0070] The first color filter 170 can include various color filters based on the unit pixel region PX. For example, the first color filter 170 can be arranged in a Bayer pattern, including a red filter, a green filter, and a blue filter. However, this is only an example. The first color filter 170 can include a yellow filter, a magenta filter, and a cyan filter, and can further include a white filter.

[0071] The grating pattern 160 can be formed on the surface insulating film 150. The grating pattern 160 can be formed in a grating shape in a plan view, and can be inserted between multiple first color filters 170.

[0072] The grating pattern 160 can include a low refractive index material having a refractive index lower than that of silicon (Si). For example, the grating pattern 160 can include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, the inventive concept of the present disclosure is not limited thereto. The grating pattern 160 including the low refractive index material can refract or reflect light obliquely incident on the image sensor to improve the quality of the image sensor.

[0073] In some embodiments, the first protective film 165 can be formed on the surface insulating film 150 and the grating pattern 160. The first protective film 165 can be inserted between the surface insulating film 150 and the first color filter 170 and between the grating pattern 160 and the first color filter 170. For example, the first protective film 165 can extend along the upper surface of the surface insulating film 150 and the contours of the sides and upper surface of the grating pattern 160.

[0074] The first protective film 165 can include, for example, aluminum oxide. However, the inventive concept of the present disclosure is not limited thereto. The first protective film 165 can limit and / or prevent damage to the surface insulating film 150 and the grating pattern 160.

[0075] The microlens 180 may be formed on the first color filter 170. The microlens 180 may be disposed to correspond to each unit pixel region PX. For example, the microlens 180 may be two-dimensionally arranged in a plan view, for example, in a matrix form.

[0076] The microlens 180 has a convex shape and may have a desired and / or alternative predefined radius of curvature. Thus, the microlens 180 can focus light to be incident on the photoelectric conversion layer PD. The microlens 180 may include, for example, a light-transmitting resin. However, the inventive concept of the present disclosure is not limited thereto.

[0077] In some embodiments, the second protective film 185 may be formed on the microlens 180. The second protective film 185 may extend along the surface of the microlens 180. The second protective film 185 may include, for example, an inorganic oxide film. For example, the second protective film 185 may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof. However, the inventive concept of the present disclosure is not limited thereto. In some embodiments, the second protective film 185 may include a low-temperature oxide (LTO).

[0078] The second protective film 185 can protect the microlens 180 from external influences. For example, the second protective film 185 may include an inorganic oxide film to protect the microlens 180 containing an organic material. In addition, the second protective film 185 can improve the light focusing ability of the microlens 180. For example, the second protective film 185 can fill the space between the microlenses 180 to reduce reflection, refraction, and scattering of incident light reaching the space between the microlenses 180.

[0079] The image sensor according to some embodiments may further include a first connection structure 360, a second connection structure 350, and a third connection structure 450.

[0080] The first connection structure 360 may be formed in the light-blocking region OB. The first connection structure 360 can limit and / or prevent light from entering the light-blocking region OB. The first connection structure 360 may be formed on the surface insulating film 150 and in the light-blocking region OB. The first connection structure 360 may be in contact with the pixel defining pattern 120. The first connection structure 360 may be in contact with the first defining pattern (121 in FIG. 7) of the pixel defining pattern 120.

[0081] For example, a fourth trench t4 exposing the first defined pattern 121 may be formed in the first substrate 110, the surface insulating film 150, and the light-blocking region OB. The first connection structure 360 may be formed in the fourth trench t4 and may contact the first defined pattern 121 in the light-blocking region OB. The first connection structure 360 may extend along the contours of the sidewalls and the bottom surface of the fourth trench t4.

[0082] The first connection structure 360 may be electrically connected to the first defined pattern 121. For example, the first connection structure 360 may be electrically connected to a first conductive layer (121F in FIG. 7) of the first defined pattern 121. The first connection structure 360 may include, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film stacked in sequence.

[0083] In some embodiments, a first pad pattern 365 may be formed on the first connection structure 360. The first pad pattern 365 may fill the remaining portion of the fourth trench t4 not filled by the first connection structure 360. A first voltage may be applied to the first defined pattern 121 of the pixel defined pattern 120 via the first pad pattern 365. For example, the first voltage may be applied to the first conductive layer (121F in FIG. 7) via the first pad pattern 365 and the first connection structure 360 including a conductive material. The first voltage may be a negative voltage. Therefore, charges generated due to ESD or the like may be discharged to the first pad pattern 365 via the first defined pattern 121, so that ESD scratch defects can be effectively restricted and / or prevented.

[0084] The first pad pattern 365 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and their alloys. However, the inventive concept of the present disclosure is not limited thereto.

[0085] The second connection structure 350 may be formed in the light-blocking region OB. The second connection structure 350 may restrict and / or prevent light from entering the light-blocking region OB. The second connection structure 350 may be formed on the surface insulating film 150 and in the light-blocking region OB. The second connection structure 350 may contact the pixel defined pattern 120. The second connection structure 350 may contact a second defined pattern (122 in FIG. 7) of the pixel defined pattern 120. The second connection structure 350 may contact a second conductive layer of the pixel defined pattern 120. The second defined pattern may refer to the second conductive layer.

[0086] For example, a third trench t3 exposing the second defined pattern 122 may be formed in the first substrate 110, the surface insulating film 150, and the light-blocking region OB. A second connection structure 350 may be formed in the third trench t3 to contact the second defined pattern 122 in the light-blocking region OB. The second connection structure 350 may extend along the contour of the sidewalls and the bottom surface of the third trench t3.

[0087] The second connection structure 350 may be electrically connected to the second defined pattern 122. For example, the second connection structure 350 may be electrically connected to the second conductive layer of the second defined pattern 122. The second connection structure 350 may include, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film stacked in sequence.

[0088] In some embodiments, a second pad pattern 355 may be formed on the second connection structure 350. The second pad pattern 355 may fill the remaining portion of the third trench t3 not filled by the second connection structure 350. A second voltage may be applied to the second defined pattern 122 of the pixel-defined pattern 120 via the second pad pattern 355 and the second connection structure 350 including a conductive material. For example, the second voltage may be applied to the second conductive layer 122 via the second pad pattern 355 and the second connection structure 350. The second voltage may be a well bias voltage.

[0089] The second pad pattern 355 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, the inventive concept of the present disclosure is not limited thereto.

[0090] In some embodiments, a fifth trench t5 may be formed in the first substrate 110 and the light-blocking region OB. The fifth trench t5 may expose a part of each of the first line patterns 145 and 146 of the first semiconductor wafer 100. The fifth trench t5 may expose a part of the second line pattern 242 of the second semiconductor wafer 200. A first connection structure 360 may be formed in the fifth trench t5 to connect the first line patterns 145 and 146 to the second line pattern 242. The first connection structure 360 may extend along the sidewalls and the bottom surface of the fifth trench t5.

[0091] In some embodiments, a first filling insulating film 370 may be formed on the first connection structure 360. The first filling insulating film 370 may fill the remaining portion of the fifth trench t5 not filled by the first connection structure 360. The first filling insulating film 370 may include at least one of, for example, silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, the inventive concept of the present disclosure is not limited thereto.

[0092] In some embodiments, the first capping pattern 375 may be formed on the first filling insulating film 370. The first capping pattern 375 may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and silicon oxynitride) and a high-k dielectric material (e.g., hafnium oxide and aluminum oxide). The first capping pattern 375 may include the same material as the material of the capping film 121C. However, the inventive concept of the present disclosure is not limited thereto.

[0093] In some embodiments, the second color filter 170c may be formed on the first connection structure 360 and the second connection structure 350. For example, the second color filter 170c may be formed to cover a part of the first protection film 165 in the light blocking region OB. The second color filter 170c may include, for example, a blue color filter. However, the inventive concept of the present disclosure is not limited thereto.

[0094] In some embodiments, the third protection film 380 may be formed on the second color filter 170c. For example, the third protection film 380 may be formed to cover a part of the first protection film 165 in the light blocking region OB. In some embodiments, the second protection film 185 may extend along the surface of the third protection film 380. The third protection film 380 may include, for example, a light-transmitting resin. However, the inventive concept of the present disclosure is not limited thereto. In some embodiments, the third protection film 380 may contain the same material as the material of the microlens 180.

[0095] The third connection structure 450 may be formed in the pad region PAD. The third connection structure 450 may be formed on the surface insulating film 150 and in the pad region PAD.

[0096] In some embodiments, the sixth trench t6 may be formed in the first substrate 110 and in the pad region PAD. The third connection structure 450 may fill a part of the sixth trench t6. The third connection structure 450 may be formed along the sidewalls and the bottom surface of the sixth trench t6.

[0097] The seventh trench t7 exposing the second wiring pattern 242 may be formed in the second semiconductor wafer 200 and in the pad region PAD. The third connection structure 450 may fill a part of the seventh trench t7. The third connection structure 450 may be formed along the sidewalls and the bottom surface of the seventh trench t7.

[0098] The third connection structure 450 may be formed in the seventh trench t7 to contact a part of the second wiring pattern 242. The third connection structure 450 may electrically connect a part of the second wiring pattern 242 to the third pad pattern 455. The third connection structure 450 may include, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film stacked in sequence.

[0099] On the third connection structure 450, a third pad pattern 455 may be formed. The third pad pattern 455 may fill the remaining portion of the sixth trench t6 not filled by the third connection structure 450. The third pad pattern 455 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, the inventive concept of the present disclosure is not limited thereto.

[0100] In some embodiments, a portion of the third pad pattern 455 may be exposed. For example, an exposure opening may be formed to partially expose the third pad pattern 455. Thus, the third pad pattern 455 may be configured to connect to an external device and the like to transmit / receive a telecom signal between the image sensor and the external device according to some embodiments.

[0101] The second filling insulating film 470 may be formed on the third connection structure 450. The second filling insulating film 470 may fill the remaining portion of the seventh trench t7 not filled by the third connection structure 450. The second filling insulating film 470 may include at least one of, for example, silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, the inventive concept of the present disclosure is not limited thereto.

[0102] In some embodiments, the second capping pattern 475 may be formed on the second filling insulating film 470. The second capping pattern 475 may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and silicon oxynitride) and a high dielectric material (e.g., hafnium oxide and aluminum oxide). The second capping pattern 475 may include the same material as the material of the capping film 121C. However, the inventive concept of the present disclosure is not limited thereto.

[0103] In some embodiments, the fourth protection film 480 may be formed on the third connection structure 450 and in the pad region PAD. For example, the fourth protection film 480 may be formed to cover a portion of the first protection film 165 in the pad region PAD. In some embodiments, the second protection film 185 may extend along the surface of the fourth protection film 480. The fourth protection film 480 may include, for example, a light-transmitting resin. However, the inventive concept of the present disclosure is not limited thereto. In some embodiments, the fourth protection film 480 may include the same material as the material of the microlens 180.

[0104] FIG. 6A and FIG. 6B are enlarged views of the P region of FIG. 4. FIG. 7 is a cross-sectional view taken along line B-B of FIG. 6A. Hereinafter, with reference to FIGS. 6A to 7, an image sensor according to some embodiments will be described in more detail.

[0105] Referring to FIGS. 6A to 7, the element isolation pattern 105 may define each of the active regions ACT.

[0106] In the plan view, each of the active regions ACT may have a linear shape extending in the second direction D2. However, the shape of each of the active regions ACT is not limited to the shapes shown in FIGS. 6A and 6B and may be modified differently. The floating diffusion region FD, the transfer transistor TX, and the select transistors AX, reset transistor RX, and source follower transistor SX may be disposed on the active region ACT. The transfer transistor TX may include a transfer gate TG.

[0107] In FIG. 6A, the floating diffusion region FD may be disposed on one side of the transfer transistor TX. The floating diffusion region FD may have a conductivity type opposite to that of the first substrate 110. For example, n-type impurities may be doped in the floating diffusion region FD. In FIG. 6B, the floating diffusion region FD may surround the transfer gate TG of the transfer transistor TX.

[0108] In some embodiments, a portion of the unit pixel region PX may contain the select transistor AX and the source follower transistor SX. The select transistor AX may include a select gate SEL, and the source follower transistor SX may include a source follower gate SF. Another portion of the unit pixel region PX may contain the reset transistor RX. The reset transistor RX may include a reset gate RG. However, the inventive concept of the present disclosure is not limited thereto, and the configuration and number of transistors included in the unit pixel region PX may be modified.

[0109] In some embodiments, the pixel defining pattern 120 may define each of the unit pixel regions PX. For example, the pixel defining pattern 120 may be disposed between adjacent unit pixel regions PX. In the plan view, the pixel defining pattern 120 may have a grid structure. In the plan view, the pixel defining pattern 120 may surround all of each of the unit pixel regions PX. The pixel defining pattern 120 may be configured in a grid structure extending in the first direction D1 and the second direction D2.

[0110] In the cross-sectional view, the pixel defining pattern 120 may extend in the third direction D3 through the first substrate 110. The pixel defining pattern 120 may extend from the first surface 110a of the first substrate 110 to its second surface 110b. The pixel defining pattern 120 may be embodied as a deep trench isolation (DTI) film. The width of the pixel defining pattern 120 in the second direction D2 may gradually decrease as the pattern 120 extends from the first surface 110a of the first substrate 110 toward its second surface 110b. However, the inventive concept of the present disclosure is not limited thereto.

[0111] In some embodiments, the pixel defining pattern 120 may include a first defining pattern 121 and a second defining pattern 122. The first defining pattern 121 may be disposed in the first trench t1. The second defining pattern 122 may be disposed in the second trench t2. The first trench t1 and the second trench t2 may be aligned with each other in the third direction D3. That is, the first defining pattern 121 and the second defining pattern 122 may be aligned with each other in the third direction D3.

[0112] The first defining pattern 121 may include a lining film 121L, a first conductive layer 121F, and a capping film 121C. The lining film 121L may be disposed along and on the sidewalls and the bottom surface of the first trench t1. In the present disclosure, the bottom surface of the first trench t1 is defined as the surface facing the first surface 110a of the first substrate 110. The first conductive layer 121F may be disposed on the lining film 121L. The capping layer 121C may be disposed on the first conductive layer 121F.

[0113] The lining film 121L may include an oxide film having a refractive index lower than that of the first substrate 110. For example, the lining film 121L may include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, the inventive concept of the present disclosure is not limited thereto. The lining film 121L having a refractive index lower than that of the first substrate 110 may refract or reflect light obliquely incident on the photoelectric conversion layer PD. In addition, the lining film 121L may limit and / or prevent the photoelectric charges generated in a specific unit pixel region PX due to incident light from randomly drifting and moving to an adjacent unit pixel region PX. That is, the lining film 121L may improve the light reception of the photoelectric conversion layer PD to improve the quality of the image sensor according to some embodiments.

[0114] In some embodiments, the first conductive layer 121F may include a conductive material. For example, the first conductive layer 121F may include, but is not limited to, polycrystalline silicon (polycrystalline Si). In some embodiments, a negative voltage may be applied to the first conductive layer 121F including the conductive material. Therefore, the electrostatic discharge (ESD) scratch defect of the image sensor according to some embodiments can be effectively limited and / or prevented. In this regard, the ESD scratch defect refers to a phenomenon in which charges generated by ESD or the like accumulate on the surface of the substrate (for example, the second surface 110b), resulting in scratch-like stains on the image.

[0115] In some embodiments, the capping film 121C may comprise an insulating material. For example, the capping layer 121C may comprise a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and silicon oxynitride) and a high-k dielectric material (e.g., hafnium oxide and aluminum oxide). The capping film 121C may comprise the same material as each of the first capping pattern 375 and the second capping pattern 475. However, the inventive concept of the present disclosure is not limited thereto.

[0116] The second defining pattern 122 may be disposed in the second trench t2. The second defining pattern 122 may comprise a second conductive layer. In one example, the second defining pattern 122 may be composed of the second conductive layer. The second defining pattern 122 may be in contact with the first substrate 110. The second conductive layer 122 may be in contact with the first substrate 110. Hereinafter, the second defining pattern 122 is referred to as the second conductive layer 122. In some embodiments, the second conductive layer 122 may be a single layer. However, the inventive concept of the present disclosure is not limited thereto. In some embodiments, the upper surface 122US of the second conductive layer 122 may be coplanar with the second surface 110b of the first substrate 110.

[0117] The second conductive layer 122 may comprise a conductive material. The second conductive layer 122 may comprise, for example, polysilicon (polycrystalline Si) or silicon doped with arsenic (As), phosphorus (P), or carbon (C). However, the inventive concept of the present disclosure is not limited thereto. The first conductive layer 121F and the second conductive layer 122 may comprise the same material. However, the inventive concept of the present disclosure is not limited thereto. The material constituting the second conductive layer 122 may be different from the material constituting the first conductive layer 121F. In this case, the material constituting the second conductive layer 122 and the material constituting the first conductive layer 121F may have an etching selectivity with respect to each other. When the material constituting the second conductive layer 122 is different from the material constituting the first conductive layer 121F, the first conductive layer 121F may comprise polysilicon, while the second conductive layer 122 may comprise a metal material. However, the inventive concept of the present disclosure is not limited thereto.

[0118] In some embodiments, a second voltage may be applied to the second conductive layer 122 comprising a conductive material. The second voltage may be a well bias voltage. When the well bias voltage is applied to the second conductive layer 122, a separate ground region may not be disposed on the first surface 110a of the first substrate 110. The ground voltage may be applied to the first substrate 110 via the second conductive layer 122. The second conductive layer 122 is in contact with the first substrate 110 such that when the second voltage is applied to the second conductive layer 122, the second voltage can be applied to the first substrate 110. Accordingly, an image sensor with improved integration can be manufactured.

[0119] The first conductive layer 121F and the second conductive layer 122 may be spaced apart from each other. The first conductive layer 121F and the second conductive layer 122 may be spaced apart from each other in the third direction D3. The first conductive layer 121F and the second conductive layer 122 may be electrically insulated from each other. The lining film 121L containing an insulating material may be disposed between the first conductive layer 121F and the second conductive layer 122. Different voltages may be applied to the first conductive layer 121F and the second conductive layer 122, respectively. For example, a first voltage may be applied to the first conductive layer 121F, and a second voltage may be applied to the second conductive layer 122.

[0120] In some embodiments, the first conductive layer 121F includes an upper surface 121F_US. The upper surface 121F_US of the first conductive layer 121F may face the second surface 110b of the first substrate 110. The photoelectric conversion layer PD includes an upper surface PD_US. The upper surface PD_US of the photoelectric conversion layer PD may face the second surface 110b of the first substrate 110.

[0121] In some embodiments, the vertical horizontal height of the upper surface 121F_US of the first conductive layer 121F based on the first surface 110a of the first substrate 110 is higher than the vertical horizontal height of the upper surface PD_US of the photoelectric conversion layer PD based on the first surface 110a of the first substrate 110. Accordingly, the first conductive layer 121F may overlap the entire photoelectric conversion layer PD in the second direction D2. In some embodiments, the vertical length of the first conductive layer 121F may be greater than the vertical length of the second conductive layer 122.

[0122] In some embodiments, the width W1 of the first conductive layer 121F in the second direction D2 may be smaller than the width W2 of the second conductive layer 122 in the second direction D2. Since the first conductive layer 121F is disposed between two opposing lining films 121L and the second conductive layer 122 is a single layer filling the second trench t2, the width W1 of the first conductive layer 121F in the second direction D2 may be smaller than the width W2 of the second conductive layer 122 in the second direction D2.

[0123] FIG. 8 is an enlarged view of the Q region of FIG. 4. FIG. 9 is a cross-sectional view taken along line C-C in FIG. 8. For ease of description, the following description is based on its differences from those described using FIGS. 6A to 7.

[0124] Referring to FIGS. 4, 8, and 9, in the light receiving region APS, the unit pixel region PX may include a first pixel region PR1 and a second pixel region PR2.

[0125] The first pixel region PR1 and the second pixel region PR2 may be adjacent to each other and may be spaced apart from each other. The first pixel region PR1 may be the same as the unit pixel region PX described with reference to FIGS. 6A to 7.

[0126] The second pixel region PR2 may include a first sub-pixel SP1 and a second sub-pixel SP2. The first sub-pixel SP1 and the second sub-pixel SP2 may be adjacent to each other. In FIG. 8, the first sub-pixel SP1 and the second sub-pixel SP2 are illustrated as being aligned with each other in the second direction D2. However, the inventive concept of the present disclosure is not limited thereto.

[0127] The second pixel region PR2 may include a ground region GND. That is, each of the first sub-pixel SP1 and the second sub-pixel SP2 may include a ground region GND in its pixel region. In contrast, the first pixel region PR1 may not include a ground region GND.

[0128] In each of the first sub-pixel SP1 and the second sub-pixel SP2, the ground region GND may be disposed on one side of the transfer transistor TX. Different from the illustration, the ground region GND may be formed in a region in each of the first sub-pixel SP1 and the second sub-pixel SP2 other than the region on one side of the transfer transistor TX.

[0129] In FIG. 9, the ground region GND may be disposed between opposite portions of the element isolation pattern 105. That is, in each of the first sub-pixel SP1 and the second sub-pixel SP2, the element isolation pattern 105 may define the ground region GND.

[0130] The image sensor according to some embodiments may further include a first ground contact CT1 connected to the ground region GND. The first ground contact CT1 may be connected to the ground region GND and may apply a second voltage to the ground region GND. The second voltage may be, for example, a well bias voltage. That is, the voltage applied to the ground region GND and the voltage applied to the second conductive layer 122 may be the same as each other.

[0131] In some embodiments, the first sub-pixel SP1 and the second sub-pixel SP2 may share a microlens 180. That is, one microlens 180 may cover the first sub-pixel SP1 and the second sub-pixel SP2. The first sub-pixel SP1 and the second sub-pixel SP2 share the microlens 180 so that signals respectively generated from the first sub-pixel SP1 and the second sub-pixel SP2 can be used as information for autofocus in an image signal processor (ISP) of a logic chip.

[0132] FIG. 10 is a cross-sectional view taken along line D-D of FIG. 4. For ease of description, the following description is based on its differences from those described using FIGS. 4 and 5.

[0133] Referring to FIG. 10, an image sensor according to some embodiments may include a first pad pattern 365 and a second pad pattern 355.

[0134] The first pad pattern 365 may fill a part of the fourth trench t4. The first pad pattern 365 may be connected to the first conductive layer 121F of the first defining pattern 121. The first pad pattern 365 may be electrically connected to the first conductive layer 121F of the first defining pattern 121. Thus, a first voltage may be applied to the first conductive layer 121F via the first pad pattern 365. The first voltage may be, for example, a negative voltage.

[0135] The second pad pattern 355 may fill a part of the third trench t3. The second pad pattern 355 may be connected to the second conductive layer 122. The second pad pattern 355 may be electrically connected to the second conductive layer 122. Thus, a second voltage may be applied to the second conductive layer 122 via the second pad pattern 355. The second voltage may be different from the first voltage. The second voltage may be, for example, a well bias voltage.

[0136] In some embodiments, the depth of the first pad pattern 365 in the third direction D3 may be greater than the depth of the second pad pattern 355 in the third direction D3. For example, the first pad pattern 365 may include a bottom surface 365BS. The bottom surface 365BS of the first pad pattern 365 may face the second surface 110b of the first substrate 110. The second pad pattern 355 may include a bottom surface 355BS. The bottom surface 355BS of the second pad pattern 355 may face the second surface 110b of the first substrate 110.

[0137] The bottom surface 365BS of the first padding pattern 365 may be lower in vertical horizontal height based on the first surface 110a of the first substrate 110 than the bottom surface 355BS of the second padding pattern 355 based on the first surface 110a of the first substrate 110. That is, the bottom surface 365BS of the first padding pattern 365 may be closer to the first surface 110a of the first substrate 110 than the bottom surface 355BS of the second padding pattern 355. In addition, the first padding pattern 365 may include a portion that does not overlap with the second padding pattern 355 in the second direction D2. Since the first padding pattern 365 is connected to the first conductive layer 121F, the second padding pattern 355 is connected to the second conductive layer 122, and the first conductive layer 121F and the second conductive layer 122 are spaced apart from each other in the third direction D3, the bottom surface 365BS of the first padding pattern 365 may be lower in vertical horizontal height based on the first surface 110a of the first substrate 110 than the bottom surface 355BS of the second padding pattern 355 based on the first surface 110a of the first substrate 110.

[0138] FIG. 11 is a cross-sectional view taken along line E-E of FIG. 4. For ease of description, the following description is based on its differences from those described using FIGS. 4 and 5.

[0139] Referring to FIG. 11, in an image sensor according to some embodiments, the dummy unit pixel region DPX may include a ground region GND.

[0140] In the dummy unit pixel region DPX, the ground region GND may be disposed in the first surface 110a of the first substrate 110. The ground region GND may be disposed between opposite portions of the element isolation pattern 105. A well bias voltage may be applied to the ground region GND. For example, a second ground contact CT2 connected to the ground region GND may be provided. The well bias voltage may be applied to the ground region GND via the second ground contact CT2. The voltage applied to the ground region GND of the dummy unit pixel region DPX and the voltage applied to the second conductive layer 122 may be the same as each other.

[0141] FIG. 12 is an exemplary cross-sectional view of an image sensor according to some embodiments. For ease of description, the following description is based on its differences from those described using FIGS. 6A to 7.

[0142] Referring to FIG. 12, the pixel defining pattern 120 may be disposed in the first trench t1 and the second trench t2. The pixel defining pattern 120 may include a first defining pattern 121 and a second defining pattern 122. The first defining pattern 121 may fill the first trench t1, and the second defining pattern 122 may fill the second trench t2. The second defining pattern 122 may refer to the second conductive layer.

[0143] The second trench t2 can be recessed from the second surface 110b of the first substrate 110. That is, the width of the second trench t2 in the second direction D2 can gradually decrease as the trench t2 extends from the second surface 110b of the first substrate 110 toward its first surface 110a. The first trench t1 can be recessed from the first surface 110a of the first substrate 110. That is, the width of the first trench t1 in the second direction D2 can gradually decrease as the trench t1 extends from the first surface 110a of the first substrate 110 toward its second surface 110b.

[0144] The width of the pixel defining pattern 120 in the second direction D2 can gradually decrease and then gradually increase as the pattern 120 extends from the first surface 110a of the first substrate 110 toward its second surface 110b.

[0145] In some embodiments, at the boundary between the first trench t1 and the second trench t2, the width of the first trench t1 in the second direction D2 can be the same as the width of the second trench t2 in the second direction D2. However, the inventive concept of the present disclosure is not limited thereto.

[0146] FIG. 13 is an example cross-sectional view of an image sensor according to some embodiments. For ease of description, the following description is based on its differences from those described using FIGS. 6A to 7 and FIG. 12.

[0147] Referring to FIG. 13, at the boundary between the first trench t1 and the second trench t2, the width of the first trench t1 in the second direction D2 and the width of the second trench t2 in the second direction D2 can be different from each other.

[0148] For example, at the boundary between the first trench t1 and the second trench t2, the width of the first trench t1 in the second direction D2 can be greater than the width of the second trench t2 in the second direction D2. This structure can occur when the first trench t1 and the second trench t2 are not aligned with each other during the process of forming the second trench t2 after forming the first defining pattern 121.

[0149] FIG. 14 is an example cross-sectional view of an image sensor according to some embodiments. For ease of description, the following description is based on its differences from those described using FIGS. 6A to 7 and FIG. 12.

[0150] Referring to FIG. 14, a portion of the second conductive layer 122 can overlap with the first defining pattern 121 in the second direction D2.

[0151] In the process of forming the second trench t2 after forming the first defining pattern 121, the first trench t1 and the second trench t2 may not be aligned with each other. In this case, a part of the second trench t2 may overlap with the first defining pattern 121 in the second direction D2. When the second conductive layer 122 fills the second trench t2, the first defining pattern 121 and the second conductive layer 122 may partially overlap with each other in the second direction D2.

[0152] FIG. 15 is an example cross-sectional view of an image sensor according to some embodiments. For ease of description, the following description is based on their differences from those described with reference to FIGS. 6A to 7.

[0153] Referring to FIG. 15, the second conductive layer 122 according to some embodiments may not be a single layer.

[0154] The second conductive layer 122 may include, for example, a first portion 122_1 and a second portion 122_2. The first portion 122_1 of the second conductive layer 122 may be disposed on the inner sidewall of the second trench t2. The second portion 122_2 of the second conductive layer 122 may be disposed between opposite portions of the first portion 122_1 of the second conductive layer 122.

[0155] In some embodiments, the first portion 122_1 of the second conductive layer 122 may include a conductive material. For example, the first portion 122_1 of the second conductive layer 122 may include titanium nitride (TiN). However, the inventive concept of the present disclosure is not limited thereto. The second portion 122_2 of the second conductive layer 122 may include a conductive material. For example, the second portion 122_2 of the second conductive layer 122 may include polysilicon (polycrystalline Si). However, the inventive concept of the present disclosure is not limited thereto.

[0156] FIG. 16 is an example cross-sectional view of an image sensor according to some embodiments. For ease of description, the following description is based on their differences from those described with reference to FIGS. 6A to 7.

[0157] Referring to FIG. 16, the upper surface 121F_US of the first conductive layer 121F may be lower in the vertical horizontal height based on the first surface 110a of the first substrate 110 than the upper surface PD_US of the photoelectric conversion layer PD based on the first surface 110a of the first substrate 110. That is, a part of the first conductive layer 121F may not overlap with the photoelectric conversion layer PD in the second direction D2.

[0158] Hereinafter, a method for manufacturing an image sensor according to some embodiments will be described with reference to FIGS. 17 to 31.

[0159] Figures 17 to 24 illustrate structures of intermediate operations for showing a method of manufacturing an image sensor according to some embodiments. For reference, the image sensor manufactured with reference to Figures 17 to 24 may be, for example, the image sensor of Figure 7.

[0160] Referring to Figure 17, a first substrate 110 including a first surface 110a and a third surface 110c opposite to each other may be provided.

[0161] The element isolation pattern 105 may be formed in the first substrate 110. First, a trench may be formed by recessing a part of the first surface 110a of the first substrate 110. The element isolation pattern 105 may be formed in the trench. Each of the element isolation patterns 105 may define an active area.

[0162] Referring to Figure 18, a first mask film MASK1 may be formed on the first surface 110a of the first substrate 110. The first mask film MASK1 may have an opening approximately specifying the position of the pre-trench pt. The first mask film MASK1 may be composed of at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC), and a silicon nitride film.

[0163] Subsequently, the pre-trench pt may be formed using the first mask film MASK1 as an etching mask. The pre-trench pt may extend through the element isolation pattern 105.

[0164] Referring to Figure 19, a pre-second conductive layer 122p may be formed. The pre-second conductive layer 122p may fill the pre-trench pt. The pre-second conductive layer 122p may cover all of the first mask film MASK1. The pre-second conductive layer 122p may include a conductive material. For example, the pre-second conductive layer 122p may include polysilicon.

[0165] Referring to Figure 20, the second conductive layer 122 may be formed by etching the pre-second conductive layer 122p. The second conductive layer 122 may refer to a second defined pattern. The first trench t1 and the second trench t2 may be formed by etching the pre-second conductive layer 122p. Specifically, the second conductive layer 122 may be formed through an etch-back process. The second conductive layer 122 may fill the second trench t2. The first trench t1 may expose the second conductive layer 122.

[0166] Since the first mask film MASK1 is disposed on the first surface 110a of the first substrate 110, damage to the first substrate 110 may be minimized during the process of forming the second conductive layer 122.

[0167] In some embodiments, the material of the pre-second conductive layer 122p may have an etching selectivity relative to the material constituting the first substrate 110. For example, when the pre-second conductive layer 122p is silicon doped with arsenic (As), phosphorus (P), or carbon (C), the pre-second conductive layer 122p may have an etching selectivity relative to the first substrate 110 containing silicon. In this case, the second conductive layer 122 can be formed without damaging the first substrate 110.

[0168] Referring to FIG. 21, a pre-inner lining film 121Lp can be formed along and on the sidewalls and bottom surface of the first trench t1. In the present disclosure, the bottom surface of the first trench t1 is defined as the surface facing the first surface 110a of the first substrate 110. The pre-first conductive layer 121Fp can be formed on the pre-inner lining film 121Lp.

[0169] The pre-inner lining film 121Lp can extend along and on the upper surface of the first mask film MASK1. The pre-inner lining film 121Lp can include an insulating material. For example, the pre-inner lining film 121Lp can include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, the inventive concept of the present disclosure is not limited thereto.

[0170] The pre-first conductive layer 121Fp can include a conductive material. For example, the pre-first conductive layer 121Fp can include polysilicon. However, the inventive concept of the present disclosure is not limited thereto.

[0171] Referring to FIG. 22, the first conductive layer 121F can be formed by etching a portion of the pre-first conductive layer 121Fp. The first conductive layer 121F can be formed via an etch-back process.

[0172] Referring to FIG. 23, a pixel defining pattern 120 can be formed. The pixel defining pattern 120 can include a first defining pattern 121 and a second conductive layer 122.

[0173] First, a pre-capping film (not shown) can be formed on the first conductive layer 121F. Then, a portion of the pre-capping film, a portion of the pre-inner lining film 121Lp, and the first mask film MASK1 can be removed to form the inner lining film 121L and the capping film 121C. A portion of the pre-capping film, a portion of the pre-inner lining film 121Lp, and the first mask film MASK1 can be removed such that the first surface 110a of the first substrate 110 can be exposed.

[0174] Referring to FIG. 24, the second conductive layer 122 can be exposed by removing a portion of the first substrate 110.

[0175] The first substrate 110 can be removed from a third side 110c of the first substrate 110 in a starting manner. A portion of the first substrate 110 can be removed to form a second surface 110b. The second surface 110b of the first substrate 110 can expose the second conductive layer 122. One side of the second conductive layer 122 can be coplanar with the second surface 110b of the first substrate 110.

[0176] FIGS. 25 to 31 illustrate structures for showing intermediate operations of a method for manufacturing an image sensor according to some embodiments. For reference, the image sensor manufactured with reference to FIGS. 25 to 31 can be, for example, the image sensor illustrated in FIG. 12.

[0177] Referring to FIG. 25, a first substrate 110 including a first surface 110a and a second surface 110b opposite to each other can be provided.

[0178] An element isolation pattern 105 can be formed in the first substrate 110. First, trenches in which a portion is recessed from the first surface 110a of the first substrate 110 can be formed in the first substrate 110. The element isolation pattern 105 can be formed in the trenches. Each of the active regions can be defined by the element isolation pattern 105.

[0179] Referring to FIG. 26, a second mask film MASK2 can be formed on the first surface 110a of the first substrate 110. The second mask film MASK2 can have an opening that generally specifies the position of the first trench t1. The second mask film MASK2 can be composed of at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC), and a silicon nitride film.

[0180] Subsequently, the first trench t1 can be formed using the second mask film MASK2 as an etching mask. The first trench t1 can extend through the element isolation pattern 105.

[0181] Referring to FIG. 27, a pre-inner lining film 121Lp can be formed along sidewalls and a bottom surface of the first trench t1. A pre-first conductive layer 121Fp can be formed on the pre-inner lining film 121Lp.

[0182] The pre-inner lining film 121Lp can extend along and on an upper surface of the second mask film MASK2. The pre-inner lining film 121Lp can include an insulating material. For example, the pre-inner lining film 121Lp can include at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, the inventive concept of the present disclosure is not limited thereto.

[0183] The preliminary first conductive layer 121Fp may include a conductive material. For example, the preliminary first conductive layer 121Fp may include polysilicon. However, the inventive concept of the present disclosure is not limited thereto.

[0184] Referring to FIG. 28, a first defining pattern 121 may be formed. The first defining pattern 121 may include a liner film 121L, a first conductive layer 121F, and a capping film 121C.

[0185] First, the first conductive layer 121F may be formed by etching a portion of the preliminary first conductive layer 121Fp. The first conductive layer 121F may be formed via an etch-back process. Subsequently, a preliminary capping film (not shown) may be formed on the first conductive layer 121F. Then, a portion of the preliminary capping film, a portion of the preliminary liner film 121Lp, and the second mask film MASK2 may be removed to form the liner film 121L and the capping film 121C. A portion of the preliminary capping film, a portion of the preliminary liner film 121Lp, and the second mask film MASK2 may be removed such that the first surface 110a of the first substrate 110 may be exposed.

[0186] Referring to FIG. 29, a third mask film MASK3 may be formed on the second surface 110b of the first substrate 110. The third mask film MASK3 may have an opening that generally specifies the position of the second trench t2. The third mask film MASK3 may be composed of at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC), and a silicon nitride film.

[0187] Subsequently, the third mask film MASK3 may be used as an etching mask to form the second trench t2. The second trench t2 may expose the first defining pattern 121.

[0188] Referring to FIG. 30, a preliminary second conductive layer 122p that fills the second trench t2 may be formed. The preliminary second conductive layer 122p may cover all of the third mask film MASK3. The preliminary second conductive layer 122p may include a conductive material. For example, the preliminary second conductive layer 122p may include polysilicon. However, the inventive concept of the present disclosure is not limited thereto.

[0189] Referring to FIG. 31, the second conductive layer 122 may be formed by removing a portion of the preliminary second conductive layer 122p. The second conductive layer 122 may be formed such that a pixel defining pattern 120 may be formed. The pixel defining pattern 120 may include the first defining pattern 121 and the second defining pattern 122. The second defining pattern 122 may refer to the second conductive layer.

[0190] Subsequently, the third mask film MASK3 may be removed.

[0191] In one or more of the example embodiments discussed above, a power circuit system, such as the power circuit system in the first semiconductor wafer 100 and / or the second semiconductor wafer 200 and / or the power circuit system in an external power source (e.g., a battery) connected to the first semiconductor wafer 100 and / or the second semiconductor wafer 200, may apply a first voltage to the first conductive layer 121F via the first pad pattern 355, apply a second voltage (e.g., a well bias voltage) to the second conductive layer 122 via the second pad pattern 365, and / or apply a second voltage (e.g., a well bias voltage, a ground voltage) to the ground region GND via a ground contact (e.g., the first ground contact CT1).

[0192] One or more of the elements disclosed above may include or be implemented in a processing circuit system, such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0193] In summary, those of ordinary skill in the art will understand that many changes and modifications can be made to the presented embodiments without substantially departing from the principles of the disclosure. Therefore, the presented embodiments disclosed herein are used only in a general and descriptive sense and not for purposes of limitation.

Brief Description of the Drawings

[0012] The above and other aspects and features of the embodiments of the present disclosure will become more apparent by referring to the following detailed description of its exemplary embodiments with reference to the accompanying drawings, in which: FIG. 1 is an exemplary block diagram of an image sensor according to some embodiments. FIG. 2 is a block diagram showing the pixel array, logic circuit, and ADC of FIG. 1. FIG. 3 is a circuit diagram showing the unit pixel region of the pixel array of FIG. 1. FIG. 4 is an exemplary plan view of an image sensor according to some embodiments. FIG. 5 is a cross-sectional view taken along line A-A of FIG. 4. FIGS. 6A and 6B are enlarged views of the P region of FIG. 4. FIG. 7 is a cross-sectional view taken along line B-B of FIG. 6A. FIG. 8 is an enlarged view of the Q region of FIG. 4. FIG. 9 is a cross-sectional view taken along line C-C in FIG. 8. FIG. 10 is a cross-sectional view taken along line D-D of FIG. 4. FIG. 11 is a cross-sectional view taken along line E-E of FIG. 4. FIG. 12 is an exemplary cross-sectional view of an image sensor according to some embodiments. FIG. 13 is an exemplary cross-sectional view of an image sensor according to some embodiments. FIG. 14 is an exemplary cross-sectional view of an image sensor according to some embodiments. FIG. 15 is an exemplary cross-sectional view of an image sensor according to some embodiments. FIG. 16 is an exemplary cross-sectional view of an image sensor according to some embodiments. FIGS. 17 to 24 illustrate the structures for showing the intermediate operations of a method for manufacturing an image sensor according to some embodiments. FIGS. 25 to 31 illustrate the structures for showing the intermediate operations of a method for manufacturing an image sensor according to some embodiments.

Claims

1. An image sensor, comprising: A substrate comprising a first surface and a second surface opposite to each other, the substrate comprising a plurality of unit pixel regions therein, each of the plurality of unit pixel regions comprising a photoelectric conversion layer; A pixel-defined pattern extends through the substrate in a first direction, wherein the first direction is from a first surface of the substrate toward a second surface of the substrate, and the pixel-defined pattern defines each of the plurality of unit pixel regions; And a microlens, located on the second surface of the substrate and corresponding to the plurality of unit pixel regions, wherein the pixel defining pattern includes a first conductive layer and a second conductive layer spaced apart from the first conductive layer in the first direction.

2. The image sensor of claim 1, wherein the image sensor is configured to apply a first voltage to the first conductive layer, the image sensor is configured to apply a second voltage to the second conductive layer, and the first voltage is different from the second voltage.

3. The image sensor as claimed in claim 1, wherein the plurality of unit pixel regions include a first pixel region and a second pixel region, the first pixel region does not include a ground region, the second pixel region includes a ground region, and the image sensor is configured to use a signal generated from the second pixel region as information for autofocus.

4. The image sensor of claim 3, wherein the second pixel region comprises a first sub-pixel and a second sub-pixel adjacent to each other, each of the first sub-pixel and the second sub-pixel includes the ground region, and the first sub-pixel and the second sub-pixel share the microlens.

5. The image sensor as claimed in claim 1, wherein the upper surface of the second conductive layer is coplanar with the second surface of the substrate.

6. The image sensor of claim 1, wherein the width of the first conductive layer in the second direction is smaller than the width of the second conductive layer in the second direction, and the second direction intersects the first direction.

7. The image sensor of claim 1, wherein the substrate includes a first trench and a second trench, the pixel defining pattern includes a first defining pattern in the first trench and a second defining pattern in the second trench, the first defining pattern including an inner liner film and a first conductive layer on the inner liner film, the inner liner film being disposed along and on the sidewalls and bottom surface of the first trench, and the second defining pattern including the second conductive layer.

8. The image sensor as claimed in claim 7, wherein the second conductive layer is a single layer.

9. The image sensor of claim 7, wherein the second conductive layer comprises a first portion and a second portion, the first portion of the second conductive layer being disposed along and on the sidewall of the second trench, and the second portion of the second conductive layer being surrounded by the first portion of the second conductive layer.

10. The image sensor of claim 7, wherein at the boundary between the first trench and the second trench, the width of the first trench in a second direction is greater than the width of the second trench in the second direction, and the second direction intersects the first direction.

11. An image sensor, comprising: A substrate includes a first region, a second region, a first surface, and a second surface opposite to the first surface. The substrate includes a plurality of unit pixel regions, each of which includes a photoelectric conversion layer. A pixel-defining pattern extends through the substrate in a first direction, wherein the first direction is from a first surface of the substrate toward a second surface of the substrate, the pixel-defining pattern defining each of the plurality of unit pixel regions, the pixel-defining pattern comprising a first defining pattern and a second defining pattern aligned with each other in the first direction; A microlens is located on the second surface of the substrate in the first region of the substrate, the microlens corresponding to the plurality of unit pixel regions; A first pad pattern is located on the second surface of the substrate in the second region of the substrate, and the first pad pattern is electrically connected to the first defined pattern; And a second pad pattern, located on the second surface of the substrate in the second region of the substrate, the second pad pattern being electrically connected to the second defining pattern, wherein the second defining pattern is in contact with the substrate.

12. The image sensor of claim 11, wherein the image sensor is configured to apply a first voltage to the first defined pattern via the first pad pattern, the image sensor is configured to apply a second voltage to the second defined pattern via the second pad pattern, and the second voltage is different from the first voltage.

13. The image sensor of claim 11, wherein the first defining pattern includes a first conductive layer connected to the first pad pattern, and the second defining pattern includes a second conductive layer electrically insulated from the first conductive layer and connected to the second pad pattern.

14. The image sensor as claimed in claim 11, further comprising: A contact is located on the first surface of the substrate, wherein the second region of the substrate includes a dummy unit pixel region, the dummy unit pixel region includes a ground region and does not contain the photoelectric conversion layer, the contact is connected to the ground region, and the image sensor is configured to apply a well bias voltage to the ground region via the contact.

15. The image sensor of claim 11, wherein the bottom surface of the first pad pattern is at a vertical horizontal height relative to the first surface of the substrate, which is lower than the bottom surface of the second pad pattern is at a vertical horizontal height relative to the first surface of the substrate.

16. The image sensor of claim 11, wherein the plurality of unit pixel regions in the first region include a first pixel region and a second pixel region, the first pixel region does not include a ground region, the second pixel region includes the ground region, and the image sensor is configured to use a signal generated from the second pixel region as information for autofocus.

17. An image sensor, comprising: A substrate comprising a first region, a second region, a first surface, a second surface opposite to the first surface, a first trench, and a second trench; the substrate includes a plurality of unit pixel regions within the substrate, each of the plurality of unit pixel regions including a photoelectric conversion layer; the second region of the substrate includes dummy unit pixel regions within the substrate, each dummy unit pixel region including a ground region and not containing the photoelectric conversion layer; a pixel defining pattern extending through the substrate, the pixel defining pattern defining each of the plurality of unit pixel regions and the dummy unit pixel region; the pixel defining pattern including a first defining pattern in the first trench and a second defining pattern in the second trench; the first defining pattern including an inner liner film and a first conductive layer on the inner liner film; the inner liner film being disposed along and on the sidewalls and bottom surface of the first trench; the second defining pattern including a second conductive layer; a microlens located on the second surface of the substrate in the first region of the substrate, the microlens corresponding to the plurality of unit pixel regions; A first pad pattern is located on the second surface of the substrate in the second region of the substrate, and the first pad pattern is electrically connected to the first conductive layer; And a second pad pattern, located on the second surface of the substrate in the second region of the substrate, the second pad pattern being electrically connected to the second conductive layer, wherein the image sensor is configured to apply a first voltage to the first conductive layer via the first pad pattern, the image sensor is configured to apply a second voltage to the second conductive layer via the second pad pattern, and the image sensor is configured to apply the second voltage to the ground region of the dummy cell pixel region.

18. The image sensor of claim 17, wherein the first voltage is a negative voltage and the second voltage is a well bias voltage.

19. The image sensor of claim 17, wherein the plurality of unit pixel regions in the first region include a first pixel region and a second pixel region, the first pixel region does not include the ground region, the second pixel region includes the ground region, and the image sensor is configured to use a signal generated from the second pixel region as information for autofocus.

20. The image sensor of claim 19, wherein the second pixel region comprises a first sub-pixel and a second sub-pixel adjacent to each other, each of the first sub-pixel and the second sub-pixel comprising the ground region, and the first sub-pixel and the second sub-pixel sharing the microlens with each other.

Images