Package comprising spacers between integrated devices

Abstract

A package includes: a first integrated device including a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device including a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

Description

Encapsulation including spacers between integrated devices This patent application claims priority and benefit to non-provisional application No. 17 / 574,360, filed on January 12, 2022, with the United States Patent and Trademark Office. The entire contents of the aforementioned application are incorporated herein by reference, as if their entire contents were fully set forth below for all applicable purposes. The various features relate to a package including integrated devices, and more specifically to a package including several integrated devices. A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing various electrical functions. There is a growing need to provide packages with better performance and reduce the overall size of the package. Various features relate to packaging that includes integrated devices, and more specifically to packaging that includes several integrated devices. One example provides a package comprising: a first integrated device including a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device including a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device. Another example provides a package comprising: a substrate, and a stack of integrated devices coupled to the substrate via a first plurality of solder interconnects. The stack of integrated devices includes: a first integrated device including a first plurality of interconnects; a second plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device including a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the second plurality of solder interconnects, and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device. Another example provides a method for manufacturing a package. The method provides a second integrated device including a second plurality of interconnects and a plurality of solder interconnects coupled to the second plurality of interconnects. The method provides a polymer layer and a plurality of spacer balls over the second integrated device. The method couples a first integrated device including a first plurality of interconnects to the second integrated device such that the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects. The first integrated device is coupled to the second integrated device such that the polymer layer and the plurality of spacer balls are located between the first integrated device and the second integrated device. In the following description, specific details are provided to offer a thorough understanding of the various embodiments disclosed. However, those skilled in the art will understand that these embodiments can be implemented without using such specific details. For example, circuits may be shown in block diagrams to avoid obscuring the embodiments with unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail to avoid confusing the embodiments presented herein. This application describes a package comprising: a first integrated device including a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device including a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects, and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device. The use of the plurality of spacer balls helps to ensure that the space (e.g., bonding wire thickness) between the first integrated device and the second integrated device is consistent and / or uniform, thereby helping to provide a robust and reliable connection (e.g., solder joint) between the first integrated device (e.g., a first die) and the second integrated device (e.g., a second die). An exemplary package including an integrated device coupled to an integrated device having spacers between the integrated devices. Figure 1 illustrates a package 100 including integrated device-to-integrated device coupling (e.g., die-to-die coupling), wherein spacers are present between the integrated devices. Package 100 includes an integrated device stack 101, an integrated device 103, a substrate 102, and a substrate 104. Substrate 102 may be a package substrate. Substrate 104 may be an interlayer. Substrate 104 is coupled to substrate 102 via a plurality of solder interconnects 110. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The plurality of solder interconnects 110 are coupled to the plurality of interconnects 122 and the plurality of interconnects 142. Integrated device 103 is coupled to a first surface (e.g., top surface) of substrate 104 via a plurality of solder interconnects 130. Integrated device stack 101 is coupled to the first surface of substrate 104 via a plurality of solder interconnects 150. Figure 2 illustrates a close-up view of an integrated device stack 101 (e.g., an integrated device stack, a vertical stack of integrated devices) including a plurality of integrated devices. The integrated device stack 101 may be a package including a plurality of integrated devices. The integrated device stack 101 includes integrated devices stacked on top of each other (e.g., vertically stacked integrated devices). The integrated device stack 101 includes integrated device 105, integrated device 107a, integrated device 107b, and integrated device 107c. The integrated device stack 101 includes a plurality of spacer balls 190a, a plurality of spacer balls 190b, a plurality of spacer balls 190c, polymer layers 192a, polymer layers 192b, polymer layers 192c, and underfill 204a, underfill 204b, and underfill 204c. As will be further described below, a plurality of spacer balls (e.g., 190a, 190b, 109c) are spacers located between integrated devices to help provide a consistent and uniform gap between the integrated devices, thus helping to ensure proper, robust and / or reliable connections (e.g., solder joints) between the integrated devices. As mentioned above, the integrated device stack 101 can be coupled to the substrate 104. The integrated device 105 can be coupled to a first surface of the substrate 104 via a plurality of solder interconnects 150. Integration device 107a is coupled to integration device 105 via a plurality of solder interconnects 170a. A plurality of spacer balls 190a, a polymer layer 192a, and an underfill 204a are located between integration device 105 and integration device 107a. Integration device 107b is coupled to integration device 107a via a plurality of solder interconnects 170b. A plurality of spacer balls 190b, a polymer layer 192b, and an underfill 204b are located between integration device 107b and integration device 107a. Integration device 107c is coupled to integration device 107b via a plurality of solder interconnects 170c. A plurality of spacer balls 190c, a polymer layer 192c, and an underfill 204c are located between integration device 107c and integration device 107b. The integration device 105 includes a plurality of pad interconnects 250, a plurality of pillar interconnects 252, a plurality of pad interconnects 254, and a plurality of interconnects 255. The plurality of pad interconnects 250, pillar interconnects 252, and / or pad interconnects 254 may be examples of a plurality of interconnects for the integration device 105. The plurality of interconnects 255 are coupled to the plurality of pad interconnects 250 and the plurality of pad interconnects 254. The plurality of interconnects 255 may include a plurality of die interconnects and / or a plurality of through-substrate vias. The integration device 107a includes a plurality of pad interconnects 270a, a plurality of pillar interconnects 272a, a plurality of pad interconnects 274a, a plurality of pillar interconnects 276a, and a plurality of interconnects 275a. The plurality of pad interconnects 270a, pillar interconnects 272a, pad interconnects 274a, and / or pillar interconnects 276a may be examples of a plurality of interconnects for the integration device 107a. The plurality of interconnects 275a are coupled to the plurality of pad interconnects 270a and the plurality of pad interconnects 274a. The plurality of interconnects 275a may include a plurality of die interconnects and / or a plurality of through-substrate vias. The integrated device 107b includes a plurality of pad interconnects 270b, a plurality of pillar interconnects 272b, a plurality of pad interconnects 274b, a plurality of pillar interconnects 276b, and a plurality of interconnects 275b. The plurality of pad interconnects 270b, pillar interconnects 272b, pad interconnects 274b, and / or pillar interconnects 276b may be examples of a plurality of interconnects for the integrated device 107b. The plurality of interconnects 275b are coupled to the plurality of pad interconnects 270b and the plurality of pad interconnects 274b. The plurality of interconnects 275b may include a plurality of die interconnects and / or a plurality of through-substrate vias. The integrated device 107c includes a plurality of pad interconnects 270c, a plurality of pillar interconnects 272c, and a plurality of interconnects 275c. The plurality of pad interconnects 270c and the plurality of pillar interconnects 272c may be examples of a plurality of interconnects for the integrated device 107c. The plurality of interconnects 275c may be coupled to the plurality of pad interconnects 270c. The plurality of interconnects 275c may include a plurality of die interconnects and / or a plurality of through-substrate vias. A plurality of solder interconnects 150 are coupled to a plurality of pillar interconnects 252. A plurality of solder interconnects 170a are coupled to a plurality of pad interconnects 254 and a plurality of pillar interconnects 272a. A plurality of solder interconnects 170b are coupled to a plurality of pillar interconnects 276a and a plurality of pillar interconnects 272b. A plurality of solder interconnects 170c are coupled to a plurality of pillar interconnects 276b and a plurality of pillar interconnects 272c. In some embodiments, the integration device 105 may include a logic die (e.g., a logic semiconductor die). In some embodiments, the integration device 107a may include a memory die (e.g., a memory semiconductor die). In some embodiments, the integration device 107b may include a memory die (e.g., a memory semiconductor die). In some embodiments, the integration device 107c may include a memory die (e.g., a memory semiconductor die). The integrated device may include a die substrate (e.g., a silicon substrate), a plurality of through-substrate vias (TSVs), a plurality of transistors and / or logic cells (not shown), a plurality of die dielectric layers, and a plurality of die interconnects. The plurality of transistors and / or logic cells may be formed in and / or on the die substrate. A front-end line (FEOL) process may be used to form the plurality of transistors and / or logic cells in and on the die substrate. The plurality of die dielectric layers and the plurality of die interconnects may be formed on the die substrate and the plurality of transistors and / or logic cells. A back-end line (BEOL) process may be used to form the plurality of die dielectric layers and the plurality of die interconnects. The plurality of die interconnects may be coupled to the plurality of transistors and / or logic cells. The plurality of die interconnects may be coupled to the plurality of through-substrate vias (TSVs). It should be noted that a plurality of interconnects 275 (e.g., 275a, 275b, 275c) can conceptually represent interconnects that may be located in an integrated device. For example, a plurality of interconnects 275 (e.g., 275a, 275b, 275c) of an integrated device can conceptually represent one or more through-substrate vias (TSVs) and / or one or more die interconnects of the integrated device. The integrated device may include a front side and a back side. The back side of the integrated device may include a side or surface containing a die substrate. The front side of the integrated device may be the side opposite to the back side. As shown in FIG2, the integrated device may include a plurality of interconnects located on the back surface of the integrated device. The plurality of interconnects located on the back surface of the integrated device may be a plurality of back surface interconnects. The plurality of back surface interconnects may include a plurality of pillar interconnects (e.g., back surface pillar interconnects) and / or a plurality of pad interconnects (e.g., back surface pad interconnects). In one example, a plurality of pad interconnects 250 and a plurality of pillar interconnects 252 can be considered as front-side interconnects for integrating device 105, and a plurality of pad interconnects 254 can be considered as back-side interconnects for integrating device 105. In one example, a plurality of pad interconnects 250 and a plurality of pillar interconnects 252 can be considered as back-side interconnects for integrating device 105, and a plurality of pad interconnects 254 can be considered as front-side interconnects for integrating device 105. In one example, a plurality of pad interconnects 270a and a plurality of pillar interconnects 272a can be considered as front-side interconnects for integrating device 107a, and a plurality of pad interconnects 274a and a plurality of pillar interconnects 276a can be considered as back-side interconnects for integrating device 107a. In one example, a plurality of pad interconnects 270b and a plurality of pillar interconnects 272b can be considered as front-side interconnects for integrating device 107b, and a plurality of pad interconnects 274b and a plurality of pillar interconnects 276b can be considered as back-side interconnects for integrating device 107b. In another example, a plurality of pad interconnects 270b and a plurality of pillar interconnects 272b can be considered as back-side interconnects for integrating device 107b, and a plurality of pad interconnects 274b and a plurality of pillar interconnects 276b can be considered as front-side interconnects for integrating device 107b. In one example, a plurality of pad interconnects 270c and a plurality of pillar interconnects 272c can be considered as front-side interconnects for integrating device 107c. In another example, a plurality of pad interconnects 270c and a plurality of pillar interconnects 272c can be considered as back-side interconnects for integrating device 107c. Figure 3 illustrates a package 300 including an integrated device 305 (e.g., a first integrated device, a first die) and an integrated device 307 (e.g., a second integrated device, a second die). Package 300 illustrates an example of integrated device-to-integrated device coupling (e.g., die-to-die coupling). Integrated device 305 is coupled to integrated device 307 via a plurality of solder interconnects 170. Integrated device 305 includes a passivation layer 353, a plurality of pad interconnects 350, and a plurality of pillar interconnects 352. Integrated device 307 includes a passivation layer 373, a plurality of pad interconnects 370, and a plurality of pillar interconnects 372. The plurality of solder interconnects 170 are coupled to the plurality of pillar interconnects 352 and the plurality of pillar interconnects 372. An underfill 204 exists between integrated device 305 and integrated device 307. The underfill 204 may laterally surround the plurality of solder interconnects 170, the plurality of pillar interconnects 352, and / or the plurality of pillar interconnects 372. A plurality of spacer balls 190 (e.g., spacers) and a polymer layer 192 are located between the integration device 305 and the integration device 307. The plurality of spacer balls 190 may be at least partially located in the polymer layer 192. The plurality of spacer balls 190 and the polymer layer 192 are positioned along the periphery of the integration device 305, the integration device 307 and / or the package 300. In some embodiments, the spacing between adjacent solder interconnects from a plurality of solder interconnects 170 is approximately 5-20 micrometers. In some embodiments, the spacing between adjacent pillar interconnects from a plurality of pad interconnects 350 is approximately 5-20 micrometers. In some embodiments, the spacing between adjacent pillar interconnects from a plurality of pillar interconnects 352 is approximately 5-20 micrometers. In some embodiments, the spacing between adjacent pillar interconnects from a plurality of pad interconnects 370 is approximately 5-20 micrometers. In some embodiments, the spacing between adjacent pillar interconnects from a plurality of pillar interconnects 372 is approximately 5-20 micrometers. In some embodiments, a plurality of spacer balls 190 (e.g., spacers) may have a diameter of approximately 5-20 micrometers. A gap 301 exists between the passivation layer 353 of integrated device 305 and the passivation layer 373 of integrated device 307. The gap 301 may represent the bonding line thickness (BLT) between integrated device 305 and integrated device 307. The gap 301 is provided by using a plurality of spacer balls 190 (e.g., spacers). The plurality of spacer balls 190 helps to provide a uniform, constant, or substantially constant gap between integrated device 305 and integrated device 307. This, in turn, helps to ensure a robust and reliable connection between integrated device 305 and integrated device 307. In some embodiments, the gap 301 may be approximately 5-20 micrometers. Figure 3 illustrates an example of front-to-front coupling of the integrated device. That is, the front of the first integrated device is coupled to the front of the second integrated device. However, the two integrated devices can be coupled together via front-to-back coupling, where the front of one integrated device is coupled to the back of another integrated device. In another example, the two integrated devices can be coupled together via back-to-back coupling, where the back of one integrated device is coupled to the back of another integrated device. The integrated device stack 101 of Figures 1 and 2 (e.g., a stack of integrated devices) may include integrated devices coupled to each other via front-to-front coupling, front-to-back coupling, back-to-front coupling, and / or back-to-back coupling. For clarity, note that package 300 does not necessarily illustrate all components of the integrated device. For example, integrated device 305 and / or integrated device 307 may each include other components, such as a die substrate (e.g., a silicon substrate), a plurality of transistors and / or logic cells, a plurality of die interconnects, at least one die dielectric layer, a plurality of through-substrate vias, and / or a plurality of back-side interconnects (e.g., back-side pad interconnects, back-side pillar interconnects). The plurality of through-substrate vias may be coupled to the plurality of die interconnects. The plurality of through-substrate vias may be coupled to the plurality of back-side interconnects. The plurality of die interconnects may be coupled to the plurality of pad interconnects. Integrated device 305 and / or integrated device 307 may be similar to or the same as integrated devices 105, 107a, 107b, and / or 107c of Figures 1 and 2. Figure 4 illustrates an example of what might happen when integrated devices are coupled together without the use of spacers. Figure 4 illustrates a package 400 similar to package 300. However, package 400 does not include any spacers. In the coupling process between integrated device 307 and integrated device 305, more pressure may be applied to one side of the integrated device, resulting in a gap 401a on one side of package 400 and a gap 401b on the other side of package 400. Gap 401b is larger than gap 401a. The difference in gaps and / or variations in gaps can lead to poor or open connections between integrated device 305 and integrated device 307. For example, the solder interconnect 470 between integrated device 305 and integrated device 307 may be less robust or reliable than the solder interconnect 170 because the solder interconnect 470 has been elongated due to the higher gap 401b between integrated device 305 and integrated device 307. Multiple spacers 190 help ensure that such variations in gaps are minimized, reduced, and / or eliminated. Figure 5 illustrates a wafer 500 including a plurality of integrated devices 502 (e.g., uncuttered integrated devices). The plurality of integrated devices 502 are manufactured simultaneously and subsequently diced in a manufacturing process. The plurality of integrated devices 502 includes integrated device 502a and integrated device 502b. The plurality of integrated devices 502 may be separated by a dicing region 504. The dicing region 504 may be a region of the wafer 500 that can be filled with a plurality of spacer balls 190 and a polymer layer 192. The dicing region 504 may include dicing lines 506, which are portions of the wafer that are cut or removed to divide the integrated devices. The plurality of spacer balls 190 may be at least partially located in the polymer layer 192. The polymer layer 192 may include an adhesive. The polymer layer 192 helps to position the spacer balls 190 in appropriate areas between the uncuttered integrated devices. The plurality of spacer spheres 190 may include particles comprising monodisperse particles, silicon dioxide, glass, polymers, ceramics, and / or metals. For example, the plurality of spacer spheres 190 may include polyethylene polymer particles. The underfill 204 (e.g., nonconductive film (NCF) underfill, wafer-level underfill (WLUF)) may laterally surround the plurality of weld interconnects 170 and / or the plurality of pillar interconnects 352. The integrated device (e.g., 105, 107, 305, 307) may include a die (e.g., a semiconductor bare die). The integrated device may include a die substrate (e.g., a silicon substrate), a plurality of transistors and / or logic units, a plurality of die interconnects, and a plurality of pad interconnects. The integrated device may include logic dies, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memory, power management processors (e.g., power management integrated circuits (PMICs)), and / or combinations thereof. The integrated device (e.g., 105, 107, 305, 307) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). In some embodiments, the integrated device may be a chiplet. Smaller wafers can provide better yield during manufacturing, thus reducing the overall cost of manufacturing them. Different wafers can have different sizes and / or shapes. Different wafers can be configured to provide different functions. Different wafers can have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some implementations, several wafers can be used to perform the functions of one or more wafers (e.g., one or more integrated devices). Using several wafers performing several functions can reduce the overall cost of the package compared to using a single wafer to perform all the functions of the package. Various packages having integrated device-to-integrated device couplings, wherein there are multiple spacers (e.g., spacer balls) between the integrated devices, have been described. Procedures for manufacturing packages including integrated device-to-integrated device couplings will now be described below. An exemplary sequence for manufacturing a package comprising an integrated device coupled to an integrated device having spacers between them. Figures 6A-6B illustrate an exemplary sequence for providing or manufacturing a package. In some embodiments, the sequence of Figures 6A-6B can be used to provide or manufacture the package 300 of Figure 3, or any package described herein. It should be noted that the sequence of Figures 6A-6B can be combined with one or more stages to simplify and / or clarify the sequence used to provide or manufacture the package. In some embodiments, the order of procedures can be changed or modified. In some embodiments, one or more procedures can be replaced or substituted without departing from the scope of this invention. Different embodiments can manufacture packages in different ways. The sequence of Figures 6A-6B illustrates an example of manufacturing two packages together. However, the sequence of Figures 6A-6B can be used to manufacture more than two packages that are vertically stacked on top of each other. As shown in Figure 6A, Stage 1 illustrates the state of wafer 600 after integrating devices 307a and 307b. Integration devices 307a and 307b are uncut integration devices among a plurality of integration devices from wafer 600. Each integration device may include a plurality of pad interconnects 370, a plurality of pillar interconnects 372, and a plurality of solder interconnects 170. Wafer 600 may be a second wafer including a plurality of second integration devices. Figures 8A-8B illustrate examples of procedures that can be used to form a wafer including integration devices. Phase 2 illustrates the state after a plurality of spacer balls 190 and a polymer layer 192 are provided on wafer 600 such that the plurality of spacer balls 190 and the polymer layer 192 are positioned between uncut integrated devices. For example, the plurality of spacer balls 190 and the polymer layer 192 may be provided in a dicing region 504 of the wafer. The dicing region 504 may be a region cut to divide the integrated devices of wafer 600. The polymer layer 192 may include an adhesive layer to help position the spacer balls in appropriate regions of wafer 600. Phase 3 illustrates the state after underfill 204 is formed on the integration device (e.g., an uncut integration device) of wafer 600, such that the underfill can laterally surround a plurality of pillar interconnects 372 and / or a plurality of solder interconnects 170. As shown in Figure 6B, stage 4 illustrates the state of wafer 610 after integrating devices 305a and 305b. Integration devices 305a and 305b are uncut integration devices among a plurality of integration devices from wafer 610. Each integration device may include a plurality of pad interconnects 350, a plurality of pillar interconnects 352, and a plurality of solder interconnects 170. Wafer 610 may be a first wafer including a plurality of first integration devices. Figures 8A-8B illustrate examples of processes that can be used to form a wafer including integration devices. Phase 5 illustrates the state after wafer 600 is coupled to wafer 610. A solder reflow process can be used to couple wafer 600 to wafer 610. Wafer 600 (including integration device 307) is coupled to wafer 610 (including integration device 305) via a plurality of solder interconnects 170. A plurality of spacer balls 190 help ensure that the gap between wafer 600 and wafer 610 is uniform or nearly uniform. Stage 6 illustrates the state after wafers 600 and 610 have been diced to create a plurality of packages including integrated devices coupled to each other. Wafers 600 and 610 can be diced along dicing line 620. After dicing, packages 300a and 300b can be formed. The wafers can be diced using mechanical processes (e.g., sawing) or laser processes. In some embodiments, additional wafers can be coupled prior to dicing to form packages including more than two integrated devices, as described in Figure 2. An exemplary flowchart of a method for manufacturing an integrated package including integrated devices coupled together with spacers between them. In some embodiments, manufacturing a package includes several procedures. Figure 7 illustrates an exemplary flowchart of a method 700 for providing or manufacturing a package. In some embodiments, the method 700 of Figure 7 can be used to provide or manufacture the package 300 of Figure 3 described in this specification. However, method 700 can be used to provide or manufacture any package described in this specification. It should be noted that the method of Figure 7 can combine one or more procedures to simplify and / or clarify the method for providing a package with several integrated devices. In some embodiments, the order of the procedures can be changed or modified. This method provides (at 705) a wafer comprising a plurality of integrated devices. For example, the method can provide a wafer 600 comprising a plurality of integrated devices. The plurality of integrated devices are undrilled integrated devices. Wafer 600 can be a second wafer comprising a plurality of second integrated devices. Each undrilled integrated device may include a plurality of pad interconnects 370, a plurality of pillar interconnects 372, and a plurality of solder interconnects 170. Figures 8A-8B illustrate examples of procedures that can be used to form a wafer comprising integrated devices. Stage 1 of Figure 6A shows and describes an example of providing a wafer comprising undrilled integrated devices. This method provides (at 710) a plurality of spacer balls 190 and a polymer layer 192 on a wafer (e.g., 600) such that the plurality of spacer balls 190 and the polymer layer 192 are located between uncut integrated devices. For example, the plurality of spacer balls 190 and the polymer layer 192 may be provided in a dicing region 504 of the wafer. The dicing region 504 may be a region cut to divide the integrated devices of the wafer (e.g., 600). The polymer layer 192 may include an adhesive layer to help position the spacer balls in appropriate regions of the wafer (e.g., 600). Phase 2 of Figure 6A illustrates and describes an example of providing spacer balls and a polymer layer. This method provides (e.g., at 715) an underfill (e.g., 204) on the integration device of the wafer (e.g., 600) such that the underfill can laterally surround a plurality of pillar interconnects 372 and / or a plurality of solder interconnects 170. Stage 3 of Figure 6A illustrates and describes an example of providing the underfill. This method provides (at 720) a wafer (e.g., 610) comprising a plurality of integrated devices. For example, the method can provide a wafer 610 comprising a plurality of integrated devices. Wafer 610 comprises uncuttered integrated devices. Each uncuttered integrated device may include a plurality of pad interconnects 350, a plurality of pillar interconnects 352, and a plurality of solder interconnects 170. Wafer 610 may be a first wafer comprising a plurality of first integrated devices. Figures 8A-8B illustrate examples of procedures that can be used to form a wafer comprising integrated devices. Stage 4 of Figure 6B shows and describes an example of providing a wafer comprising uncuttered integrated devices. This method couples a second wafer (e.g., 600) to a first wafer (e.g., 610) at 725. A solder reflow process can be used to couple the second wafer to the first wafer. The second wafer (e.g., 600), including a plurality of second integrated devices, can be coupled to the first wafer (e.g., 610), including a plurality of first integrated devices, via a plurality of solder interconnects (e.g., 170). A plurality of spacer balls 190 help ensure that the gap between wafers 600 and 610 is uniform or nearly uniform. Stage 5 of Figure 6B illustrates and describes an example of coupled wafers. In some embodiments, additional wafers can be coupled to the coupled wafers. This method slits (at 730) the wafer to form a slit package comprising a plurality of integrated devices with spacer balls and a polymer layer between the integrated devices. The wafer can be slit using a mechanical process (e.g., sawing) or a laser process. Stage 6 of Figure 6B illustrates and describes an example of wafer slitting. Exemplary sequence for manufacturing an integrated device with column interconnections Figures 8A-8B illustrate exemplary sequences for providing or manufacturing an integrated device with column interconnects. In some embodiments, the sequence of Figures 8A-8B can be used to provide or manufacture the integrated device of Figure 3 (e.g., 305, 307), or any integrated device described herein. It should be noted that the sequence of Figures 8A-8B can be combined with one or more stages to simplify and / or clarify the sequence for providing or manufacturing the integrated device. In some embodiments, the order of procedures can be changed or modified. In some embodiments, one or more procedures can be replaced or substituted without departing from the scope of this invention. Different embodiments can manufacture the integrated device differently. As shown in Figure 8A, Phase 1 illustrates the state after the integration device 305 is provided. The integration device 305 may include a die (e.g., a bare semiconductor die). The integration device 305 may include a die substrate (e.g., a silicon substrate) and a plurality of transistors (e.g., active devices). The integration device 305 may include a plurality of pad interconnects 350. The integration device 305 may include die interconnects and / or through-substrate vias. Phase 2 illustrates the state after a seed layer 811 has been formed on the front side of the integrated device 305. The seed layer 811 may include a metal layer. The seed layer 811 may be deposited on the integrated device 305. An electroplating process may be used to form the seed layer 811. Stage 3 illustrates the state after the photoresist layer 800 is formed on the seed layer 811. The photoresist layer 800 can be deposited on the seed layer 811. Phase 4 illustrates the state after the photoresist layer 800 has been patterned, with at least one opening 801 created in the photoresist layer 800, which exposes a portion of the seed layer 811. As shown in Figure 8B, stage 5 illustrates the state after a plurality of pillar interconnects 830 and a plurality of solder interconnects 832 are formed on the seed layer 811 via openings 801 in the photoresist layer 800. The plurality of pillar interconnects 830 can be formed on the seed layer 811 via an electroplating process. The plurality of solder interconnects 830 can be formed on the pillar interconnects 830 via a deposition process. Stage 6 illustrates the state after removing the photoresist layer 800 and removing (e.g., etching) a portion of the seed layer 811. Removing the photoresist layer 800 may include stripping the photoresist layer 800. Stage 7 illustrates the state after a reflow soldering process in which a plurality of solder interconnects 170 are coupled (e.g., bonded) to a plurality of pillar interconnects 830. Stage 7 may show an integrated device with pillar interconnects (e.g., 305, 307). The plurality of pillar interconnects 830 may represent a plurality of pillar interconnects 352. A seed layer 811 may be considered as part of the pillar interconnects 830. Therefore, the seed layer 811 and the plurality of pillar interconnects 830 may represent the plurality of pillar interconnects 352. Exemplary flowchart of a method for manufacturing an integrated device including column interconnects In some embodiments, manufacturing an integrated device with column interconnects includes several procedures. Figure 9 illustrates an exemplary flowchart of a method 900 for providing or manufacturing an integrated device with column interconnects. In some embodiments, method 900 of Figure 9 can be used to provide or manufacture the integrated device of Figure 3 described in this description (e.g., 305, 307). However, method 900 can be used to provide or manufacture any integrated device described in this description. It should be noted that the method 900 of Figure 9 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing an integrated device with column interconnects. In some embodiments, the order of the procedures can be changed or modified. This method provides an integration device (e.g., 305, 307) at 905. Phase 1 of Figure 8A illustrates and describes the provided integration device 305. Integration device 305 may include a die having an active device (e.g., a transistor). Integration device may include a plurality of pad interconnects. Integration device may include a die substrate, die interconnects, and / or through-substrate vias. This method forms a seed layer (e.g., 811) on the front side of the integrated device (at 910). Seed layer 811 may include a metal layer. Seed layer 811 may be deposited on the integrated device 305. An electroplating process may be used to form seed layer 811. Stage 2 of Figure 8A illustrates and describes an example of forming a seed layer. This method involves forming (at 915) a photoresist layer (e.g., 800) on a seed layer (e.g., 811). The photoresist layer 800 may be formed on the seed layer 811 and patterned. The photoresist layer 800 may be deposited on the seed layer 811 and patterned to create at least one opening 801 in the photoresist layer 800 that exposes a portion of the seed layer 811. Stages 3-4 of Figure 8A illustrate and describe an example of forming and patterning a photoresist layer on a seed layer. This method involves forming (at 920) a plurality of pillar interconnects (e.g., 830) and / or solder interconnects (e.g., 170) on a seed layer (e.g., 811) via openings 801 in a photoresist layer (e.g., 800). The plurality of pillar interconnects can be formed on the seed layer via an electroplating process. The plurality of solder interconnects can be formed on the plurality of pillar interconnects via a deposition process and / or a printing process. Stage 5 of Figure 8B illustrates and describes an example of forming the plurality of pillar interconnects and / or solder interconnects. This method removes (at 925) the photoresist layer (e.g., 800). Removing the photoresist layer may include stripping the photoresist layer. Stage 6 of Figure 8B illustrates an example of photoresist layer removal. In some embodiments, portions of the seed layer 811 may also be removed (at 925). An etching process can be used to remove portions of the seed layer. Stage 6 of Figure 8B shows and describes an example of a portion of the seed layer being removed. It should be noted that the formation of the photoresist layer, pillar interconnects, and / or solder interconnects, as described at 915, 920, and 925, and the removal of the photoresist layer can be repeated. This method performs a reflow soldering process (at 930) coupling (e.g., bonding) a plurality of solder interconnects (e.g., 170) to a plurality of pillar interconnects (e.g., 830). The plurality of pillar interconnects 830 and / or seed layer 811 may represent a plurality of pad interconnects 350. Stage 7 of Figure 8B illustrates and describes an example of a reflow soldering process. In some embodiments, the integrated device is part of a wafer, and dicing can be performed to cut the wafer into individual integrated devices. Method 900 can be used to manufacture any integrated device described in this specification. Exemplary electronic devices Figure 10 illustrates various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1002, laptop device 1004, fixed-location terminal device 1006, wearable device 1008, or motor vehicle 1010 may include the device 1000 described herein. Device 1000 can be any device and / or integrated circuit (IC) package described herein, as shown below. Devices 1002, 1004, 1006, and 1008, as well as vehicle 1010, shown in Figure 10 are merely exemplary. Other electronic devices may also include device 1000, including but not limited to a group of devices (e.g., electronic devices) comprising the following: mobile devices, handheld personal communication system (PCS) units, portable data units (e.g., personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (e.g., meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof. One or more of the elements, programs, features, and / or functions shown in Figures 1-5, 6A-6B, 7, 8A-8B, and / or 9-10 can be rearranged and / or combined into a single element, program, feature, or function, or embodied in several elements, programs, or functions. Additional elements, components, programs, and / or functions may also be added without departing from the scope of this invention. It should also be noted that Figures 1-5, 6A-6B, 7, 8A-8B, and / or 9-10 and their corresponding descriptions in this invention are not limited to chips and / or ICs. In some embodiments, Figures 1-5, 6A-6B, 7, 8A-8B, and / or 9-10 and their corresponding descriptions can be used to manufacture, establish, provide, and / or produce equipment and / or integrate devices. In some embodiments, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a thermal device, and / or an interlayer. It should be noted that the accompanying drawings in this document may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, these drawings may not be drawn to scale. In some instances, not all elements and / or components may be shown for clarity. In some instances, the orientation, position, size, and / or shape of the various components and / or elements in the drawings may be exemplary. In some embodiments, the various elements and / or components in the drawings may be optional. As used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any implementation or manner described herein as "exemplary" is not necessarily to be construed as preferred or superior to other manners in this content. Similarly, the term "manner" does not require that all manners in this content include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, then objects A and C are still considered coupled to each other—even if they are not physically in direct contact. The term "electrical coupling" may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. There may or may not be current flowing between the two electrically coupled objects. The use of the terms "first," "second," "third," and "fourth" (and / or any higher than fourth) is arbitrary. Any element described may be a first element, a second element, a third element, or a fourth element. For example, an element referred to as a second element can be a first element, a second element, a third element, or a fourth element. The term "encapsulation" means that the object can partially or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. An element located at the top may be above an element located at the bottom. A top element can be considered a bottom element, and vice versa. As described in the content of this case, a first element located "above" a second element can be displaced to be located above or below the second element, depending on how bottom or top is arbitrarily defined. In another instance, a first element may be located above (e.g., above) a first surface of a second element, and a third element may be located above (e.g., below) a second surface of a second element, where the second surface is opposite the first surface. It should also be noted that, in the context of an element being above another element, the term "above" as used in this case can be used to mean an element on and / or in another element (e.g., on the surface of an element or embedded in an element). Therefore, for example, "first element on second element" can mean (1) the first element is on the second element but does not directly contact the second element, (2) the first element is on the second element (e.g., on its surface), and / or (3) the first element is (e.g., embedded) in the second element. A first element located "in" the second element can be partially or completely located in the second element. Values ​​of X-XX can mean values ​​between X and XX, including X and XX. Values ​​between X and XX can be discrete or continuous. The terms "approximately 'value X'" or "approximately value X" as used in this context mean within 10% of 'value X'. For example, a value approximately 1 or approximately 1 would mean a value in the range of 0.9-1.1. In some embodiments, an interconnect is a device or package element or component that allows or facilitates an electrical connection between two points, components, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or sequences to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or electroplating processes may be used to form interconnects. Furthermore, it should be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, diagrams, block diagrams, or block diagrams. Although a flowchart may describe operations as a sequential procedure, many operations within an operation can be executed in parallel or concurrently. Moreover, the order of such operations can be rearranged. The program terminates when its operations are completed. The following provides an overview of the nature of the case: Specimen 1: A package comprising: a first integrated device including a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device including a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device. Version 2: The encapsulation according to Version 1, wherein the polymer layer includes an adhesive layer. State 3: The encapsulation according to State 1 to State 2, wherein the plurality of spacer spheres are at least partially located in the polymer layer. State 4: Packaged according to State 1 to State 3, wherein the plurality of spacer spheres comprise particles containing monodisperse particles, silicon dioxide, glass, polymer, ceramic and / or metal. Sample 5: Packaged according to Samples 1 to 3, wherein the plurality of spacer spheres comprise polyethylene polymer particles. Version 6: Based on the packaging of versions 1 to 5, it further includes bottom filling located between the first integrated device and the second integrated device. State 7: Package according to State 1 to State 6, wherein the spacing between adjacent interconnects from the first plurality of interconnects is approximately 20 micrometers or less. State 8: Package according to State 1 to State 7, wherein the spacing between adjacent solder interconnects from the plurality of solder interconnects is approximately 20 micrometers or less. Type 9: Package according to Types 1 to 8, wherein the first plurality of interconnects includes a first plurality of pillar interconnects, and wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects and the first plurality of pillar interconnects. State 10: Packaged according to State 1 to State 9, wherein the first integrated device includes a first die, and wherein the second integrated device includes a second die. State 11: Packaged according to State 1 to State 10, wherein the first integrated device includes a first memory die, and wherein the second integrated device includes a logic die or a second memory die. Version 12: According to the packaging of versions 1 to 11, it further includes: a third integrated device including a third plurality of interconnects; a second polymer layer located between the third integrated device and the second integrated device; and a second plurality of spacer balls located between the third integrated device and the second integrated device. Version 13: According to the package of Version 12, the third integrated device is coupled to the second integrated device via the third plurality of interconnects and the second plurality of solder interconnects. Version 14: Packaged according to Version 12, wherein the second integrated device includes a plurality of through-holes in the substrate. Type 15: Package according to Type 1 to Type 14, wherein the first plurality of interconnects includes a first plurality of pillar interconnects and / or a first plurality of pad interconnects, and wherein the second plurality of interconnects includes a second plurality of pillar interconnects and / or a second plurality of pad interconnects. Version 16: Package according to versions 1 to 15, wherein the first integrated device includes a third plurality of interconnects, wherein the first plurality of interconnects are located on a first surface of the first integrated device, and wherein the third plurality of interconnects are located on a second surface of the first integrated device. Type 17: Packages according to Types 1 to 16, wherein the package is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles. Sample 18: A package comprising: a substrate; and a stack of integrated devices coupled to the substrate via a first plurality of solder interconnects. The stack of integrated devices comprises: a first integrated device including a first plurality of interconnects; a second plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device including a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the second plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device. Version 19: Package according to Version 18, wherein the first integrated device from the stack of the integrated device is coupled to the substrate via the first plurality of solder interconnects. Sample 20: Packaged according to Samples 18 to 19, wherein the plurality of spacer spheres comprise particles containing monodisperse particles, polyethylene polymer particles, silicon dioxide, glass, polymer, ceramic and / or metal. Version 21: According to the packaging of versions 18 to 20, it further includes bottom filler located between the first integrated device and the second integrated device. State 22: According to the package of states 18 to 21, the first integrated device is coupled to the second integrated device via front-to-front coupling, front-to-back coupling, back-to-front coupling or back-to-back coupling. Sample 23: A method for manufacturing a package, comprising: providing a second integrated device including a second plurality of interconnects and a plurality of solder interconnects coupled to the second plurality of interconnects; providing a polymer layer and a plurality of spacer balls over the second integrated device; and coupling a first integrated device including a first plurality of interconnects to the second integrated device such that the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects, wherein the first integrated device is coupled to the second integrated device such that the polymer layer and the plurality of spacer balls are located between the first integrated device and the second integrated device. Sample 24: The method according to Sample 23, wherein the polymer layer includes an adhesive layer. Sample 25: According to the method of Samples 23 to 24, wherein the plurality of spacer spheres comprises particles containing monodisperse particles, polyethylene polymer particles, silicon dioxide, glass, polymer, ceramic and / or metal. Version 26: The method according to versions 23 to 25 further includes: providing a bottom filler on the second integrated device, wherein the first integrated device is coupled to the second integrated device such that the bottom filler is located between the first integrated device and the second integrated device. Without departing from the disclosed content, the various features of the disclosed content described herein can be implemented in different systems. It should be noted that the above-described forms of the content are merely examples and should not be construed as limiting the scope of the claims. The descriptions of the forms of the content are intended to be illustrative and not to limit the scope of the claims. Therefore, the teachings of this invention can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art. 100: Package; 101: Integrated Device Stack; 102: Substrate; 103: Integrated Device; 104: Substrate; 105: Integrated Device; 107a: Integrated Device; 107b: Integrated Device; 107c: Integrated Device; 110: Solder Interconnect; 120: Dielectric Layer; 122: Interconnect; 130: Solder Interconnect; 140: Dielectric Layer; 142: Interconnect; 150: Solder Interconnect; 170: Solder Interconnect; 170a: Solder Interconnect; 170b: Solder Interconnect; 170c: Solder Interconnect; 190: Spacer Ball; 190a: Spacer Ball; 190b: Spacer Ball; 190c: Spacer Ball 2: Polymer layer 192a: Polymer layer 192b: Polymer layer 192c: Polymer layer 204: Underfill 204a: Underfill 204b: Underfill 204c: Underfill 250: Pad interconnect 252: Pillar interconnect 254: Pad interconnect 255: Interconnect 270a: Pad interconnect 270b: Pad interconnect 270c: Pad interconnect 272a: Pillar interconnect 272b: Pillar interconnect 272c: Pillar interconnect 274a: Pad interconnect 274b: Pad interconnect 275a: Interconnect 275b: Interconnect 275c: Interconnect 276 a: Interconnect 276 b: Interconnect 300: Package 300 a: Package 300 b: Package 301: Gap 305: Integration Device 305 a: Integration Device 305 b: Integration Device 307: Integration Device 307 a: Integration Device 307 b: Integration Device 350: Pad Interconnect 352: Interconnect 353: Passivation Layer 370: Pad Interconnect 372: Pillar Interconnect 373: Passivation Layer 400: Package 401 a: Gap 401 b: Gap 470: Solder Interconnect 500: Wafer 502: Integration Device 502 a: Integration Device 502 b: Integration Apparatus 504: Cutting area 506: Cutting line 600: Wafer 610: Wafer 620: Cutting line 700: Method 705: Operation 710: Operation 715: Operation 720: Operation 725: Operation 730: Operation 800: Photoresist layer 801: Opening 811: Seed layer 830: Pillar interconnect 900: Method 905: Operation 910: Operation 915: Operation 920: Operation 925: Operation 930: Operation 1000: Equipment 1002: Equipment 1004: Equipment 1006: Equipment 1008: Equipment 1010: Vehicle Various features, properties and advantages will become apparent from the specific embodiments described below in conjunction with the accompanying drawings, in which the same element symbols are correspondingly identified throughout. Figure 1 illustrates a cross-sectional view of an integrated device package including an integrated device coupled to another integrated device, wherein spacer balls are present between the integrated devices. Figure 2 illustrates a cross-sectional view of a package including a first integrated device coupled to a second integrated device, wherein a spacer ball is present between the first integrated device and the second integrated device. Figure 3 illustrates a cross-sectional view of a package of a first integrated device coupled to a second integrated device, wherein a spacer ball is present between the first integrated device and the second integrated device. Figure 4 illustrates a cross-sectional view of a package including a first integrated device coupled to a second integrated device, wherein there is no spacer ball between the first integrated device and the second integrated device. Figure 5 illustrates a wafer comprising several integrated devices having polymer layers and spacer spheres. Figures 6A-6B illustrate an exemplary sequence for manufacturing a package including a first integrated device coupled to a second integrated device, wherein a spacer ball is present between the first integrated device and the second integrated device. Figure 7 illustrates an exemplary flowchart of a method for manufacturing a package including a first integrated device coupled to a second integrated device, wherein a spacer ball is present between the first integrated device and the second integrated device. Figures 8A-8B illustrate an exemplary sequence for manufacturing an integrated device with column interconnections. Figure 9 illustrates an exemplary flowchart of a method for manufacturing an integrated device with column interconnections. Figure 10 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None. 101: Integrated Device Stack 105: Integrated Device 107a: Integrated device 107b: Integrated device 107c: Integrated device 150: Welded Interconnection 170a: Welded Interconnection 170b: Welded Interconnection 170c: Welded interconnect 190a: Interval ball 190b: Interval ball 190c: Interval ball 192a: Polymer layer 192b: Polymer layer 192c: Polymer layer 204a: Bottom Fill 204b: Bottom Fill 204c: Bottom Fill 250: Pad interconnect 252: Column Interconnection 254: Pad interconnect 255: Interconnection 270a: Pad interconnect 270b: Pad interconnect 270c: Pad interconnect 272a: Column Interconnection 272b: Column Interconnection 272c: Column Interconnect 274a: Pad interconnect 274b: Pad interconnect 275a: Interconnection 275b: Interconnection 275c: Interconnect 276a: Interconnection 276b: Interconnection

Claims

1. A package, comprising: A first integrated device, comprising a first plurality of interconnects; A plurality of welded interconnects, which are coupled to the first plurality of interconnects; A second integrated device includes a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of weld interconnects, and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; a plurality of spacer balls located between the first integrated device and the second integrated device; and an underfill at least partially surrounding the plurality of weld interconnects; wherein a portion of the polymer layer at least partially surrounds the plurality of spacer balls and is laterally adjacent to and in direct contact with the underfill.

2. The encapsulation as described in claim 1, wherein the polymer layer includes an adhesive layer.

3. The package as described in claim 1, wherein the plurality of spacer spheres comprises particles comprising monodisperse particles, silicon dioxide, glass, polymer, ceramic and / or metal.

4. The encapsulation as described in claim 1, wherein the plurality of spacer spheres comprise polyethylene polymer particles.

5. The package as described in claim 1, wherein the bottom filler is located between the first integrated device and the second integrated device.

6. The package as described in claim 1, wherein a spacing between adjacent interconnects from the first plurality of interconnects is approximately 20 micrometers or less.

7. The package as described in claim 1, wherein a spacing between adjacent solder interconnects from the plurality of solder interconnects is approximately 20 micrometers or less.

8. The package as claimed in claim 1, wherein the first plurality of interconnects includes a first plurality of pillar interconnects, and wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects and the first plurality of pillar interconnects.

9. The package as claimed in claim 1, wherein the first integrated device includes a first die, and wherein the second integrated device includes a second die.

10. The package as described in claim 1, wherein the first integrated device includes a first memory die, and wherein the second integrated device includes a logic die or a second memory die.

11. The encapsulation as described in claim 1, further comprising: The third integration device includes a third plurality of interconnections; A second polymer layer is located between the third integrated device and the second integrated device; and a second plurality of spacer balls, which are located between the third integrated device and the second integrated device.

12. The package as described in claim 11, wherein the third integrated device is coupled to the second integrated device via the third plurality of interconnects and the second plurality of solder interconnects.

13. The package as described in claim 11, wherein the second integrated device includes a plurality of through-holes in the substrate.

14. The package as claimed in claim 1, wherein the first plurality of interconnects includes a first plurality of pillar interconnects and / or a first plurality of pad interconnects, and wherein the second plurality of interconnects includes a second plurality of pillar interconnects and / or a second plurality of pad interconnects.

15. The package as claimed in claim 1, wherein the first integrated device includes a third plurality of interconnects, wherein the first plurality of interconnects are located on a first surface of the first integrated device, and wherein the third plurality of interconnects are located on a second surface of the first integrated device.

16. The package as described in claim 1, wherein the package is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

17. The encapsulation as claimed in claim 1, wherein the polymer layer forms a first sidewall, and the bottom fill forms a second sidewall, and the first sidewall and the second sidewall are in direct contact.

18. A package comprising: One substrate; A stack of integrated devices coupled to the substrate via a first plurality of solder interconnects, wherein the stack of integrated devices comprises: a first integrated device including a first plurality of interconnects; a second plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device including a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the second plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; a plurality of spacer balls located between the first integrated device and the second integrated device; and an underfill at least partially surrounding the plurality of solder interconnects; wherein a portion of the polymer layer at least partially surrounds the plurality of spacer balls and is laterally adjacent to and in direct contact with the underfill.

19. The package as described in claim 18, wherein the first integrated device from the stack of the integrated device is coupled to the substrate via the first plurality of solder interconnects.

20. The package as described in claim 18, wherein the plurality of spacer spheres comprises particles comprising monodisperse particles, polyethylene polymer particles, silicon dioxide, glass, polymer, ceramic and / or metal.

21. The package as described in claim 18, wherein the bottom filler is located between the first integrated device and the second integrated device.

22. The package as described in claim 18, wherein the first integrated device is coupled to the second integrated device via front-to-front coupling, front-to-back coupling, back-to-front coupling, or back-to-back coupling.

23. A method for manufacturing a package, comprising the steps of: providing a second integrated device including a second plurality of interconnects and a plurality of solder interconnects coupled to the second plurality of interconnects; providing an underfill at least partially surrounding the plurality of solder interconnects; providing a polymer layer and a plurality of spacer balls over the second integrated device; and coupling a first integrated device including a first plurality of interconnects to the second integrated device such that the second integrated device is coupled to the first integrated device via the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects, wherein the first integrated device is coupled to the second integrated device such that the polymer layer and the plurality of spacer balls are located between the first integrated device and the second integrated device; wherein a portion of the polymer layer at least partially surrounds the plurality of spacer balls and is laterally adjacent to and in direct contact with the underfill.

24. The method as described in claim 23, wherein the polymer layer includes an adhesive layer.

25. The method as described in claim 23, wherein the plurality of spacer spheres comprises particles comprising monodisperse particles, polyethylene polymer particles, silicon dioxide, glass, polymer, ceramic and / or metal.

26. The method as described in claim 23, wherein the bottom filler is located between the first integrated device and the second integrated device.

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