Semiconductor device and fabrication method thereof

Abstract

A semiconductor device includes: a fin-like structure disposed on a substrate; and an epitaxial semiconductor layer disposed on the upper part of the fin-like structure, wherein the epitaxial semiconductor layer has a bottom recess. The epitaxial semiconductor layer has a bilaterally symmetrical concave polygonal cross-section.

Description

Semiconductor Device and Method of Manufacturing the Same The present invention relates to the field of semiconductor technology, and more particularly to an improved fin field effect transistor device and a method of manufacturing the same. It is known that compressive stress can increase the carrier mobility of P-channel metal oxide semiconductor (PMOS) devices. One method of introducing compressive stress in the PMOS transistor channel region involves growing a SiGe epitaxial layer in a recess in the source / drain region. In this method, the lattice size difference between the epitaxial SiGe and the silicon substrate generates uniaxial compressive stress in the channel region. In order to effectively increase the channel compressive strain in PMOS devices, a relatively high germanium concentration is required in the epitaxial SiGe. As the germanium concentration increases, the level of uniaxial compressive strain that appears in the channel region further increases. This uniaxial compressive strain can increase the mobility of holes in the channel region of PMOS transistors. However, as the germanium concentration in the epitaxial SiGe increases, a high density of defects is generated, limiting its application. The main object of the present invention is to provide an improved semiconductor transistor device and a method of manufacturing the same to solve the deficiencies or drawbacks of the prior art. One aspect of the present invention provides a semiconductor device, comprising: a fin structure disposed on a substrate; and an epitaxial semiconductor layer disposed on top of the fin structure, and the epitaxial semiconductor layer has a bottom recess. According to an embodiment of the present invention, the fin structure protrudes from the substrate along a first direction, and the bottom recess has a surface parallel to a second direction intersecting the first direction. According to an embodiment of the present invention, the bottom recess has a curved surface. According to an embodiment of the present invention, the substrate comprises silicon. According to an embodiment of the present invention, the fin structure comprises silicon. According to an embodiment of the present invention, the semiconductor device is a PMOS transistor and the epitaxial semiconductor layer comprises compressive stress silicon germanium. According to an embodiment of the present invention, the semiconductor device further comprises: an oxide liner conformally covering the bottom recess; and an isolation structure surrounding the fin structure, wherein the oxide liner directly contacts the isolation structure. According to an embodiment of the present invention, the oxide liner comprises silicon dioxide. According to an embodiment of the present invention, the thickness of the oxide liner is 1 - 30 angstroms. According to an embodiment of the present invention, the epitaxial semiconductor layer has a left-right symmetric concave polygon cross-section. On the other hand, the present invention provides a method for forming a semiconductor device, comprising: providing a fin structure on a substrate; forming an epitaxial semiconductor layer on the upper part of the fin structure; and after forming the epitaxial semiconductor layer, etching the lower part of the epitaxial semiconductor layer to form a bottom recess. According to an embodiment of the present invention, the fin structure protrudes from the substrate along a first direction, and the bottom recess has a surface parallel to a second direction intersecting the first direction. According to an embodiment of the present invention, the bottom recess has a curved surface. According to an embodiment of the present invention, the substrate comprises silicon. According to an embodiment of the present invention, the fin structure comprises silicon. According to an embodiment of the present invention, the semiconductor device is a PMOS transistor and the epitaxial semiconductor layer comprises compressively strained silicon germanium. According to an embodiment of the present invention, the method further comprises: forming an oxide liner to conformally cover the bottom recess; and forming an isolation structure around the fin structure, wherein the oxide liner directly contacts the isolation structure. According to an embodiment of the present invention, the oxide liner comprises silicon dioxide. According to an embodiment of the present invention, the thickness of the oxide liner is 1-30 angstroms. According to an embodiment of the present invention, the epitaxial semiconductor layer has a concave polygonal cross-section that is symmetric about a left-right axis. Hereinafter, details will be described with reference to the accompanying drawings, which also form part of the detailed description of the specification and are shown in a specific example manner for implementing the embodiments. The following embodiments have described sufficient details to enable those of ordinary skill in the art to implement them. Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as a limitation. Instead, the embodiments included therein will be defined by the appended claims. Please refer to FIG. 1 and FIG. 2. FIG. 1 is a layout schematic diagram of a fin field-effect transistor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional schematic diagram taken along the tangent line I-I' in FIG. 1. As shown in FIG. 1 and FIG. 2, the fin field-effect transistor device 1 may include a plurality of fin structures 101a - 101d disposed on a semiconductor substrate 100. The plurality of fin structures 101a - 101d are surrounded by an isolation structure 102. For example, the isolation structure 102 may be a shallow trench isolation structure. The isolation structure 102 may be a silicon dioxide layer, but is not limited thereto. According to an embodiment of the present invention, for example, the semiconductor substrate 100 may be a silicon substrate, but is not limited thereto. According to an embodiment of the present invention, for example, the semiconductor substrate 100 may include silicon. According to an embodiment of the present invention, the plurality of fin structures 101a - 101d include silicon. According to an embodiment of the present invention, as shown in FIG. 1, the plurality of fin structures 101a - 101d may extend along the x-axis direction of the reference coordinate and protrude from the upper surface of the isolation structure 102. A gate structure 110 is disposed on the plurality of fin structures 101a - 101d and extends along the y-axis direction of the reference coordinate. According to an embodiment of the present invention, the gate structure 110 may be a metal gate, but is not limited thereto. According to an embodiment of the present invention, for example, the fin field-effect transistor device 1 may be a PMOS transistor, and an epitaxial semiconductor layer 201 is formed on the upper portions of the plurality of fin structures 101a - 101d on both sides of the gate structure 110. According to an embodiment of the present invention, for example, the epitaxial semiconductor layer 201 includes compressive stress silicon germanium. According to an embodiment of the present invention, as shown in FIG. 2, the fin structures 101a and 101b protrude from the substrate 100 along the first direction D1. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 protrudes from the upper surface 102a of the isolation structure 102. According to an embodiment of the present invention, the epitaxial semiconductor layer has a bottom recess 201c, and the bottom recess 201c has a surface S1 parallel to the second direction D2. According to an embodiment of the present invention, the first direction D1 is not parallel to the second direction D2. According to an embodiment of the present invention, the first direction D1 intersects the second direction D2. According to an embodiment of the present invention, the first direction D1 is perpendicular to the second direction D2. According to an embodiment of the present invention, the bottom recess 201c further has a surface S2 connected to and lower than the surface S1. According to an embodiment of the present invention, the surface S2 is not parallel to the first direction D1. According to an embodiment of the present invention, the surface S2 is not perpendicular to the second direction D2. According to an embodiment of the present invention, the interior angle Ɵ1 formed by the surface S1 and the surface S2 is greater than 180 degrees. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 has a surface S3 that is connected to and lower than the surface S2. According to an embodiment of the present invention, the surface S3 is not parallel to the first direction D1. According to an embodiment of the present invention, the surface S3 is not perpendicular to the second direction D2. According to an embodiment of the present invention, the interior angle Ɵ2 formed by the surface S3 and the surface S2 is less than 180 degrees. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 has a left-right symmetric profile with respect to the central axis AX. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 has a left-right symmetric concave polygon cross-section. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 has an inclined top surface S4. According to an embodiment of the present invention, the top surface S4 is not parallel to the first direction D1. According to an embodiment of the present invention, the top surface S4 is not perpendicular to the second direction D2. According to an embodiment of the present invention, the interior angle Ɵ3 formed by the top surface S4 and the surface S1 is less than 90 degrees. According to another embodiment of the present invention, the bottom recess 201c may have a curved surface. According to an embodiment of the present invention, as shown in FIG. 2, the semiconductor device 1 further includes an oxide liner 201e that conformally covers the surfaces S1 and S2 of the bottom recess 201c, wherein the oxide liner 201e is in direct contact with the isolation structure 102. According to an embodiment of the present invention, the oxide liner 201e includes silicon dioxide. According to an embodiment of the present invention, the thickness of the oxide liner 201e is 1-30 angstroms. In addition, according to an embodiment of the present invention, a Si-rich silicon germanium layer 201s may be formed on the top surface S4 of the semiconductor device 1, and its silicon concentration is higher than the rest of the epitaxial semiconductor layer 201. Please refer to FIGS. 3 to 6, which are schematic diagrams of a method for manufacturing a fin field effect transistor device according to an embodiment of the present invention. First, as shown in FIG. 3, a fin structure 101a and 101b and an isolation structure 102 are formed on the PMOS region PA of the substrate 100 by using a lithography process, an etching process, a deposition process, etc. The isolation structure 102 may be a shallow trench isolation structure. The fin structures 101a and 101b protrude from the upper surface 102a of the isolation structure 102. Then, a sidewall sublayer 312 and a hard mask layer 314 are sequentially formed on the substrate 100. According to an embodiment of the present invention, for example, the sidewall sublayer 312 may be a silicon oxide layer, and the hard mask layer 314 may be a silicon nitride layer. According to an embodiment of the present invention, the fin structures 101a and 101b protrude from the substrate 100 along the first direction D1. Next, as shown in FIG. 4, the sidewall sublayer 312 and the hard mask layer 314 on the PMOS region PA are removed by using a lithography process and an etching process. Then, an etching process is performed to etch a concave structure R in the portion where the fin structures 101a and 101b protrude from the isolation structure 102. Then, an ion implantation process may be performed to implant a predetermined dopant into the fin structures 101a and 101b. Subsequent steps may include a cleaning process before epitaxy. Next, as shown in FIG. 5, using an epitaxial process, an epitaxial semiconductor layer 201 is formed on the upper portions of the fin structures 101a and 101b. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 protrudes from the upper surface 102a of the isolation structure 102. If the fin structures 101a and 101b are very close to each other, the epitaxial semiconductor layers 201 of the fin structures 101a and 101b may be connected to each other. According to an embodiment of the present invention, for example, the epitaxial semiconductor layer 201 includes compressive-stress silicon germanium. At this time, the epitaxial semiconductor layer 201 has a diamond or rhombus-like cross section. As shown in FIG. 6, after the epitaxial semiconductor layer 201 is formed, a recess process is continued to etch the lower portion of the epitaxial semiconductor layer 201, thereby forming a bottom recess 201c. According to an embodiment of the present invention, the above-mentioned recess process may include dry etching, wet etching, annealing, or a combination thereof. According to an embodiment of the present invention, the bottom recess 201c has a surface S1 parallel to the second direction D2. According to an embodiment of the present invention, the first direction D1 is not parallel to the second direction D2. According to an embodiment of the present invention, the first direction D1 intersects the second direction D2. According to an embodiment of the present invention, the first direction D1 is perpendicular to the second direction D2. According to an embodiment of the present invention, the bottom recess 201c further has a surface S2 connected to the surface S1 and lower than the surface S1. According to an embodiment of the present invention, the surface S2 is not parallel to the first direction D1. According to an embodiment of the present invention, the surface S2 is not perpendicular to the second direction D2. According to an embodiment of the present invention, the inner angle Ɵ1 formed by the surface S1 and the surface S2 is greater than 180 degrees. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 has a surface S3 connected to the surface S2 and lower than the surface S2. According to an embodiment of the present invention, the surface S3 is not parallel to the first direction D1. According to an embodiment of the present invention, the surface S3 is not perpendicular to the second direction D2. According to an embodiment of the present invention, the inner angle Ɵ2 formed by the surface S3 and the surface S2 is less than 180 degrees. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 has a left-right symmetric profile with respect to the central axis AX. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 has a left-right symmetric concave polygon cross section. According to an embodiment of the present invention, the epitaxial semiconductor layer 201 has an inclined top surface S4. According to an embodiment of the present invention, the top surface S4 is not parallel to the first direction D1. According to an embodiment of the present invention, the top surface S4 is not perpendicular to the second direction D2. According to an embodiment of the present invention, the inner angle Ɵ3 formed by the top surface S4 and the surface S1 is less than 90 degrees. According to another embodiment of the present invention, the bottom recess 201c may have a curved surface. According to an embodiment of the present invention, oxide liners 201e may be formed on surfaces S1 and S2. The oxide liners 201e conformally cover surfaces S1 and S2 of the bottom recess 201c, wherein the oxide liners 201e are in direct contact with the isolation structure 102. According to an embodiment of the present invention, the oxide liners 201e comprise silicon dioxide. According to an embodiment of the present invention, the thickness of the oxide liners 201e is 1 - 30 angstroms. Further, according to an embodiment of the present invention, a Si-rich silicon germanium layer 201s may be present on the top surface S4, having a higher silicon concentration than the rest of the epitaxial semiconductor layer 201. The Si-rich silicon germanium layer 201s on the top surface S4 may result in a faster etching rate for the lower portion of the epitaxial semiconductor layer 201 during the aforementioned recess process, thereby forming the bottom recess 201c. By forming a compressively stressed silicon germanium layer with a bottom recess in the source or drain region of a PMOS fin field-effect transistor device, the present invention can effectively improve the operating performance of the PMOS fin field-effect transistor device. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention. 1: Fin field-effect transistor device 100: Semiconductor substrate 101a - 101d: Fin structures 102: Isolation structure 102a: Upper surface 110: Gate structure 201: Epitaxial semiconductor layer 201e: Oxide liner 201c: Bottom recess 201s: Si-rich silicon germanium layer 312: Sidewall sublayer 314: Hard mask layer AX: Central axis D1: First direction D2: Second direction PA: PMOS region R: Concave structure S1 - S3: Surfaces S4: Top surface Ɵ1 - Ɵ3: Interior angles FIG. 1 is a layout schematic diagram of a fin field-effect transistor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional schematic diagram taken along the tangent line I - I' in FIG. 1. FIGS. 3 to 6 are schematic diagrams of a method for manufacturing a fin field-effect transistor device according to an embodiment of the present invention. 1: Fin field-effect transistor device 100: Semiconductor substrate 101a, 101b: Fin structures 102: Isolation structure 102a: Upper surface 201: Epitaxial semiconductor layer 201e: Oxide liner 201c: Bottom recess 201s: Si-rich silicon germanium layer AX: Central axis D1: First direction D2: Second direction S1 - S3: Surface S4: Top surface Θ1 - Θ3: Interior angle

Claims

1. A semiconductor device comprising: a fin-like structure disposed on a substrate; an epitaxial semiconductor layer disposed on the upper portion of the fin-like structure, the epitaxial semiconductor layer having a bottom recess; an oxide substrate conformally covering the bottom recess; and an isolation structure surrounding the fin-like structure, wherein... The oxide liner is in direct contact with the isolation structure.

2. The semiconductor element as claimed in claim 1, wherein, The fin-like structure protrudes from the base along a first direction, and the bottom recess has a surface parallel to a second direction intersecting the first direction.

3. The semiconductor element as claimed in claim 1, wherein, The bottom recess has a curved surface.

4. The semiconductor element as claimed in claim 1, wherein, The substrate contains silicon.

5. The semiconductor element as claimed in claim 1, wherein, The fin-like structure contains silicon.

6. The semiconductor element as claimed in claim 1, wherein, The semiconductor device is a PMOS transistor and the epitaxial semiconductor layer contains compressive silicon germanium.

7. The semiconductor element as claimed in claim 1, wherein, The oxide liner contains silicon dioxide.

8. The semiconductor element as claimed in claim 1, wherein, The thickness of the oxide liner is 1-30 angstroms.

9. The semiconductor element as claimed in claim 1, wherein, The epitaxial semiconductor layer has a concave polygonal cross-section that is symmetrical from left to right.

10. A method of forming a semiconductor device, comprising: providing a fin-like structure on a substrate; forming an epitaxial semiconductor layer on an upper portion of the fin-like structure; after forming the epitaxial semiconductor layer, etching a lower portion of the epitaxial semiconductor layer to form a bottom recess; forming an oxide liner conformally covering the bottom recess; and forming an isolation structure around the fin-like structure, wherein the oxide liner is in direct contact with the isolation structure.

11. The method according to request item 10, wherein, The fin-like structure protrudes from the base along a first direction, and the bottom recess has a surface parallel to a second direction intersecting the first direction.

12. The method according to request item 10, wherein, The bottom recess has a curved surface.

13. The method according to claim 10, wherein, The substrate contains silicon.

14. The method according to claim 10, wherein, The fin-like structure contains silicon.

15. The method according to request item 10, wherein, The semiconductor device is a PMOS transistor and the epitaxial semiconductor layer contains compressive silicon germanium.

16. The method according to claim 10, wherein, The oxide liner contains silicon dioxide.

17. The method according to claim 10, wherein, The thickness of the oxide liner is 1-30 angstroms.

18. The method according to request item 10, wherein, The epitaxial semiconductor layer has a concave polygonal cross-section that is symmetrical from left to right.

19. A semiconductor device comprising: a fin-like structure disposed on a substrate, the fin-like structure protruding from the substrate along a first direction; an epitaxial semiconductor layer disposed on an upper portion of the fin-like structure, the epitaxial semiconductor layer having a bottom recess, the bottom recess having a first surface parallel to a third direction perpendicular to the first direction, wherein... The bottom recess further has a second surface connected to and lower than the first surface, and a third surface connected to and lower than the second surface, wherein the interior angle formed by the first surface and the second surface is greater than 180 degrees, and the interior angle formed by the third surface and the second surface is less than 180 degrees; an oxide liner conformally covering the bottom recess; and an isolation structure surrounding the fin structure, wherein the oxide liner is in direct contact with the isolation structure.

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