Electronic load testing system and method of testing characteristic of electrical system

Abstract

An electronic load testing system is configured to simulate the characteristics of an integrated circuit (IC). A control module of the system is configured to be electrically coupled to a first location on a printed circuit board (PCB) of an electronic component, and a load module is configured to be electrically coupled to a second location on the PCB. The load module includes a load unit configured to selectively conduct current from a power supply of the electronic component. The first and second locations are spaced apart and are electrically communicated via one or more lines on the PCB. The control module is configured to communicate with the load module via the one or more lines on the PCB. In some examples, the load module and the IC have an equivalent form factor, such that the load module can be mounted in place of the IC.

Description

[Technical Field]

[0001] This disclosure relates to systems and methods for electronic load testing. More specifically, the disclosed embodiments relate to electronic load testing of power supply components used in printed circuit boards. Interactive Reference

[0002] The following applications and information are incorporated herein in their entirety for all purposes: U.S. Provisional Patent Application No. 63 / 300,215, filed January 17, 2022; U.S. Provisional Patent Application No. 63 / 352,182, filed June 14, 2022; and U.S. Provisional Patent Application No. 63 / 380,219, filed October 19, 2022. [Previous Technology]

[0003] Electronic load testing is commonly used in the testing of power supplies, power distribution systems, voltage regulators, and other power circuits. Efforts have recently been made to introduce electronic load testing into printed circuit boards (PCBs). For example, load testing systems have been developed to test current and voltage regulators used in PCBs, such as those used in digital signal processors (DSPs), central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and other large-scale integrated circuits (ICs) and / or multi-chip modules, such as physical layer (PHY) circuits. With advancements in semiconductor technology and the increasing complexity of PCBs, the voltage and current requirements of ICs and other electronic modules have also increased. Therefore, load testing systems must be developed to ensure that the power systems, regulators, and other circuits fully meet those requirements and reliably provide power to the systems within expected tolerances.

[0004] Existing electronic load test systems are generally divided into two types. The first type is a system where the control circuitry of the test system is installed in the same component as the power load section (e.g., an array of transistors). While this configuration reduces the overall complexity of the system, the form factor can pose challenges for small systems. The second type is a system where the power load section is separated from the control circuitry. This allows for a smaller form factor and can be better adapted to compact systems. Furthermore, this enables larger current capacity because it increases the number of power circuits that can be installed in the available space. However, these systems typically require large multi-conductor cables (e.g., ribbon cables) to make connections between the power load section and the control circuitry. In complex systems (e.g., PCBs with many processors, GPUs, DSPs, FPGAs, memory, etc., or systems using multiple PCBs), this becomes cumbersome and difficult to implement. Moreover, because processors and similar ICs have very stringent power requirements (e.g., transient current step requirements and / or impedance requirements), the power supply voltage must remain within specifications when the IC current steps from lower to higher currents. Because the step size is typically in the hundreds or even thousands of amperes, the current slew rate usually exceeds 1000 A / µs. Therefore, connecting to an external load (e.g., using a large-gauge cable or ribbon cable) results in an inductance that is too large to allow for such a slew rate. Thus, improvements to the load testing system are necessary. [Summary of the Invention]

[0005] This disclosure provides for systems, equipment and methods relating to shape factor testing apparatus.

[0006] In some examples, an electronic load testing system includes: a control module configured to be electrically coupled to a first location on a printed circuit board (PCB) assembly of an electronic component; and a load module configured to be electrically coupled to a second location on the PCB assembly, wherein the first location and the second location are spaced apart and are electrically communicated via one or more lines of the PCB assembly; the load module includes a load unit configured to simulate a load by selectively conducting current from a power supply of the PCB assembly, the load unit including a transistor and a current sensing resistor; wherein the control module is configured to communicate with the load module via the one or more lines of the PCB assembly.

[0007] In some examples, a method for testing an electrical characteristic of an electrical system includes: sending a drive signal from a control module coupled to the electrical system at a first location to a gate of a transistor coupled to a load cell of the electrical system at a second location, wherein the first location and the second location are spaced apart and are electrically communicated via one or more lines of the electrical system; measuring a voltage across a current-sensing resistor of the load cell using the control module via the one or more lines; and evaluating the characteristic of the electrical system by comparing the measured voltage with a expected voltage.

[0008] In some examples, an electronic load test system configured to simulate the characteristics of an integrated circuit (IC) includes: a control module configured to be electrically coupled to a first location on a printed circuit board (PCB) of an electronic component; and a load module configured to be electrically coupled to a second location on the PCB, the load module including a load unit configured to selectively conduct current from a power source of the electronic component, the load unit including a transistor and a current sensing resistor; wherein the first location and the second location are spaced apart and electrically communicate via one or more lines of the PCB; wherein the control module is configured to communicate with the load module via the one or more lines of the PCB; and wherein the load module and the IC have an equivalent form factor.

[0009] Features, functions and advantages may be achieved independently in various embodiments of the present disclosure or may be combined in other embodiments, further details of which can be found in the following description and figures.

Implementation Method

[0028] Various features and examples of an electronic load testing system are described below and illustrated in the associated drawings. Unless otherwise specified, an electronic load testing system and / or various components thereof according to the present teaching may include at least one of the structures, components, functions and / or variations described, depicted and / or incorporated herein. Furthermore, unless expressly excluded, process steps, structures, components, functions and / or variations relating to the present teaching described, depicted and / or incorporated herein may be incorporated into other similar apparatuses and methods, which are interchangeable among the disclosed embodiments. The following description of various examples is merely illustrative in nature and is in no way intended to limit the content, application or use of this disclosure. Moreover, the advantages provided by the examples and embodiments described below are illustrative in nature, and therefore not all examples and embodiments provide the same advantages or advantages of the same degree.

[0029] This detailed description comprises the following sections, which immediately follow: (1) Definitions; (2) Overview; (3) Examples, Components and Alternatives; (4) Advantages, Features and Benefits; and (5) Conclusions. The section on Examples, Components and Alternatives is further divided into subsections, each with a corresponding label. Definitions

[0030] Unless otherwise specified, the following definitions apply here.

[0031] “Including,” “containing,” and “having” (and their verbal inflections) can be used interchangeably to indicate inclusion but not limitation, and are open-ended terms that do not intend to exclude additional, unstated elements or method steps.

[0032] For example, the terms “first,” “second,” and “third” are used to distinguish or identify various components of a group or similar entities, and are therefore not intended to indicate a limit on the sequence or number.

[0033] “Also known as” means “also referred to as” and can be used to indicate an alternative or corresponding term for one or more given elements.

[0034] “DUT” means “Device Under Test”.

[0035] “FFED” means “shape factor equivalent device”.

[0036] “IC” stands for “Integrated Circuit”.

[0037] “PCB” means “Printed Circuit Board”.

[0038] “DSP” stands for “Digital Signal Processor”.

[0039] “CPU” stands for “Central Processing Unit”.

[0040] “GPU” stands for “Graphics Processing Unit”.

[0041] “FPGA” stands for “Field Programmable Gate Array”.

[0042] “DAC” stands for “Digital to Analog Converter”.

[0043] “ADC” stands for “Analog to Digital Converter”.

[0044] “DIMM” stands for “Dual In-line Memory Module”.

[0045] “CS” means “Current Sensing”.

[0046] “Coupled” means a permanent or releasable connection, whether direct or indirect through an intermediate component.

[0047] "Processing logic" describes any suitable device or hardware configured to process data by performing one or more logical and / or arithmetic operations (e.g., executing coded instructions). For example, processing logic may include one or more processors (e.g., central processing unit (CPU) and / or graphics processing unit (GPU)), microprocessors, clusters of processing cores, FPGAs (Field Programmable Gate Arrays), artificial intelligence (AI) accelerators, digital signal processors (DSPs), and / or any other suitable logic hardware combination.

[0048] A “controller”, “control module”, or “electronic controller” includes processing logic programmed with instructions to perform a control function of a related control element. For example, an electronic controller may be configured to receive an input signal, compare the input signal with a selected control value or setpoint value, and determine an output signal to a control element (e.g., a motor or actuator) based on the comparison to provide corrective action. In another example, an electronic controller may be configured to interface between a host device (e.g., a desktop computer, a mainframe computer, etc.) and a peripheral device (e.g., a memory device, an input / output device, etc.) to control and / or monitor input and output signals to and from the peripheral device.

[0049] In the context of a method, “providing” may include receiving, obtaining, purchasing, manufacturing, generating, processing, preprocessing and / or the like, such that an object or material is provided in a state and configuration for use in other steps to be performed.

[0050] In this disclosure, one or more publications, patents, and / or patent applications may be incorporated by reference. However, such information is included only if there is no conflict between the included information and the statements and figures listed herein. In any event of such conflict, including any conflict in terminology, this disclosure shall prevail. Overview

[0051] Generally, a form factor equivalent load test apparatus (FFED) disclosed herein is configured to evaluate the performance of integrated circuits (ICs), such as microprocessors, GPUs, FPGAs, DSPs, and similar PCBs and other electronic devices. The FFED is configured to be form-equivalent, fit-equivalent, and functionally equivalent to the device to be evaluated. In other words, the FFED is configured to closely match the dimensions and operating parameters of an IC to evaluate the PCB's ability to meet the minimum operating requirements of the IC. These evaluations include load testing of power management, and other evaluations such as internal and external power distribution impedance, decoupling, clock timing, data transmission, and thermal management. These evaluations can be performed individually, interactively among themselves, or in conjunction with other externally provided tests. This electronic load test system can be used in test PCB level voltage regulators to calculate loads for applications such as servers, desktops, mobile devices, DSPs, FPGAs, GPUs, memory, and similar applications.

[0052] The electronic load test system described herein includes at least one control module (also referred to as a control circuit) and at least one load module (also referred to as a power supply circuit). The control module and load module of the test system disclosed herein are configured to be directly mounted to the PCB, for example, using existing sockets, or directly soldered to the board. In a typical PCB, there are various interconnections between different ICs and modules, which are usually referred to as lines or buses. For example, a processor may communicate electronically with a memory module and / or other circuitry surrounding the PCB via one or more buses. The control module and load module of the FFED are configured to communicate with each other using these existing PCB bus connections.

[0053] Since power supply performance can be highly dependent on the number and layout of ICs / modules, placing the load tester directly on the PCB (i.e., in a socket or soldered off) instead of connecting it via one or more external cables makes it easier to test, tune, and optimize the voltage source with all components in place. For example, PCBs may have various inherent parasitic resistances, capacitances, and inductances, which can significantly affect the response; therefore, verifying performance in these practical situations is crucial to ensuring the board continues to meet specifications.

[0054] Furthermore, large ICs (such as CPUs, GPUs, etc.) may have multiple power inputs, requiring different voltages and currents. In some cases, depending on the internal layout of a large IC or module, the IC may draw more current through specific power pins. A multi-channel, socket / board-level electronic load tester can be used to test these complex requirements. Multiple FFEDs can be optionally employed to test a fully interactive board power distribution and voltage regulator system. Systems and methods configured to test power systems are described below.

[0055] Furthermore, since the form factor equivalent load tester disclosed herein can have substantially the same (or substantially similar) dimensions as the IC, the tester is intended to mimic the IC and may also include the same (or substantially similar) materials and structure as the IC. The load tester has the same (or substantially similar) thermal properties. Therefore, since the load used in the tester is substantially similar to the IC load, having a form factor equivalent device facilitates highly accurate testing and verification of the thermal management system of the PCB.

[0056] An additional benefit of the FFED disclosed herein is the use of fast internal switching (e.g., rise and fall times of 1 ns or less) within the device. Fast internal switching can be used to evaluate and improve capacitive decoupling within the IC package, and interactions with power pins, ground pins, and external components can be tested. Since clock jitter can be affected by large, fast transient currents within an IC, clock timing can be evaluated using the FFED by simulating these fast transient currents. Multiple tests can be performed individually and in combination (e.g., interactively) in each of these areas to increase the robustness of the testing and evaluation efforts.

[0057] The features of the electronic load testing system disclosed herein can be embodied as a computer method, computer system, or computer program product. Thus, the features of the system can take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, and the like), or an embodiment combining software and hardware features, all of which can be generally referred to herein as a "circuit," "module," or "system." Furthermore, the features of the system can take the form of a computer program product embodied in a computer-readable medium (or multiple media) having computer-readable code / instructions embodied thereon.

[0058] Any combination of computer-readable media may be used. A computer-readable media can be a computer-readable signal medium and / or a computer-readable storage medium. A computer-readable storage medium may comprise an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, device, or apparatus, or any suitable combination thereof. More specific examples of a computer-readable storage medium may include: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable read-only optical disc (CD-ROM), an optical storage device, a magnetic storage device, and / or any suitable combination thereof and / or similar. In the context of this disclosure, a computer-readable storage medium may comprise any suitable non-transitory physical medium that may contain or store a program for use by or associated with an instruction execution system, device, or apparatus.

[0059] A computer-readable signal medium may contain a propagating data signal with computer-readable code embodied therein, for example, in a baseband frequency or as part of a carrier wave. Such propagating signal may take any of various forms, including but not limited to electromagnetic, optical, and / or any suitable combination thereof. A computer-readable signal medium may contain any computer-readable medium that is not a computer-readable storage medium but is capable of communicating, transmitting, or delivering a program for use by or associated with an instruction execution system, device, or apparatus.

[0060] The program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired lines, fiber optic cables, RF, and / or the like, and / or any suitable combination of these.

[0061] The computer program code that performs the operations for the features of the electronic load test system can be written in one or any combination of programming languages, including an object-oriented programming language (e.g., Java, C++), a conventional programming language (e.g., C), and a functional programming language (e.g., Haskell).

[0062] Mobile applications can be developed using any suitable language, including those previously mentioned, as well as Objective-C, Swift, C#, HTML5, and similar languages. The code can be executed entirely on a user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), and / or can be configured to connect to an external computer (e.g., via the Internet using an Internet service provider).

[0063] The features of the test system may be described below with reference to flowcharts and / or block diagrams of methods, devices, systems, and / or computer program products. Each block and / or combination of blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. The computer program instructions may be programmed into processing logic or otherwise provided to processing logic (e.g., a processor of a general-purpose computer, a special-purpose computer, a field-programmable gate array (FPGA), or other programmable data processing device) to create a machine such that the (e.g., machine-readable) instructions are executed by the processing logic, producing means for implementing the functions / actions specified in the blocks of the flowcharts and / or block diagrams.

[0064] Alternatively or additionally, these computer program instructions may be stored in a computer-readable medium that may instruct processing logic and / or any other suitable means to operate in a particular manner, such that the instructions stored in the computer-readable medium produce a product containing instructions that perform the functions / actions specified in the flowchart and / or block diagram blocks.

[0065] The computer program instructions may also be loaded onto processing logic and / or any other suitable means to cause a series of operational steps to be executed on the means to produce a computer-implemented program, such that the executed instructions provide a program for implementing the functions / actions specified in the flowchart and / or block diagram blocks.

[0066] Any flowcharts and / or block diagrams in the figures are intended to depict the architecture, functionality, and / or operation of possible implementations of systems, methods, and computer program products based on the characteristics of the test system. In this regard, each block may represent a module, segment, or portion of code, comprising one or more executable instructions for performing the specified logical function. In some implementations, the functions specified in the blocks may occur in a different order than indicated in the figures. For example, two blocks shown as consecutive may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functions involved. Each block and / or combination of blocks may be implemented by a hardware-specific system (or a combination of hardware-specific and computer instructions) that performs the specified functions or actions. Examples, components, and alternatives

[0067] The following sections describe illustrative electronic load testing systems and related system and / or method features. The examples in these sections are for illustrative purposes only and should not be construed as limiting the scope of this disclosure. Each section may contain one or more different embodiments or examples, and / or background or related information, functionality, and / or structure. A. Illustrative Electronic Load Testing System

[0068] This section describes an illustrative test system 100 (see Figures 7-15). System 100 is a form factor equivalent device (FFED) configured to test and verify the performance of support systems for integrated circuits (ICs). System 100 is an example of the aforementioned form factor equivalent device.

[0069] An illustrative IC 10 is depicted in Figures 1 and 2. Generally, IC 10 can be constructed from a large single-die device or multiple dies mounted and connected in a single package. For example, IC 10 may include one or more microprocessors, central processing units (CPUs), floating-point units (FPUs), graphics processing units (GPUs), artificial intelligence (AI) processors, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), or any other physical layer, and / or combinations thereof. As computer systems become more powerful, large ICs such as these continue to increase in complexity and size. This increase in complexity and size is accompanied by the need for more robust support systems, such as power supplies, decoupling solutions, thermal management systems, clocks, data transfer, etc.

[0070] Regarding power supply, during operation, a large IC, such as IC 10, may require current ranging from zero amperes to hundreds or thousands of amperes. In some cases, the current may rapidly step from a low value to a high value, where the step size is close to the maximum rated current with an edge time of less than 1µs. Complicating these issues are the stringent regulatory requirements for high-performance operation. For example, if the voltage drops too low, even briefly, the IC may fail to function properly. Conversely, if the voltage becomes too high, the IC may overheat or fail due to overvoltage.

[0071] Voltage regulators that meet these requirements can be complex and may utilize up to 24 or more phases. Control is complex and can therefore incur considerable costs.

[0072] Similarly, testing these voltage regulators is challenging, requiring high-current load units with rapid load stepping capabilities to simulate the current consumption of a large IC. While known test equipment solutions are capable of fitting into large IC sockets, these test equipment are typically much larger than the IC itself. Therefore, those solutions are not form factor equivalent.

[0073] Turning to Figure 2, an illustrative structure of IC 10 is shown. Generally, IC 10 includes a bottom solder ball layer 12 (also referred to as a ball grid array (BGA)), a multilayer substrate 14 with power, return, and signal connections, various die layers 16, a thermal interface layer 18, and an integrated heatsink (IHS) cover 20. Generally, the number and type of die layers depend on the specific function required by the IC. In some cases, one die is sufficient, while in others, multiple dies may be used.

[0074] The bottom solder ball layer 12 typically enables a connection between the substrate 14 and a PCB, for example, using a reflow soldering process. This connection can be directly to the main PCB, an interconnect platform grid array (LGA) PCB, or a pin grid array (PGA) package. As those familiar with this technology will recognize, there are many other variations in typical IC structures.

[0075] Regarding electrical characteristics, due to the conductive properties of the multilayer substrate 14 and the BGA layer 12, these layers will impose electrical characteristics such as impedance, inductance, resistance, capacitance, transmission line, skin effect, etc., on the connections of the main PCB for power and signal connections. If an LGA or PGA socket is used to mount the IC, other electrical characteristics may be applied.

[0076] Although some heat will be conducted away from the bottom layer, most of the heat generated during operation is conducted away from the top of the IC through the use of the thermal interface layer 18. Additional heat conduction is provided by the IHS cover 20, which also acts as the top of the IC package. Generally, the IHS cover is constructed of copper, aluminum, or other suitable thermally conductive material. Figure 3 depicts IC 10 mounted in a system 22. In this example, IC 10 is mounted in a socket 24 on a PCB 26, below an upper heatsink / cooling system 28.

[0077] Turning to Figure 4, an example of a known electronic load test system 40 is depicted having a control module (also referred to as control circuitry) and a load module (also referred to as load circuitry or load section) integrated together within the same component. The load test system 40 is configured to connect to a device under test (DUT) 42 (here, a PCB) via a surface mount connector 44, such as a PCB socket. As mentioned above, this configuration can help reduce the overall complexity of the architecture, but presents challenges in tightly packed systems.

[0078] Turning to Figure 5, a second known test system 50 is depicted. In this example, a load module 52 is mounted on a DUT 54 (i.e., a PCB) via a socket 56. The load module 52 is electrically communicated with a control module 58 via an interconnect cable 59. As mentioned above, this configuration provides a smaller form factor and capacity for larger currents. However, due to the necessity of the interconnect cable 59, system 50 becomes more difficult to implement as the complexity of the DUT 54 increases. Furthermore, systems such as system 50 that utilize an external cable for connection may have excessively large inductance, which would not allow for the slew rates seen in sufficiently powerful systems (e.g., systems utilizing extremely fast control signals and / or high-speed digital signals).

[0079] A solution to the problems presented by systems 40 and 50 is provided by a test system utilizing the common structures present in all modern PCBs. Turning to Figure 6, a simplified schematic view of a PCB 60 is shown, having a processor socket 62 (e.g., utilized by an IC) communicating with a plurality of memory sockets 64 (in this example, DDR4 sockets) via a plurality of lines 66 referred to herein as buses. In this example, electrical communication is feasible by transmitting electrical signals along one or more of the lines described in the bus 66.

[0080] Generally, system 100 is constructed to recreate the operating parameters and requirements of an IC it is to emulate. For example, system 100 may have substantially similar dimensions, thermal properties, power supply, grounding, clock connections / timing, etc. Thus, system 100 is configured to fit into the same physical space as the IC and is practically indistinguishable from the IC from the viewpoint of the DUT. Therefore, system 100 can more realistically and accurately test and verify the functionality of the DUT.

[0081] As shown in Figure 7, system 100 includes a load module 102 (also referred to as a power supply circuit) and a control module 104 (also referred to as a controller and / or control circuit). The load module 102 is directly connected to a DUT 106 via a processor socket 108 (in this example, the DUT is a PCB substantially similar to PCB 60). In some examples, the load module is connected to the DUT via another type of socket and / or via soldering, or other suitable methods. The control module 104 is connected to at least one of the DDR4 sockets 110 and communicates electrically with the load unit via bus 112.

[0082] In a typical DDR4 bus, sixty-four lines connect the DDR4 socket to the processor socket. If a processor and memory module are not installed, those sixty-four lines are available for communication and control between the DDR4 socket and the processor socket. Further connections between the processor socket and other PCB modules further increase the available signal lines. Since these available connections are typically high-speed digital buses, they are compatible with both analog and digital signals, both of which can be utilized via system 100.

[0083] Generally, system 100 may receive power via one or more power supplies and / or power sources, including an external power supply, which may be provided, for example, via an external power cable, a combined power and data cable (e.g., a USB cable, an IEEE 1394 (also known as a FireWire) cable, a Thunderbolt cable, etc.), or other suitable connections. In some examples, the one or more power sources may be on-board power supplies, such as one or more batteries, one or more photovoltaic cells, or other suitable on-board power supplies. In some examples, system 100 may receive power via one or more power layers (also known as power rails) of the PCB.

[0084] In some examples, system 100 communicates with other electronic devices (e.g., personal computers, servers, personal devices such as smartphones, etc.) to provide data on relevant test parameters, such as for reference, recording, analysis, measurement, etc. Communication can be provided via a wired connection or a wireless connection. The wired connection may include an Ethernet cable or other cables suitable for data transmission. The wireless connection may include a Bluetooth connection, a Wi-Fi connection, a wireless mesh network, and / or a wireless sensor network. In some examples, communication can be provided via a cable, including optical fiber (also known as fiber optic cable).

[0085] Turning to Figure 8, a block diagram is shown depicting the features of system 100. In this example, system 100 may include, but is not limited to, the following: a load unit 114 comprising both a main load unit and a very fast load unit, a clock (not shown), a clock buffer 116, flash memory 118, a voltage-controlled crystal oscillator (VCXO) 120, one or more temperature sensors 122, one or more substrate capacitors, and a plurality of interconnects 124, such as one or more data bus interconnects, package pins, power interconnects, clock interconnects, and communication bus interconnects. As described above, system 100 may have additional components and materials similar to an IC (e.g., shown in Figures 1 and 2), including a BGA or LGA compatible bottom layer, a substrate layer, a thermal interface material, and an integrated heatsink.

[0086] System 100 is referred to as a form factor equivalent device. Generally, "form factor equivalent" means that a selected set of actual dimensions of the device is the same as the corresponding dimensions of the IC that the system is intended to simulate. For example, within a given tolerance (e.g., + / -5% or + / -3% to 5%), system 100 may have the same coverage area (i.e., XY dimensions) as the IC. Additionally or alternatively, within the same tolerance, system 100 may have the same height (i.e., Z dimension) as the IC. In some examples, form factor equivalence means having a coverage area substantially the same as the IC's coverage area, such that system 100 is mounted to the same socket, and a height that allows system 100 to avoid interfering with existing components (e.g., mounted below or within them), such as a PCB socket latch / retainer and / or a cooling solution. In some examples, a form factor equivalent device has at least the same power and ground pins as the simulated device. In some examples, a form factor equivalent device has thermal properties similar to those of the simulated device; for example, a form factor equivalent device may have a thermal conductivity within 10% of the thermal conductivity of the IC.

[0087] Regarding electrical functions, load units 114 (e.g., main load units and very fast load units) are used to test the external power domain network (PDN) of the DUT 106, as well as the internal distribution and decoupling network of the DUT 106.

[0088] The high-current load units are controllable current sources that can load the PDN to its maximum current and beyond to measure PDN functionality and limitations. Because they are installed within a form factor equivalent structure of system 100, they can generate transients in a more realistic environment compared to load units of a non-form factor equivalent test system.

[0089] For example, system 100 can test the PDN more realistically and accurately because it uses the same parasitic package components as its test section. Similarly, system 100 can test internal IC decoupling by utilizing a similar layout, such as load cells located at the processor or other core locations, and similar decoupling capacitors and setups. Furthermore, because of this, the overall impedance and frequency response of the entire power network can be tested as a whole, for example, in manufacturing applications.

[0090] In some examples, system 100 can test power and ground solutions by individually controlling various load units 114 within system 100. High-current power and ground pins enter in an array at the bottom of an IC circuit board and then pass through a substrate for distribution within the IC. A group of load units in system 100 can operate in parallel for the overall load, or they can operate individually, or they can cancel each other out in current. By utilizing multiple voltage measurement points on the power and ground planes, both planes can be characterized and evaluated for impedance. This characterization can extend to the power and ground planes of the system PCB below the IC socket, allowing for a more optimized and efficient PDN copper and socket pin pattern.

[0091] In order to illustrate the benefits of the many control lines, the different architectures and exemplary embodiments of system 100 are described below with reference to Figures 10-15.

[0092] As shown in Figure 10, the load module 102 is depicted having a single load cell 114, which includes a transistor 126 (e.g., a metal-oxide-semiconductor field-effect transistor or MOSFET) and a current-sensing resistor 128 (also referred to as a current shunt), wherein the load module 102 communicates with the control module 104. The control method utilized by the control module 104 may include any analog, digital, or mixed-signal method of operating the gate voltage to turn on, off, and / or regulate the MOSFET 126 at a given current level. In this example, the control module 104 is located remotely from the load cell 114 (e.g., connected to the memory socket 110) and communicates via the PCB bus 112.

[0093] In operation, the load current is sensed by measuring the voltage across the current resistor 128, for example, via CS+ and CS-. This voltage is differentially sensed for accuracy at high currents, fed back to the control module 104, and compared with a reference signal to adjust the MOSFET current to a reference value.

[0094] To achieve high current levels (e.g., in the hundreds to thousands of amperes), multiple load units can operate in parallel. In the example depicted in FIG10, for the load unit 114, there are three signal connections between the control module 104 and the load module 102. Due to the limitation imposed by the number of lines in the bus 112, the number of load units 114 is limited to a given set of signal lines.

[0095] The gate threshold voltage used in most MOSFETs has a negative temperature coefficient. Therefore, as power dissipation increases, the current increases for the same gate voltage. Consequently, in a parallel connection of two or more MOSFETs, one will become hotter due to current imbalance, conducting increasingly larger currents, and may therefore suffer thermal runaway and failure. Thus, simply paralleling MOSFET devices is ineffective in linear applications.

[0096] To mitigate these problems while still providing a large current source, the transistor device and current shunt can be connected as depicted in Figure 11. This configuration is partly achieved by utilizing a single negative current sensing (CS-) connection for multiple units. As shown in Figure 11, the two load units 114 are arranged in a mirror-symmetric manner, with the current sensing resistors 128 being quite close to each other. The two negative current sensing connections (i.e., CS1- and CS2-) are combined into a single CS- signal. This configuration is advantageous because it generates five connections for two units instead of six as used in the previous example, effectively reducing the number of connections per unit in an array of load units to 2.5.

[0097] In a similar manner, as illustrated in the example of Figure 12, four units can be closely positioned together on the board using a single CS-signal. Thus, the number of connections required for the four units can be reduced from twelve to nine. For a 64-line bus (e.g., those present in memory modules and processor sockets), this configuration enables up to twenty-eight individually controlled load units, corresponding to 2.25 connections per load unit.

[0098] Turning to Figure 13, a gate driving method for transistor 126 is depicted for a single load unit, utilizing a digital driver 130 in parallel with a linear driver 132. When a linear driver is used to control a MOSFET or similar power switch, the gate voltage is transitioned from 0V (or in some examples from a negative gate voltage) to a voltage level that will begin to turn on the MOSFET. This voltage level is known as the gate critical voltage (also referred to as Vgs(th)). A finite amount of time is required to linearly voltage-transfer the driver output to Vgs(th). This delay causes skew in the duty cycle when switching loads at high frequencies. The example depicted in Figure 13 reduces this delay by utilizing a buffer output of a digital driver to quickly shift the gate voltage of the MOSFET, thereby producing higher accuracy in both timing and duty cycle. In some examples, the digital driver 130 may be configured as a floating driver in series with the linear driver 132 to, for example, provide a lower impedance for driving the gate.

[0099] In operation, the gate drive signal is generated by a resistive voltage divider between an output of the digital driver 130 (operating as a buffer gate) and an output of the linear driver 132. This configuration operates according to the following steps: When the load switch is fully turned off, both the linear driver and the buffer voltage are at zero volts, ensuring that the load switch gate voltage is at a minimum. To turn on the switch, a reference signal is applied to the linear driver, causing the driver output voltage to rise. Simultaneously, the buffer output is switched on rapidly, for example, on the order of nanoseconds or less. The resulting voltage divider output quickly shifts the gate voltage just below Vgs(th), minimizing the required switching voltage and voltage transition time for the linear driver. The gate voltage is quickly voltage-transferred to Vgs(th), which turns on the MOSFET. Rh can be replaced by a current source selected to shift the output voltage from the minimum voltage to Vgs(th). This configuration has the advantage that the increase in the linear driver conversion rate is not slowed down by the voltage divider network.

[0100] Other systems and methods may be used to increase the number of units or reduce the number of connections per unit, such as in the example depicted in Figure 14. As shown in Figure 14, the output of an array of digital-to-analog converters (DACs) drives the load units of an array.

[0101] In the example depicted in Figure 14, the load transistor is characterized by a current relative to the gate drive voltage. These characteristics are digitally stored in a processor (e.g., in control module 104) that controls the outputs of two DACs 134. The DAC output voltage is non-linearly stepped by control module 104 to generate a linear load cell current, which includes a programmed slew rate, a fixed current, or an arbitrary waveform. The DAC output is programmed to compensate for MOSFET gain, non-linearity of capacitance and resistance, temperature effects, current sensing resistor value, inductance, and any parasitic voltages of DUT 106. DAC compensation can be achieved by various methods, including lookup tables, programmed equations, or other digital signal processing methods. For load transistors that are not well matched in Vgs(th) and transconductance, each load cell can have its own DAC and gate drive.

[0102] This process, along with the individual CS+ and CS- signals used for each unit, makes the actual load current more accurately reflect the programmed current. However, load units with digital compensation as described above can be made to reasonably match (within 20% or less) other load units in terms of current output, even if individual CS+ and CS- signals are not used for individual load unit feedback. In this example, CS+ and CS- signals from multiple units can be combined as shown in Figure 14, which significantly reduces the average pin requirements per unit. For example, five units connected in parallel in this way will utilize five gate signals, but only a single CS+ and CS- combination, resulting in a combination of seven connections; this is equivalent to only 1.4 connections per unit. Using this method, the number of units that can be connected in parallel is effectively unlimited.

[0103] Referring to Figure 15, if the load transistors of different units are reasonably matched in Vgs(th) and transconductance (e.g., within approximately 20%), a single DAC output and gate drive will be sufficient to control multiple load units. For example, for an array of five units, a single gate drive, CS+, and CS- signals are all required. This configuration produces only a total of three connections for five load units, equivalent to 0.6 connections per unit. Similarly, there is no minimum or maximum number of units that can be combined in this way.

[0104] System 100 may further include the use of many types of analog and digital signals transmitted along the PCB traces of bus 112. For example, system 100 may utilize connections between a device controller and the load controller (e.g., between a separate PC and control module 104), connections between load module 102 and a digital compensator, connections between the digital compensator and a gate of MOSFET 126, current sensing and return connections, temperature measurement connections, load cell voltage sensing connections, connections relating to PMBus, POK, AVS buses, and / or other power management related signals, as well as all of the above analog, digital, and mixed signal forms, as will be understood by those skilled in the art.

[0105] Turning to Figure 16, the form factor equivalent system 100 is an additional advantage for the use of a thermal solution in conjunction with load testing. For example, Figure 16 depicts an illustrative thermal solution 136, which is used in conjunction with system 100 for a large IC. As shown in Figure 16, a second thermal interface layer 138 (see TIM2) is added between the IHS and the heat sink. The heat sink can be air-cooled, liquid-cooled (water, oil, heat pipes, or others), or any other cooling method, as will be understood by those skilled in the art.

[0106] Large ICs typically have peak current requirements and thermal current requirements. Peak current requirements are related to the manufacturing process, applied voltage, operating frequency, and operating parameters. Operating parameters are the most variable, as the IC may be idle or may have one or more components operational, such as various types of processor cores, PHYs, or other functions.

[0107] The thermal current requirement is lower than the peak current requirement and is the maximum power that can be dissipated in the IC package. The thermal current represents a long-term average with shorter, above-average bursts, where the quality of the thermal management system can absorb temporary increases in power dissipation. Because the same peak load current and thermal current correspond precisely to the heat dissipation capability of the thermal solution, a form factor equivalent device is ideal for testing and evaluating both the PDN and the thermal solution together. Variable dissipation levels and durations will allow for more thorough and accurate testing of the thermal solution, resulting in better overall system performance.

[0108] Furthermore, since the thermal solution is improved through the use of system 100, those improvements can be converted back into increased capacitance of the PDN and, in particular, IC performance itself. IC clock speed, data processing capacity, use of more silicon area, and similar performance capacity are generally related to the thermal solution. Thus, due to the integrated verification function, system 100 helps to maximize IC performance.

[0109] Testing the aforementioned heat dissipation solution is a function of all load units, especially the high-current load units, because they dissipate the most power. Conversely, although both types of load units are used to test PDN response and clock speeds, the very fast load units have a unique application due to their high speed.

[0110] Referring to Figures 17 and 18, the characteristics of the clock and clock timing related to system 100 will now be discussed. The lower limit of the current rise and fall time of the load cell is typically on the order of 200 ns, although it is moving towards 50 ns and lower. In contrast, load cells referred to as "very fast load cells" have rise and fall times of 1 ns or less. This gives the very fast load cells the ability to induce very fast edge noise within system 100 for testing internal decoupling, layout, clock, and data functions. To enable the fastest transition time, very fast load cells typically include a MOSFET that switches a load resistor on and off. In some cases, the edge time can be lengthened as needed to adapt for different use cases. Furthermore, edge times below 1 ns also provide time-domain reflectometry (TDR) type measurement capabilities both inside and outside system 100.

[0111] Referring to Figure 17, the clock function can be tested by placing a clock 140, phase-locked loops 142 and 144 (PLL), and other clock-related components, such as timers, re-timers, and windings, in a location in system 100 similar to the IC and system PCB layout. Noise sensitivity and immunity can then be tested by using high-current loads and the aforementioned very fast load units at various levels.

[0112] Clock jitter (see Figure 18) and PLL synchronization can be tested using both common-mode and differential-mode methods. Differential-mode testing is performed on noise on the clock or PLL power supply, noise capacitively coupled from an adjacent power supply, or differential electromagnetic coupling into the clock signal.

[0113] To achieve capacitive coupling, the load cell 114 may be placed under the MOSFET drain node of a very high-speed load cell in a pad region. For coupling, this pad is positioned close to the clock signal. The load current, frequency, and transition time can be adjusted to change the injection amount.

[0114] Inductive coupling is achieved by setting up a line or loop by connecting the MOSFET in series and the clock signal in parallel. Similarly, the load current, frequency, and switching time are adjusted to accommodate permissive induction.

[0115] In order to test common-mode noise, the capacitive pad coupling may be located close to the differential clock signal, and the inductive common-mode coupling will cause the inductive line or loop (as previously described) to be connected in parallel with the same differential clock signal.

[0116] Data communication, such as memory buses, I / O signals, or any similar signals, can be tested in the same manner. Eye diagrams can be evaluated without load activity, and then at different levels of load cell amplitude, frequency, and transition time. Differential mode and common-mode injection can be achieved as previously described for clock evaluation.

[0117] The effectiveness of the substrate capacitors and their layout can be fully tested using System 100. In existing load cells, the load cells are not on the substrate of the IC but are located externally. These existing load cells are limited in their current conversion efficiency due to their inductive connection to the IC. Furthermore, the existing load cells are typically inserted into an intermediary or other adapter where the IC will be located, and therefore are not laid out in the same way as the IC and its substrate. Therefore, existing load cells cannot properly evaluate the decoupling effectiveness of internal IC decoupling solutions. In contrast, System 100 is designed with an IC-equivalent substrate layout, decoupling capacitor size, number, and location, and load cells are located where power-consuming chips will be mounted. They can therefore properly evaluate internal decoupling solutions.

[0118] Furthermore, by employing multiple load units at multiple locations on the substrate, and multiple voltage sensing points for the input voltage and ground, the input voltage plane and ground plane can be evaluated and characterized. The load units can be controlled to have equal or proportional currents, or they can be individually controlled, or they can be intermodulated. This variability will affect the magnitude and direction of current conduction in different regions of the power supply and ground plane, thus allowing for characterization.

[0119] Temperature sensors can be placed at various points in system 100 depending on the application. Where a load cell is located, where a power-consuming IC die is located, the temperature sensor will provide an equivalent thermal image of the IC's internal structure. Furthermore, this interacts with the heat dissipation solution and its evaluation. Various scenarios for short-term and long-term temperature and power dissipation can be tested. Furthermore, the maximum temperature of different die regions and the performance of each die can be evaluated as part of the overall system, either individually or interactively. The system firmware and software can then be designed to operate optimally based on thermal functionality, resulting in increased performance of the IC.

[0120] In some examples, system 100 includes processing logic and / or has one or more computer-readable storage media having program instructions stored therein for test operations. A processor of system 100 may be configured to process the program instructions, such as starting a test, recording generated test analysis for storage, and / or compiling communication data for subsequent transmission. For example, system 100 may be configured to provide one or more test scenarios, such as power cycling, virus simulation, changes in load demand, etc., and record any generated analysis data. In some examples, system 100 is configured to operate autonomously. Thus, system 100 may be fully pre-programmed, partially pre-programmed, and / or configured to receive real-time instructions, for example, through the use of one or more of the wired and / or wireless technologies described above. B. Component Symbols

[0121] The following component symbols are used in this written description and drawings: 10 Integrated Circuit (IC) 12 Ball Grid Array (BGA) Layer 14 Multilayer Substrate 16 Die Layer 18 Thermal Interface Layer 20 Integrated Heatsink (HIS) Cover 22 System 24 Socket 26 PCB 28 Heatsink / Cooling System 40 Load Test System 42 Device Under Test (DUT) 44 Surface Mount Connector 50 Test System 52 Load Module 54 DUT 56 Socket 58 Control Module 59 Interconnect Cable 60 PCB 62 Processor Socket 64 Memory Socket 66 Bus / Line 100 Load Test System 102 Load Module 104 Control Module 106 DUT 108 Processor Socket 110 Memory Socket 112 Bus 114 Load Cell 116 Clock Buffer 118 Flash Memory 120 Voltage-Controlled Crystal Oscillator (VCXO) 122 Temperature Sensor 124 Connecting Wire 126 Transistor 128 Current Sensing Resistor 130 Digital Driver 132 Linear Driver 134 Digital-to-Analog Converter (DAC) 136 Thermal Solution 138 Thermal Interface Layer 140 Clock 142 Phase-Locked Loop 144 Phase-Locked Loop C. Examples of Combinations and Additional Examples

[0122] This section describes additional aspects and features of the electronic load test system described herein, which are presented in a series of paragraphs without limitation, some or all of which may be named alphanumerically for clarity and efficiency. Each of these paragraphs may be combined in any suitable manner with one or more other paragraphs and / or disclosures from elsewhere in this application. Some of the following paragraphs may explicitly refer to and further limit the other paragraphs, providing examples of certain suitable combinations without limitation.

[0123] A1. An electronic load testing system comprising: a control module configured to be electrically coupled to a first location on a printed circuit board (PCB) assembly of an electronic component; and a load module configured to be electrically coupled to a second location on the PCB assembly, wherein the first location and the second location are spaced apart and electrically communicate via one or more lines of the PCB assembly; the load module includes a load unit configured to simulate a load by selectively conducting current from a power supply of the PCB assembly, the load unit including a transistor and a current sensing resistor; wherein the control module is configured to communicate with the load module via the one or more lines of the PCB assembly.

[0124] A2. An electronic load test system as described in paragraph A1, wherein at least one of the first position and / or the second position includes an integrated socket of the PCB.

[0125] A3. An electronic load test system as described in paragraphs A1 or A2, wherein the first position includes a memory module socket and the second position includes a processor socket.

[0126] A4. An electronic load test system as described in any of paragraphs A0 to A3, wherein the load unit is a first load unit, and wherein the load module includes at least one second load unit, such that the first load unit and the second load unit share a common negative current sensing connection.

[0127] A5. An electronic load test system as described in any of paragraphs A0 to A4, wherein the transistor comprises a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0128] A6. An electronic load test system as described in any of paragraphs A0 to A5, wherein the control module includes a linear driver configured to generate a drive voltage applied to a gate of the transistor.

[0129] A7. An electronic load test system as described in paragraph A6, wherein the linear driver is coupled to an output of a digital-to-analog converter such that the control module is configured to adjust the nonlinearity of the transistor.

[0130] A8. An electronic load test system as described in any of paragraphs A0 to A7, wherein the load unit is a first load unit, and the load module includes at least one second load unit; wherein the control module is configured to utilize individual linear drivers to generate drive voltages applied to individual transistors of the load units; and wherein the first load unit and the second load unit share a common negative current sensing connection and a common positive current sensing connection.

[0131] A9. An electronic load test system as described in paragraph A8, wherein the linear driver is configured to adjust the nonlinearity of the transistor using the individual outputs of a digital-to-analog converter.

[0132] A10. An electronic load test system as described in paragraph A8, wherein the linear driver is configured to adjust the nonlinearity of the transistor using an output of an identical digital-to-analog converter.

[0133] A11. An electronic load test system as described in any of paragraphs A0 to A10, further comprising a temperature sensor, wherein the electronic load test system is configured to use the temperature sensor to measure one or more thermal management properties of the electronic component.

[0134] A12. An electronic load test system as described in any of paragraphs A0 to A11, further comprising the electronic component, wherein the electronic load test system is coupled to the electronic component, and wherein the electronic component comprises a computer motherboard, the first location being a memory module socket, the second location being a processor socket, and the one or more lines comprising a data bus of the motherboard.

[0135] B0. A form factor equivalent device (FFED) for evaluating the performance of various solutions for large integrated circuits (ICs).

[0136] B1. The device as described in paragraph B0, wherein the actual size of the FFED is similar to (configured to mimic) the IC, so as to allow installation in the same place and in the same manner as the IC.

[0137] B1A. The device as described in paragraph B1, wherein the coverage area size (XY) of the FFED is within 5% of the corresponding coverage area size of the IC.

[0138] B2. A device as described in paragraphs B0, B1, or B1A, wherein a package structure of said device includes a material having substantially the same thermal and electrical properties as said IC, to allow equivalent performance to be evaluated.

[0139] B3. A device as described in any of paragraphs B0 to B2, wherein the thermal characteristics are similar to (configured to mimic) the IC.

[0140] B4. An apparatus as described in any of paragraphs B0 to B3, wherein the mounted PCB is similar to (configured to mimic) the PCB of the mounted IC.

[0141] B5. An apparatus as described in any of paragraphs B0 to B4, wherein a substrate is laid out in a manner similar to (configured to mimic) the IC.

[0142] B6. A device as described in any of paragraphs B0 to B5, wherein the resistors, capacitors, and inductors are similar to (configured to mimic) the IC.

[0143] B7. The device as described in any of paragraphs B0 to B6, further comprising at least one high-current load unit.

[0144] B8. An apparatus as described in any of paragraphs B0 to B7, further comprising at least one very fast load unit having a rise time of 1 ns or less.

[0145] B9. The apparatus of any one of paragraphs B0 to B8, further comprising at least one voltage measurement point for the incoming power supply.

[0146] B10. The apparatus of any one of paragraphs B0 to B9, further comprising at least one voltage measurement point for power supply return.

[0147] B11. The device as described in any of paragraphs B0 to B10, further comprising at least one clock.

[0148] B12. The device as described in any of paragraphs B0 to B11, further comprising at least one external clock connection.

[0149] B13. The device as described in any of paragraphs B0 to B12, further comprising at least one external data connection.

[0150] B14. The device as described in any of paragraphs B0 to B13, further comprising at least one internal bypass capacitor.

[0151] B15. The device as described in any of paragraphs B0 to B14, further comprising at least one temperature sensor.

[0152] B16. The device as described in any of paragraphs B0 to B15, further comprising a plurality of high-current load units and a plurality of temperature sensors, the plurality of high-current load units and the plurality of temperature sensors being configured to evaluate and characterize the thermal properties of the device, the IC, and the heat dissipation solution.

[0153] B17. The apparatus as described in paragraph B16, wherein the plurality of high-current load units are individually and together modulated to simulate power consumption in an IC.

[0154] B18. A device as described in any of paragraphs B0 to B17, wherein the ADC and DAC circuitry are integrated into the package.

[0155] B19. A device as described in any of paragraphs B0 to B18, which is further configured to incorporate a digital signal.

[0156] B20. A device as described in any of paragraphs B0 to B19, which is further configured to incorporate an analog signal.

[0157] B21. The device of any of paragraphs B0 to B20 is further configured to communicate via an analog signal.

[0158] B22. The device as described in any of paragraphs B0 to B21 is further configured to communicate via a PCB digital bus.

[0159] B23. The device as described in any of paragraphs B0 to B21 is further configured to communicate and / or receive power via an external cable.

[0160] B25. A device as described in any of paragraphs B1 to B21 is further configured to communicate and / or receive power via a combination of power and data cables, such as a Universal Serial Bus (USB) cable, an IEEE 1394 (also known as a FireWire) cable, a Thunderbolt cable, etc.

[0161] B26. The device of any of paragraphs B0 to B25 is further configured to be powered via a PCB power rail (also referred to as a power plane).

[0162] B27. The device as described in any of paragraphs B0 to B26 is further configured to communicate via an Ethernet cable.

[0163] B28. A device as described in any of paragraphs B0 to B27, which is configured to communicate wirelessly.

[0164] B29. A device as described in paragraph B28, which is configured to communicate using a Bluetooth connection.

[0165] B30. The device as described in paragraph B28 is configured to communicate using a Wi-Fi connection.

[0166] B31. The device as described in paragraph B28 is configured to communicate using a wireless mesh network.

[0167] B32. The device, as described in paragraph B31, is configured to communicate using a Zigbee connection.

[0168] B33. The device, as described in paragraph B28, is configured to communicate using a wireless sensor network.

[0169] B33. A device as described in any of paragraphs B0 to B27, which is configured to communicate via a fiber optic cable.

[0170] B34. The apparatus of any one of paragraphs B0 to B33, further comprising a battery power source.

[0171] B35. An apparatus as described in any of paragraphs B0 to B34, further comprising a power source including one or more photovoltaic cells.

[0172] B36. A device as described in any of paragraphs B0 to B35, wherein the device is pre-programmed and configured to operate autonomously.

[0173] C0. The device as described in paragraph B7 further includes a plurality of high-current load units and voltage sensing points on the input voltage and ground, which are configured to evaluate and characterize internal and external power distribution.

[0174] C1. The apparatus as described in paragraph C0, which is configured to evaluate clock performance due to noise on the power supply.

[0175] C2. A device as described in any of paragraphs C0 or C1, wherein the device is further configured to evaluate clock performance using a pad, line, or loop.

[0176] C3. A device as described in any of paragraphs C0 to C2, which is configured to evaluate data performance.

[0177] C4. A device as described in any of paragraphs C0 to C3, which is used to evaluate data performance due to noise on the power supply.

[0178] C5. A device, such as any one of paragraphs C0 to C4, that uses a pad, line, or loop to evaluate data performance.

[0179] D0. The apparatus as described in paragraph B8, wherein the very fast load unit is used to evaluate clock performance.

[0180] D1. The apparatus as described in paragraph D0, which is used to evaluate clock performance due to noise on the power supply.

[0181] D2. A device, such as any one of paragraphs D0 or D1, that uses a pad, line, or loop to evaluate clock performance.

[0182] D3. An apparatus as described in any of paragraphs D0 to D2, wherein the very fast load unit is used to evaluate data performance.

[0183] D4. A device as described in any of paragraphs D0 to D3, which is used to evaluate data performance due to noise on the power supply.

[0184] D5. A device, such as any one of paragraphs D0 to D4, that uses a pad, line, or loop to evaluate data performance.

[0185] D6. An apparatus as described in any of paragraphs D0 to D5, wherein the very fast load unit is used to perform time-domain reflectometry (TDR) measurements both inside and outside the FFED to the PCB and power domain network.

[0186] E0. A load testing system comprising a control circuit and a load circuit, wherein the control circuit is located at one point on a PCB assembly, and the load circuit is located at a second point on the PCB assembly; and wherein existing wiring on the PCB is used for communication between the control circuit and the load circuit.

[0187] E1. The load test system as described in paragraph E0, wherein the control circuit and / or the load circuit is located in and connected to an integrated circuit socket.

[0188] E2. A load test system as described in paragraphs E0 or E1, wherein the control circuit and / or the load circuit is located in and connected to the module connector.

[0189] E3. A load test system as described in any of paragraphs E0 to E2, wherein the control circuit and / or the load circuit is located in and connected to the PCB coverage area of ​​the integrated circuit.

[0190] E4. A load test system as described in any of paragraphs E0 to E3, further comprising: a plurality of control circuits and / or a plurality of load circuits; and wherein existing PCB traces are used for communication between any parts of the load test system.

[0191] E5. A load test system as described in any of paragraphs E0 to E4, further comprising a load unit, wherein the load unit includes: a controller, a MOSFET, a current sensing resistor, and a gate-to-current sensing connection.

[0192] E6. A load testing system as described in paragraph E5, comprising two or more of the load units, wherein the two or more load units utilize a common current sensing connection.

[0193] E7. A load test system as described in any of paragraphs E0 to E6, wherein the controller utilizes a DAC output to compensate for MOSFET nonlinearity and parasitic components.

[0194] E8. A load test system as described in any of paragraphs E0 to E7, wherein two or more load units use a common current sensing positive signal.

[0195] E9. A load test system as described in any of paragraphs E0 to E8, wherein the controller utilizes a linear gate drive with a digital level converter.

[0196] F0. An electronic load test system configured to simulate the characteristics of an integrated circuit (IC), the test system comprising: a control module configured to be electrically coupled to a first location on a printed circuit board (PCB) of an electronic component; and a load module configured to be electrically coupled to a second location on the PCB, the load module including a load unit configured to selectively conduct current from a power source of the electronic component, the load unit including a transistor and a current sensing resistor; wherein the first location and the second location are spaced apart and electrically communicate via one or more lines of the PCB; wherein the control module is configured to communicate with the load module via the one or more lines of the PCB; and wherein the load module and the IC have an equivalent form factor (e.g., an XY coverage area of ​​the load module is the same as an XY coverage area of ​​the IC within a 5% tolerance).

[0197] F1. An electronic load test system as described in paragraph F0, wherein the load module is configured to have substantially the same thermal properties as the IC.

[0198] F2. An electronic load test system as described in paragraph F1, further comprising a temperature sensor, wherein the electronic load test system is configured to use the temperature sensor to measure one or more thermal management properties of the electronic component.

[0199] F3. An electronic load test system as described in any of paragraphs F0 to F2, further comprising the electronic component; wherein the electronic load test system is coupled to the electronic component; and wherein the electronic component comprises a computer motherboard, the first location being a memory module socket, the second location being a processor socket, and the one or more lines comprising a data bus of the motherboard.

[0200] F4. An electronic load test system as described in any of paragraphs F0 to F3, wherein the load unit is a first load unit, and the load module further includes a second load unit that shares a common negative current sensing connection with the first load unit.

[0201] F5. An electronic load test system as described in any of paragraphs F0 to F4, wherein the control module is actually separate from the load module.

[0202] G0. A method for testing a characteristic of an electrical system using an electronic load test system as described in any one of paragraphs A1 to A12, wherein the electrical system comprises the PCB of the electronic component, the method comprising: sending a drive signal from the control module via one or more of the lines of the PCB component to a gate of the transistor to induce a current in the load cell; measuring a voltage across the current-sensing resistor using the control module via one or more of the lines; and evaluating the characteristic of the electrical system by comparing the measured voltage with a expected voltage.

[0203] G1. The method as described in paragraph G0, wherein the actual size of a coverage area of ​​the load cell is similar to (configured to mimic) an integrated circuit (IC) of the electrical system (e.g., within 5%), and the method further includes mounting the load cell in the same location and in the same manner as the IC is typically mounted.

[0204] H0. A method for testing an electrical characteristic of an electrical system, the method comprising: sending a drive signal from a control module coupled to the electrical system at a first location to a gate of a transistor coupled to a load cell of the electrical system at a second location, wherein the first location and the second location are spaced apart and are electrically communicated via one or more lines of the electrical system; measuring a voltage across a current-sensing resistor of the load cell using the control module via the one or more lines; and evaluating the characteristic of the electrical system by comparing the measured voltage with a expected voltage.

[0205] H1. The method as described in paragraph H0, wherein the actual size of a coverage area of ​​the load unit is similar to (configured to mimic) an integrated circuit (IC) typically mounted at the second location of the electrical system (e.g., within 5%), and the method further includes coupling the load unit to the electrical system at the second location in the same manner as the IC would use.

[0206] H2. The method as described in paragraph H1, wherein the height of the load cell is within 5% of the height of the IC. Advantages, features, and benefits.

[0207] The various embodiments and examples of the electronic load test system described herein offer several advantages over known solutions for power supply systems used to test electrical modules. For example, the illustrative embodiments and examples described herein meet the current and future requirements for increased current and current steps for highly transient electronic loads.

[0208] In addition to other benefits, the illustrative embodiments and examples described herein are for implementing and coordinating multiple loads for power systems at the socket, module, board, and system levels.

[0209] In addition to other benefits, the illustrative embodiments and examples described herein are configured to fit existing mechanical form factors.

[0210] In addition, and for other benefits, the illustrative embodiments and examples described herein utilize existing buses and interconnects to reduce excessive wiring between the load control circuitry and the load power supply circuitry.

[0211] In addition to other benefits, the illustrative embodiments and examples described herein utilize available PCB connections to control as many individual load units as possible.

[0212] In addition, and other benefits, the illustrative embodiments and examples described herein allow all power-related components of a large system comprising multiple modules to be tested simultaneously under operating parameters similar to those of conventional and heavy use.

[0213] In addition to other benefits, the illustrative embodiments and examples described herein allow for time-domain reflectometry (TDR) type measurements.

[0214] Other existing load systems cannot perform all the functions described herein because they utilize standardized load units configured to connect to the socket via cables or intermediaries. Some custom load systems best perform DC and dynamic loading within a package that can be soldered to the main PCB or inserted into a socket; however, these are not form factor equivalent and are not laid out in the same manner as the IC substrate in terms of equivalent load location, parasitic impedance, and decoupling solutions, and therefore cannot be mounted in a system equivalent to the IC.

[0215] No known system or apparatus can perform these functions. However, not all embodiments and examples described herein offer the same advantages or advantages of the same degree. Conclusion

[0216] The disclosure described above may cover a number of different examples with independent utility. Although each of these examples has been disclosed in its preferred form, the specific embodiments disclosed and depicted herein are not intended to be limiting, as many variations are possible. With regard to the section headings used in this disclosure, such headings are for organizational purposes only. The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of the various elements, features, functions, and / or properties disclosed herein. The following claims specifically indicate that certain combinations and sub-combinations are considered novel and non-obvious. Other combinations and sub-combinations of features, functions, elements, and / or properties may be claimed in applications claiming priority to this application or related applications. Such claims, whether broader, narrower, equal to, or different in scope from the original claims, are also considered to be included within the subject matter of this disclosure. [Simplified Explanation of the Diagram]

[0010] [Figure 1] An example illustrating an integrated circuit (IC).

[0011] [Figure 2] is an exploded view of the IC in Figure 1.

[0012] [Figure 3] The IC of Figure 1 is mounted on a printed circuit board (PCB).

[0013] [Figure 4] A schematic diagram of a load test unit configured to be inserted into a socket on a PCB, which has an integrated power supply circuit and a control circuit.

[0014] [Figure 5] is a schematic diagram of a load test unit having a control circuit connected to a power supply circuit via an interconnecting cable.

[0015] [Figure 6] depicts a schematic view of a printed circuit board (PCB) having multiple DDR4 DIMM sockets connected via one or more buses and a processor socket.

[0016] [Figure 7] is a schematic view of an illustrative electronic load test system, which includes a control circuit and a power supply circuit mounted on the PCB of Figure 6.

[0017] [Figure 8] A block diagram depicting the features of the electronic load test system of Figure 7 according to the present disclosure.

[0018] [Figure 9] is an example of a load unit used in the electronic load test system of Figure 7.

[0019] [Figure 10] Depicts an illustrative load cell for the electronic load test system of Figure 7.

[0020] [Figure 11] depicts the configuration of two load units for the electronic load test system of Figure 7, which have a common connection for current sensing return.

[0021] [Figure 12] depicts an example of four load units for the electronic load test system of Figure 7, which have a common connection for current sensing return.

[0022] [Figure 13] depicts an example of a load unit for the electronic load test system of Figure 7, which has a linear gate drive and a digital gate level converter.

[0023] [Figure 14] illustrates an example of an array of load cells driven by individual DAC outputs for the electronic load test system of Figure 7, which utilizes a combination of CS+ and CS- signals.

[0024] [Figure 15] illustrates an example of an array of load cells used in the electronic load test system of Figure 7, driven by a common DAC output and employing a combination of CS+ and CS- signals.

[0025] [Figure 16] is an example of a heat dissipation solution based on the characteristics of this disclosure.

[0026] [Fig. 17] A block diagram depicting the characteristics of a clock used in the device of FIG. 7.

[0027] [Fig. 18] Depicts the edge of a timing pulse with the jitter of the clock in Fig. 17.

Claims

1. An electronic load testing system, comprising: A control module configured to be electrically coupled to a first location on the printed circuit board (PCB) assembly of the electronic components; and a load module configured to be electrically coupled to a second location on the PCB assembly, wherein the first location and the second location are spaced apart and electrically communicate via one or more lines of the PCB assembly; the load module includes a load unit configured to mimic a load by conducting current from a power source of the PCB assembly, the load unit including a transistor and a current sensing resistor; wherein the control module is configured to communicate with the load module via the one or more lines of the PCB assembly.

2. The electronic load test system of claim 1, wherein at least one of the first position and / or the second position includes an integrated socket of the PCB.

3. The electronic load test system of claim 1, wherein the first position includes a memory module socket and the second position includes a processor socket.

4. The electronic load testing system of claim 1, wherein the load unit is a first load unit; and wherein the load module includes at least one second load unit, such that the first load unit and the second load unit share a common negative current sensing connection.

5. The electronic load test system of claim 1, wherein the transistor includes a metal-oxide-semiconductor field-effect transistor (MOSFET).

6. The electronic load test system of claim 1, wherein the control module includes a linear driver configured to generate a drive voltage applied to the gate of the transistor.

7. The electronic load test system of claim 6, wherein the control module includes a digital-to-analog converter configured to convert the output of the control module into an analog signal, wherein the input of the linear driver is coupled to the output of the digital-to-analog converter of the control module, such that the control module is configured to adjust the nonlinearity of the transistor.

8. The electronic load test system of claim 1, wherein the load unit is a first load unit, and the load module includes at least one second load unit; wherein the control module is configured to utilize a first linear driver and a second linear driver to generate drive voltages applied to individual transistors of the load units; and wherein the first load unit and the second load unit share a common negative current sensing connection and a common positive current sensing connection.

9. The electronic load test system of claim 8, wherein the control module includes a first digital-to-analog converter and a second digital-to-analog converter, wherein the first linear driver is configured to utilize the output of the first digital-to-analog converter, and wherein the second linear driver is configured to utilize the output of the second digital-to-analog converter to adjust the nonlinearity of the transistor.

10. The electronic load test system of claim 8, wherein the control module includes a digital-to-analog converter having a first output and a second output, wherein a first linear driver is configured to utilize the first output of the digital-to-analog converter, and wherein a second linear driver is configured to utilize the second output of the digital-to-analog converter to adjust the nonlinearity of the transistor.

11. The electronic load test system of claim 1, further comprising a temperature sensor, wherein the electronic load test system is configured to use the temperature sensor to measure one or more thermal management properties of the electronic component, such that the electronic load test system can provide an equivalent thermal image.

12. The electronic load test system of claim 1, wherein the electronic load test system is coupled to the electronic component, and wherein the electronic component includes a computer motherboard, the first location is a memory module socket, the second location is a processor socket, and the one or more lines include data buses of the computer motherboard.

13. A method for testing the characteristics of an electrical system using an electronic load test system as claimed in claim 1, wherein the electrical system comprises the PCB of the electronic component, the method comprising: The electrical system is characterized by sending a drive signal from the control module to the gate of the transistor via one or more of the lines of the PCB assembly to induce current in the load unit; measuring the voltage across the current sensing resistor using the control module via one or more of the lines; and evaluating the characteristics of the electrical system by comparing the measured voltage with a expected voltage.

14. An electronic load test system configured to simulate the characteristics of an integrated circuit (IC), the electronic load test system comprising: A control module is configured to be electrically coupled to a first location on the printed circuit board (PCB) of the electronic component; and a load module configured to be electrically coupled to a second location on the PCB, the load module including a load unit configured to conduct current from the power supply of the electronic component, the load unit including a transistor and a current sensing resistor; wherein the first location and the second location are spaced apart and are electrically communicated via one or more lines on the PCB; wherein the control module is configured to communicate with the load module via the one or more lines on the PCB; and wherein the load module and the IC have the same physical coverage area.

15. The electronic load test system of claim 14, wherein the load module is configured to have substantially the same thermal properties as the IC by utilizing the same size, materials and structure.

16. The electronic load test system of claim 15, further comprising a temperature sensor, wherein the electronic load test system is configured to use the temperature sensor to measure one or more thermal management properties of the electronic component, such that the electronic load test system is able to provide an equivalent thermal image.

17. The electronic load test system of claim 14, wherein the electronic load test system is coupled to the electronic component; and wherein the electronic component includes a computer motherboard, the first location being a memory module socket, the second location being a processor socket, and the one or more lines including data buses of the computer motherboard.

18. The electronic load test system of claim 14, wherein the load unit is a first load unit, and the load module further includes a second load unit, the second load unit sharing a common negative current sensing connection with the first load unit.

19. The electronic load testing system of claim 14, wherein the control module is physically separate from the load module.

20. A method for testing the electrical characteristics of an electrical system, the method comprising: A drive signal is sent from a control module to the gate of a transistor in a load unit of a load module via one or more lines of the electrical system. The control module is coupled to the electrical system at a first position, and the gate of the transistor is coupled to the electrical system at a second position, wherein the first and second positions are spaced apart and are electrically communicated via the one or more lines of the electrical system. The control module is used to measure the voltage across a current-sensing resistor of the load unit via the one or more lines. The characteristics of the electrical system are evaluated by comparing the measured voltage with a expected voltage.

21. The method of claim 20, wherein the actual size of the actual coverage area of ​​the load module is configured to mimic an integrated circuit (IC) typically mounted at the second location in the electrical system, and the method further comprises coupling the load module to the electrical system at the second location in the same manner as the IC would use.

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