Memory device and method for programming memory device

Abstract

This invention relates particularly to a method for programming a memory device comprising a plurality of memory arrays. The method may include: receiving a command for programming one or more of the plurality of memory arrays, and programming the one or more of the plurality of memory arrays based on the command. The method may, if necessary, include erasing the one or more of the plurality of memory arrays prior to programming.

Description

[Technical Field]

[0001] Embodiments of the present invention particularly relate to systems and methods for magnetoresistive random access memory (MRAM) devices, including systems and methods for supporting an erase operation in an MRAM device. [Previous Technology]

[0002] Generally speaking, a memory system may include a memory device for storing data and a host (or controller) for controlling the operation of the memory device. Memory devices can be classified into volatile memory (such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), etc.) and non-volatile memory (such as, for example, electrically erasable programmable read-only memory (EEPROM), ferroelectric random access memory (FRAM), phase-change memory (PRAM), magnetoresistive memory (MRAM), resistive random access memory (RRAM / ReRAM), flash memory, etc.).

[0003] Serial NOR memory uses a large page buffer (e.g., a 256-byte buffer for data) to perform page programming operations. However, before performing page programming, serial NOR memory requires an erase operation on a portion of the memory containing the pages addressed for programming. This erase operation is necessary because a floating gate bit cell in serial NOR memory may need to have all floating gates written to a specific state before a write operation is performed. Therefore, an erase operation is required before performing a programming operation in serial NOR memory. Performing an erase operation results in additional write time and resources (e.g., energy) required to write bits into serial NOR memory.

Implementation Method

[0009] Cross-reference to related applications

[0010] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 269,660, filed March 21, 2022, the entire contents of which are incorporated herein by reference.

[0011] Detailed illustrative examples are disclosed herein. However, the specific structural and functional details disclosed herein are representative only for the purpose of describing exemplary embodiments of the invention. The invention may be embodied in many alternative forms and should not be construed as being limited to the embodiments set forth herein. Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments described herein.

[0012] When the specification refers to "an embodiment" or "an embodiment," it is intended to mean that a particular feature, structure, characteristic, or function described in connection with the discussed embodiment is included in at least one contemplated embodiment of the invention. Therefore, the phrases "in one embodiment" or "in one embodiment" appearing in different places in the specification do not constitute a plurality of references to a single embodiment of the invention.

[0013] As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" are intended to include the plural forms as well. It should also be noted that in some alternative embodiments, the described features and / or steps may not occur in the order shown in the figures or discussed herein. For example, two steps or figures shown consecutively may alternatively be performed substantially simultaneously or sometimes in reverse order, depending on the function / action involved. In some cases, without departing from the scope of the embodiments described herein, depending on the function / action involved, one or more described features or steps may be completely omitted, or may be performed using an intermediate step between them.

[0014] Furthermore, the terms "first," "second," etc., used herein do not indicate any order, quantity, or importance, but are used to distinguish one element from another. Similarly, terms of relative orientation (such as "top," "bottom," etc.) are used with reference to the orientation of the structure illustrated in the described figures. It should also be noted that all values ​​disclosed herein are subject to variation of ±10% from the disclosed values ​​(unless a different variation is specified). In addition, all related terms such as "about," "substantially," and "approximately" are used to indicate possible variations of ±10% (unless otherwise stated or specified).

[0015] In one embodiment, the present invention relates to techniques and embodiments for programming storage devices, such storage devices including, for example, non-volatile or "permanent" memory (e.g., flash memory, MRAM, or ReRAM) capable of retaining data when a power source is turned off. Although the following description refers to MRAM or ReRAM memory device cells, the present invention can be implemented in other memory devices including, but not limited to, electrically erasable programmable read-only memory (EEPROM) and / or ferroelectric random access memory (FRAM).

[0016] Serial NOR and / or NAND non-volatile memory requires an erase operation because the bits to be written need to be erased before programming operations. An erase operation writes each bit to a first state, which is then a programming operation that can write each bit to a second state. Without writing the first state, the second state cannot be written to serial NOR and / or NAND memory.

[0017] Furthermore, serial static random access memory (SRAM) volatile memory may not require an erase operation. For example, serial SRAM memory can be configured to write a state during a programming / write command without an erase operation. However, although serial SRAM can be used to program write commands without an erase operation, serial SRAM is volatile memory, thus limiting its use.

[0018] Furthermore, an MRAM-1 transistor and a 1-MTJ (1T1MTJ) bit array are typically configured in columns and rows. For example, 256 or 512 bits in a row can share dedicated bit lines (BL) and source lines (SL) conductors for each row. A word line (WL) can connect to multiple bits along the column direction. If the source lines are placed on a lower-level metal layer, the parasitic resistance can be large. Therefore, one variation of this standard source line array can include a common source line array of two rows sharing a wide horizontal source line. In a standard or common source line array, the direction of MTJ current flow for writing 1 and writing 0 states can be from transistor to MTJ or from MTJ to transistor, respectively. For example, a write 1 current can make the voltage (V) across the MTJ resistance at the source of a selected transistor equal to the current (I) * resistance (R), thereby reducing the gate-source voltage of the transistor. Therefore, two different word line voltage levels can be used to drive the maximum current during writing 0 and writing 1, respectively. In flash memory applications such as those with erase and programmed commands, writing 0 and 1 states separately can address the issue of different word line voltage levels at the cost of longer write timings. The selected word line voltage level is driven to one level above VDD to maximize the drive current of the select transistor during writing. Therefore, it is necessary to boost the unselected cell lines along the column to avoid time-dependent dielectric collapse (TDDB) stress on the select transistor.

[0019] Certain embodiments described herein can solve one or more of the above-described problems. For example, certain embodiments of the disclosed persistent xSPI MRAM device can support performing a programmed operation without an erase operation, while being non-volatile, and can provide an alternative bit array scheme, such as a local source line array, to solve the write problem identified above. Furthermore, the disclosed persistent xSPI MRAM device can also support an optional erase command. This erase command can be optional and can be executed before a write or programmed command is issued. The xSPI MRAM device disclosed herein can be non-volatile memory or may include one or more non-volatile memory components.

[0020] Alternatively or additionally, the xSPI MRAM memory disclosed herein may include a non-volatile erase bit value register storing an erase bit value that can be set or reset by a controller. For example, an erase bit value of 1 may indicate an erase with a state of 1, and an erase bit value of 0 may indicate an erase with a state of 0. According to some embodiments, these bits may be inverted to indicate a 1 or 0 state. Therefore, when an erase command is initiated, the erase bit value (e.g., 1 or 0) can be referenced. Based on the erase bit value stored in the non-volatile erase bit value register, an erase operation can be performed on the respective bits, such that the respective bits are programmed to be 1 or 0.

[0021] According to the implementation, when the erase bit value is 0, an erase command can write data state 0 to the MRAM memory array. When the bit is set to 1, an erase command can write data state 1 to the MRAM memory array. An erase command can be implemented using either a data state of 1 or 0, depending on the erase bit value provided in the non-volatile erase bit value register. The programming or write commands disclosed herein for xSPI MRAM memory use an erase command as needed before the programming or write command (e.g., an erase command is not required before the programming or write command). Therefore, xSPI MRAM memory provides an option to erase data in the address space before issuing a programming or write command, but does not require erasing data in the address space before issuing a programming or write command.

[0022] As described herein, configuring an MRAM device to perform an erase operation as needed before a write or programming command can reduce or eliminate the operations required to program the MRAM device. This can save energy that would otherwise be consumed by operating the MRAM device and / or reduce the latency associated with programming the MRAM device.

[0023] FIG1 illustrates a functional block diagram of an exemplary MRAM device 100 according to one aspect of the present invention. The write speed of an MRAM device 100 can be faster than that of a serial NOR memory device. For example, a write to the local storage device (e.g., cache) can be performed simultaneously with writing data from a local storage device of the MRAM device 100 to the main memory array, and a write to the main memory array can be performed relatively quickly (e.g., compared to a NOR memory device). Therefore, an MRAM device 100 can allow write operations of data ranging in size from 1 byte to a substantially unlimited number of bytes. Therefore, an MRAM device 100 does not have the limitation of using a page buffer of a set size to perform a page programming operation as in a NOR memory device, because a write to the main memory array can be performed in the background simultaneously with a write to the local storage device (e.g., cache). Because writing to the main memory array in an MRAM device 100 is fast, the cache size can be kept small (e.g., 256 bits), and writing to the main memory array can be performed in parallel with writing to the cache. Furthermore, functionality is improved because the controller 104 can stop data transfer to the memory array libraries 101, 111 at any time after one byte has been written.

[0024] As shown in FIG1, the MRAM device 100 may include a first memory array library 101 (e.g., illustrated as an MRAM array library) and a second memory array library 111. A controller 104 may be connected to a cache 102 and an address decoder 103 of the first memory array library 101, a cache 112 and an address decoder 113 of the second memory array library 111, a set of temporary registers 105, a counter 106, and an input / output interface 107 (labeled "interface I / O" in FIG1). The memory array libraries 101 and 111 may be accessed independently of each other to read and / or write any desired address. Caches 102 and 112 may be coupled to memory array libraries 101 and 111 respectively to allow data transfer between the memory array libraries and the caches. In some embodiments, each of caches 102 and 112 may include static random access memory (SRAM) cells, while in other embodiments, caches 102 and 112 may include registers, flip-flops, or other storage circuitry for storing data. Caches 102 and 112 may contain sufficient storage to accommodate data pages from the memory array library, and may also include additional storage devices to store page addresses, page parity checks or other error correction code (ECC) information, and any inversion or other page-related information. The instance size of the cache may include 32 bits and 256 bits; however, instance embodiments are not limited to these sizes. The size of the cache and the size of the accessed pages can be adjusted to meet application needs.

[0025] Configuration register 105 (labeled "configuration register" in FIG1) may include at least one configuration register bit that identifies whether the MRAM device 100 operates in a first mode or a second mode. For example, configuration register 105 may be a write-mode configuration register that indicates whether the MRAM device 100 operates in a NOR analog mode (i.e., NOR flash programming mode) or a persistent memory mode. Configuration register 105 may be written to and / or read from controller 104 and interface I / O 107 (e.g., a serial interface connected to controller 104 for external communication). Users may access configuration register bits (e.g., for reading or writing) via interface I / O 107. When configuration register 105 is set to 0 to operate in, for example, a NOR analog mode, counter 106 may be used.

[0026] The configuration register 105 may be a separate component from an erase bit value register (not shown in FIG. 1) that stores a bit value indicating whether to perform a selected erase operation in certain embodiments. Alternatively, in some embodiments, the configuration register 105 and the erase bit value register may be implemented in a combined component. For example, in some embodiments, a single register may be used to store configuration register bits and erase bit values.

[0027] Counter 106 may be an address counter used to track information, such as when certain operations should occur. For example, address counter 106 may contain a counter value that increments once for each byte written. When the counter value reaches its limit, controller 104 may cause the data of the next byte to be written to a starting address, thereby overwriting the previously written data.

[0028] The first memory array library 101 and the second memory array library 111 can be used together to achieve a high-speed serial interface (e.g., 200 MHz or higher). Using double data rate (DDR), data can be obtained at both the rising and falling edges of the clock. For DDR, the first memory array library 101 can initially be used to write data. If the first memory array library 101 takes too long to write a page (e.g., a 256-bit page), the second memory array library 111 can be used. For example, the first memory array library 101 and the second memory array library 111 can be used independently of each other to improve the speed and performance of the MRAM device 100.

[0029] Although some embodiments are described herein as relating to a memory array library, some embodiments may relate to a memory array. A memory array may include an array of storage elements, such as an MRAM byte array, and associated sensing, write driving, and word line driving circuitry. Alternatively, a memory array may contain only an array of storage elements, such as only MRAM byte arrays. A memory library may contain one or more memory arrays defined by a common memory library address.

[0030] Figure 2 illustrates a functional block diagram of an exemplary xSPI MRAM device 200 according to one aspect of the present invention. For example, the xSPI MRAM device 200 may include a 64 Mb chip or a chip of any other size. The xSPI MRAM device 200 may include: a memory bank and / or bias power supply 202, a bias system 204 connected to the memory bank and / or bias power supply 202, a magnetic tunneling junction (MTJ) antifuse block 206 included in the bias system 204, a first memory array bank 208-1 (labeled "Memory Bank 1" in Figure 2) and a second memory array bank 208-2 (labeled "Memory Bank 0" in Figure 2) connected to the bias system 204, an error correction code (ECC) data path 210-1 (labeled "ECC Data Path 1" in Figure 2) connected to the memory array bank 208-1, and an ECC data path 210-2 connected to the memory array bank 208-2. (labeled "ECC data path 0" in Figure 2), an xSPI interface 212 connected to one of the ECC data paths 210-1 and 210-2, and an xSPI power supply (e.g., interface power supply) and / or input / output 214 (labeled "IOs" in Figure 2) connected to the ECC data path 210 and connected to the MTJ antifuse block 206 and / or bias system 204.

[0031] In some embodiments, the memory array library 208 may be similar to the memory array libraries 101 and 111 of FIG1, and the xSPI interface 212 and / or IOs may be similar to the interface I / O 107 of FIG1. ​​In addition, the xSPI MRAM device 200 may include one or more other components illustrated in FIG1, such as a controller similar to controller 104.

[0032] An erase bit value register may have one of the volatile registers in the xSPI interface 212 and may have one of the dedicated MRAM bit registers for non-volatile values ​​in either or both of the memory array libraries 208. For example, the MTJ-based antifuse block 206 can be used to program read / write bias levels, timing, and / or redundancy mapping. Isolated voltage sources (memory library and bias power supply 202) can be used for better noise isolation. For peak read and write bandwidths up to, for example, 400 MB / s, the xSPI interface 212 can independently drive the two memory array libraries 208, thereby managing the overlapping timing required in different serial (single, double, quad, octave) modes.

[0033] Therefore, a controller (not shown in Figure 2) may output an erase operation command before and / or as part of a programming or write operation. Based on the erase operation command, the xSPI interface 212, memory array library 208-1, and / or memory array library 208-2 may provide erase bit value register bits (i.e., erase bit values) stored therein. Based on the erase bit value register bits, one or more data in the address space may be replaced (e.g., replaced to a 0 state or a 1 state). After the address space is replaced during the erase operation, a write and / or programming command may be executed.

[0034] The optional erase operation supported by the xSPI MRAM device 200 disclosed herein allows for compatibility with existing serial NOR controllers. For example, although writing to or programming the xSPI MRAM device 200 disclosed herein does not require an erase operation, an existing serial NOR controller configured to output an erase command can operate with the xSPI MRAM device 200 disclosed herein. This controller can output an erase command, and the xSPI MRAM device 200 can perform an erase operation based on the erase bit value register bits disclosed herein. Additionally or alternatively, certain states disclosed herein provide additional security, wherein a portion of the memory can be erased to state 0 or 1 based on an erase command.

[0035] Alternatively, as disclosed herein, a controller may not apply (e.g., may skip or determine not to execute) an erase command, but may use a programmed or write command without any erase operation to reduce write power and / or write time compared to a serial NOR device using erase plus programmed commands.

[0036] Serial interface memory products can use 1 to 8 low-pin counts of I / Os with chip select (CS), clock (CK), and data strobe (DS). High bandwidth can be achieved using single transfer rate (STR) or double (data at the two clock edges) transfer rate (DTR).

[0037] Figure 3 illustrates an exemplary signal protocol 300 for read and / or write operations of the xSPI MRAM device of Figure 2 according to one aspect of the present invention. For example, Figure 3 illustrates the signal protocol 300 for typical read and / or write operations, wherein, for example, an 8-bit command arithmetic code 304 may be followed by an address 306 and a data stream 308 as IOs 302. Figure 3 also illustrates, for example, CS\ (at 310) and CK (at 312) for the signal protocol 300. Due to the fast internal access capability, internal memory array read and / or write operations can occur instantaneously during the data stream portion of the protocol in the serial SRAM. However, serial NOR products may have asymmetric read and / or write operations and timing, wherein internal reads can occur instantaneously, but internal writes can operate on a page buffer (e.g., 2K or 4K bits), and CS\ at 310 is low. NOR memory array writes can occur after the CS at 310 enters one of the high states shown in Figure 3 during a busy state (typically several hundred microseconds). Through the chip architecture and array circuitry disclosed herein, certain embodiments disclosed herein can perform real-time MRAM array read and / or write operations, such as serial SRAM.

[0038] FIG4A illustrates an exemplary local source line array 400 having a write current flow direction and return path according to one aspect of the present invention. The local source line array 400 includes various word lines (WL) 402 (e.g., WL1 as WL 402-1 to WLn as WL 402-N), various bit lines (BL) 404 (e.g., BL1 as BL 404-1 to BLn as BL 404-N), various isolation switches (ISO) 406 (e.g., ISO 406-1 to ISO 406-N), and various local word lines (LWL) 408 (e.g., LWL1 as 408-1 to LWLn as LWL 408-N). As further illustrated in Figure 4A, for each BL 404, the local source line array 400 may include an MTJ 410 connected to one of the transistors 412 and BL 404, where the transistor 412 is connected to an LWL 408. In this way, one local source line along the column direction can be used to connect a small group of MTJs and distribute return current in unselected BL 404s. For example, an MTJ group size of 32 BL 404s helps ensure that no interference occurs in unselected BL 404s. For the return current paths illustrated in Figure 4A using write 0 and write 1, WL 402-1 may be the selected word line, BL 404-1 may be the selected cell line, and BL 404-2 to BL 404-N may be return current paths. Furthermore, an LWL 408 for the local source lines MTJ 410 of the same group can be connected to WL 402 in the column direction via ISO 406.

[0039] FIG4B illustrates a graphical graph 414 of one of the LWL 408 voltage levels in a selected column during a write operation of the xSPI MRAM device 200 of FIG2 according to one embodiment of the present invention. For example, FIG4B illustrates an exemplary LWL 408 auto-boot. When BL 404 is grounded in a standby mode, the voltage (V(LWL)) of LWL 408 can reach a voltage WL (Vwl) level, where Vwl can be the expected LWL 408 voltage level before a write voltage is applied across BL 404. Subsequently, LWL 408 can be isolated from WL 402 and the Vwl level can be automatically booted to a higher level depending on the write 1 or write 0 voltage applied on BL 404. The LWL 408 auto-boot can be attributed to coupling with a selected transistor 412 in a local source line group. This scheme allows simultaneous writing of 0 or 1 states or write-inhibited states to a local source line group along the same column, and avoids any need to promote the BL 404 to a local source line group that is write-inhibited.

[0040] FIG5 illustrates a flowchart of an exemplary method 500 for programming the xSPI MRAM device 200 of FIG2 according to one aspect of the present invention. Method 500 can be implemented in a controller in a microprocessor, microcontroller, or system-on-a-chip (SoC) connected to the xSPI MRAM device 200. Method 500 can program one or more memory array libraries 208 of the xSPI MRAM device 200.

[0041] Method 500 may include receiving a command at step 502 for programming a device. For example, a controller associated with an xSPI MRAM device 200 may receive a command for programming one or more memory array libraries 208 of the xSPI MRAM device 200 (e.g., programming one or more memory array libraries 208 with values ​​of 0 or 1). Depending on what application a user is executing, the controller may receive the command from one or more other components, such as a microprocessor, microcontroller, or SoC.

[0042] Method 500 may include erasing the device as needed at step 504. For example, the controller may erase the xSPI MRAM device 200 as needed. In some embodiments, the selective erasure at step 504 may include erasing the xSPI MRAM device 200 after receiving a command, or it may include not erasing the xSPI MRAM device 200 after receiving a command. If method 500 includes erasing the xSPI MRAM device 200, then method 500 may include erasing one or more memory array libraries 208 after receiving a command. As discussed above, based on the erase bit value register bits stored in the xSPI interface and / or memory array libraries, one or more data in the address space may be replaced (e.g., with a 0 state or a 1 state). If method 500 does not include erasing the xSPI MRAM device 200, then method 500 may proceed to step 506 after step 502 without performing an erasure operation. When performance or operating time is critical, such as during random access in a static random access memory (SRAM) application, the controller may determine to program the xSPI MRAM device 200 without performing an erase operation. In some embodiments, if an erase operation is required, the controller may determine to program the xSPI MRAM device 200 to emulate NOR flash memory after performing an erase operation. The controller may further determine to perform an erase operation to safely erase the xSPI MRAM device 200 so that the erased data can no longer be accessed.

[0043] Method 500 may include programming the device at step 506 based on a command and after erasing the device as needed. For example, the controller may program one or more memory array libraries 208 of the xSPI MRAM device 200. Programming of the xSPI MRAM device 200 may occur after erasing one or more memory array libraries 208 or after receiving a command at step 502 without erasing one or more memory array libraries 208. In some embodiments, one or more memory array libraries 208 may apply one or more voltages to the circuitry of the xSPI MRAM device 200 to perform programming at step 506, as described in more detail elsewhere herein, for example, in conjunction with Figures 4A and 4B. For example, one or more memory array libraries 208 may apply a set of voltages to a WL 402, a BL 404, and / or an LWL 408 to write a 0 or 1 value to one or more memory array libraries 208. Alternatively, one or more memory array libraries 208 may control the voltage level on BL 404 to facilitate writing to values ​​of 0 or 1.

[0044] FIG6 illustrates a flowchart of an exemplary method 600 for controlling a write operation of the xSPI MRAM device 200 of FIG2 according to one aspect of the present invention. For example, method 600 may use a write enable command to control the write operation.

[0045] Method 600 may include receiving a write enable command at a device at 602. For example, a controller associated with an xSPI MRAM device 200 may receive the write enable command. The write enable command may configure the controller to perform write or programming operations on one or more memory array libraries 208 of the xSPI MRAM device 200. For example, the controller may be prevented from writing to or programming the memory array libraries 208 until the write enable command is received. The write enable command may be received from a microprocessor, microcontroller, or SoC connected to the xSPI MRAM device 200.

[0046] In some embodiments, method 600 may include receiving a single write enable command for one of one or more write or programmable operations. For example, the controller may receive a single write enable command for one of multiple write or programmable operations, rather than a write enable command for each write or programmable operation to be performed. This saves resources that would otherwise be consumed in sending and receiving a write enable command for each write or programmable operation to be performed. Furthermore, this can reduce the potential time associated with performing one or more write or programmable operations by reducing or eliminating the need to process a write enable command for each of the write or programmable operations.

[0047] Method 600 may include performing one or more programmed operations on one or more memory array libraries at step 604. For example, the controller may write a 0 or 1 value to one or more memory array libraries 208 in a manner similar to that described elsewhere herein. The one or more programmed operations may be similar to the programming performed at step 506 of method 500 in FIG. 5.

[0048] In some embodiments, the controller may perform multiple write or programmed operations after receiving a write enable command. For example, the controller may perform a write or programmed operation after receiving a single write enable command at step 602. Continuing with the foregoing example, the controller may perform multiple write or programmed commands after receiving a single write enable command.

[0049] Method 600 may include receiving a write disable command at 606 at the device. For example, the controller may receive a write disable command for the xSPI MRAM device 200 in a manner similar to that described elsewhere herein. The write disable command may configure the controller to prevent the performance of write or programming operations. In some embodiments, the controller may receive a single write disable command. For example, after performing multiple write or programming operations, the controller may receive a single write disable command to configure the controller to stop writing or programming one or more memory bank arrays 208 and / or prevent the controller from performing additional write or programming operations (e.g., instead of receiving a write disable command for each write or programming operation). Receiving a single write disable command for one of multiple write or programming operations saves resources that would otherwise be consumed to receive and process a write disable command for each of the performed write or programming operations. Furthermore, this can reduce the latency associated with performing one or more write or programming operations by reducing or eliminating the steps that need to be performed between write or programming operations.

[0050] Although methods 500 and 600 are described with respect to the two flowcharts, methods 500 and 600 may be combined in some embodiments. For example, a combined method may include receiving a command for programming the device at step 502, erasing the device as needed at step 504, receiving a write enable command at step 602, programming the device at steps 504 and / or 604, and receiving a write disable command at step 606.

[0051] In this manner, certain embodiments described herein offer various technical advantages. For example, a fast (e.g., sub-20 nanosecond (ns)) write pulse width and an architecture of two memory array libraries 208 with simultaneous writes of 0 and 1 can facilitate RAM-like persistent memory operations in the xSPI MRAM device 200 design. As illustrated in FIG3, data can be written directly to the MRAM array during the data streaming phase 308 of the serial command protocol 300. Therefore, the write time can be a function of single, double, quadruple, and eight times the I / O mode and one of the single or double transfer rates set in the xSPI configuration register (e.g., similar to configuration register 105). The xSPI configuration register may further include a write mode bit to simulate a NOR flash programming mode for, for example, a 256-bit page buffer. When this bit is set, the programming / write address can be wrapped around 256 bits of data, for example, simulating NOR flash programming, in the address space as if a 256-bit page buffer existed. Additionally or alternatively, erase commands may also be supported, but may be supported in the xSPI interface 212 as needed for compatibility with the serial flash protocol. Additionally or alternatively, some embodiments described herein may not require write verification. Therefore, MRAM write times may be several orders of magnitude better than some NOR devices. Furthermore, some embodiments can provide several orders of magnitude better write energy improvements than some NOR devices at a given throughput with effective current consumption of the target IDD or the power supply (VDD) from the xSPI MRAM device 200.

[0052] In one embodiment, a method for programming a memory device including one of a plurality of memory arrays may include: receiving a command for programming one or more of the plurality of memory arrays; and programming the one or more of the plurality of memory arrays based on the command, wherein the method may include, as needed, erasing the one or more of the plurality of memory arrays prior to the programming.

[0053] Various embodiments of the method may include: erasing one or more of the plurality of memory arrays after receiving the command, wherein programming the one or more of the plurality of memory arrays further includes: programming the one or more of the plurality of memory arrays after erasing the one or more of the plurality of memory arrays; programming the one or more of the plurality of memory arrays further includes: programming the one or more of the plurality of memory arrays without erasing the one or more of the plurality of memory arrays before programming; the memory device includes an extended serial peripheral interface (xSPI) magnetoresistive random access memory (MRAM) device; the memory device further includes The method includes: a bias system connected to the plurality of memory arrays; an error correction code data path corresponding to each of the plurality of memory arrays; and an interface; the bias system includes one or more magnetoresistive antifuse blocks; the interface is connected to the one or more magnetoresistive antifuse blocks; the bias system is connected to an array power supply or a bias power supply; the interface is connected to an interface power supply and one or more inputs or outputs of the memory devices; the method further includes: receiving a write enable command at the memory device before programming the one or more of the plurality of memory arrays; and receiving a write disable command at the memory device after programming the one or more of the plurality of memory arrays.

[0054] In another embodiment, a memory device may include: a plurality of memory arrays, the memory device being configured to: receive a command for programming one or more of the plurality of memory arrays; and program the one or more of the plurality of memory arrays based on the command, wherein the memory device is configured to erase the one or more of the plurality of memory arrays as needed before the programming.

[0055] Various embodiments of the memory device may include: the method device is further configured to: erase one or more of the plurality of memory arrays after receiving the command, wherein when programming the one or more of the plurality of memory arrays, the memory device is further configured to: program the one or more of the plurality of memory arrays after erasing the one or more of the plurality of memory arrays; when programming the one or more of the plurality of memory arrays, the memory device is further configured to: program the one or more of the plurality of memory arrays without erasing the one or more of the plurality of memory arrays before programming; the memory device further includes: a bias The system includes a bias system connected to the plurality of memory arrays, an error correction code data path corresponding to each of the plurality of memory arrays, and an interface; the bias system includes one or more magnetoresistive antifuse blocks; the interface is connected to the one or more magnetoresistive antifuse blocks; the bias system is connected to an array power supply or a bias power supply; the interface is connected to an interface power supply and one or more inputs or outputs of the memory devices; the memory devices are further configured to: receive a write enable command at the memory device before programming the one or more of the plurality of memory arrays; and receive a write disable command at the memory device after programming the one or more of the plurality of memory arrays.

[0056] In another embodiment, a method for programming a memory device including one of a plurality of memory arrays may include: receiving a write enable command at the memory device; receiving a command for programming one or more of the plurality of memory arrays; performing one or more programming operations on the one or more of the plurality of memory arrays after receiving the write enable command, wherein the method may include, as needed, erasing the one or more of the plurality of memory arrays before performing the one or more programming operations; and receiving a write disable command at the memory device after performing the one or more programming operations.

[0057] The foregoing description of the invention has been provided for clarity and understanding purposes. It is not intended to limit the invention to the precise forms disclosed. Various modifications are possible within the scope and equivalents of this application. [Simplified Explanation of the Diagram]

[0004] In the following detailed description, reference will be made to the accompanying drawings. The accompanying drawings illustrate different aspects of the invention, and where appropriate, reference numerals illustrating the same structures, components, materials, and / or elements are similarly labeled in different drawings. It should be understood that various combinations of structures, components, and / or elements other than those specifically shown are considered and are within the scope of the invention.

[0005] Furthermore, numerous embodiments of the present invention are described and illustrated herein. The present invention is not limited to any single form or embodiment thereof, nor to any combination and / or arrangement of such forms and / or embodiments. Moreover, each form and / or embodiment of the present invention may be used alone or in combination with one or more of other forms and / or embodiments of the present invention. For the sake of brevity, certain arrangements and combinations are not discussed and / or described separately herein; however, all arrangements and combinations are considered to fall within the scope of the present invention.

[0006] Figure 1 illustrates a functional block diagram of an exemplary MRAM device according to one aspect of the present invention. Figure 2 illustrates a functional block diagram of an exemplary Extended Serial Peripheral Interface (xSPI) MRAM device according to one aspect of the present invention. Figure 3 illustrates an exemplary signal protocol for read and / or write operations of the xSPI MRAM device of Figure 2 according to one aspect of the present invention. Figure 4A illustrates an exemplary local source line array having a write current flow direction and return path according to one aspect of the present invention. Figure 4B illustrates a graphical curve of a local word line (LWL) voltage level in a selected column during a write operation of the xSPI MRAM device of Figure 2 according to one aspect of the present invention. Figure 5 illustrates a flowchart of an exemplary method for programming the xSPI MRAM device of Figure 2 according to one aspect of the present invention. Figure 6 illustrates a flowchart of an exemplary method for controlling the write operation of the xSPI MRAM device of Figure 2 according to one aspect of the present invention.

[0007] Furthermore, numerous embodiments are described and illustrated herein. The invention is not limited to any single variant or embodiment thereof, nor to any combination and / or arrangement of such variants and / or embodiments. Each variant and / or embodiment of the invention may be used alone or in combination with one or more of other variants and / or embodiments of the invention. For the sake of brevity, many of these combinations and arrangements are not discussed separately herein.

[0008] As used herein, the terms "comprises," "comprising," or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes one of the lists of elements may include not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "illustrative" is used in the meaning of "example" rather than "ideal."

Claims

1. A method for programming a memory device comprising a plurality of memory arrays and a non-volatile erase bit value register, the method comprising: Receive a command for programming one or more of the plurality of memory arrays; and program the one or more of the plurality of memory arrays based on the command, wherein the method includes erasing the one or more of the plurality of memory arrays as needed before programming, wherein erasing the one or more of the plurality of memory arrays as needed includes: If performance or operation time is critical, one of the erase bit values ​​in the erase bit value register is assigned a first state; or if performance or operation time is not critical, the erase bit value in the erase bit value register is assigned a second state, and the erase bit value is received from the erase bit value register. When the erase bit value is in the first state, a selective erase command is initiated, for example, erasing one or more of the memory arrays. When the erase bit value is in the second state, a selective erase command is not initiated, for example, not erasing one or more of the memory arrays.

2. The method of request item 1, further comprising: Upon receiving the command, one or more of the plurality of memory arrays are erased, wherein the programming of one or more of the plurality of memory arrays further includes: after erasing one or more of the plurality of memory arrays, programming of one or more of the plurality of memory arrays.

3. The method of claim 1, wherein the programming of one or more of the plurality of memory arrays further includes: Program one or more of the plurality of memory arrays without erasing the one or more of the plurality of memory arrays prior to the programming.

4. The method of claim 1, wherein the memory device includes an extended serial peripheral interface (xSPI) magnetoresistive random access memory (MRAM) device.

5. The method of claim 1, wherein the memory device further comprises: A bias system connected to the plurality of memory arrays, an error correction code data path corresponding to each of the plurality of memory arrays, and an interface.

6. The method of claim 5, wherein the bias system includes one or more magnetoresistive antifuse blocks.

7. The method of claim 6, wherein the interface is connected to the antifuse block of the one or more magnetoresistive devices.

8. The method of claim 5, wherein the bias system is connected to an array power supply or a bias power supply.

9. The method of claim 5, wherein the interface is connected to an interface power supply and one or more inputs or outputs of the memory device.

10. The method of claim 1, further comprising: Before programming one or more of the plurality of memory arrays, a write enable command is received at the memory device; And after programming one or more of the plurality of memory arrays, a write deactivation command is received at the memory device.

11. A memory device comprising: A plurality of memory arrays and a non-volatile erase bit value register, wherein the memory device includes: a bias system connected to the plurality of memory arrays, wherein the bias system includes one or more magnetoresistive antifuse blocks; an error correction code data path corresponding to each of the plurality of memory arrays; and an interface connected to the one or more magnetoresistive antifuse blocks, and wherein the memory device is configured to: receive a command for programming one or more of the plurality of memory arrays; and program the one or more of the plurality of memory arrays based on the command, wherein the memory device is configured to erase the one or more of the plurality of memory arrays as needed before programming, wherein the erase of the one or more of the plurality of memory arrays as needed includes: The system determines the operation time of the program; and if performance or operation time is critical, it assigns a first state to an erase bit value in the erase bit value register, or if performance or operation time is not critical, it assigns a second state to the erase bit value in the erase bit value register, and receives the erase bit value from the erase bit value register, wherein when the erase bit value is in the first state, a selective erase command is initiated, for example, erasing one or more of the plurality of memory arrays, and when the erase bit value is in the second state, a selective erase command is not initiated, for example, not erasing one or more of the plurality of memory arrays.

12. The memory device of claim 11, further configured to: erase one or more of the plurality of memory arrays after receiving the command, wherein when programming the one or more of the plurality of memory arrays, the memory device is further configured to: program the one or more of the plurality of memory arrays after erasing the one or more of the plurality of memory arrays.

13. The memory device of claim 11, wherein when one or more of the plurality of memory arrays are programmed, the memory device is further configured to: program one or more of the plurality of memory arrays without erasing one or more of the plurality of memory arrays prior to the programming.

14. The memory device of claim 11, wherein the interface is connected to an interface power supply and one or more inputs or outputs of the memory device.

15. The memory device of claim 11, further configured to: receive a write enable command at the memory device before programming one or more of the plurality of memory arrays; and receive a write disable command at the memory device after programming one or more of the plurality of memory arrays.

16. A method for programming a memory device comprising one of a plurality of memory arrays, the method comprising: A write enable command is received at the memory device, wherein the memory device includes: a bias system connected to the plurality of memory arrays, wherein the bias system includes one or more magnetoresistive antifuse blocks; an error correction code data path corresponding to each of the plurality of memory arrays; and an interface connected to the one or more magnetoresistive antifuse blocks; upon receiving the write enable command, one or more programming operations are performed on one or more of the plurality of memory arrays, wherein the method includes erasing one or more of the plurality of memory arrays as needed before performing the one or more programming operations; wherein the erasure of one or more of the plurality of memory arrays includes: The system determines the operation time of the programmed operation; and if performance or operation time is critical, assigns a first state to one of the erase bit values ​​in the erase bit value register, or assigns a second state to the erase bit value in the erase bit value register if performance or operation time is not critical, and receives the erase bit value from the erase bit value register, wherein, when the erase bit value is in the first state, an erase command is initiated, for example, erasing one or more of the plurality of memory arrays, and when the erase bit value is in the second state, an optional erase command is not initiated, for example, not erasing one or more of the plurality of memory arrays; and after performing one or more programmed operations, a write disable command is received at the memory device; and after programming one or more of the plurality of memory arrays, a write disable command is received at the memory device.

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