Semiconductive device and fabricating method of the same

Abstract

A semiconductor device includes a substrate, a high-voltage transistor disposed in a high-voltage region of the substrate, wherein the high-voltage transistor includes a first gate dielectric layer disposed on the substrate, a first gate electrode disposed on the first gate dielectric layer, a first source / drain doped region and a second source / drain doped region respectively disposed in the substrate on both sides of the first gate electrode, a first metal silicide covering and contacting the first source / drain doped region, a second metal silicide covering and contacting the second source / drain doped region, a first conductive plate penetrating the first metal silicide and contacting the first source / drain doped region, and a second conductive plate penetrating the second metal silicide and contacting the second source / drain doped region.

Description

Semiconductor Device and Method of Fabricating the Same The present invention relates to a high-voltage transistor, and more particularly to a high-voltage transistor having a metal silicide layer disposed on a source / drain doped region of the high-voltage transistor. At the current level of semiconductor technology, the industry has been able to integrate control circuits, memories, low-voltage operating circuits, high-voltage operating circuits, and components on a single chip simultaneously, thereby reducing costs and improving operating efficiency. Among them, high-voltage components fabricated in the chip, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT), and lateral-diffusion metal-oxide-semiconductor (LDMOS), are more commonly used because of their better power switching efficiency. As is known to those skilled in the art, the aforementioned high-voltage components are often required to withstand a higher breakdown voltage and operate at a lower resistance value. In addition, as the device size continues to shrink, the development of conventional planar field-effect transistor devices has faced process limitations. To overcome the process limitations, it has become the current mainstream development trend to replace planar transistors with non-planar field-effect transistor devices, such as fin field effect transistor (Fin FET) devices. Since the three-dimensional structure of the fin field effect transistor device can increase the contact area between the gate and the fin structure, the gate's control over the carrier channel region can be further increased, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small-size devices and suppressing the short channel effect (SCE). Furthermore, since the fin field effect transistor device will have a wider channel width at the same gate length, a doubled drain drive current can be obtained. Moreover, the threshold voltage of the transistor device can also be adjusted by adjusting the work function of the gate. However, there are still many challenges in the integration of current high-voltage components and fin structures as the device size continues to shrink. Therefore, how to improve the existing high-voltage component architecture is an important issue today. In view of this, the present invention provides metal silicides on the source / drain doping regions of high-voltage transistors to reduce the on-resistance of the high-voltage transistors. According to a preferred embodiment of the present invention, a semiconductor device includes a substrate including a high-voltage region and a low-voltage region, a first deep trench isolation and a second deep trench isolation disposed in the substrate within the high-voltage region, a high-voltage transistor disposed within the high-voltage region, wherein the high-voltage transistor includes a first gate dielectric layer disposed on a first surface of the substrate, the first gate dielectric layer being located between the first deep trench isolation and the second deep trench isolation and contacting the first deep trench isolation and the second deep trench isolation, a first gate electrode disposed on the first gate dielectric layer, a first source / drain doping region disposed in the substrate on one side of the first deep trench isolation and the first source / drain doping region contacting the first deep trench isolation, a second source / drain doping region disposed in the substrate on one side of the second deep trench isolation and the second source / drain doping region contacting the second deep trench isolation, a first metal silicide covering and contacting the first source / drain doping region, a second metal silicide covering and contacting the second source / drain doping region, a first conductive plate penetrating the first metal silicide and contacting the first source / drain doping region, and a second conductive plate penetrating the second metal silicide and contacting the second source / drain doping region, a fin transistor disposed within the low-voltage region, wherein the fin transistor includes a fin structure protruding from a second surface of the substrate, a second gate electrode disposed on the fin structure, and two shallow trench isolations located on both sides of the fin structure. According to another preferred embodiment of the present invention, a method for manufacturing a semiconductor device includes providing a substrate including a high-voltage region and a low-voltage region, then forming a first deep trench isolation and a second deep trench isolation in the substrate within the high-voltage region, and then forming a high-voltage transistor in the high-voltage region and a fin transistor in the low-voltage region, wherein the high-voltage transistor includes a first gate dielectric layer disposed on a first surface of the substrate and being located between the first deep trench isolation and the second deep trench isolation and contacting the first deep trench isolation and the second deep trench isolation, a first gate electrode disposed on the first gate dielectric layer, a first source / drain doping region disposed in the substrate on one side of the first deep trench isolation and the first source / drain doping region contacting the first deep trench isolation, a second source / drain doping region disposed in the substrate on one side of the second deep trench isolation and the second source / drain doping region contacting the second deep trench isolation, a first metal silicide covering and contacting the first source / drain doping region, a second metal silicide covering and contacting the second source / drain doping region, a first conductive plate penetrating the first metal silicide and contacting the first source / drain doping region, a second conductive plate penetrating the second metal silicide and contacting the second source / drain doping region, the fin transistor including a fin structure protruding from a second surface of the substrate, a second gate electrode disposed on the fin structure, and two shallow trench isolations located on both sides of the fin structure. To make the above objects, features, and advantages of the present invention more clearly understandable, the following preferred embodiments are specifically presented and described in detail in conjunction with the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and illustration purposes and are not used to limit the present invention. FIG. 1 is a semiconductor device illustrated according to a preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor device 100 includes a substrate 10. The substrate 10 includes a high-voltage region HV, a medium-voltage region MV, and a low-voltage region LV. A first deep trench isolation A1 and a second deep trench isolation A2 are disposed in the substrate 10 within the high-voltage region HV. The first deep trench isolation A1 and the second deep trench isolation A2 are each composed of a deep trench filled with an insulating layer. The upper surfaces of the first deep trench isolation A1 and the second deep trench isolation A2 are flush. A high-voltage transistor T1 is disposed within the high-voltage region HV, a medium-voltage transistor T2 is disposed within the medium-voltage region MV, and a fin transistor T3 is disposed within the low-voltage region LV. The high-voltage transistor HV includes a first gate dielectric layer 12a disposed on a first surface 10a of the substrate 10. The first gate dielectric layer 12a is located between the first deep trench isolation A1 and the second deep trench isolation A2 and contacts the first deep trench isolation A1 and the second deep trench isolation A2. In addition, the upper surface of the first gate dielectric layer 12a is preferably flush with the upper surfaces of the first deep trench isolation A1 and the second deep trench isolation A2. The first gate dielectric layer 12a includes silicon oxide. A first gate electrode 14a is disposed on the first gate dielectric layer 12a. The first gate electrode 14 preferably contacts the first deep trench isolation A1 and the second deep trench isolation A2 simultaneously. The first gate electrode 14a preferably includes an electrode made of polysilicon and sidewalls 28a disposed on both sides of the polysilicon electrode. Of course, the electrode can also be composed of other semiconductor materials or metals. A first source / drain doping region 16a is disposed in the substrate 10 on one side of the first deep trench isolation A1 and the first source / drain doping region 16a contacts the first deep trench isolation A1. A second source / drain doping region 16b is disposed in the substrate 10 on one side of the second deep trench isolation A2 and the second source / drain doping region 16b contacts the second deep trench isolation A2. That is to say, the first source / drain doping region 16a and the first gate dielectric layer 12a are separated by the first deep trench isolation A1, and the second source / drain doping region 16b and the first gate dielectric layer 12a are separated by the second deep trench isolation A2. A first metal silicide 18a covers and contacts the first source / drain doping region 16a, and a second metal silicide 18b covers and contacts the second source / drain doping region 16b. A first conductive plate 20a penetrates the first metal silicide 18a and contacts the first source / drain doping region 16a, and a second conductive plate 20b penetrates the second metal silicide 18b and contacts the second source / drain doping region 16b. In addition, there is no epitaxial layer within the first source / drain doping region 16a and the second source / drain doping region 16b or on the surfaces of the first source / drain doping region 16a and the second source / drain doping region 16b. The medium-voltage transistor T2 includes a second gate dielectric layer 12c disposed on a third surface 10c of the substrate 10. The second gate dielectric layer 12c includes silicon oxide. A third gate electrode 14c is disposed on the second gate dielectric layer 12c. The third gate electrode 14c preferably includes an electrode made of polysilicon, sidewall spacers 28c, and sidewall spacers 28c. The sidewall spacers 28c are disposed on both sides of the polysilicon electrode. Of course, the electrode can also be composed of other semiconductor materials or metals. A third source / drain doping region 16c is disposed in the substrate 10 on one side of the third gate electrode 14c, and a fourth source / drain doping region 16d is disposed in the substrate 10 on the other side of the third gate electrode 14c. A third metal silicide 18c covers and contacts the third source / drain doping region 16c, and a fourth metal silicide 18d covers and contacts the fourth source / drain doping region 16d. A third conductive plate 20c penetrates the third metal silicide 18c and contacts the third source / drain doping region 16c, and a fourth conductive plate 20d penetrates the fourth metal silicide 18d and contacts the fourth source / drain doping region 16d. In addition, third deep trench isolations A3 and fourth deep trench isolations A4 are disposed in the substrate 10 on both sides of the medium-voltage transistor T2 to define the active region where the medium-voltage transistor T2 is located in the substrate 10. The fin transistor T3 includes a fin structure 22 protruding from a second surface 10b of the substrate 10. A second gate electrode 14b is disposed on the fin structure 22, and two shallow trench isolations A5 are located on both sides of the fin structure 22. The second gate electrode 14b may include a polysilicon gate and a sidewall spacer 28b. The sidewall spacer 28b is disposed on both sides of the polysilicon gate. The polysilicon gate can also be replaced by a metal gate. A third gate dielectric layer 12b is disposed between the fin structure 22 and the second gate electrode 14b. A first epitaxial layer 24a and a second epitaxial layer 24b are respectively buried in the fin structure 22 on both sides of the second gate electrode 14b. Preferably, no metal silicide layer is disposed on the first epitaxial layer 24a and the second epitaxial layer 24b. A fifth conductive plate 20e and a sixth conductive plate 20f respectively contact the first epitaxial layer 24a and the second epitaxial layer 24b. The fifth conductive plate 20e and the sixth conductive plate 20f are preferably strip-shaped. In addition, the second surface 10b is lower than the third surface 10c, and the first surface 10a is lower than the third surface 10c. The depth of the shallow trench isolation A5 is less than the depth of the first deep trench isolation A1. The first conductive plate 20a, the second conductive plate 20b, the third conductive plate 20c, the fourth conductive plate 20d, the fifth conductive plate 20e, and the sixth conductive plate 20f are preferably metals, alloys, or metal silicides. Furthermore, the upper cover layer 26a, the upper cover layer 26c, and the upper cover layer 26b cover the upper surface of the first gate electrode 14a, the upper surface of the third gate electrode 14c, and the upper surface of the second gate electrode 14b, respectively. A first gate conductive plate 30a contacts the first gate electrode 14a and a second gate conductive plate 30c contacts the third gate electrode 14c. FIG. 2 shows a top view of the high-voltage transistor in FIG. 1. FIG. 3 shows a top view of the medium-voltage transistor in FIG. 1, where components having the same functions and positions in FIGS. 2 and 3 will use the component symbols in FIG. 1. Please refer to FIGS. 1 and 2 simultaneously. On the first source / drain doping region 16a of the high-voltage transistor T1, only the first conductive plate 20a penetrates the first metal silicide 18a, and no other conductive components penetrate the first metal silicide. The first conductive plate 20a directly contacts the first source / drain doping region 16a. And on the second source / drain doping region 16b of the high-voltage transistor T1, only the second conductive plate 20b penetrates the second metal silicide 18b, and no other conductive components penetrate the second metal silicide 18b. The second conductive plate 20b directly contacts the second source / drain doping region 16b. That is to say, the first source / drain doping region 16a is electrically connected to the outside only through the first conductive plate 20a, and the second source / drain doping region 16b is electrically connected to the outside only through the second conductive plate 20b. The first conductive plate 20a and the second conductive plate 20b are preferably strip-shaped. In FIG. 2, the first deep trench isolation A1 and the second deep trench isolation A2 are separated by a dashed line, but actually the first deep trench isolation A1 and the second deep trench isolation A2 are connected. In addition, as shown in FIG. 2, when viewed from the top view, a first direction D1 is parallel to the long side E1 of the first gate electrode 14a, a second direction D2 is parallel to the short side E2 of the first gate electrode 14a, and a third direction D3 is also parallel to the short side E2 of the first gate electrode 14a but opposite to the second direction D2. According to a preferred embodiment of the present invention, the shortest distance L1 between the first conductive plate 20a and the edge of the first metal silicide 18a along the first direction D1 is between 10 and 90 nanometers, the shortest distance L2 between the first conductive plate 20a and the edge of the first metal silicide 18a along the second direction D2 is between 10 and 90 nanometers, and the shortest distance L3 between the first conductive plate 20a and the first gate electrode along the third direction D3 is between 350 and 1050 nanometers. Taking the first gate electrode 14a as the axis of symmetry, the first conductive plate 20a and the second conductive plate 20b are symmetric, and the first metal silicide 18a and the second metal silicide 18b are symmetric. Therefore, the relative positions between the second conductive plate 20b and the second metal silicide 18b are the same as those between the first conductive plate 20a and the first metal silicide 18a, which will not be elaborated here. According to a preferred embodiment of the present invention, the numerical ranges of the shortest distance L1, the shortest distance L2, and the shortest distance L3 described above are particularly applicable to high-voltage transistors with 40 volts. If they are to be used in high-voltage transistors with other voltages, such as 8 volts or 12 volts, the numerical ranges of the shortest distance L1, the shortest distance L2, and the shortest distance L3 need to be readjusted. As shown in FIGS. 1 and 3, only the third conductive plate 20c penetrates the third metal silicide 18c on the third source / drain doping region 16c of the medium-voltage transistor T2, and no other conductive elements penetrate the third metal silicide 18c. Also, only the fourth conductive plate 20d penetrates the fourth metal silicide 18d on the fourth source / drain doping region 16d of the medium-voltage transistor T2, and no other conductive elements penetrate the fourth metal silicide 18d. That is to say, the third source / drain doping region 16c is only externally electrically connected through the third conductive plate 20c, and the fourth source / drain doping region 16d is only externally electrically connected through the fourth conductive plate 20d. The third conductive plate 20c and the fourth conductive plate 20d are preferably strip-shaped. In FIG. 3, the third deep trench isolation A3 and the fourth deep trench isolation A4 are separated by a dotted line, but actually the third deep trench isolation A3 and the fourth deep trench isolation A4 are connected. In addition, a fourth direction D4 is parallel to the long side E3 of the second gate electrode 14c, a fifth direction D5 is parallel to the short side E4 of the second gate electrode 14c, and a sixth direction D6 is also parallel to the short side E4 of the second gate electrode 14c but opposite to the fifth direction D5. According to a preferred embodiment of the present invention, the shortest distance L4 between the third conductive plate 20c along the fourth direction D4 and the edge of the third metal silicide 18c is between 5 and 55 nanometers, the shortest distance L5 between the third conductive plate 20c along the fifth direction D5 and the edge of the third metal silicide 18c is between 5 and 35 nanometers, and the shortest distance L6 between the third conductive plate 20c along the sixth direction D6 and the second gate electrode 14c is between 40 and 140 nanometers. Taking the second gate electrode 14c as the symmetry axis, the third conductive plate 20c and the fourth conductive plate 20d are symmetric, and the third metal silicide 18c and the fourth metal silicide 18d are symmetric. Therefore, the relative positions between the fourth conductive plate 20d and the fourth metal silicide 18d are the same as those between the third conductive plate 20c and the third metal silicide 18c, which will not be elaborated here. As shown in FIG. 1, the method for manufacturing a semiconductor device according to the present invention includes providing a substrate 10, the substrate 10 including a high-voltage region HV, a medium-voltage region MV, and a low-voltage region LV. Then, a first deep trench isolation A1 and a second deep trench isolation A2 are formed in the substrate 10 within the high-voltage region HV. Next, a high-voltage transistor T1 is formed in the high-voltage region HV, a medium-voltage transistor T2 is formed in the medium-voltage region MV, and a fin transistor T3 is disposed in the low-voltage region LV. The high-voltage transistor T1 includes a first gate dielectric layer 12a disposed on a first surface 10a of the substrate 10 and located between the first deep trench isolation A1 and the second deep trench isolation A2 and in contact with the first deep trench isolation A1 and the second deep trench isolation A2, a first gate electrode 14a disposed on the first gate dielectric layer 12a, a first source / drain doping region 16a disposed in the substrate 10 on one side of the first deep trench isolation A1 and the first source / drain doping region 16a in contact with the first deep trench isolation A1, a second source / drain doping region 16b disposed in the substrate 10 on one side of the second deep trench isolation A2 and the second source / drain doping region 16b in contact with the second deep trench isolation A2, a first metal silicide 18a covering and contacting the first source / drain doping region 16a, a second metal silicide 18b covering and contacting the second source / drain doping region 16b, a first conductive plate 20a penetrating the first metal silicide 18a and contacting the first source / drain doping region 16a, and a second conductive plate 20b penetrating the second metal silicide 18b and contacting the second source / drain doping region 16b. The medium piezoelectric crystal T2 includes a second gate dielectric layer 12c disposed on a third surface 10c of the substrate 10, a third gate electrode 14c disposed on the second gate dielectric layer 12c, a third source / drain doping region 16c disposed in the substrate 10 on one side of the third gate electrode 14c, a fourth source / drain doping region 16d disposed in the substrate 10 on the other side of the third gate electrode 14c, a third metal silicide 18c covering and contacting the third source / drain doping region 16c, a fourth metal silicide 18d covering and contacting the fourth source / drain doping region 16d, a third conductive plate 20c penetrating the third metal silicide 18c and contacting the third source / drain doping region 16c, and a fourth conductive plate 20d penetrating the fourth metal silicide 18d and contacting the fourth source / drain doping region 16d. The fin-shaped transistor T3 includes a fin-shaped structure 22 protruding from the second surface 10b of the substrate 10, a second gate electrode 14b disposed on the fin-shaped structure 22, and two shallow trench isolations A5 located on both sides of the fin-shaped structure 22. A third gate dielectric layer 12b is disposed between the fin-shaped structure 22 and the second gate electrode 14b. A first epitaxial layer 24a and a second epitaxial layer 24b are respectively buried in the fin-shaped structure 22 on both sides of the second gate electrode 14b. A fifth conductive plate 20e and a sixth conductive plate 20f respectively contact the first epitaxial layer 24a and the second epitaxial layer 24b. Thus, the semiconductor device 100 of the present invention is completed. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention. 10: Substrate 10a: First surface 10b: Second surface 10c: Third surface 12a: First gate dielectric layer 12b: Third gate dielectric layer 12c: Second gate dielectric layer 14a: First gate electrode 14b: Second gate electrode 14c: Third gate electrode 16a: First source / drain doped region 16b: Second source / drain doped region 16c: Third source / drain doped region 16d: Fourth source / drain doped region 18a: First metal silicide 18b: Second metal silicide 18c: Third metal silicide 18d: Fourth metal silicide 20a: First conductive plate 20b: Second conductive plate 20c: Third conductive plate 20d: Fourth conductive plate 20e: Fifth conductive plate 20f: Sixth conductive plate 22: Fin structure 24a: First epitaxial layer 24b: Second epitaxial layer 26a: Capping layer 26b: Capping layer 26c: Capping layer 28a: Sidewall 28b: Sidewall 28c: Sidewall 30a: First gate conductive plate 30c: Second gate conductive plate 100: Semiconductor device A1: First deep trench isolation A2: Second deep trench isolation A3: Third deep trench isolation A4: Fourth deep trench isolation A5: Shallow trench isolation D1: First direction D2: Second direction D3: Third direction D4: Fourth direction D5: Fifth direction D6: Sixth direction E1: Long side E2: Short side E3: Long side E4: Short side HV: High voltage region L1: Shortest distance L2: Shortest distance L3: Shortest distance L4: Shortest distance L5: Shortest distance L6: Shortest distance LV: Low voltage region MV: Medium voltage region T1: High voltage transistor T2: Medium voltage transistor T3: Fin transistor FIG. 1 is a semiconductor device according to a preferred embodiment of the present invention. FIG. 2 is a top view of the high voltage transistor in FIG. 1. FIG. 3 is a top view of the medium voltage transistor in FIG. 1. 14a: First gate electrode 16a: First source / drain doped region 16b: Second source / drain doped region 18a: First metal silicide 18b: Second metal silicide 20a: First conductive plate 20b: Second conductive plate 30a: First gate conductive plate A1: First deep trench isolation A2: Second deep trench isolation D1: First direction D2: Second direction D3: Third direction E1: Long side E2: Short side L1: Shortest distance L2: Shortest distance L3: Shortest distance T1: High-voltage transistor

Claims

1. A semiconductor device comprising: a substrate including a high-voltage region and a low-voltage region; a first deep trench isolation and a second deep trench isolation disposed in the substrate within the high-voltage region; a high-voltage transistor disposed in the high-voltage region, wherein the high-voltage transistor comprises: a first gate dielectric layer disposed on a first surface of the substrate, the first gate dielectric layer being located between and contacting the first deep trench isolation and the second deep trench isolation; a first gate electrode disposed on the first gate dielectric layer; a first source / drain doped region disposed in the substrate on one side of the first deep trench isolation and contacting the first deep trench isolation; a second source / drain doped region disposed in the substrate on one side of the second deep trench isolation and contacting the second deep trench isolation; and a first metal silicide covering and contacting the first source / drain doped region; A second metal silicide covers and contacts the second source / drain doped region; a first conductive plate penetrates the first metal silicide and contacts the first source / drain doped region, and one end of the first conductive plate is higher than one upper surface of the first metal silicide; and a second conductive plate penetrates the second metal silicide and contacts the second source / drain doped region, and one end of the second conductive plate is higher than one upper surface of the second metal silicide; a finned transistor is disposed in the low-voltage region, wherein the finned transistor comprises: a finned structure protruding from a second surface of the substrate; a second gate electrode disposed on the finned structure; and two shallow trench isolation sites on both sides of the finned structure.

2. The semiconductor device as claimed in claim 1, wherein only the first conductive plate penetrates the first metal silicide in the first source / drain doped region, and no other conductive element penetrates the first metal silicide.

3. The semiconductor device as claimed in claim 1, wherein a first direction is parallel to the long side of the first gate electrode, a second direction is parallel to the short side of the first gate electrode, and a third direction is parallel to the short side of the first gate electrode and opposite to the second direction.

4. The semiconductor element as claimed in claim 3, wherein the shortest distance between the first conductive plate along the first direction and the edge of the first metal silicide is between 10 and 90 nanometers.

5. The semiconductor element as claimed in claim 3, wherein the shortest distance between the first conductive plate along the second direction and the edge of the first metal silicide is between 10 and 90 nanometers.

6. The semiconductor element as claimed in claim 3, wherein the shortest distance between the first conductive plate along the third direction and the first gate electrode is between 350 and 1050 nanometers.

7. The semiconductor device as claimed in claim 1, wherein the depth of each of the shallow trench isolations is less than the depth of the first deep trench isolation.

8. The semiconductor device as claimed in claim 1, wherein neither the first source / drain doped region nor the second source / drain doped region contains an epitaxial layer.

9. The semiconductor element as claimed in claim 1, wherein the voltage of the high voltage transistor is 40 volts.

10. The semiconductor device as claimed in claim 1, further comprising a first epitaxial layer and a second epitaxial layer respectively embedded in the fin structure on both sides of the second gate electrode.

11. A method of fabricating a semiconductor device, comprising: providing a substrate, the substrate including a high-voltage region and a low-voltage region; forming a first deep trench isolation and a second deep trench isolation in the substrate within the high-voltage region; forming a high-voltage transistor in the high-voltage region, wherein the high-voltage transistor comprises: a first gate dielectric layer disposed on a first surface of the substrate and located between and in contact with the first deep trench isolation and the second deep trench isolation; a first gate electrode disposed on the first gate dielectric layer; a first source / drain doped region disposed in the substrate on one side of the first deep trench isolation and in contact with the first deep trench isolation; a second source / drain doped region disposed in the substrate on one side of the second deep trench isolation and in contact with the second deep trench isolation; and a first metal silicide covering and in contact with the first source / drain doped region; A second metal silicide covers and contacts the second source / drain doped region; a first conductive plate penetrates the first metal silicide and contacts the first source / drain doped region, and one end of the first conductive plate is higher than one upper surface of the first metal silicide; and a second conductive plate penetrates the second metal silicide and contacts the second source / drain doped region, and one end of the second conductive plate is higher than one upper surface of the second metal silicide; a fin-shaped transistor is formed in the low-voltage region, wherein the fin-shaped transistor comprises: a fin-shaped structure protruding from a second surface of the substrate; a second gate electrode disposed on the fin-shaped structure; and two shallow trench isolation sites on both sides of the fin-shaped structure.

12. A method for manufacturing a semiconductor element as claimed in claim 11, wherein only the first conductive plate penetrates the first metal silicide in the first source / drain doped region, and no other conductive element penetrates the first metal silicide.

13. A method of manufacturing a semiconductor device as claimed in claim 11, wherein a first direction is parallel to the long side of the first gate electrode, a second direction is parallel to the short side of the first gate electrode, and a third direction is parallel to the short side of the first gate electrode and opposite to the second direction.

14. A method of fabricating a semiconductor element as described in claim 13, wherein the shortest distance between the first conductive plate along the first direction and the edge of the first metal silicide is between 10 and 90 nanometers.

15. A method of fabricating a semiconductor element as described in claim 13, wherein the shortest distance between the first conductive plate along the second direction and the edge of the first metal silicide is between 10 and 90 nanometers.

16. A method of fabricating a semiconductor element as claimed in claim 13, wherein the shortest distance between the first conductive plate along the third direction and the first gate electrode is between 350 and 1050 nanometers.

17. A method of manufacturing a semiconductor element as claimed in claim 11, wherein the depth of each of the shallow trench isolations is less than the depth of the first deep trench isolation.

18. A method for fabricating a semiconductor device as claimed in claim 11, wherein neither the first source / drain doped region nor the second source / drain doped region contains an epitaxial layer.

19. A method for manufacturing a semiconductor element as described in claim 11, wherein the voltage of the high voltage transistor is 40 volts.

20. The method of fabricating a semiconductor device as described in claim 11, further comprising embedding a first epitaxial layer and a second epitaxial layer in the fin structure on both sides of the second gate electrode.

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