Method of calibrating output of ADC and ADC using the same

Abstract

According to the present disclosure, an analog-to-digital converter (ADC) is provided, the ADC including but not limited to: a digital-to-analog converter (DAC) configured to generate a positive input differential voltage and a negative input differential voltage; a comparator electrically connected to the DAC and configured to receive the positive input differential voltage to generate a first digital output value and receive the negative input differential voltage to generate a second digital output value; logic circuitry configured to receive the first digital output value and the second digital output value from the comparator to generate a digital quantization code based on half the sum of the first digital output value and the second digital output value; and a calibration circuitry configured to receive the digital quantization code from the logic circuitry and calibrate the output of the ADC based on the digital quantization code to eliminate bias error values.

Description

Method for calibrating the output of an analog-to-digital converter and analog-to-digital converter using the same The present disclosure relates to a method for calibrating the output of an analog-to-digital converter (ADC) and an ADC using the method. Ideally, an ADC converts an analog input voltage into digital output values ​​that perfectly represent the analog input voltage. For simplicity, the ADC shown in Figure 1 only has two bits, but real-world ADCs have more than two bits. As shown in Figure 1, assume that ADC 102 receives an analog input voltage 101 that increases over time and spans the entire dynamic range of ADC 102. Analog input voltage 101 is then converted into a corresponding set of digital output values ​​103 that increase in a step-like manner over time. Assuming ADC 102 is perfectly ideal, digital output signal 103 is perfectly proportional to analog input voltage 101. In practice, digital output signal 103 deviates from the expected value due to the ADC's inherent offset error voltage. This offset error must be corrected through a calibration mechanism to ensure the ADC operates as expected. FIG2 shows a comparison between an ADC under non-ideal conditions and an ideal ADC. Curve 201 shown in FIG2 is an ideal ADC with an ideal step. For example, if analog input value 101 is less than 0.5 volts (V), digital output signal 103 is 000; if the analog input value is between 0.5 and 1.5 volts, digital output signal 103 is 001, and so on. However, in reality, an uncalibrated ADC may follow an actual step 202 containing offset error, rather than the actual step of curve 201. If the ADC's curve 201 follows an ideal step, the step would begin at the ideal bias point 203. However, the ADC's actual step 202 will begin at the actual bias point 204 due to offset error voltage 205. Consequently, the ADC will not output the expected digital output signal 103. FIG3 shows the effect of an offset error voltage (eg, 205) on a comparator of an ADC (eg, 503 shown in FIG5). In an ideal ADC 301 with an ideal transfer curve (eg, 201), if the input voltage V in 303 is greater than the reference voltage V ref 304, then the digital output D of ADC i is a binary value of 1. Otherwise, the digital output D of the ideal ADC 301 is iThe binary value of is 0. However, in reality, the ADC 301 with an offset error voltage (eg, 205) will behave differently. For the ADC 302 with a transfer curve that takes a real step (eg, 202), if the input voltage V in 305 minus the bias error voltage (eg, 205) is greater than the reference voltage V ref 306, the digital output D of ADC 302 i is a binary value of 1. Otherwise, the digital output D of ADC 302 is i The binary value of is 0. As shown in the examples of Figures 2 and 3, ADCs in actual practice often have an offset error voltage (e.g., 205), which causes the digital output values ​​of the ADC to deviate from the expected ideal values. Therefore, a mechanism for calibrating the ADC output by eliminating or minimizing the offset error voltage will enhance the performance of non-ideal ADCs. Therefore, to address the above challenges, the present disclosure relates to a method for calibrating the output of an analog-to-digital converter (ADC) and an ADC using the same. In one aspect, the present disclosure relates to a method for calibrating an output of an ADC. The method includes, but is not limited to: generating a positive input differential voltage by a digital-to-analog converter (DAC); receiving the positive input differential voltage by a comparator to generate a first digital output value; generating a negative input differential voltage having the same magnitude as the positive input differential voltage by the DAC; receiving the negative input differential voltage by the comparator to generate a second digital output value; determining a digital quantization code by a logic circuit based on half the sum of the first digital output value and the second digital output value; and calibrating the output of the ADC by a calibration circuit using the digital quantization code to eliminate an offset error value. In another aspect, the present disclosure relates to an ADC, comprising, but not limited to: a digital-to-analog converter (DAC) configured to generate a positive input differential voltage and a negative input differential voltage; a comparator electrically connected to the DAC and configured to receive the positive input differential voltage to generate a first digital output value and receive the negative input differential voltage to generate a second digital output value; a logic circuit configured to receive the first digital output value and the second digital output value from the comparator to generate a digital quantization code based on half the sum of the first digital output value and the second digital output value; and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate the output of the ADC based on the digital quantization code to eliminate an offset error value. In order to make the aforementioned features and advantages of the present disclosure easier to understand, exemplary embodiments are described in detail below in conjunction with the figures. It should be understood that both the aforementioned general description and the following detailed description are exemplary and are intended to further illustrate the claimed present disclosure. However, it should be understood that this summary of the invention may not contain all aspects and embodiments of the present disclosure and is therefore not intended to be limiting or restrictive in any way. In addition, the present disclosure will include improvements and modifications that are obvious to those skilled in the art. Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts. As previously described, the performance of a real ADC can be improved by a calibration mechanism. One concept for achieving the calibration mechanism disclosed herein is shown in FIG4 . By applying a differential analog input voltage (differential input voltage or ΔV) to a real ADC 401 , the output voltage D out is ΔV plus the offset error voltage V offset The expected digital equivalent of . This can be achieved by eliminating V offset To improve the performance of the real ADC 401. The inventive concept of the present disclosure is shown in FIG5 , which provides an output of ADC 501 (D outA or D outB ) is a mechanism for calibration. At the first time period T501, a positive (+) ΔV is provided to the ADC 501, and the ADC 501 converts the +ΔV into a digital value D outA . Digital value D outA Including digital representation of positive ΔV (D outA ) plus the offset error value (V offset At a second time period T502 (which may be before or after the first time period T501), a negative (-) ΔV is provided to the (same) ADC 501, which converts the -ΔV into a digital value D outB . Digital value D outB Including digital representation of -ΔV (D outB ) plus the offset error value (V offset ). outA With D outB After adding, D outA With D outB The sum is V offset = twice the size of D, and +ΔV and -ΔV cancel each other out. outA With D outB Adding to produce the sum to know V offset , and then the sum (D outA + D outB ) divided by 2 to derive V offset , V offset In digital form and V offset Quantization code. To achieve the concepts of the present invention as described above and shown in FIG5 , the present disclosure provides an ADC having a mechanism for calibrating the ADC output, as shown in FIG6 , and a method for calibrating the ADC output, as shown in FIG7 . As shown in FIG6 , the present disclosure provides an ADC 600 having a calibration mechanism that eliminates or minimizes offset error voltage by calibrating the ADC output. ADC 600 includes, but is not limited to, a sample and hold (S / H) circuit 601, a digital-to-analog converter (DAC) 602, a comparator 603, a successive approximation register (SAR) digital logic circuit 604, and a SAR calibration circuit 605. Since the operating principles of an ADC under normal operation are currently known, they need not be explained further. However, the operating principles for calibrating the output (ADC_OUT) of ADC 600 are described below. At a first time period (eg, T501), the DAC 602 will generate a positive input differential voltage (eg, +ΔV), which is received by the comparator 603 to generate a first digital output value (eg, D outAAt a second time period (eg, T502), the DAC 602 will generate a negative value (eg, -ΔV), which is received by the comparator 603 to generate a second digital output value (eg, D outB ). It should be noted that the functions performed during the first time period and the functions performed during the second time period are interchangeable. -ΔV can ideally have the same magnitude as +ΔV. For example, if +ΔV is 1.8 volts, then -ΔV is -1.8 volts. Based on the first digital output value and the second digital output value, the SAR logic circuit 604 can determine V by calculating the sum derived by adding the first digital output value and the second digital output value. offset Quantization code. Then divide the sum by 2 to get V offset Quantization code. In other words, V offset The quantization code is half of the sum of the first digital output value and the second digital output value. After obtaining the quantization code, the SAR calibration circuit 605 can use the digital V offset The quantization code is used to calibrate the output of the ADC 600 (ADC_OUT), for example, by subtracting V from the raw output of the ADC obtained before calibration. offset Quantization code to eliminate bias error value (V offset ) or make the offset error value (V offset ) minimized. Referring to the method for calibrating the output of an ADC shown in FIG7 , in step S701, the ADC (e.g., 600) will use the DAC (e.g., 602) to generate a positive input differential voltage (e.g., +ΔV). In step S702, the comparator (e.g., 703) will receive the positive input differential voltage to generate a first digital output value (e.g., D outA In step S703, the ADC will use the DAC to generate a negative input differential voltage (e.g., -ΔV) of the same magnitude as the positive input differential voltage. In step S704, the comparator will receive the negative input differential voltage to generate a second digital output value (e.g., D outB In step S705, the SAR logic circuit (e.g., 604) calculates a digital quantization code based on half the sum of the first digital output value and the second digital output value. In step S706, the calibration circuit (e.g., 605) uses the digital quantization code to calibrate the ADC output to eliminate the offset error value (e.g., V offset ). To further expand on the concepts of the present invention, Figures 8 and 9 illustrate in greater detail the operation of the circuitry of a DAC (e.g., 602) and a comparator (e.g., 603). First, the structure of the DAC's capacitor array will be described. Referring to Figure 8 , the DAC includes a capacitor array comprising a first block 830 connected to an input switch 801 and a second block 831 connected to a comparator 603. First block 830 may include a first capacitor 841 and a second capacitor 842. First capacitor 841 has one terminal to be set to a first voltage (e.g., Vrep) and another terminal connected to the input switch 801 and the first terminal of the comparator 603. Second capacitor 842 has one terminal to be set to a second voltage (e.g., Vren) and another terminal connected to the input switch 801 and the second terminal of the comparator 603. Each row of the second block 831 includes a pair of capacitors, one of which is connected to the first terminal of the comparator 603 and the other to the second terminal of the comparator 603. Each row of the second block is connected in parallel to the other rows and the first block 830. The capacitors of the second block 831 closer to the input switch 801 have a larger capacitance than the capacitors of the second block 831 closer to the comparator 603. For example, each of the capacitors 851 in the first row has a value of 1C, each of the capacitors 852 in the second row has a value of 2C, and each of the capacitors 853 in the third row has a value of 4C. Each of the first capacitor 841 and the second capacitor 842 in the first block 830 may also have a value of 4C. For all capacitors in the second block 831, one of the terminals is connected to the first or second input of the comparator 603 shown in FIG. 8 , and the other terminal is connected to a bias voltage of the common voltage (Vcm). The bias voltage of the second block 831 does not change during the operations of FIG. 8 and FIG. 9 described below. At time period T801, the input switch 801 of the DAC (e.g., 602) is connected to the capacitor array in a closed state. At time period T802, the SAR logic circuit 604 controls the input switch 801 to transition from the closed state to a floating state relative to the capacitor array to disconnect from the first block 830. At time period T803, when the switch is in the floating state, the SAR logic circuit 604 sets one of the terminals of the first capacitor 841 to a first voltage (Vrep) and one of the terminals of the second capacitor 842 to a second voltage (Vren) in the manner shown in FIG8 . ΔV is the difference between the first voltage and the second voltage. For example, if the first voltage is +1.8 volts and the second voltage is 0 volts, ΔV is positive 1.8 volts. After generating +ΔV, the first digital output value (e.g., D outA ). The first digital output value at this time will include the value of +ΔV and the offset error value. 9 , at time period T901, the input switch 801 of the DAC (e.g., 602) is connected to the capacitor array in a closed state. At time period T902, the SAR logic circuit 604 controls the input switch 801 to switch from the closed state to a floating state relative to the capacitor array to disconnect from the first block 830. At time period T903, when the switch is in the floating state, the SAR logic circuit 604 sets one of the terminals of the first capacitor 841 to the second voltage (Vren) and sets one of the terminals of the second capacitor 842 to the first voltage (Vrep). ΔV is the difference between the second voltage and the first voltage. For example, if the second voltage is set to 0 volts for the first capacitor 841 and the first voltage is set to 1.8 volts for the second capacitor, ΔV is negative 1.8 volts. After generating -ΔV, the second digital output value (e.g., D outB ). The second digital output value includes the magnitude of -ΔV and the offset error value. It should be noted that the functions executed during T801 to T803 are interchangeable with the functions executed during T901 to T903. Once the first digital output value and the second digital output value are determined, the SAR logic circuit 604 calculates V based on the sum of the first digital output value and the second digital output value divided by 2. offset Quantization code. Then the SAR calibration circuit 605 receives V offset quantization code, the SAR calibration circuit 605 can use V offsetThe quantization code is used to calibrate the ADC output value (ADC_OUT), for example, by using V offset The quantized code is subtracted from the original converted value. In summary, the present disclosure is suitable for use in ADCs and can minimize or eliminate the error offset voltage inherent in the ADC, so that the ADC can convert an analog signal into a digital signal that is equal to or very similar to a desired value. None of the elements, actions or instructions used in the detailed description of the embodiments disclosed in this application should be considered to be absolutely important or essential to the present disclosure unless so explicitly stated. In addition, each of the indefinite articles "a and an" used herein may include more than one item. If only one item is intended to be included, the term "single" or similar language will be used. In addition, the term "any of..." used herein after a series of multiple items and / or multiple item categories is intended to include "any of" the items and / or item categories, "any combination of" the items and / or item categories, "any number of" the items and / or item categories, and / or "any combination of" the items and / or item categories, the multiple items and / or multiple item categories being individual or combined with other items and / or other item categories. In addition, the term "group" used herein is intended to include any number (including zero) of items. In addition, the term "number" used herein is intended to include any number (including zero). It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the following claims and their equivalents. 1C, 2C, 4C: Values ​​101: Analog input voltage / Analog input value 102, 302, 501, 600: Analog-to-digital converter (ADC) 103: Digital output value / Digital output signal 201: Curve 202: Actual step 203: Ideal bias point 204: Actual bias point 205: Offset error voltage 301: Ideal ADC / ADC 303, 305, V in : Input voltage 304, 306, V ref: Reference voltage 401: Real ADC 601: Sample and hold (S / H) circuit 602: Digital to analog converter (DAC) 603: Comparator 604: Successive approximation register (SAR) digital logic circuit / SAR logic circuit 605: SAR calibration circuit / calibration circuit 801: Input switch 830: First block 831: Second block 841: First capacitor 842: Second capacitor 851, 852, 853: Capacitor ADC_OUT: Output D i :Digital output D out :Output voltage D outA :Output / digital value / first digital output value D outB : Output / digital value / second digital output value S701, S702, S703, S704, S705, S706: Step T501: First time period T502: Second time period T801, T802, T803, T901, T902, T903: Time period Vcm: Common voltage V offset :Offset error voltage Vrep:First voltage Vren:Second voltage ΔV:Differential ratiometric input voltage / differential input voltage The accompanying drawings are included herein to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to illustrate the principles of the present disclosure. FIG. 1 illustrates the operation of an ADC. FIG. 2 illustrates a typical ADC transfer curve for an ADC with a bias error. FIG. 3 illustrates the effect of a bias error value on a comparator located within the ADC. FIG. 4 illustrates an output code of an ADC with a bias error value. FIG. 5 is a hardware block diagram of an ADC according to an exemplary embodiment of the present disclosure. FIG. 6 is a flow chart illustrating a method for calibrating the output of an ADC according to an exemplary embodiment of the present disclosure. FIG. 7 illustrates a mechanism for obtaining a quantization code for a bias error value according to an exemplary embodiment of the present disclosure. FIG. 8 illustrates the operating principle of a circuit for generating a positive input differential voltage according to an exemplary embodiment of the present disclosure. FIG. 9 illustrates the operating principle of a circuit for generating a negative input differential voltage according to an exemplary embodiment of the present disclosure. 600: Analog to Digital Converter (ADC) 601: Sample and hold (S / H) circuit 602: Digital to Analog Converter (DAC) 603: Comparator 604: Successive Approximation Register (SAR) digital logic circuit / SAR logic circuit 605:SAR calibration circuit / calibration circuit ADC_OUT: output

Claims

1. A method for calibrating the output of an analog-to-digital converter (ADC), the method comprising: A positive input differential voltage is generated by a digital-to-analog converter (DAC); The comparator receives the positive input differential voltage to generate a first digital output value; The digital-to-analog converter generates a negative input differential voltage having the same magnitude as the positive input differential voltage; the comparator receives the negative input differential voltage to generate a second digital output value; logic circuitry determines a digital quantization code based on half the sum of the first digital output value and the second digital output value; and calibration circuitry uses the digital quantization code to calibrate the output of the analog-to-digital converter to eliminate bias error values, wherein generating the positive input differential voltage by the digital-to-analog converter includes: the logic circuitry controlling the input switch of the digital-to-analog converter to open from a closed state to a floating state; The logic circuit sets a first capacitor in the capacitor array of the digital-to-analog converter to a first voltage, wherein the first capacitor is connected to a first terminal of the comparator; and the logic circuit sets a second capacitor in the capacitor array of the digital-to-analog converter to a second voltage smaller than the first voltage to generate the positive input differential voltage, wherein the positive input differential voltage is the difference between the first voltage and the second voltage, wherein the second capacitor is connected to a second terminal of the comparator.

2. The method of claim 1, wherein generating the negative input differential voltage by the digital-to-analog converter comprises: The logic circuit controls the input switch of the digital-to-analog converter to open from the closed state to the floating state; The logic circuit sets the first capacitor in the capacitor array of the digital-to-analog converter to the second voltage, wherein the first capacitor is connected to the first terminal of the comparator; and the logic circuit sets the second capacitor in the capacitor array of the digital-to-analog converter to the first voltage to generate the negative input differential voltage, which is the difference between the second voltage and the first voltage.

3. The method as described in claim 2, wherein receiving the positive input differential voltage by the comparator to generate the first digital output value comprises: The comparator receives the positive input differential voltage to generate a first digital output value that includes the positive input differential voltage and the bias error value.

4. The method as described in claim 3, wherein receiving the negative input differential voltage by the comparator to generate the second digital output value comprises: The comparator receives the negative input differential voltage to generate a second digital output value that includes the negative input differential voltage and the bias error value.

5. The method of claim 1, wherein the capacitor array includes a first block connected to the input switch and a second block connected to the comparator, the first block including the first capacitor and the second capacitor.

6. The method of claim 5, wherein the first capacitor includes a first terminal set to the first voltage and a second terminal connected to the first terminal of the input switch and the comparator.

7. The method of claim 5, wherein the second capacitor includes a third terminal set to the second voltage and a fourth terminal connected to the second terminal of the input switch and the comparator.

8. The method of claim 5, wherein when the first capacitor in the capacitor array of the digital-to-analog converter is set to the first voltage by the logic circuit, and when the second capacitor in the capacitor array of the digital-to-analog converter is set to the second voltage by the logic circuit, the bias voltage of the plurality of capacitors in the second block does not change.

9. The method as described in claim 5, wherein the plurality of capacitors in the second block closer to the input switch have a larger capacitance value than the plurality of capacitors in the second block closer to the comparator.

10. An analog-to-digital converter (ADC) comprising: A digital-to-analog converter (DAC) is configured to generate a positive input differential voltage and a negative input differential voltage. A comparator, electrically connected to the DAC and configured to receive the positive input differential voltage to generate a first digital output value and receive the negative input differential voltage to generate a second digital output value. Logic circuitry is configured to receive the first and second digital output values ​​from the comparator to generate a digital quantization code based on half the sum of the first and second digital output values. A calibration circuit is configured to receive the digital quantization code from the logic circuitry and calibrate the output of the DAC based on the digital quantization code to eliminate bias error values. The DAC includes an input switch and a capacitor array, the capacitor array including a first capacitor and a second capacitor. The DAC generates the positive input differential voltage by configuring the logic circuitry to open the input switch of the DAC from a closed state to a floating state. The first capacitor in the capacitor array of the digital-to-analog converter is set to a first voltage, wherein the first capacitor is connected to a first terminal of the comparator, and the second capacitor in the capacitor array of the digital-to-analog converter is set to a second voltage smaller than the first voltage to generate the positive input differential voltage, wherein the positive input differential voltage is the difference between the first voltage and the second voltage, wherein the second capacitor is connected to a second terminal of the comparator.

11. The analog-to-digital converter of claim 10, wherein the digital-to-analog converter generates the negative input differential voltage by configuring the logic circuitry to perform the following operations: opening the input switch of the digital-to-analog converter from the closed state to the floating state; setting the first capacitor in the capacitor array of the digital-to-analog converter to the second voltage, wherein the first capacitor is connected to the first terminal of the comparator; and setting the second capacitor in the capacitor array of the digital-to-analog converter to the first voltage to generate the negative input differential voltage, the negative input differential voltage being the difference between the second voltage and the first voltage.

12. The analog-to-digital converter as claimed in claim 11, wherein the comparator is configured to receive the positive input differential voltage to produce the first digital output value, comprising: The comparator is configured to receive the positive input differential voltage to generate a first digital output value that includes the positive input differential voltage and the bias error value.

13. The analog-to-digital converter as claimed in claim 12, wherein the comparator is configured to receive the negative input differential voltage to produce the second digital output value, comprising: The comparator is configured to receive the negative input differential voltage to generate a second digital output value that includes the negative input differential voltage and the bias error value.

14. The analog-to-digital converter as claimed in claim 10, wherein the capacitor array includes a first block connected to the input switch and a second block connected to the comparator, the first block including the first capacitor and the second capacitor.

15. The analog-to-digital converter as claimed in claim 14, wherein the first capacitor includes a first terminal set to the first voltage and a second terminal connected to the first terminal of the input switch and the comparator.

16. The analog-to-digital converter as claimed in claim 14, wherein the second capacitor includes a third terminal set to the second voltage and a fourth terminal connected to the second terminal of the input switch and the comparator.

17. The analog-to-digital converter as claimed in claim 14, wherein the bias voltage of the plurality of capacitors in the second block does not change when the logic circuit sets the first capacitor in the capacitor array of the digital-to-analog converter to the first voltage, and when the logic circuit sets the second capacitor in the capacitor array of the digital-to-analog converter to the second voltage.

18. The analog-to-digital converter as claimed in claim 14, wherein a plurality of capacitors in the second block closer to the input switch have a larger capacitance value than a plurality of capacitors in the second block closer to the comparator.

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