Semiconductor structure and method of forming the same

Abstract

A method for forming a semiconductor structure and the semiconductor structure are described. The method includes patterning a substrate to form a first opening and a second opening, the substrate including an n-type transistor and a p-type transistor, the first opening being on the n-type transistor and the second opening being on the p-type transistor. The substrate is pre-cleaned. A molybdenum silicon dioxide (MoSi) layer is deposited on one or more of the p-type and n-type transistors. A titanium silicon dioxide (TiSi) layer is formed on the n-type and p-type transistors. A capping layer may be formed on the TiSi layer. This method can be an integration method performed in a processing chamber without disrupting the vacuum.

Description

Contact Resistance Reduction by Integration of Molybdenum and Titanium Embodiments of the present disclosure relate to the field of semiconductor devices and semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a method of reducing contact resistance of NMOS and PMOS by integrating a molybdenum process with titanium. Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single wafer. During the evolution of integrated circuits, the functional density (i.e., the number of interconnected components per unit wafer area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. Transistors are key components of most integrated circuits. Since the drive current and thus the speed of a transistor are proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Thus, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting transistor goals of having the maximum drive current and the minimum size. FinFETs are characterized by a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the footprint of the transistor, and finFETs are now applied in many integrated circuits. However, finFETs also have their own drawbacks. As the feature sizes of transistor devices continue to shrink to achieve greater circuit density and higher performance, it is necessary to improve the transistor device structure and reduce the contact resistance. Examples of transistor device structures include planar structures, fin field-effect transistor (finFET) structures, and gate all around (GAA) structures. The performance of a logic gate is related to the characteristics of the materials used and the thickness and area of the structural layers. However, challenges have arisen as some gate characteristics are adjusted to accommodate device scaling. As we enter advanced nodes below the 2-nanometer node, it is desirable to improve the speed and drive current of the device by reducing the contact resistance. Therefore, improved methods of reducing contact resistance are needed. One or more embodiments of the present disclosure are directed to a method of forming a semiconductor structure. The method includes: depositing a molybdenum silicide (MoSi) layer on one or more of the p-type transistors and n-type transistors of a substrate, the substrate including n-type transistors and p-type transistors and having a first opening over the n-type transistors and a second opening over the p-type transistors; optionally, in hydrogen (H 2)Anneal the substrate in situ in an atmosphere; form a titanium silicide (TiSi) layer on the n-type transistor and the p-type transistor; and form a capping layer on the titanium silicide (TiSi) layer. Another embodiment of the present disclosure is directed to a method of forming a semiconductor structure. In one or more embodiments, the method includes: pre-cleaning a substrate that includes an n-type transistor and a p-type transistor, a first opening over the n-type transistor, and a second opening over the p-type transistor; depositing a molybdenum silicide (MoSi) layer on the p-type transistor and the n-type transistor; optionally, annealing the substrate in a hydrogen (H 2 ) atmosphere in situ; forming a titanium silicide (TiSi) layer on the molybdenum silicide (MoSi) layer; forming a capping layer on the titanium silicide (TiSi) layer; and depositing a gap filling material in the first opening and the second opening. Other embodiments of the present disclosure are directed to a semiconductor structure. The semiconductor structure includes: an n-type transistor and a p-type transistor; a molybdenum silicide (MoSi) layer on one or more of the p-type transistor and the n-type transistor; a titanium silicide (TiSi) layer on the p-type transistor and the n-type transistor; a capping layer on the titanium silicide (TiSi) layer; and a gap filling material. Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways. As used herein, the term "about" means approximate or close, and in the context of the recited numerical values or ranges, "about" means a variation of ±15% or less of that numerical value. For example, values that differ by ±14%, ±10%, ±5%, ±2%, or ±1% will satisfy the definition of "about". As used in this specification and the appended claims, the term "substrate" or "wafer" refers to the surface or a portion of the surface on which a process acts. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, a reference to a substrate may refer only to a portion of the substrate. In addition, a reference to depositing on a substrate may refer to a bare substrate or a substrate having one or more films or features deposited or formed thereon. In addition, as used herein, the term "substrate" refers to any substrate or the surface of a material formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials, such as metals, metal nitrides, metal alloys, dielectric materials, other conductive materials, or combinations of the foregoing. In some embodiments, the substrate includes silicon (Si), ruthenium (Ru), cobalt (Co), tungsten (W), molybdenum (Mo), silicon phosphide (SiP), titanium silicon (TiSi), titanium nitride (TiN), titanium aluminide (TiAl), silicon germanium (SiGe), silicon germanium boron (SiGeB), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ) or combinations of the foregoing. The substrate includes, but is not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any film processing step disclosed can also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlying layer as referred to in the context. As used in this specification and the appended claims, the term "selectively" refers to a process that acts on a first surface with an effect greater than that on another second surface. Such a process will be described as acting "selectively" on the first surface relative to the second surface. The term "relative to" used in this sense does not mean a physical orientation in which one surface is located above another surface, but rather a relationship of the thermodynamic or kinetic properties of a chemical reaction of one surface relative to another surface. According to one or more embodiments, the term "on" with respect to a film or film layer includes a film or layer directly located on a surface such as a substrate surface, and a film or layer that serves as one or more underlying layers between the film or layer and a surface such as a substrate surface. Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on" refers to a layer or film in contact with a surface (e.g., the substrate surface) without an intermediate layer. Thus, the phrase "layer directly on the substrate surface" refers to a layer in direct contact with the substrate surface without an intermediate layer. As used herein, the term "substrate surface" refers to any substrate surface on which a layer can be formed. The substrate surface can have one or more features formed therein, one or more layers formed thereon, and combinations of the foregoing. The shape of the feature can be any suitable shape, including but not limited to peaks, grooves, and cylindrical vias. In this sense, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include but are not limited to grooves having a top, two sidewalls, and a bottom, peaks having a top and two sidewalls extending upward from the surface, and vias having sidewalls extending downward from the surface and having an open bottom. As used herein, the term "processing chamber" includes the portion of the processing chamber adjacent to the substrate surface, but does not include the entire internal volume of the processing chamber. For example, in a spatially separated section of the processing chamber, one or more reactive compounds are purged from the portion of the processing chamber adjacent to the substrate surface through any suitable technique, including but not limited to moving the substrate through a gas curtain to a portion or section of the processing chamber that is free or substantially free of reactive compounds. As used herein, the term "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate surface is sequentially exposed to two or more reactive compounds introduced into the reaction zone of the processing chamber. The sequential exposure of the reactive gases prevents or minimizes gas-phase reactions between the reactive gases. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adsorb onto and / or react on the substrate surface. In a spatial ALD process, different portions of the substrate surface or the material on the substrate surface are simultaneously exposed to two or more reactive compounds such that any given point on the substrate is not substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, those skilled in the art will understand that the term "substantially" as used in this sense means that due to diffusion, a small portion of the substrate may be simultaneously exposed to multiple reactive gases, and the simultaneous exposure is not intentional. In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay period, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or remove any residual reactive compounds or by-products from the reaction zone. Alternatively, the purge gas can flow continuously throughout the deposition process such that only the purge gas flows during the time delay periods between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsing compound A, the purge gas, compound B, and the purge gas is one cycle. The cycle can start with compound A or compound B and continue in their respective cycle sequences until a film of the desired thickness is obtained. In one or more embodiments, the time-domain ALD process can be performed with more than two reactive compounds in a predetermined sequence. In one aspect of a spatial ALD process, a first reactive gas and a second reactive gas are simultaneously delivered to the reaction zone but are separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery apparatus such that any given point on the substrate is exposed to the first reactive gas and the second reactive gas. In one or more embodiments, the spatial ALD process can be performed with more than two reactive compounds in a predetermined sequence. In some embodiments, the substrate surface is substantially sequentially exposed to a first reactive compound and a second reactive compound. As used throughout the specification, "substantially sequentially" means that most of the duration of the exposure to the first reactive compound does not overlap with the exposure to the second reactive compound, but there may be some overlap. As used herein, the term "chemical vapor deposition" refers to exposing at least one reactive compound to deposit a material layer on a substrate surface. In some embodiments, a chemical vapor deposition (CVD) process includes mixing two or more reactive compounds in a processing chamber to allow gas-phase reactions and deposition of the reactive compounds. In some embodiments, a CVD process includes simultaneously exposing a substrate surface to two or more reactive compounds. In some embodiments, a CVD process includes continuously exposing a substrate surface to a first reactive compound and intermittently exposing it to a second reactive compound. In some embodiments, the substrate surface undergoes a CVD reaction to deposit a film of a predetermined thickness. In a CVD process, a film can be deposited in a single exposure to a mixture of reactive compounds, or can be deposited by multiple exposures to a mixture of reactive compounds with purging in between. In some embodiments, the substrate surface is substantially simultaneously exposed to a first reactive compound and a second reactive compound. As used throughout the specification, "substantially simultaneous" means that the majority of the duration of exposure of the first reactive compound overlaps with the exposure of the second reactive compound. As used herein, the term "purge" includes any suitable purge process for removing unreacted precursors, reaction products, and by-products from the process area. Suitable purge processes include moving the substrate through a gas curtain to a portion or section of the processing area that is free or substantially free of reactants. In one or more embodiments, purging the processing chamber includes applying a vacuum. In some embodiments, purging the processing area includes flowing a purge gas over the substrate. In some embodiments, the purge process includes flowing an inert gas. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N 2 ), helium (He), and argon (Ar). In some embodiments, prior to exposing the substrate to the second reactive compound, the first reactive compound is purged from the reaction chamber for a duration in the range of 0.1 seconds to 30 seconds, 0.1 seconds to 10 seconds, 0.1 seconds to 5 seconds, 0.5 seconds to 30 seconds, 0.5 seconds to 10 seconds, 0.5 seconds to 5 seconds, 1 second to 30 seconds, 1 second to 10 seconds, 1 second to 5 seconds, 5 seconds to 30 seconds, 5 seconds to 10 seconds, or 10 seconds to 30 seconds. Plasma enhanced chemical vapor deposition (PECVD) is widely used for depositing thin films due to cost efficiency and the diversity of film properties. For example, in a PECVD process, a hydrocarbon source, such as a gaseous hydrocarbon already entrained in a carrier gas or a liquid phase hydrocarbon vapor, is introduced into the PECVD chamber. A plasma-initiated gas (typically helium) is also introduced into the chamber. Subsequently, a plasma is initiated in the chamber to generate excited CH-radicals. The excited CH-radicals chemically bond to the surface of the substrate located within the chamber, forming the desired film thereon. The embodiments described herein with reference to the PECVD process can be implemented using any suitable thin film deposition system. Any device description herein is and should not be construed or interpreted as limiting the scope of the embodiments described herein. As used herein, the term "liner" or "barrier layer" refers to a layer that is conformally formed along at least a portion of the sidewalls and / or the lower surface of an opening such that, prior to deposition of the layer, the majority of the opening remains unfilled after deposition of the layer. The liner can be formed along the entire sidewall and lower surface of the opening. The liner can be formed by any process known to those skilled in the art. In some embodiments, the liner includes a metal nitride, a PVD metal, or a combination of the foregoing. In one or more embodiments, a "liner" or "barrier layer" can also be selectively formed at the bottom of a structure. A transistor is a circuit component or element that is typically formed on a semiconductor device. Depending on the circuit design, many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other elements. A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage of the insulated gate determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used to amplify or convert electronic signals. Generally, a transistor includes a gate formed between a source and a drain region. The source and drain regions may include doped regions of a substrate and may exhibit a doping profile suitable for a particular application. The gate is located above the channel region and may include a gate dielectric interposed between the gate electrode and the channel region in the substrate. As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of an FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which is the terminal that modulates the channel conductivity. It is known that the current entering the channel at the source (S) is referred to as I S , and the current entering the channel at the drain (D) is referred to as I D . The drain-to-source voltage is referred to as V DS . By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ) can be controlled. A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage of the insulated gate determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used to amplify or convert electronic signals. The MOSFET is based on the modulation of the charge concentration by a metal-oxide-semiconductor (MOS) capacitor between the body electrode and the gate electrode located above the body, and is insulated from all other device regions through the gate dielectric layer. Compared with the MOS capacitor, the MOSFET includes two additional terminals (source and drain), each terminal connected to a single highly doped region separated by the body region. These regions can be p-type or n-type, but they are both of the same type and are of the type opposite to the body region. The source and drain (different from the body) are highly doped, as indicated by the "+" sign after the doping type. If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions, and the body is a p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions, and the body is an n region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) flowing through the channel; similarly, the drain is where the charge carriers leave the channel. Embodiments of the present disclosure provide a semiconductor structure and a method of forming the semiconductor structure. To improve the speed and drive current of devices with advanced nodes below 2 nanometer nodes, it is necessary to reduce the contact resistance. In one or more embodiments, the integration of molybdenum and titanium presents the benefit of a reduced contact resistance (R c ). Surprisingly, such a reduction is observed in the NMOS contact, even though molybdenum (Mo) is regarded as a p-type metal and the contact resistance is very high if only molybdenum is used in the NMOS contact. Therefore, in one or more embodiments, the performance of the NMOS is particularly unexpected. Embodiments of the present disclosure are described through diagrams that show the processes of forming NMOS and PMOS. FIG. 1 shows a process flowchart of a method 10 of forming a semiconductor structure. FIG. 1 shows a method of forming any semiconductor structure of one or more embodiments shown in FIGS. 2A to 2E. FIG. 3 shows a process flowchart of a method 50 of forming a semiconductor structure. FIG. 3 shows a method of forming any semiconductor structure of one or more embodiments shown in FIGS. 4A to 4E. Referring to FIG. 1, in one or more embodiments, a method 10 of forming a semiconductor structure includes pre-cleaning a substrate in operation 12. The substrate can be pre-cleaned by any suitable method known to those skilled in the art. In operation 14, a molybdenum silicide (MoSi) layer is deposited on the p-type transistor. In operation 16, the method 10 optionally includes in-situ annealing of the transistor in a hydrogen (H 2 ) atmosphere. In operation 18, the method 10 includes forming a titanium silicide (TiSi) layer on the n-type transistor and the p-type transistor. In operation 20, the method 10 includes forming a capping layer on the n-type transistor and the p-type transistor. In operation 22, the method 10 optionally includes annealing the semiconductor structure. In operation 24, the method 10 optionally includes gap filling. In one or more embodiments not shown, the substrate can be patterned to form at least one of a first opening 106 and a second opening 108. In one or more embodiments, patterning the substrate includes using one or more patterning techniques known to those of ordinary skill in the field of microelectronic device manufacturing. In some embodiments, a semiconductor structure 100 is provided and patterning is not required to form the semiconductor structure 100. Referring to FIGS. 1 and 2A-2E, in operation 12, the method 10 includes pre-cleaning the substrate. In one or more embodiments, maintaining the pre-cleaning process under vacuum ensures that no oxides are introduced / formed on the substrate surface during the method. In some embodiments, pre-cleaning the substrate (or the substrate surface) can remove oxides from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, cleaning the surface forms a surface that is substantially free of oxides. The term "substantially free of oxides" as used in this manner means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, anisotropic etching is used to remove oxides from the surface. In one or more embodiments, anisotropic etching removes more oxides from the surface of the source / drain material than from the dielectric material. In one or more embodiments, pre-cleaning the surface forms a source / drain material that is substantially free of oxides. Referring to FIGS. 2A-2E, a semiconductor structure 100 is shown. The semiconductor structure 100 includes an n-type transistor 102 and a p-type transistor 104. In one or more embodiments, each of the n-type transistor 102 and the p-type transistor 104 includes a dielectric material 110, source / drain materials 120, 122, and a substrate 130. In one or more embodiments, the dielectric material 110 may include any suitable dielectric material known to those skilled in the art. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material 110 includes one or more of silicon, silicon oxide, silicon nitride, silicon carbide, and low-k dielectrics. As used herein, terms such as "silicon oxide" and "silicon nitride" refer to materials that contain silicon and oxygen or silicon and nitrogen. "Silicon oxide" and "silicon nitride" should not be understood to imply any stoichiometry. In other words, a dielectric material containing silicon oxide or silicon nitride can be stoichiometric or non-stoichiometric, silicon-rich or silicon-poor. In some embodiments, the dielectric material 110 includes silicon oxide (SiO 2 ). In some embodiments, the dielectric material 110 includes silicon nitride (SiN). In some embodiments, the n-type transistor 102 and the p-type transistor 104 include source and drain contacts. In one or more embodiments, the source / drain materials 120, 122 may have more than one layer. In one or more particular embodiments, the source / drain material 120 of the n-type transistor 102 includes silicon (Si). The source / drain 120 material of the n-type transistor 102 may be doped or undoped. In one or more embodiments, the source / drain material 120 of the n-type transistor 102 includes silicon (Si) doped with phosphorus (P). In one or more embodiments, the source / drain material 122 of the p-type transistor 104 includes silicon germanium (SiGe). In one or more embodiments, the germanium (Ge) in the silicon germanium (SiGe) can have any suitable germanium concentration. In some embodiments, the germanium concentration of the silicon germanium (SiGe) is in the range from 10% to 100%, or in the range from 20% to 60%. The source / drain 122 material of the p-type transistor 104 may be doped or undoped. In one or more embodiments, the source / drain material 122 of the p-type transistor 104 includes silicon germanium (SiGe) doped with boron (B). Referring to FIGS. 2A to 2E, in one or more embodiments, there is a first opening 106 in the n-type transistor 102 and a second opening 108 in the p-type transistor 104. The first opening 106 and the second opening 108 may have any suitable aspect ratio (the ratio of the depth of the opening to the width of the opening). In one or more embodiments, the first opening 106 and the second opening 108 may independently have an aspect ratio in the range from 3:1 to 15:1, or in the range from 6:1 to 15:1, or in the range from 9:1 to 15:1, or in the range from 12:1 to 15:1. In one or more embodiments, the first opening 106 and the second opening 108 may independently have an aspect ratio greater than 10:1. Referring to FIGS. 1 and 2B, in operation 14, a molybdenum silicide (MoSi) layer 140 is deposited on one or more of the source / drain 122 of the p-type transistor 104 and the source / drain 122 of the n-type transistor 102. In the embodiments shown in FIGS. 2A-2E, the molybdenum silicide (MoSi) layer 140 is deposited only on the source / drain 122 of the p-type transistor 104, but those skilled in the art will recognize that the deposition of the molybdenum silicide layer 104 need not be selective to the p-type transistor. In one or more embodiments, the molybdenum silicide layer 140 can be formed by any suitable means. In one or more embodiments, the molybdenum silicide layer 140 is deposited on the p-type transistor by a chemical vapor deposition (CVD) process. In some embodiments, the molybdenum silicide layer 140 is selectively deposited on the source / drain material 122 of the p-type transistor, rather than on the source / drain material 120 of the n-type transistor. As used in this specification and the appended claims, the term "selectively depositing a film on one surface relative to another surface" and the like means that a first amount of the film is deposited on the first surface and a second amount of the film is deposited on the second surface, where the second amount of the film is less than the first amount of the film, or no film is deposited on the second surface. The selectivity of the deposition process is generally expressed as a multiple of the growth rate. For example, if the growth (or deposition) rate of one surface is 25 times faster than that of another surface, the process will be described as having a selectivity of 25:1. In this sense, a higher ratio indicates a more selective process. In one or more embodiments, the substrate 100 is optionally exposed to a blocking compound. This process step can be used to control the selectivity of the deposition process on a substrate including a metal surface and a dielectric surface. In one or more embodiments, the molybdenum silicide (MoSi) layer 140 is deposited by CVD. The substrate 100 is exposed to a processing gas for a period of time. The processing gas includes a molybdenum precursor, which reacts with the substrate surface to deposit a molybdenum film. The reactive gas can also be referred to as a metal precursor gas. The molybdenum precursor can be any suitable precursor that reacts with the substrate. In some embodiments, the molybdenum precursor includes a metal center and one or more ligands. In some embodiments, the metal center contains one or more metal atoms. In other words, in some embodiments, the metal precursor is one or more of a dimer, trimer, or tetramer. The molybdenum precursor can be any suitable precursor with a decomposition temperature higher than the deposition temperature. The molybdenum precursor of one or more embodiments is volatile and thermally stable, and thus suitable for vapor deposition. In some embodiments, the molybdenum precursor includes molybdenum halide. As used herein, the term "halide" refers to a binary phase in which one part is a halogen atom and the other part is an element or group with an electronegativity less than that of the halogen to form a compound such as fluoride, chloride, bromide, iodide, or astatide. A halogen ion is a negatively charged halogen atom. As is known to those skilled in the art, halogen anions include fluoride ion (F-), chloride ion (Cl-), bromide ion (Br-), iodide ion (I-), and astatide ion (At-). Thus, as used herein, the term "molybdenum halide" refers to any coordination complex of molybdenum with one or more halogen or halide ligands. The term molybdenum halide includes molybdenum mixed halides having at least two different halide atoms. In one or more embodiments, the molybdenum halide is selected from one or more of molybdenum chloride, molybdenum pentachloride, molybdenum bromide, molybdenum iodide, molybdenum bromochloride, molybdenum bromoiodide, molybdenum chlorobromide, molybdenum chloroiodide, molybdenum iodobromide, and molybdenum iodochloride. In other embodiments, the molybdenum precursor is substantially free of oxygen or nitrogen atoms. Thus, in these embodiments, the metal precursor does not contain carbonyl, oxo, amine, or imine ligands. Within these parameters, the number and type of ligands on the molybdenum precursor can vary based on, for example, the oxidation state of the molybdenum atom. The molybdenum precursor can be homoleptic or heteroleptic. In some embodiments, the molybdenum precursor contains at least one ligand that includes an optionally alkyl-substituted cyclopentadiene (Cp) ring. In some embodiments, the molybdenum precursor includes at least one ligand that includes an optionally alkyl-substituted benzene ring. In some embodiments, the molybdenum precursor includes at least one p-cymene ligand. In some embodiments, the molybdenum precursor includes at least one ligand that includes an open-chain or closed-chain diene. In one or more embodiments, the molybdenum precursor is delivered to the processing chamber as a molybdenum precursor gas or via a carrier gas such as argon (Ar), nitrogen (N 2 )), hydrogen (H 2 ), etc.). The molybdenum precursor gas or carrier gas can be provided in one or more pulses or continuously. The flow rate of the molybdenum precursor gas or carrier gas can be any suitable flow rate, including but not limited to a flow rate in the range of about 1 to about 5000 sccm, or in the range of about 2 to about 4000 sccm, or in the range of about 3 to about 3000 sccm, or in the range of about 5 to about 2000 sccm. The molybdenum precursor gas can be provided at any suitable pressure, including but not limited to a pressure in the range of about 5 mTorr to about 500 Torr, or in the range of about 10 mTorr to about 500 Torr, or in the range of about 100 mTorr to about 500 Torr, or in the range of about 5 Torr to about 500 Torr. The time for which the substrate is exposed to the molybdenum precursor gas can be any suitable time that allows the metal precursor to react with the substrate surface. For example, the process gas can flow into the process chamber for a period of greater than or equal to about 60 seconds. In some embodiments, the exposure time to the molybdenum precursor is about 0.5 seconds. In some embodiments, the exposure time to the molybdenum precursor is about 100 seconds, about 200 seconds, about 300 seconds, about 400 seconds, or about 500 seconds. In one or more embodiments, the deposition process is cyclic; the exposure time for each cycle of the molybdenum precursor is about 500 milliseconds. The flow is then turned off for about 3.5 seconds. In one or more embodiments, the deposition process is cyclic, and each cycle can be represented as follows: H 2 The gas is always on; the precursor exposure is 0.5 seconds, and with H 2 simultaneously; only H is on during purging 2 is on for 3.5 seconds; the total cycle duration is 4 seconds; the cycle is repeated until the target molybdenum thickness is reached. During exposure to the molybdenum precursor, the temperature of the substrate can be controlled, for example, by setting the temperature of the substrate support or pedestal. This temperature is also referred to as the deposition temperature. In some embodiments, the substrate is maintained within a temperature range of about 0°C to about 600°C, or about 25°C to about 500°C, or about 50°C to about 450°C, or about 100°C to about 400°C, or about 200°C to about 400°C, or about 250°C to about 350°C. In some embodiments, the substrate is maintained at a temperature below the decomposition temperature of the metal precursor. In one or more embodiments, the substrate is maintained at a temperature less than or equal to about 350°C, or less than or equal to about 310°C, or less than or equal to about 300°C, or less than or equal to about 250°C, or less than or equal to about 200°C. In one or more embodiments, the substrate is maintained at a temperature greater than or equal to about 200°C, or greater than or equal to about 300°C, or greater than about 350°C. In some embodiments, the substrate is maintained at a temperature within the range of about 200°C to about 310°C. In some embodiments, a carrier gas can be additionally provided to the process chamber simultaneously with the molybdenum precursor gas. The carrier gas can be mixed with the molybdenum precursor gas (e.g., as a dilution gas) or provided separately, and can be a pulsed flow or a constant flow. In some embodiments, the carrier gas flows into the process chamber at a constant flow within the range of about 1 to about 10,000 sccm. The carrier gas can be any carrier gas, such as argon, helium, neon, hydrogen, nitrogen, or a combination thereof. The deposition process is carried out as a thermal process without using plasma reactants. In other words, the method is carried out without plasma. In one or more embodiments, it is determined whether the molybdenum film has reached a predetermined thickness. If the predetermined thickness is not reached, the method returns to continue exposing the substrate to the molybdenum precursor until the predetermined thickness is reached. In some embodiments, the molybdenum film may be deposited to form a total layer thickness of about 10 angstroms to about 10,000 angstroms, or in some embodiments about 20 angstroms to about 1,000 angstroms, or in some embodiments about 50 angstroms to about 200 angstroms. In one or more embodiments, the molybdenum halide precursor directly reacts with the silicon or silicon germanium of the source / drain materials 120, 122 to form a molybdenum silicide layer 140. In other embodiments, once the molybdenum film reaches its predetermined thickness, the molybdenum film may be exposed to reactants to form a molybdenum silicide layer 140. In one or more embodiments, the reactants include an oxidizing agent, a reducing agent, or a combination thereof. In some embodiments, the reactants include hydrogen (H 2 ), ammonia (NH 3 ), silane, polysilane, or a combination thereof. In some embodiments, the silane is selected from one or more of disilane, trisilane, tetrasilane, higher-order silanes, and substituted silanes. In certain embodiments, the reactants include silane to form a molybdenum silicide (MoSi) layer 140. In one or more embodiments, a carrier gas is used to flow the reactants over the surface. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas includes one or more of N 2 , Ar, and He. In other embodiments, the reactive gas may flow continuously, and the flow of the molybdenum precursor to the chamber may be opened and closed. In other embodiments, in operation 16, the molybdenum silicide layer 140 may be annealed as appropriate. The annealing may be performed at any suitable temperature in any suitable atmosphere. In some embodiments, the molybdenum silicide layer 140 is annealed in a hydrogen (H 2 ) atmosphere at a temperature in the range of 200°C to 600°C or in the range of 400°C to 500°C. In one or more embodiments, the molybdenum silicide layer 140 is annealed at a pressure in the range of 10 millitorr to 20 torr, or in the range of 100 millitorr to 20 torr, or in the range of 500 millitorr to 10 torr. In one or more embodiments, the molybdenum silicide layer 140 can have any suitable thickness. In some embodiments, the thickness of the molybdenum silicide layer 140 ranges from 20 angstroms to about 100 angstroms, or from about 30 angstroms to about 90 angstroms, or from about 40 angstroms to about 80 angstroms, or from about 50 angstroms to about 70 angstroms. In one or more embodiments, the molybdenum silicide (MoSi) layer 140 has a thickness of about 40 angstroms. The molybdenum silicide (MoSi) layer 140 on the p-type transistor 102 has a Schottky barrier height in the range of about 0.65 eV to about 0.95 eV. Referring to FIGS. 1 and 2C, in operation 18, a titanium silicide (TiSi) layer 160 is deposited on the source / drain 120 of the n-type transistor 102 and the source / drain 122 of the p-type transistor. In one or more embodiments, the titanium silicide (TiSi) layer 160 can have any suitable thickness. In some embodiments, the thickness of the titanium silicide (TiSi) layer 160 ranges from 20 angstroms to about 100 angstroms, or from about 30 angstroms to about 90 angstroms, or from about 40 angstroms to about 80 angstroms, or from about 50 angstroms to about 70 angstroms. In one or more embodiments, the titanium silicide (TiSi) layer 160 has a thickness of about 40 angstroms. The titanium silicide (TiSi) layer 160 can be formed according to any suitable process known to those skilled in the art. In one or more embodiments, the structure 100 is first cleaned to remove the oxide from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, cleaning the surface forms a surface that is substantially free of oxide. As used in this manner, the term "substantially free of oxide" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, anisotropic etching is used to remove the oxide from the surface. In one or more embodiments, to form the titanium silicide (TiSi) layer 160, a metal film is selectively formed on the source / drain 120 of the n-type transistor 102 and the source / drain 122 of the p-type transistor, for example, on the molybdenum silicide layer 140. In some embodiments, the structure 100 is exposed to a metal precursor and a reactant. The metal film can be deposited by an ALD deposition process, a CVD deposition process, a plasma-enhanced CVD process, or a combination thereof. In some embodiments, the metal film includes a titanium silicide (TiSi) film. In one or more embodiments, the metal precursor includes a titanium precursor. In some embodiments, the titanium precursor includes a titanium halide. In some embodiments, the titanium halide includes titanium fluoride, titanium chloride, or a combination thereof. In certain embodiments, the titanium precursor includes titanium fluoride. In other certain embodiments, the titanium precursor includes titanium chloride. In one or more embodiments, a carrier gas is used to flow the precursor over the surface. In some embodiments, the carrier gas flows through an ampoule containing the precursor. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas includes one or more of N 2 , Ar, and He. In one or more embodiments, the reactants include an oxidizing agent, a reducing agent, or a combination thereof. In some embodiments, the reactants include hydrogen (H 2 ), silane, polysilane, or a combination thereof. In some embodiments, the silane is selected from one or more of disilane, trisilane, tetrasilane, higher-order silanes, and substituted silanes. In certain embodiments, the reactant includes silane to form a titanium silicide (TiSi) layer 160. In one or more embodiments, a carrier gas is used to flow the reactants over the surface. In some embodiments, the carrier gas is an inert gas. In some embodiments, the inert gas includes one or more of Ar and He. In other embodiments, the reactive gas can flow continuously, and the flow of the titanium precursor to the chamber can be turned on and off. In other embodiments, the titanium silicide film is formed by reacting titanium tetrachloride (TiCl 4 ), hydrogen gas (H 2 ) and plasma with the underlying silicon substrate. In one or more embodiments, no additional silicon source is provided. In one or more embodiments, by combining Mo and Ti in an integrated manner, the contact resistance is reduced more than when there is a single metal silicide. In other words, the combination of Mo and Ti produces a contact resistance that is lower than the contact resistance when only Mo is present and lower than the contact resistance when only Ti is present. Referring to FIG. 1, in one or more embodiments, operations 12 and 14 are performed in an integrated system without a vacuum interruption between the operations. In other embodiments, operations 12, 14, 16, and 18 are performed in an integrated system without a vacuum interruption between the operations. Referring to FIGS. 1 and 2D, in operation 20, a capping layer 170 may be formed on each of the n-type transistor 102 and the p-type transistor 104. The capping layer 170 may include any suitable material known to those skilled in the art. In one or more embodiments, the capping layer 170 includes a PVD metal film. In one or more embodiments, the capping layer 170 is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), PVD tungsten (W), PVD molybdenum (Mo), and PVD ruthenium (Ru). In one or more embodiments, the capping layer 170 prevents the formation of an oxide on the titanium silicide (TiSi) layer 160. In additional embodiments, the capping layer 170 is selectively formed on the top surface of the titanium silicide (TiSi) layer 160 by nitriding the titanium silicide (TiSi) layer 160 with one or more of ammonia (NH 3 ) plasma, N 2 / H 2 plasma, etc. Referring to FIG. 1, in some embodiments, in operation 22, annealing the semiconductor structure 100, if necessary, may further reduce the contact resistance of the structure 100. In one or more embodiments, annealing the semiconductor structure 100 may produce a smooth surface. The semiconductor structure 100 may be annealed by any process known to those skilled in the art. In some embodiments, the semiconductor structure is annealed by a rapid thermal process (RTP). In one or more embodiments, the rapid thermal process (RTP) includes annealing the semiconductor structure 100 to a temperature in the range of about 400°C to about 700°C. In one or more embodiments, the rapid thermal process (RTP) includes annealing the semiconductor structure 100 to a temperature of about 600°C. Referring to FIGS. 1 and 2E, in operation 24, the first opening 106 on the n-type transistor 102 and the second opening 108 on the p-type transistor 104 are independently filled with a gap filling material 180 and a gap filling material 182, respectively. In one or more embodiments, the gap filling material 180 and the gap filling material 182 are substantially void-free or seam-free. The gap filling material 180 and the gap filling material 182 can independently include any suitable gap filling material known to those skilled in the art. In one or more embodiments, the gap filling material 180 and the gap filling material 182 independently include one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). In one or more embodiments, the gap filling material 180 in the first opening 106 on the n-type transistor 102 is the same as the gap filling material 182 in the second opening 108 on the p-type transistor 104. In one or more embodiments, the gap filling material 180 in the first opening 106 on the n-type transistor 102 is different from the gap filling material 182 in the second opening 108 on the p-type transistor 104. In one or more embodiments, the gap filling material 180 and the gap filling material 182 are the same and include tungsten (W). The gap filling process can include any suitable gap filling process known to those skilled in the art. In one or more embodiments, the gap filling process includes exposing the semiconductor structure 100 to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor. In some embodiments, the gap filling process is a bottom-up gap filling process. In other embodiments, the gap filling process includes a conformal gap filling process. Referring to FIG. 3, in one or more embodiments, a method 50 of forming a semiconductor structure includes: in operation 52, pre-cleaning a substrate. The substrate can be pre-cleaned by any suitable method known to those skilled in the art. In operation 54, a molybdenum silicide (MoSi) layer is deposited on the p-type transistor and the n-type transistor. In operation 56, the method 50 optionally includes in-situ annealing of the transistors in a hydrogen (H 2 ) atmosphere. In operation 58, the method 50 includes forming a titanium silicide (TiSi) layer on the n-type transistor and the p-type transistor. In operation 60, the method 50 includes forming a capping layer on the n-type transistor and the p-type transistor. In operation 62, the method 50 optionally includes annealing the semiconductor structure. In operation 64, the method 50 optionally includes gap filling. Referring to FIGS. 3 and 4A - 4E, in operation 52, method 50 includes pre - cleaning a substrate. In one or more embodiments, maintaining the pre - cleaning process under vacuum ensures that no oxides are introduced / formed on the substrate surface during the method. In some embodiments, the pre - cleaning removes oxides from the substrate (or substrate surface). In some embodiments, the oxide is a native oxide. In some embodiments, cleaning the surface forms a surface that is substantially free of oxides. As used in this way, the term "substantially free of oxides" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, anisotropic etching is used to remove oxides from the surface. In one or more embodiments, anisotropic etching removes more oxides from the surface of the source / drain material than from the dielectric material. In one or more embodiments, the pre - cleaned surface forms a source / drain material that is substantially free of oxides. Referring to FIGS. 4A - 4E, a semiconductor structure 300 is shown. The semiconductor structure 300 includes an n - type transistor 302 and a p - type transistor 304. In one or more embodiments, each of the n - type transistor 302 and the p - type transistor 304 includes a dielectric material 310, source / drain materials 320, 322, and a substrate 330. In one or more embodiments, the dielectric material 310 can include any suitable dielectric material known to those skilled in the art and as described above for dielectric material 110. In some embodiments, the dielectric material 310 includes silicon oxide (SiO 2 ). In some embodiments, the dielectric material 310 includes silicon nitride (SiN). In some embodiments, the n - type transistor 302 and the p - type transistor 304 include source and drain contacts. In one or more embodiments, the source / drain materials 320, 322 can have more than one layer. In one or more specific embodiments, the source / drain material 320 of the n - type transistor 302 includes silicon (Si). The source / drain 320 material of the n - type transistor 302 can be doped or undoped. In one or more embodiments, the source / drain material 320 of the n - type transistor 302 includes silicon (Si) doped with phosphorus (P). In one or more embodiments, the source / drain material 322 of the p-type transistor 304 includes silicon germanium (SiGe). In one or more embodiments, the germanium (Ge) in the silicon germanium can have any suitable germanium concentration. In some embodiments, the germanium concentration of the silicon germanium (SiGe) ranges from 10% to 100%, or ranges from 20% to 60%. The source / drain 322 material of the p-type transistor 304 can be doped or undoped. In one or more embodiments, the source / drain material 322 of the p-type transistor 304 includes boron (B)-doped silicon germanium (SiGe). Referring to FIGS. 4A to 4E, in one or more embodiments, a first opening 306 is formed in the n-type transistor 302, and a second opening 308 is formed in the p-type transistor 304. The first opening 306 and the second opening 308 can have any suitable aspect ratio (the ratio of the depth of the opening to the width of the opening). In one or more embodiments, the first opening 306 and the second opening 308 can independently have an aspect ratio in the range of 3:1 to 15:1, or in the range of 6:1 to 15:1, or in the range of 9:1 to 15:1, or in the range of 12:1 to 15:1. In one or more embodiments, the first opening 306 and the second opening 308 can independently have an aspect ratio greater than 10:1. Referring to FIGS. 3 and 4B, in operation 54, a molybdenum silicide (MoSi) layer 340 is deposited on the source / drain 322 of the p-type transistor 304 and the source / drain 320 of the n-type transistor. In one or more embodiments, the molybdenum silicide layer 340 can be formed by any suitable method, as described above for the molybdenum silicide (MoSi) layer 140. In one or more embodiments, the molybdenum silicide layer 340 is deposited on the p-type transistor and the n-type transistor through a chemical vapor deposition (CVD) process, as described above for the molybdenum silicide layer 140. In one or more embodiments, it is determined whether the molybdenum film has reached a predetermined thickness. If the predetermined thickness is not reached, the method returns to continue exposing the substrate to the molybdenum precursor until the predetermined thickness is reached. In some embodiments, the molybdenum film can be deposited to form a total layer thickness of about 10 angstroms to about 10,000 angstroms, or in some embodiments, about 20 angstroms to about 1,000 angstroms, or in some embodiments, about 50 angstroms to about 200 angstroms. In one or more embodiments, once the molybdenum film reaches its predetermined thickness, the molybdenum film can be exposed to reactants to form the molybdenum silicide layer 340, as described above for the molybdenum silicide layer 140. In other embodiments, in operation 56, the molybdenum silicide layer 340 may be annealed as appropriate. The annealing may be carried out at any suitable temperature in any suitable atmosphere. In some embodiments, the molybdenum silicide layer 340 is annealed in a hydrogen (H 2 ) atmosphere at a temperature in the range of 200°C to 600°C or in the range of 400°C to 500°C. In one or more embodiments, the molybdenum silicide layer 340 is annealed at a pressure in the range of 10 mTorr to 20 Torr, or in the range of 100 mTorr to 20 Torr, or in the range of 500 mTorr to 10 Torr. In one or more embodiments, the molybdenum silicide layer 340 may have any suitable thickness. In some embodiments, the thickness of the molybdenum silicide layer 340 is in the range from 20 Å to about 100 Å, or in the range from about 30 Å to about 90 Å, or in the range from about 40 Å to about 80 Å, or in the range from about 50 Å to about 70 Å. In one or more embodiments, the molybdenum silicide (MoSi) layer 340 has a thickness of about 40 Å. Referring to FIGS. 3 and 4C, in operation 58, a titanium silicide (TiSi) layer 360 is deposited on the source / drain 320 of the n-type transistor 302 and the source / drain 322 of the p-type transistor. In one or more embodiments, the titanium silicide (TiSi) layer 360 may have any suitable thickness. In some embodiments, the thickness of the titanium silicide (TiSi) layer 360 is in the range from 20 Å to about 100 Å, or in the range from about 30 Å to about 90 Å, or in the range from about 40 Å to about 80 Å, or in the range from about 50 Å to about 70 Å. In one or more embodiments, the titanium silicide (TiSi) layer 360 has a thickness of about 40 Å. The titanium silicide (TiSi) layer 360 may be formed according to any suitable process known to those skilled in the art, as described above with respect to the titanium silicide (TiSi) layer 160. In one or more embodiments, the structure 100 is first cleaned to remove oxides from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, cleaning the surface forms a surface substantially free of oxides. As used in this manner, the term "substantially free of oxides" means that there are less than or equal to 5%, 2%, 1%, or 0.5% oxygen atoms on the surface. In one or more embodiments, anisotropic etching is used to remove oxides from the surface. In one or more embodiments, by combining Mo and Ti in an integrated manner, the contact resistance is reduced more than when there are separate metal silicides. In other words, on n-type and p-type transistors, the combination of Mo and titanium Ti produces a contact resistance that is lower than the contact resistance when using only Mo and lower than the contact resistance when using only Ti. Referring to FIG. 3, in one or more embodiments, operations 52 and 54 are performed in an integrated system with no vacuum break between the operations. In other embodiments, operations 52, 54, 56, and 58 are performed in an integrated system with no vacuum break between the operations. Referring to FIGS. 3 and 4D, in operation 60, a capping layer 370 may be formed on each of the n-type transistor 302 and the p-type transistor 304. The capping layer 370 may include any suitable material known to those skilled in the art. In one or more embodiments, the capping layer 370 includes a PVD metal film. In one or more embodiments, the capping layer 370 is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), PVD tungsten (W), PVD molybdenum (Mo), and PVD ruthenium (Ru). In one or more embodiments, the capping layer 370 prevents the formation of an oxide on the titanium silicide (TiSi) layer 360. In additional embodiments, the titanium silicide (TiSi) layer 360 is selectively nitrided by one or more of ammonia (NH 3 ) plasma, N 2 / H 2 plasma, etc. to selectively form the capping layer 370 on the top surface of the titanium silicide (TiSi) layer 360. Referring to FIG. 3, in some embodiments, annealing the semiconductor structure 300, optionally in operation 62, may further reduce the contact resistance of the structure 300. In one or more embodiments, annealing the semiconductor structure 300 may result in a smooth surface. The semiconductor structure 300 may be annealed by any process known to those skilled in the art. In some embodiments, the semiconductor structure is annealed by rapid thermal processing (RTP). In one or more embodiments, the rapid thermal processing (RTP) includes annealing the semiconductor structure 300 to a temperature in the range of about 500°C to about 700°C. In one or more embodiments, the rapid thermal processing (RTP) includes annealing the semiconductor structure 300 to a temperature of about 600°C. In some embodiments, the root mean square (RMS) roughness of the annealed semiconductor structure is in the range of 4% to less than 30%, 4% to less than 20%, 4% to less than 10%, 10% to less than 30%, 10% to less than 20%, or 20% to less than 30%. Referring to FIGS. 3 and 4E, in operation 64, the first opening 306 on the n-type transistor 302 and the second opening 308 on the p-type transistor 304 are independently filled with a gap filling material 380 and a gap filling material 382, respectively. In one or more embodiments, the gap filling material 380 and the gap filling material 382 are substantially void or seam free. The gap filling material 380 and the gap filling material 382 may independently include any suitable gap filling material known to those skilled in the art. In one or more embodiments, the gap filling material 380 and the gap filling material 382 independently include one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). In one or more embodiments, the gap filling material 380 in the first opening 306 on the n-type transistor 302 is the same as the gap filling material 382 in the second opening 308 on the p-type transistor 304. In one or more embodiments, the gap filling material 380 in the first opening 306 on the n-type transistor 302 is different from the gap filling material 382 in the second opening 308 on the p-type transistor 304. In one or more embodiments, the gap filling material 380 and the gap filling material 382 are the same and include tungsten (W). The gap filling process may include any suitable gap filling process known to those skilled in the art. In one or more embodiments, the gap filling process includes exposing the semiconductor structure 300 to a metal precursor and a reactant. In some embodiments, the metal precursor includes one or more of a molybdenum precursor, a tungsten precursor, a cobalt precursor, and a ruthenium precursor. In some embodiments, the gap filling process is a bottom-up gap filling process. In other embodiments, the gap filling process includes a conformal gap filling process. FIG. 5 shows a schematic top view of an example of a multi-chamber processing system 400 or cluster tool according to an embodiment of the present disclosure. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 having corresponding transfer robots 412, 414, hold chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers in the processing system 400 can be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 400 (e.g., such as the atmospheric ambient environment that may exist during manufacturing). For example, wafers can be processed in various chambers and transferred between various chambers under low pressure (e.g., less than or equal to about 300 Torr) or in a vacuum environment without disrupting the low pressure or vacuum environment between the various processes performed on the wafers in the processing system 400. Thus, the processing system 400 can provide an integrated solution for certain processing of wafers. Examples of processing systems that can be modified as appropriate in accordance with the teachings provided herein include Endura®, Producer®, or Centura® integrated processing systems or other suitable processing systems available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other processing systems, including systems from other manufacturers, may also be adapted to benefit from the aspects described herein. In the example shown in FIG. 5, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate wafer transfer. The docking station 440 is configured to receive one or more front opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes blades 448 disposed at one end of the corresponding factory interface robot 442, and the blades 448 are configured to transfer wafers from the factory interface 402 to the load lock chambers 404, 406. The load lock chambers 404, 406 have corresponding ports 450, 452 coupled to the factory interface 402 and corresponding ports 454, 456 coupled to the transfer chamber 408. The transfer chamber 408 further has corresponding ports 458, 460 coupled to the hold chambers 416, 418 and corresponding ports 462, 464 coupled to the process chambers 420, 422. Similarly, the transfer chamber 410 has corresponding ports 466, 468 coupled to the hold chambers 416, 418 and corresponding ports 470, 472, 474, 476 coupled to the process chambers 424, 426, 428, 430. The ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, 476 can be, for example, slit valve openings with slit valves to facilitate the transfer robots 412, 414 to pass wafers therethrough and to provide a seal between the respective chambers to prevent gas transfer between the respective chambers. Generally, any port is open for wafer transfer through the port. Otherwise, the port is closed. The load lock chambers 404, 406, transfer chambers 408, 410, hold chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 442 transfers wafers from the FOUP 444 to the load lock chamber 404 or 406 through ports 450 or 452. The gas and pressure control system then evacuates the load lock chamber 404 or 406. The gas and pressure control system further maintains the transfer chambers 408, 410 and the hold chambers 416, 418 in an internal low pressure or vacuum environment (which may include an inert gas). Thus, evacuating the load lock chamber 404 or 406 facilitates the transfer of wafers between the atmospheric environment, such as the factory interface 402, and the low pressure or vacuum environment of the transfer chamber 408. The wafers in the load lock chamber 404 or 406 have been evacuated, and the transfer robot 412 transfers the wafers from the load lock chamber 404 or 406 to the transfer chamber 408 through ports 454 or 456. The transfer robot 412 can then transfer the wafers to any of the processing chambers 420, 422 and / or transfer between any of the processing chambers 420, 422 through the corresponding ports 462, 464 for processing, and transfer the wafers to the hold chambers 416, 418 through the corresponding ports 458, 460 to hold and wait for further transfer. Similarly, the transfer robot 414 can access the wafers in the hold chambers 416 or 418 through ports 466 or 468, and can transfer the wafers to any of the processing chambers 424, 426, 428, 430 and / or transfer between any of the processing chambers 424, 426, 428, 430 through the corresponding ports 470, 472, 474, 476 for processing, and transfer the wafers to the hold chambers 416, 418 through the corresponding ports 466, 468 to hold and wait for further transfer. The transfer and holding of wafers within and between the various chambers can be performed in the low pressure or vacuum environment provided by the gas and pressure control system. The processing chambers 420, 422, 424, 426, 428, 430 can be any suitable chambers for processing wafers. In some embodiments, the processing chamber 420 is capable of performing a pre-clean process, the processing chamber 422 is capable of performing a chemical vapor deposition (CVD) process, and the processing chambers 424, 426, 428, 430 are capable of performing a plasma enhanced chemical vapor deposition (PECVD) process. The processing chamber 420 can be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc. of Santa Clara, California. The system controller 490 is coupled to the processing system 400 for controlling the processing system 400 or its components. For example, the system controller 490 can control the operation of the processing system 400 by using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the processing system 400 or by controlling the controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 430. In operation, the system controller 490 enables the collection of data and feedback from the individual chambers to coordinate the performance of the processing system 400. The system controller 490 generally includes a central processing unit (CPU) 492, a memory 494, and support circuitry 496. The CPU 492 can be one of any form of general-purpose processor usable in an industrial environment. The memory 494 or non-transitory computer-readable medium is accessible by the CPU 492 and can be one or more of memories such as random-access memory (RAM), read only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital memory. The support circuitry 496 is coupled to the CPU 492 and can include cache memory, clock circuits, input / output subsystems, power supplies, etc. The various methods disclosed herein can generally be implemented under the control of the CPU 492 by the CPU 492 executing computer instruction codes, such as stored as software routines in the memory 494 (or the memory of a particular processing chamber). When the computer instruction codes are executed by the CPU 492, the CPU 492 controls the chambers to perform processes according to the various methods. Other processing systems may employ other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 408, 410 and holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device in the processing system. The present disclosure will now be described with reference to the following examples. Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways. Examples Example 1: Comparison The substrate including n-type and p-type transistors is pre-cleaned, and a titanium silicide layer is deposited on the junction. A PVD tungsten capping layer is deposited on the titanium silicide layer, and the contact structure is filled with tungsten. Example 2: Comparison The substrate including n-type and p-type transistors is pre-cleaned, and a molybdenum silicide layer is deposited on the junction. A PVD tungsten capping layer is deposited on the molybdenum silicide layer, and the contact structure is filled with tungsten. Example 3 The substrate including n-type and p-type transistors is pre-cleaned. A molybdenum silicide (MoSi) layer is deposited on the p-type and n-type transistors. A titanium silicide (TiSi) layer is formed on the molybdenum silicide (MoSi) layer. A PVD tungsten capping layer is deposited on the titanium silicide (TiSi) layer, and the contacts are filled with tungsten. FIG. 6 shows the n-type transistor contact resistance of the examples. As shown in FIG. 6, compared with components having only titanium silicide (Example 1) or molybdenum silicide (Example 2), using a combination of MoSi and TiSi (Example 3) can produce components with reduced contact resistance. In the context of describing the materials and methods discussed herein, and especially in the context of the following claims, the use of the terms "a," "an," "the," and similar referents should be understood to cover both the singular and the plural, unless otherwise specified herein or clearly contradicted by the context. Unless otherwise specified herein, the recitation of numerical ranges herein is merely intended to be a shorthand way of referring individually to each separate numerical value falling within the range, and each separate numerical value is incorporated into the specification as if it were recited individually herein. Unless otherwise specified herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illuminate the materials and methods and does not impose a limitation on the scope, unless otherwise stated. Any language in the specification should not be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods. As used herein, the terms "one embodiment," "certain embodiments," "one or more embodiments," or "embodiments" refer to a particular feature, structure, material, or characteristic described in connection with the embodiments being included in at least one embodiment of the present disclosure. Thus, appearances of phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment," or "in embodiments" throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner. Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents. 10: Method 12: Operation 14: Operation 16: Operation 18: Operation 20: Operation 22: Operation 24: Operation 50: Method 52: Operation 54: Operation 56: Operation 58: Operation 60: Operation 62: Operation 64: Operation 100: Semiconductor structure 102: n-type transistor 104: p-type transistor 106: First opening 108: Second opening 110: Dielectric material 120: Source / drain material 122: Source / drain material 130: Substrate 140: Molybdenum silicide layer 160: Titanium silicide layer 170: Capping layer 180: Gap filling material 182: Gap filling material 300: Semiconductor structure 302: n-type transistor 304: p-type transistor 306: First opening 308: Second opening 310: Dielectric material 320: Source / drain material 322: Source / drain material 330: Substrate 340: Molybdenum silicide layer 360: Titanium silicide layer 370: Capping layer 380: Gap filling material 382: Gap filling material 402: Factory interface 404: Load lock chamber 406: Load lock chamber 408: Transfer chamber 410: Transfer chamber 412: Transfer robot 414: Transfer robot 416: Hold chamber 418: Hold chamber 420: Processing chamber 422: Processing chamber 424: Processing chamber 426: Processing chamber 428: Processing chamber 430: Processing chamber 440: Docking station 442: Factory interface robot 444: FOUP 448: Blade 450: Port 452: Port 454: Port 456: Port 458: Port 460: Port 464: Port 466: Port 468: Port 470: Port 472: Port 474: Port 476: Port 490: System controller 492: CPU 494: Memory 496: Support circuit R C : Contact resistance To facilitate a detailed understanding of the above features of the present disclosure, reference may be made to the embodiments for a more detailed description of the present disclosure briefly outlined above, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of the present disclosure and should not be considered as limiting its scope, as the present disclosure may admit other equivalent embodiments. FIG. 1 shows a process flowchart of a method according to one or more embodiments of the present disclosure; FIG. 2A shows a semiconductor structure according to one or more embodiments of the present disclosure; FIG. 2B shows a semiconductor structure according to one or more embodiments of the present disclosure; FIG. 2C shows a semiconductor structure according to one or more embodiments of the present disclosure; FIG. 2D illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure; FIG. 2E illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure; FIG. 3 illustrates a process flowchart of a method in accordance with one or more alternative embodiments of the present disclosure; FIG. 4A illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure; FIG. 4B illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure; FIG. 4C illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure; FIG. 4D illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure; FIG. 4E illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure; FIG. 5 illustrates a schematic top view of an exemplary multi-chamber processing system in accordance with one or more embodiments; and FIG. 6 is a bar graph of contact resistance results in accordance with an embodiment. In the figures, similar components and / or features may have the same element symbols. Additionally, various components of the same type may be distinguished by following the element symbol with a dash and a second label, the second label being used to distinguish similar components. If only the first element symbol is used in the description, the description applies to any one of the similar components having the same first element symbol, regardless of the second element symbol. Domestic deposit information (please note in the order of deposit institution, date, number) None Foreign deposit information (please note in the order of deposit country, institution, date, number) None 100: Semiconductor structure 102: n-type transistor 104: p-type transistor 106: First opening 108: Second opening 110: Dielectric material 120: Source / drain material 122: Source / drain material 130: Substrate 140: Molybdenum silicide layer 160: Titanium silicide layer 170: Capping layer

Claims

1. A method for forming a semiconductor structure, the method comprising the steps of: depositing a molybdenum silicon dioxide (MoSi) layer on one or more of a p-type transistor and an n-type transistor on a substrate, the substrate including the n-type transistor and the p-type transistor, and having a first opening on the n-type transistor and a second opening on the p-type transistor; optionally, annealing the substrate in situ in a hydrogen (H2) atmosphere; forming a titanium silicon dioxide (TiSi) layer on the n-type transistor and the p-type transistor, the titanium silicon dioxide (TiSi) layer being formed on the molybdenum silicon dioxide (MoSi) layer on the one or more transistors on which the molybdenum silicon dioxide (MoSi) layer has been deposited; and forming a capping layer on the titanium silicon dioxide (TiSi) layer.

2. The method of claim 1 further includes the step of: independently depositing a gap-filling material in the first opening and the second opening.

3. The method as described in claim 1 further includes the step of: pre-cleaning the substrate.

4. The method as described in claim 3, wherein the method is an integration method executed in a cluster tool.

5. The method of claim 1, wherein the capping layer comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

6. The method of claim 1, wherein the n-type transistor comprises phosphorus (P)-doped silicon (Si) and the p-type transistor comprises boron (B)-doped silicon germanium (SiGe).

7. The method as described in claim 2, wherein the gap-filling material is substantially free of voids or seams.

8. The method of claim 2, wherein the gap-filling material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co) and ruthenium (Ru).

9. The method of claim 4, wherein the one or more transistors have reduced contact resistance, the reduced contact resistance being lower than that of a transistor comprising a molybdenum silicon (MoSi) layer and without a titanium silicon (TiSi) layer.

10. The method of claim 4, wherein the one or more transistors have reduced contact resistance, the reduced contact resistance being lower than that of a transistor comprising a titanium silicon (TiSi) layer and without a molybdenum silicon (MoSi) layer.

11. The method of claim 1, wherein the molybdenum silicon (MoSi) layer is on the n-type transistor and the p-type transistor.

12. A method of forming a semiconductor structure, the method comprising the steps of: pre-cleaning a substrate including an n-type transistor and a p-type transistor, a first opening on the n-type transistor and a second opening on the p-type transistor; depositing a molybdenum silicon dioxide (MoSi) layer on the p-type transistor and the n-type transistor; performing in-situ annealing of the substrate in a hydrogen (H2) atmosphere, if appropriate; forming a titanium silicon dioxide (TiSi) layer on the molybdenum silicon dioxide (MoSi) layer; forming a capping layer on the titanium silicon dioxide (TiSi) layer; and depositing a gap-filling material in the first opening and the second opening.

13. The method of claim 12, wherein the capping layer comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

14. The method of claim 12, wherein the gap-filling material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co) and ruthenium (Ru).

15. The method of claim 12, wherein the n-type transistor comprises phosphorus (P)-doped silicon (Si) and the p-type transistor comprises boron (B)-doped silicon germanium (SiGe).

16. The method as described in claim 12, wherein the gap-filling material is substantially free of voids or seams.

17. The method of claim 12, wherein the p-type transistor and the n-type transistor have reduced contact resistance, the reduced contact resistance being lower than that of a transistor comprising a molybdenum silicon (MoSi) layer and without a titanium silicon (TiSi) layer.

18. The method of claim 12, wherein the p-type transistor and the n-type transistor have reduced contact resistance, the reduced contact resistance being lower than that of a transistor comprising a titanium silicon (TiSi) layer and without a molybdenum silicon (MoSi) layer.

19. A semiconductor structure comprising: An n-type transistor and a p-type transistor; a first opening on the n-type transistor and a second opening on the p-type transistor; A molybdenum silicon dioxide (MoSi) layer on one or more of the p-type and n-type transistors; a titanium silicon dioxide (TiSi) layer on the p-type and n-type transistors, wherein the TiSi layer is formed on the molybdenum silicon dioxide (MoSi) layer on the one or more transistors on which the molybdenum silicon dioxide (MoSi) layer is formed; a capping layer on the TiSi layer; and a gap-filling material located in the first opening and the second opening.

20. The semiconductor structure of claim 19, wherein the molybdenum silicon (MoSi) layer is on the n-type transistor and the p-type transistor.

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