Method of forming a metal liner for interconnect structures

Abstract

A method of forming a device includes forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the gap including sidewalls and a bottom. The method includes selectively depositing a self-assembled monolayer (SAM) at the bottom of the gap. The SAM comprises a hydrocarbon having the chemical formula HC≡CR, wherein R is an alkyl straight-chain or aryl group containing 1 to 20 carbon atoms, or has the chemical formula R'C=CR", wherein R' and R" independently comprise an alkyl straight-chain or aryl group containing 1 to 20 carbon atoms. A barrier layer is formed on the SAM, and subsequently a metal liner is selectively deposited on the barrier layer. After selectively depositing the metal liner on the barrier layer, the SAM is removed.

Description

Technical Field

[0001] This application is a continuation-in-part of U.S. patent application No. 17 / 466,732 filed on September 3, 2021, the entire contents of which are incorporated herein by reference.

[0002] Embodiments of the present disclosure generally relate to methods for forming metal liner layers for interconnect structures. More particularly, embodiments of the present disclosure are directed to methods for selectively depositing a metal liner layer. Prior Art

[0003] When scaling transistors and interconnects to the 3 nm node and below, multiple challenges hinder improvements in power and performance. Interconnects include metal lines that carry current within a device layer and metal vias that carry current between layers. Reducing the pitch narrows the width of both, increasing resistance and increasing voltage drop across the circuit, slowing down circuit speed and increasing power dissipation.

[0004] While transistor performance improves with scaling, interconnect metallization does not. Interconnect via resistance can increase by a factor of 10 with shrinking dimensions. This increased interconnect via resistance can lead to resistive-capacitive (RC) delays, reducing performance and increasing power consumption. Conventional copper interconnect structures include a barrier layer and / or metal liner deposited on the sidewalls of the gap, which provides a via with dielectric sidewalls to provide good adhesion and prevent copper diffusion into the dielectric layer. Due to its high resistivity, the barrier layer can often be the largest contributor to via resistance. Previous approaches have focused on reducing the thickness of the barrier layer or finding a barrier layer with lower resistivity to reduce via resistance. Increased via resistance remains a problem, particularly in smaller features where an increasing percentage of via volume is formed by the barrier layer on the sidewalls.

[0005] The metal liner deposited on the barrier layer adheres to the barrier layer and facilitates subsequent copper (Cu) filling in the gaps between the sidewalls. Current approaches focus on selectively growing the metal liner on the via sidewalls with high selectivity relative to the via bottom in an attempt to reduce via resistance and copper corrosion, although selective growth remains a challenge.

[0006] Therefore, there is a need for methods of depositing material layers that improve interconnect performance, for example, by reducing through-hole resistance and improving deposition selectivity. Summary of the Invention

[0007] Embodiments of the present disclosure are directed to methods for forming microelectronic devices. In one or more embodiments, the methods include forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the gap including sidewalls and a bottom; selectively depositing a self-assembled monolayer (SAM) at the bottom of the gap, the SAM comprising or consisting essentially of a hydrocarbon having the formula HC≡CR, where R is a linear alkyl or aryl group containing 1 to 20 carbon atoms, or having the formula R'C=CR", where R' and R" independently comprise a linear alkyl or aryl group containing 1 to 20 carbon atoms; forming a barrier layer on the SAM; selectively depositing a metal liner on the barrier layer on the sidewalls, the metal liner being deposited to a greater thickness on the sidewalls than on the bottom; removing the SAM after selectively depositing the metal liner on the barrier layer; and performing a gapfill process on the metal liner. Simple diagram description

[0008] For a detailed understanding of the aforementioned features of the present disclosure, the disclosure, briefly summarized above, may be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.

[0009] FIG. 1A illustrates a portion of a microelectronic component during a manufacturing stage, wherein one or more embodiments of the present disclosure have a passivation layer formed on the bottom of a gap;

[0010] Figure 1B shows a barrier layer formed after the passivation layer shown in Figure 1A is formed;

[0011] FIG 1C shows a liner layer formed on the barrier layer formed in FIG 1B;

[0012] FIG 1D shows a second liner layer formed on the liner layer formed in FIG 1C;

[0013] FIG 1E shows the passivation layer formed in FIG 1A after the optional second liner layer is formed in FIG 1D;

[0014] FIG. 2A illustrates a portion of a microelectronic component during a manufacturing stage according to one or more embodiments of the present disclosure, the microelectronic component having a first passivation layer formed on a bottom portion of a gap according to one or more embodiments of the present disclosure;

[0015] Figure 2B shows a barrier layer formed on the gap in Figure 2A;

[0016] Figure 2C shows the removal of the passivation layer formed in Figure 2A;

[0017] Figure 2D shows a second passivation layer formed on the barrier layer formed in Figure 2B;

[0018] Figure 2E shows a liner layer formed on the barrier layer in Figure 2B;

[0019] Figure 2F shows a second liner layer formed on the liner layer formed in Figure 2E;

[0020] Figure 2G shows the structure after removing the second passivation layer in Figure 2F;

[0021] FIG3 is a process flow diagram illustrating a method of manufacturing a microelectronic device according to one or more embodiments of the present disclosure; and

[0022] FIG. 4 is a process flow diagram illustrating a method for fabricating a microelectronic device according to one or more embodiments of the present disclosure. Implementation Method

[0023] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0024] As used in this specification and the appended claims, the terms "substrate" and "wafer" are used interchangeably to refer to a surface or portion of a surface upon which a process acts. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may also refer to only a portion of a substrate. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate upon which one or more films or features are deposited or formed.

[0025] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during fabrication. For example, depending on the application, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to performing film processing directly on the substrate surface itself, any of the film processing steps disclosed herein may also be performed on an underlying layer formed on the substrate, as described in more detail below, and the term "substrate surface" is intended to include such underlying layers as referred to herein. Thus, for example, where a film / layer or portion of a film / layer has already been deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface contains will depend on what film is being deposited and the specific chemistry being used.

[0026] As used in this specification and the appended claims, the terms "reactive gas," "precursor," "reactant," and similar terms are used interchangeably to refer to a gas containing species that react with a substrate surface. For example, a first "reactive gas" may simply adsorb on the substrate surface and be available for further chemical reaction with a second reactive gas.

[0027] Some embodiments of the present disclosure provide methods for improving interconnect performance. The interconnects include metal lines that carry current within the same device layer and metal vias that carry current between layers. These lines and vias are formed using a conductive metal, such as copper or cobalt, within a gap formed within the device. In one or more embodiments, the dielectric layer includes at least one feature defining the gap, the gap including sidewalls and a bottom. In one or more embodiments, the gap includes a metal line and a metal via. In one or more embodiments, the metal line has sidewalls and a bottom. In one or more embodiments, the metal via has sidewalls and a bottom. Unless otherwise specified, the term "bottom of the gap" as used in this specification and the appended claims is intended to refer to the bottom of the metal via closest to the substrate.

[0028] Embodiments of the present disclosure provide methods for forming interconnect structures in microelectronic device fabrication. In one or more embodiments, the microelectronic devices described herein include at least one top interconnect structure interconnected with at least one bottom interconnect structure. Embodiments of the present disclosure provide microelectronic devices and methods for fabricating microelectronic devices that improve interconnect performance, such as reducing through-hole resistance.

[0029] Methods of forming a microelectronic element are described herein with reference to Figures 1A through 1E and Figures 2A through 2G. Figure 3 is a flow chart of an exemplary method of forming a microelectronic element with respect to Figures 1A through 1E. Figure 4 is a flow chart of an exemplary method of forming a microelectronic element with respect to Figures 2A through 2G.

[0030] 1A to 1D , a portion of a microelectronic component 100 is illustrated during manufacturing stages. In FIG. 1A , microelectronic component 100 includes a substrate 110, a barrier layer 120 on substrate 110, a metal layer 130 on barrier layer 120, a conductive gap-filling layer 140, an aluminum oxide etch stop layer 142, and a dielectric layer 145 on aluminum oxide etch stop layer 142. Dielectric layer 145 includes at least one feature defining a gap 146. Gap 146 includes sidewalls 148 and a bottom 149. According to one or more embodiments, a passivation layer (e.g., a self-assembled monolayer (SAM)) 150 is formed on the bottom 149 of the gap. It should be understood that, in one or more embodiments, the conductive gap-filling layer 140 forms a metal line that carries current within the same component layer.

[0031] In one or more embodiments, substrate 110 is a wafer, such as a semiconductor substrate. In one or more embodiments, substrate 110 is an etch stop layer on the wafer. In one or more embodiments, substrate 110 is an aluminum oxide etch stop layer on the wafer. In one or more embodiments, barrier layer 120 comprises tantalum nitride (TaN). In one or more embodiments, barrier layer 120 comprises tantalum nitride (TaN) formed by ALD. In one or more embodiments, metal layer 130 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, metal layer 130 comprises one or more of a single layer of ruthenium (Ru) or a single layer of cobalt (Co). In one or more embodiments, a portion of metal layer 130 is etched. In one or more embodiments, SAM 150 is deposited on the etched portion of metal layer 130. In one or more embodiments, conductive gap filler 140 comprises one or more of copper (Cu) or cobalt (Co). In one or more embodiments, the etch stop layer 142 includes one or more of aluminum oxide, silicon nitride, and aluminum nitride.

[0032] In one or more embodiments, dielectric layer 145 is a low-k dielectric layer. In certain embodiments, dielectric layer 145 comprises silicon oxide (SiOx). In one or more embodiments, dielectric layer 145 comprises SiOxHy(CHz). Further embodiments provide dielectric layer 145 comprising porous or carbon-doped SiOx. In some embodiments, dielectric layer 145 is a porous or carbon-doped SiOx layer having a k value of less than approximately 5. In other embodiments, dielectric layer 145 is a multilayer structure. For example, in one or more embodiments, dielectric layer 145 comprises a multilayer structure comprising one or more of a dielectric layer, an etch stop layer, and a hard mask layer.

[0033] In one or more embodiments, dielectric layer 145 includes at least one feature that defines gap 146, which includes sidewalls 148 and a bottom 149. For illustrative purposes, the figures show a substrate with a single feature; however, those skilled in the art will appreciate that there may be more than one feature. The feature can have any suitable shape, including, but not limited to, a trench, a cylindrical via (which, when filled with metal, conducts current between layers), and a line conducting current within the same device layer. In some embodiments, the feature defines gap 146 in dielectric layer 145. In some embodiments, gap 146 defines a via portion 146V and a line portion 146L, but the illustrated embodiment is not intended to be limiting. As used herein, the term "feature" means any intentional surface irregularity. Suitable examples of features include, but are not limited to, a trench having a top, two sidewalls, and a bottom, and a peak having a top and two sidewalls. Features can have any suitable aspect ratio (the ratio of the feature's depth to its width). In some embodiments, the aspect ratio is greater than or equal to approximately 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0034] In one or more embodiments, the SAM 150 is formed on the metal layer 130. In one or more embodiments, the SAM 150 is deposited by exposing the bottom 149 of the gap to a hydrocarbon carried in argon (Ar) gas. In one or more embodiments, the SAM 150 includes an unsaturated hydrocarbon.

[0035] The use of an unsaturated hydrocarbon SAM 150 has been found to improve Cu interconnect via resistance by selectively depositing a metal liner on the via sidewalls rather than the via bottom, minimizing metal liner growth at the via bottom. Embodiments of the present disclosure provide methods for selectively growing a metal liner (such as a Ru liner) on the via sidewalls relative to the via bottom with high selectivity (e.g., a ratio of sidewall liner thickness to bottom liner thickness greater than 3, greater than 4, greater than 5, greater than 6, greater than 7, greater than 8, greater than 9, or greater than 10). The SAM chemistry and process are selected to allow metal (e.g., Ru) to nucleate and grow only on the via sidewalls, rather than at the via bottom. Growing a thinner metal (e.g., Ru), or no metal at the via bottom, reduces via resistance and Cu corrosion. Other liner materials include cobalt (Co), molybdenum (Mo), and tantalum (Ta). In certain embodiments, the SAM chemistry / process can suppress metal liner growth at the via bottom (e.g., less than 10 angstroms, less than 5 angstroms, less than 4 angstroms, less than 3 angstroms, less than 2 angstroms, or less than 1 angstrom) while maintaining metal liner growth at the via sidewalls (e.g., 5 angstroms or greater, or 10 angstroms or greater). The SAM chemistry facilitates selectivity of the via bottom (e.g., Cu, Co, W) relative to the via sidewalls (e.g., TaN).

[0036] According to one or more embodiments, selectively depositing the SAM includes exposing the bottom 149 of the gap 146 to a hydrocarbon having the chemical formula HC≡CR, where R is a linear alkyl group or an aromatic group containing 1 to 20 carbon atoms, or having the chemical formula R'C=CR", where R' and R" independently include linear alkyl groups or aromatic groups containing 1 to 20 carbon atoms.

[0037] In some embodiments, the substrate is immersed in the vapor of the unsaturated hydrocarbon. In some embodiments, the processing conditions for exposing the substrate to the unsaturated hydrocarbon can be controlled.

[0038] In some embodiments, the pressure of the processing chamber is controlled. The pressure of the processing chamber can be any suitable pressure for forming the barrier layer. In some embodiments, the pressure of the processing chamber is maintained at less than or equal to about 80 Torr, less than or equal to about 70 Torr, less than or equal to about 60 Torr, less than or equal to about 50 Torr, less than or equal to about 40 Torr, less than or equal to about 30 Torr, less than or equal to about 20 Torr, less than or equal to about 15 Torr, less than or equal to about 10 Torr, or less than or equal to about 5 Torr. In some embodiments, the pressure of the processing chamber is maintained at about 10 Torr, about 20 Torr, about 30 Torr, about 40 Torr, or about 50 Torr.

[0039] In one or more embodiments, an argon (Ar) gas flow is configured to carry the unsaturated hydrocarbon from the container to the processing chamber. In some embodiments, the argon (Ar) gas flow rate configured to carry the unsaturated hydrocarbon into the processing chamber is controlled. The argon (Ar) gas flow rate can be any suitable flow rate for forming a passivation layer. In some embodiments, the argon (Ar) gas flow rate is in a range from about 50 sccm to about 100 sccm, or in a range from about 75 sccm to about 100 sccm. In one or more embodiments, the argon (Ar) gas flow rate is about 600 sccm. In some embodiments, the flow rate of argon (Ar) gas is less than or equal to about 600 sccm, less than or equal to about 500 sccm, less than or equal to about 400 sccm, less than or equal to about 300 sccm, less than or equal to about 250 sccm, less than or equal to about 200 sccm, less than or equal to about 150 sccm, less than or equal to about 100 sccm, less than or equal to about 75 sccm, or less than or equal to 50 sccm.

[0040] In some embodiments, the immersion time period during which the unsaturated hydrocarbon is exposed to the substrate is controlled. The immersion time period can be any suitable time period for forming the barrier layer. In some embodiments, the immersion time period is 1 to 200 seconds, e.g., 1 to 10 seconds, greater than or equal to about 10 seconds, greater than or equal to about 20 seconds, greater than or equal to about 30 seconds, greater than or equal to about 45 seconds, greater than or equal to about 60 seconds, greater than or equal to about 80 seconds, greater than or equal to about 120 seconds, greater than or equal to about 150 seconds, or greater than or equal to about 200 seconds. In some embodiments, the immersion time period is about 60 seconds. In some embodiments, the immersion time period is about 200 seconds.

[0041] In one or more embodiments, when the unsaturated hydrocarbon is in a container (such as an ampoule or cylinder), the unsaturated hydrocarbon is in a liquid phase, and the unsaturated hydrocarbon is transported from the container to the chamber in a carrier gas. In some embodiments, when the container has a pressure of approximately 0.1 Torr, the unsaturated hydrocarbon is in a saturated vapor phase in the container. In one or more embodiments, the temperature of the container is lower than the temperature in the processing chamber. In one or more embodiments, a carrier gas, such as argon (Ar), transports the saturated vapor phase unsaturated hydrocarbon from the container to the processing chamber. In some embodiments, the temperature of the processing chamber is controlled during exposure to the unsaturated hydrocarbon. The temperature of the processing chamber may also be referred to as the operating temperature. In some embodiments, the temperature of the processing chamber is in a range from approximately 150°C to approximately 400°C, for example, from 200°C to approximately 300°C. In some embodiments, the temperature of the processing chamber is less than or equal to approximately 300°C, less than or equal to approximately 275°C, less than or equal to approximately 250°C, less than or equal to approximately 225°C, or less than or equal to approximately 200°C.

[0042] Referring to FIG. 1B , barrier layer 160 is shown positioned on SAM 150, i.e., above sidewalls 148. In one or more embodiments, barrier layer 160 has the same properties as barrier layer 120. In one or more embodiments, barrier layer 160 is not formed on bottom 149 of gap 146. In one or more embodiments, when SAM 150 is not present, the deposition of barrier layer 160 is substantially conformal. In one or more embodiments where SAM 150 is not present, barrier layer 160 is formed on sidewalls 148 and bottom 149 of gap 146. As used herein, a "substantially conformal" layer refers to a layer having a thickness that is substantially the same everywhere (e.g., on the top, middle, and bottom of sidewalls 148 and on bottom 149 of gap 146). A substantially conformal layer has a thickness variation of less than or equal to approximately 5%, 2%, 1%, or 0.5%. In one or more embodiments, barrier layer 160 is selectively deposited on at least a portion of sidewall 148. In one or more unillustrated embodiments, barrier layer 160 is selectively deposited on at least a portion of bottom 149. In one or more embodiments, barrier layer 160 may cover the entire sidewall 148.

[0043] In one or more embodiments, barrier layer 160 is selectively deposited using atomic layer deposition (ALD) to a thickness ranging from about 2 angstroms to about 10 angstroms. In some embodiments, barrier layer 160 is deposited in a single ALD cycle. In other embodiments, barrier layer 160 is deposited in 1 to 20 ALD cycles. In one or more embodiments, each of the 1 to 20 ALD cycles is configured to deposit barrier layer 160 to a thickness of about 0.5 angstroms.

[0044] In one or more embodiments, when barrier layer 160 is formed on bottom portion 149 and sidewalls 148, the ratio of the thickness of barrier layer 160 on sidewalls 148 to the thickness of barrier layer 160 on bottom portion 149 is greater than 6. In one or more cases, the ratio is greater than 5, greater than 4, greater than 3, greater than 2, or greater than 1. In one or more embodiments, when SAM 150 is present, the thickness of barrier layer 160 on sidewalls 148 ranges from 5 angstroms to 20 angstroms. In one or more embodiments, the thickness of barrier layer 160 on bottom portion 149 is less than or equal to 5 angstroms. In one or more embodiments, the thickness of barrier layer 160 on bottom portion 149 is less than or equal to 4 angstroms, less than or equal to 3 angstroms, less than or equal to 2 angstroms, or less than or equal to 1 angstrom. In one or more embodiments, barrier layer 160 is not formed on bottom portion 149.

[0045] Referring to FIG. 1C , a first metal liner 170 is shown positioned on the barrier layer 160 shown in FIG. 1B . In one or more embodiments, the first metal liner 170 has the same properties as the metal layer 130 . In one or more embodiments, the metal liner 170 is selectively deposited on the sidewalls 148 of the microelectronic element. In one or more embodiments, the first metal liner 170 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the first metal liner 170 comprises one or more of a single layer of ruthenium (Ru) or a single layer of cobalt (Co). In one or more embodiments, the first metal liner 170 comprises a single layer of ruthenium (Ru). In one or more embodiments, the first metal liner 170 comprises a single layer of ruthenium (Ru) selectively deposited on the sidewalls. In one or more embodiments, the first metal liner 170 comprises a multilayer film having a first liner film composed of the first metal M1 and a second liner film composed of the second metal M2. In one or more embodiments, the first metal liner 170 includes a first metal M1 including ruthenium (Ru) and a second metal M2 including cobalt (Co).

[0046] Embodiments of the present disclosure advantageously provide methods for forming microelectronic components that reduce via resistance by at least 20% compared to via resistance in microelectronic components without selectively deposited metal liners. In one or more embodiments, the via resistance of the microelectronic components described herein is reduced by at least 15%, at least 10%, or at least 5% compared to via resistance in microelectronic components without selectively deposited metal liners.

[0047] Using a typical deposition process, ruthenium (Ru) is deposited on the sidewalls and bottom. It has been found that when using the known deposition process for a period of 40 seconds, the ruthenium (Ru) layer deposited on the sidewalls has a thickness of 10 angstroms, while the ruthenium (Ru) layer deposited on the bottom has a thickness of approximately 3.87 angstroms. In one or more embodiments, the ratio of the thickness of the ruthenium (Ru) layer on the sidewalls to the thickness of the ruthenium (Ru) layer on the bottom is approximately 2.6.

[0048] It has been found that selectively depositing a single layer of ruthenium (Ru) according to embodiments of the methods described herein increases the ratio of the thickness of the metal liner on the sidewalls to the thickness of the metal liner on the bottom. In one or more embodiments, the thickness of the metal liner on the sidewalls is greater than the thickness of the metal liner on the bottom.

[0049] In one or more embodiments, when the metal liner 170 includes a single layer of ruthenium (Ru) selectively deposited on the sidewalls 148, the ratio of the thickness of the metal liner on the sidewalls 148 to the thickness of the metal liner 170 on the bottom 149 is greater than 3. In one or more embodiments, the ratio of the thickness of the metal liner on the sidewalls 148 to the thickness of the metal liner on the bottom 149 is greater than 4, greater than 5, greater than 6, or greater than 7. In one or more embodiments, the metal liner 170 is not formed on the bottom 149.

[0050] In one or more embodiments, when the metal liner 170 comprises a selectively deposited single layer of ruthenium (Ru), the thickness of the metal liner 170 on the sidewall 148 ranges from 5 angstroms to 20 angstroms. In one or more embodiments, when the metal liner 170 comprises a selectively deposited single layer of ruthenium (Ru), the thickness of the metal liner 170 on the bottom 149 is less than or equal to 5 angstroms. In one or more embodiments, when the metal liner 170 comprises a selectively deposited single layer of ruthenium (Ru), the thickness of the metal liner 170 on the bottom 149 is less than or equal to 4 angstroms, less than or equal to 3 angstroms, less than or equal to 2 angstroms, or less than or equal to 1 angstrom.

[0051] In one or more embodiments, the metal liner 170 comprising ruthenium (Ru) is selectively deposited using a selective ruthenium (Ru) deposition process. The selective ruthenium (Ru) deposition on the sidewalls comprises a cyclic deposition process including a ruthenium deposition step using a ruthenium (Ru) precursor carried by a carrier gas, such as argon (Ar). In one or more embodiments, the selective ruthenium (Ru) deposition further comprises an annealing or treatment step performed while flowing hydrogen (H2) and, optionally, a second gas, such as argon (Ar). In one or more embodiments, the selective ruthenium (Ru) deposition is performed in a substrate processing chamber, wherein the deposition step is performed while the chamber is at a first pressure, and the annealing step is performed while the chamber is at a second pressure greater than the first pressure. In one or more embodiments, the first pressure is in a range of 1 Torr to 5 Torr. In some embodiments, the first pressure is in a range of 1 Torr to 4 Torr, or in a range of 1 Torr to 3 Torr. In one or more embodiments, the second pressure is in a range of 10 Torr to 150 Torr. In some embodiments, the second pressure is in the range of 10 Torr to 40 Torr, or in the range of 10 Torr to 30 Torr. Thus, according to one or more embodiments, a cyclic deposition process includes a deposition step and an annealing / treatment step. In the deposition step, a ruthenium precursor (e.g., any suitable metal organic precursor, such as cyclohexadienyl ruthenium tricarbonyl (Ru3(Co)9)) is flowed in a carrier gas and a reactive gas (e.g., Ar and / or H2) for 2 to 10 seconds, for example, 3 to 6 seconds, to form a deposited ruthenium layer. In the annealing or treatment step, the deposited ruthenium layer is annealed or treated in the presence of a flowing gas (e.g., greater than 90% H2 and a second gas such as Ar) for 30 to 90 seconds, for example, 40 to 70 seconds. This cyclic deposition process, including cycles of deposition and annealing or treatment steps, is repeated multiple times to achieve a desired film thickness.

[0052] Referring to FIG. 1D , in one or more embodiments, an optional second metal liner 180 is illustrated positioned on the first metal liner 170. In one or more embodiments, the second metal liner 180 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the second metal liner 180 comprises one or more of ruthenium (Ru) or cobalt (Co). In one or more embodiments, the metal liner 180 comprises a single layer of cobalt (Co) deposited on the sidewalls. In one or more embodiments, when the metal liner 180 comprises a single layer of deposited cobalt (Co), the thickness of the metal liner 180 on the sidewalls 148 ranges from 5 angstroms to 20 angstroms. In one or more embodiments, when the metal liner 180 comprises a single layer of deposited cobalt (Co), the thickness of the metal liner 180 on the bottom 149 is less than or equal to 5 angstroms. In one or more embodiments, when the metal liner 180 comprises a single layer of deposited cobalt (Co), the thickness of the metal liner 180 on the bottom 149 ranges from 5 angstroms to 20 angstroms. In one or more embodiments, the second metal liner 180 is not formed on the bottom 149.

[0053] In one or more embodiments, the second metal liner 180 comprises a multilayer film having a first liner film composed of a first metal M1 and a second liner film composed of a second metal M2. In one or more embodiments, the second metal liner 180 comprises a first metal M1 comprising ruthenium (Ru) and a second metal M2 comprising cobalt (Co). In one or more embodiments, when the second metal liner 180 comprises a first metal M1 comprising ruthenium (Ru) and a second metal M2 comprising cobalt (Co), the combined thickness of the multilayer film on the sidewall 148 ranges from 10 angstroms to 20 angstroms. In one or more embodiments, when the second metal liner 180 comprises a first metal M1 comprising ruthenium (Ru) and a second metal M2 comprising cobalt (Co), the combined thickness of the multilayer film on the bottom 149 ranges from 5 angstroms to 20 angstroms.

[0054] In one or more embodiments, the microelectronic element 100 includes one or more of a first metallic liner 170 and a second metallic liner 180. In one or more embodiments, the first metallic liner 170 is the same as the second metallic liner 180. In one or more embodiments, the first metallic liner 170 is different from the second metallic liner 180.

[0055] In some embodiments, the bimetallic liner film comprises an alloy of two metals in a single layer. In some embodiments, the bimetallic liner film includes alternating layers of two metals, M1 and M2, or alternating layers of a first metal liner film and a second metal liner film. In one or more embodiments, the two metals include two metals selected from the group consisting of: (M1) Co and (M2) Tantalum (Ta); (M1) Co and (M2) Molybdenum (Mo); (M1) Ru and (M2) Ta; (M1) Ru and (M2) W; (M1) Ru and (M2) Mo; (M1) Co and (M2) Ru; and (M1) Ru and (M2) Co. In one or more embodiments, the bimetallic liner film has a thickness of less than 20 angstroms.

[0056] According to one or more embodiments, the bimetallic liner film can be formed using various deposition methods, including alternating and / or co-flowing of ALD / CVD / PE-ALD precursors (precursors with multi-metallic ligands), dopant implantation, and / or thermal diffusion. The bimetallic liner film can be formed in a single processing chamber or in multiple processing chambers. In one or more embodiments, the bimetallic liner film can be processed using various methods, including thermal, plasma, and / or chemical treatments.

[0057] Advantageously, ultrathin (e.g., 20 angstroms or less thick) bimetallic liner films according to one or more embodiments provide improved interfacial adhesion and mobility between two metals, such as a barrier layer and a gapfill metal. The bimetallic liner films and methods described according to one or more embodiments can be used in metal contact, interconnect, and capping applications. Bimetallic liner films according to one or more embodiments are thinner than current liners, which are typically greater than 20 angstroms and up to 30 angstroms. In some embodiments, the bimetallic liner film comprises two metals and has a thickness ranging from 10 to 20 angstroms, 10 to 19 angstroms, 10 to 18 angstroms, 10 to 17 angstroms, 10 to 16 angstroms, 10 to 15 angstroms, 10 to 14 angstroms, 10 to 13 angstroms, or 10 to 12 angstroms. The dual-metal liner films described herein can extend metal fill and capping to advanced nodes, such as achieving copper reflow in the 3nm / 2nm nodes, low resistivity in middle-of-the-line (MOL) and back-end-of-line (BEOL) processes, and memory. The methods described herein can also simplify current complex integrated circuit systems to a single or multiple chamber process involving CVD / ALD / PVD / PEALD / ion implantation.

[0058] In one or more embodiments, the barrier layer and / or metal film can be deposited using ALD. In a typical ALD process, the film is deposited using alternating pulses or flows of an "A" precursor and a "B" precursor. The surface is exposed to the reactants "A" and "B" alternately until a film having the desired thickness is achieved. However, as an alternative to pulsing the reactants, gases can be simultaneously flowed from one or more gas delivery heads or nozzles, and the substrate and / or gas delivery heads can be moved so that the substrate is exposed to each reactant gas sequentially. Of course, the aforementioned ALD cycles are merely examples of various ALD process cycles in which the deposited layers are formed from alternating layers of precursors and co-reactants.

[0059] In one or more embodiments, the co-reactant is in vapor or gaseous form. The reactant may be delivered using a carrier gas. The carrier gas, purge gas, deposition gas, or other process gas may contain nitrogen, hydrogen, argon, neon, helium, or combinations thereof. The various plasmas described herein, such as nitrogen plasma or inert gas plasma, may be ignited using and / or contain a plasma co-reactant gas.

[0060] In one or more embodiments, the various gases used in the process can be pulsed through the gas channels from various holes or outlets into the inlet and into the central channel. In one or more embodiments, the deposition gases can be pulsed sequentially into and through the showerhead. Alternatively, as described above, the gases can flow simultaneously through the gas supply nozzles or heads, and the substrate and / or gas supply head can be moved so that the substrate is exposed to the gases sequentially.

[0061] In one or more embodiments, a multi-chamber process is used to deposit the barrier material and liner film, and to separate the barrier material (e.g., tantalum nitride (TaN)) and the metal liner film. In other embodiments, a single-chamber approach is used, where all processes are performed in a single chamber, and the different layers / films are separated during processing using gas purges.

[0062] Some embodiments of the present disclosure are directed to barrier applications, such as copper barrier applications. A barrier layer formed from one or more embodiments can be used as a copper barrier. Suitable barrier layers for copper barrier applications include, but are not limited to, TaN and MnN. For copper barrier applications, suitable dopants include, but are not limited to, ruthenium, copper, cobalt, manganese, aluminum, tantalum, molybdenum, niobium, vanadium, or combinations thereof. Plasma treatment can be used after doping to promote intermetallic compound formation between the matrix and the dopant, remove film impurities, and increase the density of the barrier layer. In other embodiments, post-treatment may include, but is not limited to, physical vapor deposition (PVD) processing, thermal annealing, chemical enhancement, and the like. In some copper barrier applications, high-frequency plasma (defined as greater than approximately 14 MHz or approximately 40 MHz or higher) can be used with any inert gas, including, but not limited to, one or more of neon (Ne), hydrogen (H₂), and argon (Ar). In one or more embodiments, higher plasma frequencies (above 13.56 MHz) can be used to prevent low-k dielectric constant damage. In some embodiments, the barrier layer is a copper barrier and includes TaN doped with Ru.

[0063] Suitable precursors for depositing the liner layer include metal-containing precursors, such as carbonyl- and cyclopentadiene-containing precursors. In a non-limiting example, if the liner layer is RuCo, the Ru-containing precursor may be triruthenium dodecacarbonyl (Ru3(CO)12), while the Co-containing precursor may be dicobalt tributylacetyl hexacarbonyl (CCTBA). If the liner layer is TaRu, the Ta-containing precursor may be penta(dimethylamido)tantalum (PDMAT). Other suitable precursors are known to those skilled in the art. Organic species in organic-containing precursors for the liner layer may be partially incorporated into underlying layers (such as barrier or dielectric layers), which may enhance adhesion at the interface between the liner layer and the underlying layer.

[0064] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" means that the precursors flow in parallel or that the exposure of a substantial portion of the precursors overlaps.

[0065] The metal liner film can be formed by depositing alternating layers of two metals via CVD, PVD, or ALD, or by co-reacting two metal precursors. Depending on the liner metal used, a co-reactant or co-precursor can be used to deposit the liner film. In one or more embodiments, ion implantation can be used to incorporate the second metal into the liner film composed of the first metal. In other embodiments, a physical vapor deposition (PVD) co-process can be used to add the second metal to the doped liner film formed on the barrier layer. In further embodiments, the liner film can be annealed in an atmosphere containing the second metal to thermally diffuse the second metal into the liner film of the first metal, thereby forming the liner film on the barrier layer.

[0066] In one or more embodiments, a PVD process using sputtering can be used to incorporate an optional second metal into a liner film comprising the first metal. For example, a PVD process using cobalt (Co) can implant Co into a ruthenium film to form a liner film comprising ruthenium and cobalt.

[0067] In some embodiments, instead of using a co-reactant, or in addition to using a co-reactant, a post-plasma treatment step may be used after exposing the liner film comprising the first metal to the optional second metal precursor. According to one or more embodiments, the plasma comprises any suitable inert gas known to those skilled in the art. In one or more embodiments, the plasma comprises one or more of helium (He), argon (Ar), ammonia (NH₃), hydrogen (H₂), and nitrogen (N₂). In some embodiments, the plasma may comprise a mixture of Ar and H₂, such as a mixture having an Ar:H₂ molar ratio in the range of 1:1 to 1:15. The plasma power may be in the range of approximately 200 watts to approximately 1000 watts. The plasma frequency may be in the range of 350 kHz to 40 MHz. The plasma treatment time may vary from 5 seconds to 60 seconds, such as in the range of 10 seconds to 30 seconds. In some embodiments, the pressure during the plasma treatment may be in the range of 0.5 Torr to 50 Torr, such as in the range of 1 to 10 Torr. In some embodiments, the wafer pitch may be in the range of 100 mils to 600 mils.

[0068] In one or more embodiments, a liner film comprising a first metal may be exposed to a second metal precursor during deposition. That is, the second metal precursor may be used sequentially in an ALD cycle to provide a liner film comprising two metals on the barrier layer. In various embodiments, the duration of exposure to the second metal-containing precursor may be in a range of 1 second to 60 seconds, such as 3 seconds to 30 seconds or 5 seconds to 10 seconds. Longer exposure to the second metal precursor increases the amount of the second metal in the bimetallic liner film. In one or more embodiments, the bimetallic liner film is formed through a cyclic deposition process.

[0069] Referring to FIG. 1E , in one or more embodiments, the SAM 150 is removed from the structure shown in FIG. 1D using the methods described herein. In one or more embodiments, removing the SAM 150 includes a plasma treatment process that includes flowing one or more gases selected from hydrogen (H 2 ) or argon (Ar). In one or more embodiments, the plasma treatment process includes increasing the density of the barrier layer 160. In one or more embodiments, the gapfill process includes filling the gap 146 shown in FIG. 1E with one or more of copper (Cu) or cobalt (Co).

[0070] 2A and 2B , a portion of a microelectronic device 200 is illustrated at various stages of fabrication according to an alternative embodiment of the present disclosure. In one or more embodiments, the microelectronic device 200 includes a substrate 210, a barrier layer 220 on the substrate 210, a metal liner 230 on the barrier layer 220, a conductive gap 240, an aluminum oxide etch stop layer 242, and a dielectric layer 245 on the aluminum oxide etch stop layer 242. The dielectric layer 245 includes at least one feature defining a gap 246. The gap 246 includes sidewalls 248 and a bottom 249. In one or more embodiments, a first passivation layer (e.g., a first self-assembled monolayer (SAM)) 250 is formed on the bottom 249 of the gap.

[0071] In one or more embodiments, the features of the microelectronic components shown in Figures 1A-1E and 2A-2G share common characteristics, including materials, manufacturing methods, dimensions, etc. In one or more embodiments, substrate 210, barrier layer 220 on the substrate, metal liner 230 on barrier layer 220, conductive fill gap 240, aluminum oxide etch stop layer 242, and dielectric layer 245 on aluminum oxide etch stop layer 242 include at least one feature defining gap 246, gap 246 including sidewalls 248 and a bottom 249. A first SAM 250 is formed by flowing a hydrocarbon entrained in argon (Ar) gas. In one or more embodiments, first SAM 250 includes an unsaturated hydrocarbon. In one or more embodiments, first SAM 250 is deposited on dielectric layer 245.

[0072] Referring to FIG. 2B , a barrier layer 260 is shown formed on the first SAM 250 and the sidewalls 248. In FIG. 2C , the first SAM 250 has been removed. In one or more embodiments, removing the first SAM 250 includes a plasma treatment process that includes flowing one or more gases selected from hydrogen (H 2 ) or argon (Ar). In one or more embodiments, the plasma treatment process increases the density of the barrier layer 260.

[0073] Referring now to FIG. 2D , after removing the first SAM 250, a second passivation layer (e.g., a second self-assembled monolayer (SAM)) 255 is shown formed on the gap bottom 249, the barrier layer 260, and the gap bottom 249. In one or more embodiments, the first SAM 250 and the second SAM 255 are identical. In one or more embodiments, the first SAM 250 and the second SAM 255 are different. Referring now to FIG. 2E , a first metal liner 270 is shown deposited on the barrier layer 260. Referring now to FIG. 2F , in one or more embodiments, an optional second metal liner 280 is shown formed on the first metal liner 270.

[0074] Referring to FIG. 2G , the second SAM 255 has been removed. In one or more embodiments, the first SAM 250 and the second SAM 255 can be removed by the same process. In one or more embodiments, removing one or more of the first SAM and the second SAM includes a plasma treatment process that includes flowing one or more gases selected from hydrogen (H 2 ) or argon (Ar). In one or more embodiments, the plasma treatment process increases the density of the barrier layer 260.

[0075] FIG3 illustrates a process flow diagram of a method 300 for forming a microelectronic component. FIG3 illustrates a method for forming any of the microelectronic components of one or more embodiments shown in FIG1A through FIG1E. Referring to FIG3, method 300 includes forming a dielectric layer on a substrate at operation 310. The dielectric layer includes at least one feature defining a gap, the gap including sidewalls and a bottom. At operation 320, method 300 includes selectively depositing a self-assembled monolayer (SAM) at the bottom of the gap. At operation 330, method 300 includes forming a barrier layer on the SAM. At operation 340, method 300 includes selectively depositing a metal liner on the barrier layer. At operation 340, in some embodiments, the metal liner is deposited to a greater thickness on the sidewalls than on the bottom. In one or more embodiments, at operation 340, the metal liner is selectively deposited on the sidewalls rather than on the bottom. At operation 350, method 300 includes removing the SAM after selectively depositing the metal liner on the barrier layer. At operation 360, method 300 includes performing a gap-fill process on the metal liner. The gap-fill process may include forming one or more of vias and lines to form interconnects in the device.

[0076] FIG4 illustrates a process flow diagram of a method 400 for forming a microelectronic component. FIG4 illustrates a method for forming any of the microelectronic components of one or more embodiments shown in FIG2A through FIG2G. Referring to FIG4, method 400 includes forming a dielectric layer on a substrate at operation 410. The dielectric layer includes at least one feature defining a gap, the gap including sidewalls and a bottom. At operation 420, method 400 includes selectively depositing a first self-assembled monolayer (SAM) at the bottom of the gap. At operation 430, method 400 includes forming a barrier layer on the first SAM. At operation 440, method 400 includes removing the first SAM after forming the barrier layer. At operation 450, method 400 includes selectively depositing a second self-assembled monolayer (SAM) on the barrier layer after removing the first SAM.

[0077] At operation 460, method 400 includes selectively depositing a metal liner on the barrier layer. At operation 460, in some embodiments, the metal liner is deposited to a greater thickness on the sidewalls than on the bottom. In one or more embodiments, at operation 460, the metal liner is selectively deposited on the sidewalls, but not on the bottom. At operation 470, method 400 includes removing the second SAM after selectively depositing the metal liner on the barrier layer. At operation 480, method 400 includes performing a gapfill process on the metal liner. The gapfill process may include forming one or more of a via and a line to form an interconnect in the device.

[0078] In one or more embodiments, the methods described herein include optional post-processing operations. The optional post-processing operations may be, for example, processes that modify film properties (e.g., annealing) or further film deposition processes (e.g., additional ALD or CVD processes) to grow additional films. In some embodiments, the optional post-processing operations may be processes that modify the properties of the deposited film. In some embodiments, the optional post-processing operations include annealing the deposited film. In some embodiments, the annealing is performed at a temperature in the range of approximately 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C. In some embodiments, the annealing environment includes one or more of the following: an inert gas (e.g., molecular nitrogen (N2), argon (Ar)), a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)), or an oxidizing agent (e.g., but not limited to, oxygen (O2), ozone (O3), or peroxide). The annealing may be performed for any suitable duration. In some embodiments, the film is annealed for a predetermined time in a range of about 15 seconds to about 90 minutes, or in a range of about 1 minute to about 60 minutes. In some embodiments, annealing the deposited film increases the density of the metal liner layer, reduces the resistivity of the metal liner layer, and / or increases the purity of the metal liner layer.

[0079] In some embodiments, the substrate is moved from the first chamber to a separate, subsequent chamber for further processing. The substrate can be moved directly from the first chamber to a separate processing chamber, or it can be moved from the first chamber to one or more transfer chambers, and then to a separate processing chamber. In some embodiments, the deposition of the barrier layer and dopant film can be performed in a single chamber, followed by post-processing in separate chambers. Thus, a processing apparatus can include multiple chambers connected to a transfer station. Such an apparatus may be referred to as a "cluster tool," "cluster system," or the like.

[0080] Generally speaking, a cluster tool is a modular system that includes multiple chambers that perform various functions, including substrate centering and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, a cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can house a robot that transfers substrates between processing chambers and a load lock chamber. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate stage for transferring substrates from one chamber to another and / or to a load lock chamber located at the front end of the cluster tool. However, the exact arrangement and combination of chambers may vary to perform specific steps of the processes described herein. Other process chambers that may be used include, but are not limited to, cyclic deposition including a deposition step and an annealing or treatment step, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, plasma nitridation, degassing, orientation, hydroxylation, and other substrate processing. By performing the process in a chamber on a cluster tool, surface contamination of the substrate by atmospheric impurities is avoided without oxidation prior to deposition of subsequent films.

[0081] According to one or more embodiments, substrates are continuously held under vacuum or "load lock" conditions and are not exposed to ambient air while being transferred from one chamber to the next. Thus, the transfer chamber is held in a vacuum state and "evacuated" at vacuum pressure. An inert gas may be present in either the processing chamber or the transfer chamber. In some embodiments, the inert gas is used as a purge gas to remove some or all reactants (e.g., reactants). According to one or more embodiments, a purge gas is introduced at the exit of the deposition chamber to prevent reactants (e.g., reactants) from migrating from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, the inert gas flow forms a gas curtain at the chamber exit.

[0082] Substrates can be processed in a single-substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before processing another substrate. Substrates can also be processed in a continuous manner similar to a conveyor system, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The chamber and associated conveyor system can be shaped to form a linear or curved path. Furthermore, the processing chamber can be a carousel, where multiple substrates move about a central axis and are exposed to deposition, etching, annealing, cleaning, and other processes throughout the carousel path.

[0083] During processing, the substrate may be heated or cooled. This heating or cooling can be achieved by any suitable means, including but not limited to changing the temperature of the substrate support and flowing heated or cooled gas toward the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to change the substrate temperature by conduction. In one or more embodiments, the gas being used (reactive or inert) is heated or cooled to locally change the substrate temperature. In some embodiments, the heater / cooler is located within the chamber adjacent to the substrate surface to change the substrate temperature by convection.

[0084] The substrate can be stationary or rotated during processing. Rotating the substrate can occur continuously (around the substrate axis) or in discrete steps. For example, the substrate can be rotated throughout the entire process, or it can be rotated slightly between exposures to different reactive or purge gases. Rotating the substrate (continuously or in steps) during processing can help produce more uniform deposition or etching by minimizing the effects of local variability, such as gas flow geometry.

[0085] Another aspect of the present disclosure relates to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform the operations of the methods described herein. In one embodiment, the non-transitory computer-readable medium comprising instructions, when executed by a controller of a processing system, causes the processing system to perform the operations of the methods described herein with respect to Figures 1A-1E, Figures 2A-2G, and Figures 3 and 4.

[0086] Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "certain embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0087] Although the present disclosure has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to encompass such modifications and variations as come within the scope of the appended claims and their equivalents.

[0088] 100:Microelectronic components 110:Substrate 120: Barrier layer 130:Metal layer 140: Conductive filling gap 142: Aluminum oxide etch stop layer 145: dielectric layer 146: Gap 146L: Line part 146V: Through-hole part 148: Sidewall 149: bottom 150:SAM 160: Barrier layer 170: First metal liner 180: Second metal liner 200:Microelectronic components 210:Substrate 220: Barrier layer 230:Metal liner 240: Conductive filling gap 242: Aluminum oxide etch stop layer 245: dielectric layer 246: Gap 246L: Line part 246V: Through-hole part 248: Sidewall 249: bottom 250: first passivation layer | first SAM 255: Second passivation layer | Second SAM 260: Barrier layer 270: First metal liner 280: Second metal liner 300: Method 310: Operation 320: Operation 330: Operation 340: Operation 350: Operation 360: Operation 400:Method 410: Operation 420: Operation 430: Operation 440: Operation 450: Operation 460: Operation 470: Operation 480: Operation

[0089] Domestic storage information (please note the order of storage institution, date, and number) none Overseas deposit information (please note the order of deposit country, institution, date, and number) none

Claims

1. A method for forming a microelectronic device, the method comprising the steps of: forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the gap including sidewalls and a bottom; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap by exposing the bottom of the gap to a hydrocarbon carried in a carrier gas, the hydrocarbon having a chemical formula HC≡CR, wherein R is an alkyl straight-chain or an aryl group comprising 1 to 20 carbon atoms; forming a barrier layer on the bottom of the gap and on the sidewalls; selectively depositing a first metal pad on the barrier layer, wherein the thickness of the first metal pad deposited on the sidewalls is greater than the thickness of the first metal pad deposited on the bottom; A second metal liner is selectively deposited on the first metal liner to form a bimetallic liner, the second metal liner comprising a metal different from the first metal liner, the bimetallic liner having a thickness in the range of 10 angstroms to 20 angstroms on the sidewalls and a thickness in the range of 5 angstroms to 20 angstroms on the bottom; the SAM is removed after selectively depositing the second metal liner on the first metal liner; and a gap filling process is performed on the second metal liner.

2. The method of claim 1, wherein the first metal liner comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), and tantalum (Ta).

3. The method of claim 2, wherein when the first metal pad comprises a single layer of ruthenium (Ru) selectively deposited on the sidewalls, the thickness of the first metal pad on the bottom is less than 10 angstroms.

4. The method of claim 3, wherein the selective ruthenium (Ru) deposition on the sidewalls comprises a cyclic deposition process that forms a deposited ruthenium layer by using a ruthenium (Ru) precursor carried by an argon (Ar) gas.

5. The method of claim 4, wherein the cyclic deposition process further includes annealing the deposited ruthenium layer while hydrogen (H2) is flowing, and annealing the deposited ruthenium layer.

6. The method of claim 5, wherein the cyclic deposition process is performed in a substrate processing chamber under a first pressure to form the deposited ruthenium layer, and annealing of the deposited ruthenium layer is performed when the substrate processing chamber is under a second pressure greater than the first pressure.

7. The method as described in claim 1, wherein R is an aryl group.

8. The method of claim 1, wherein R is a linear alkyl chain.

9. The method of claim 1, wherein removing the SAM includes a plasma processing process that includes flowing one or more gases, such as hydrogen (H2) or argon (Ar).

10. The method of claim 1, wherein the gap-filling process includes filling the gap with one or more of copper (Cu) or cobalt (Co).

11. The method as described in claim 1, wherein, The carrier gas includes argon (Ar).

12. The method as described in claim 1, wherein, The barrier layer includes tantalum nitride (TaN) or manganese nitride (MnN).

13. The method as described in claim 2, wherein, The second metal liner includes one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), and tantalum (Ta).

14. A method of forming a microelectronic device, the method comprising the steps of: forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the gap including sidewalls and a bottom; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap by exposing the bottom of the gap to a hydrocarbon carried in a carrier gas, the hydrocarbon having a chemical formula HC≡CR, wherein R is an alkyl straight-chain or an aryl group comprising 1 to 20 carbon atoms; forming a barrier layer on the bottom of the gap and on the sidewalls; selectively depositing a first metal pad on the barrier layer, the first metal pad comprising ruthenium (Ru); selectively depositing a second metal pad on the first metal pad, the second metal pad comprising cobalt (Co); removing the SAM after selectively depositing the second metal pad on the first metal pad; and performing a gap-filling process on the second metal pad.

15. The method as described in claim 14, wherein, R is an aryl group.

16. The method as described in claim 14, wherein, R is a straight-chain alkyl group.

17. A method of forming a microelectronic device, the method comprising the steps of: forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the gap including sidewalls and a bottom; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap by exposing the bottom of the gap to a hydrocarbon carried in a carrier gas, the hydrocarbon having a chemical formula R'C=CR", wherein R' and R" independently comprise an alkyl straight chain or an aryl group comprising 1 to 20 carbon atoms; forming a barrier layer on the bottom of the gap and on the sidewalls; selectively depositing a first metal pad on the barrier layer; selectively depositing a second metal pad on the first metal pad, the first metal pad and the second metal pad each independently comprising ruthenium (Ru), cobalt (Co), molybdenum (Mo) or tantalum (Ta), and the first metal pad comprising a metal different from the second metal pad; After selectively depositing the second metal liner on the first metal liner, the SAM is removed; and a gap filling process is performed on the second metal liner.

18. The method as described in claim 17, wherein, R' and R" each independently contain a straight alkyl chain.

19. The method as described in claim 17, wherein, R' and R" each independently contain an aryl group.

20. The method as described in claim 17, wherein, The first metal liner includes ruthenium (Ru) and the second metal liner includes cobalt (Co).

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