Electronic package and manufacturing method thereof

Abstract

An electronic package and its manufacturing method are disclosed, wherein an electronic component is embedded in the package layer, and the electronic component has a first electrode pad and a second electrode pad on opposite sides to form a double-sided power supply structure, so that the circuit structure and wiring structure on opposite sides of the electronic component can be electrically connected to the first electrode pad and the second electrode pad, thereby helping to reduce power loss.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to an electronic package that can improve product performance and its manufacturing method. Prior Technology

[0002] In recent years, with the continuous maturation and development of semiconductor manufacturing technology, various high-performance electronic products have been constantly being introduced, and the functions of electronic products have developed towards humanization and multi-functionality. However, electronic products contain various integrated circuit (IC) components with different functions. In the manufacturing process of electronic components, integrated circuit packaging (IC packaging) plays a very important role. IC packaging types can be broadly classified into two categories: pin-in-hole (PIH) and surface mount technology (SMT). Pin-in-hole types include dual in-line packages (DIP) and pin grid arrays (PGA), while surface mount types include wire bonding packages (WB), tape automatic bonding (TAB), flip chip (FC), ball grid array packages (BGA), and fan-out packages. Each type of packaging has its own characteristics and application areas.

[0003] However, it is known that regardless of the packaging method used in semiconductor packaging processes, the performance of end products has gradually reached a bottleneck, for example, the problem of excessive power loss remains difficult to solve.

[0004] Therefore, how to overcome the shortcomings of conventional technology is a technical problem that all sectors urgently need to solve. Summary of the Invention

[0005] In view of the various deficiencies of the prior art, the present invention provides an electronic package comprising: a package layer; an electronic component embedded in the package layer, wherein the electronic component has a first side and a second side opposite to each other, the first side having a plurality of first electrode pads and the second side having a plurality of second electrode pads; a circuit structure disposed on the first side of the electronic component and electrically connected to the plurality of first electrode pads; and a wiring structure disposed on the second side of the electronic component and electrically connected to the plurality of second electrode pads, wherein the wiring structure has a plurality of electrical functional pads and a plurality of conductive blind vias, such that a single electrical functional pad is electrically connected to a single second electrode pad through the plurality of conductive blind vias.

[0006] The present invention also provides a method for manufacturing an electronic package, comprising: encapsulating an electronic component by a packaging layer, wherein the electronic component has a first side and a second side opposite to each other, the first side having a plurality of first electrode pads, and the second side having a plurality of second electrode pads; forming a circuit structure on the first side of the electronic component to electrically connect the circuit structure to the plurality of first electrode pads; and forming a wiring structure on the second side of the electronic component to electrically connect the wiring structure to the plurality of second electrode pads, wherein the wiring structure has a plurality of electrical functional pads and a plurality of conductive blind vias, such that a single electrical functional pad is electrically connected to a single second electrode pad through the plurality of conductive blind vias.

[0007] In the aforementioned electronic package and its manufacturing method, the function of the first electrode pad is different from the function of the second electrode pad.

[0008] In the aforementioned electronic package and its manufacturing method, the first electrode pad is a signal pad, and the second electrode pad is a power pad. Alternatively, the second electrode pad is a signal pad, and the first electrode pad is a power pad. Furthermore, the width of the power pad is different from the width of the signal pad. For example, the width of the power pad is greater than the width of the signal pad.

[0009] The aforementioned electronic package and its manufacturing method further include embedding a plurality of conductive pillars in the package layer so that the plurality of conductive pillars electrically connect the circuit structure and the wiring structure.

[0010] The aforementioned electronic package and its manufacturing method further include mounting an electronic device on the circuit structure so that the electronic device is electrically connected to the circuit structure.

[0011] The aforementioned electronic package and its manufacturing method further include forming a covering layer on the circuit structure.

[0012] The aforementioned electronic package and its manufacturing method further include mounting an electronic device on the wiring structure so that the electronic device is electrically connected to the wiring structure.

[0013] As can be seen from the above, in the electronic package and manufacturing method of the present invention, the electronic component mainly has a first electrode pad and a second electrode pad on opposite sides to form a double-sided power supply structure, so that the electrical functional pad can be electrically connected to the second electrode pad through a plurality of conductive blind holes. Therefore, compared with the prior art, when both the electrical functional pad and the second electrode pad are power pads, the electronic package of the present invention can reduce power loss. Simple Explanation of the Diagram

[0014] Figures 1A to 1F are cross-sectional schematic diagrams illustrating the manufacturing method of the first embodiment of the electronic package of the present invention.

[0015] Figure 1E-1 is a partially enlarged schematic diagram of Figure 1E.

[0016] Figures 2A and 2B are cross-sectional schematic diagrams of other states of Figure 1F.

[0017] Figure 3 is a cross-sectional schematic diagram of the manufacturing method of the second embodiment of the electronic package of the present invention. Implementation

[0018] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0019] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are only for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0020] Figures 1A to 1F are cross-sectional schematic diagrams illustrating the manufacturing method of the first embodiment of the electronic package 2 of the present invention.

[0021] As shown in Figures 1A and 1B, a carrier plate 9 with a seed layer 9a is provided, and a plurality of conductive pillars 23 are formed on the carrier plate 9 by means of the seed layer 9a. Next, at least one electronic component 21 is disposed on the carrier plate 9, wherein the electronic component 21 is coupled and electrically connected to a plurality of conductors 22, and the conductors 22 are such as conductive lines, spherical solder balls, or columnar metal materials such as copper pillars, solder bumps, or stud conductive parts made by wire bonding machines, but are not limited to these.

[0022] The carrier plate 9 is, for example, a plate made of semiconductor material (such as silicon or glass), on which a release layer 90, a metal layer 9b such as titanium / copper, and an insulating layer 91 such as dielectric material or solder resist are sequentially formed by coating, for example, so that the seed layer 9a is disposed on the insulating layer 91.

[0023] In this embodiment, a patterned resist layer (not shown) may be formed on the seed layer 9a, so that a portion of the surface of the seed layer 9a is exposed to allow the conductive pillars 23 to be arranged. After the conductive pillars 23 are fabricated, the patterned resist layer and the seed layer 9a below it are removed, as shown in FIG1B.

[0024] Furthermore, the material forming the conductive pillar 23 is a metal such as copper or solder, and the material forming the seed layer 9a is, for example, titanium / copper.

[0025] The electronic component 21 is a semiconductor wafer with a first side 21a and a second side 21b. The first side 21a has a plurality of first electrode pads 210, and the second side 21b has a plurality of second electrode pads 213.

[0026] In this embodiment, the electronic component 21 belongs to the technical field of back-end power supply chips. The difference between it and traditional chips is that in traditional chips, the signal (I / O signal), power, and ground lines of components are transmitted outwards in the same direction through dielectric materials and copper wires, and then connected to external circuits such as copper pillars, solder balls, and the substrate. However, to increase transmission speed and reduce power loss, back-end power supply chips can thin the back of the component and extend the power and ground connections from the back. Therefore, the first electrode pad 210 and the second electrode pad 213 are not electrically connected through a through-silicon via (TSV), meaning that the electronic component 21 is not in the form of a through-silicon interposer (TSI).

[0027] Furthermore, the electronic component 21 is bonded to the insulating layer 91 by means of a bonding layer 212 on its second side 21b, and the first side 21a has a protective film 211, such as a passivation material, so that the conductor 22 is formed in the protective film 211.

[0028] Furthermore, the function of the first electrode pad 210 differs from that of the second electrode pad 213. For example, the first electrode pad 210 may be a signal pad, and the second electrode pad 213 may be a power pad. Alternatively, the second electrode pad 213 may be a signal pad, and the first electrode pad 210 may be a power pad. Further, the width D2 of the power pad differs from the width D1 of the signal pad. For example, the width D2 of the power pad (such as the second electrode pad 213) may be greater than the width D1 of the signal pad (such as the first electrode pad 210).

[0029] As shown in Figure 1C, an encapsulation layer 25 is formed on the insulating layer 91 of the carrier plate 9 so that the encapsulation layer 25 covers the electronic component 21, the conductors 22 and the conductive pillars 23. The encapsulation layer 25 has a first surface 25a and a second surface 25b opposite to each other. The protective film 211, the end face 22a of the conductor 22 and the end face 23a of the conductive pillar 23 are exposed on the first surface 25a of the encapsulation layer 25, and the encapsulation layer 25 is bonded to the insulating layer 91 of the carrier plate 9 with its second surface 25b.

[0030] In this embodiment, the encapsulation layer 25 is an insulating material, such as polyimide (PI), dry film, or an encapsulating colloid or molding compound such as epoxy resin. For example, the encapsulation layer 25 can be formed on the insulating layer 91 by means of liquid compounding, injection, lamination, or compression molding.

[0031] Furthermore, a leveling process can be used to make the first surface 25a of the encapsulation layer 25 flush with the protective film 211, the end face 23a of the conductive pillar 23, and the end face 22a of the conductor 22, so that the end face 23a of the conductive pillar 23 and the end face 22a of the conductor 22 are exposed on the first surface 25a of the encapsulation layer 25. For example, the leveling process is carried out by grinding to remove part of the material of the protective film 211, part of the material of the conductive pillar 23, part of the material of the conductor 22, and part of the material of the encapsulation layer 25.

[0032] As shown in Figure 1D, a circuit structure 20 is formed on the first surface 25a of the encapsulation layer 25, and the circuit structure 20 is electrically connected to the conductive post 23 and the conductor 22.

[0033] In this embodiment, the circuit structure 20 includes multiple insulating layers 200 and multiple circuit layers 201 disposed on the insulating layers 200, such as a redistribution layer (RDL) specification, so that the circuit layers 201 electrically connect the conductive post 23 and the conductor 22, and the outermost insulating layer 200 can serve as a solder resist layer, so that the outermost circuit layer 201 is exposed to the solder resist layer to serve as an electrical contact pad 202, such as a micro pad (commonly known as a μ-pad). Alternatively, the circuit structure 20 may also include only a single insulating layer 200 and a single circuit layer 201.

[0034] Furthermore, the material forming the circuit layer 201 is copper, and the material forming the insulation layer 200 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP), or a solder resist such as green paint or ink.

[0035] As shown in Figure 1E, the carrier plate 9 and its release layer 90 and metal layer 9b are removed, while the insulating layer 91 is retained. Next, a wiring structure 29 electrically connecting the conductive post 23 is formed on the insulating layer 91. The wiring structure 29 has a plurality of conductive blind holes 290 electrically connecting the second electrode pad 213, so that a single second electrode pad 213 is connected to a plurality of (e.g., three) conductive blind holes 290 to obtain the electronic package 2 of the present invention.

[0036] In this embodiment, when peeling off the release layer 90, the metal layer 9b is used as a barrier to avoid damaging the insulating layer 91. After removing the carrier plate 9 and the release layer 90 thereon, the metal layer 9b is removed by etching.

[0037] Furthermore, the insulating layer 91 is formed with a plurality of openings by laser processing, so that the end faces 23a of the conductive pillars 23 and part of the second surface 25b of the encapsulation layer 25 are exposed through the openings for bonding the wiring structure 29. For example, the wiring structure 29 can be formed on the insulating layer 91 by RDL process, which has a plurality of electrical functional pads 291 to bond conductive components 24 such as solder bumps, copper bumps or other conductive elements.

[0038] Therefore, by providing a carrier plate 9 with an insulating layer 91, the wiring structure 29 can be formed using the insulating layer 91 after the carrier plate 9 is removed, so that there is no need to lay a dielectric layer, thus saving process time and process steps, thereby reducing process costs.

[0039] Furthermore, a single electrical functional pad 291 is connected to a plurality of (e.g., three) conductive blind vias 290, as shown in Figure 1E-1. For example, both the electrical functional pad 291 and the second electrode pad 213 are power supply pads.

[0040] In other embodiments, as shown in FIG1F, a covering layer 28 may be formed on the circuit structure 20. The covering layer 28 is an insulating material, such as polyimide (PI), dry film, an encapsulating colloid or molding compound such as epoxy resin, and can be formed on the circuit structure 20 by lamination or molding. It should be understood that the material of the covering layer 28 may be the same as or different from the material of the encapsulating layer 25.

[0041] Alternatively, as shown in Figure 2A, the electronic package 3a may have at least one electronic device 26 disposed on the circuit structure 20, and the electronic device 26 may be covered by the covering layer 28.

[0042] The electronic device 26 is electrically connected to the electrical contact pad 202 by a plurality of conductive bumps 27, such as solder bumps, copper bumps or others.

[0043] In this embodiment, there are no particular restrictions on the configuration of multiple electronic devices 26, such as graphics processing units (GPUs) and high-bandwidth memory (HBM) chips.

[0044] Furthermore, an Under Bump Metallurgy (UBM) 270 can be formed on the electrical contact pad 202 to facilitate the bonding of the conductive bump 27.

[0045] Alternatively, a leveling process, such as grinding, can be used to remove part of the material of the covering layer 28, so that the upper surface of the covering layer 28 is flush with the surface of the electronic device 26, thereby exposing the electronic device 26 to the covering layer 28.

[0046] Alternatively, the covering layer 28 can simultaneously cover the electronic device 26 and the conductive bumps 27. Or, an adhesive 260 can be formed first between the electronic device 26 and the circuit structure 20 to cover the conductive bumps 27, and then the covering layer 28 can be formed to cover the adhesive 260 and the electronic device 26.

[0047] Alternatively, as shown in Figure 2B, the electronic package 3b, the electronic device 36 can be a package module, which includes a package substrate 360, at least one semiconductor chip 361 disposed on the package substrate 360 ​​and electrically connected to the package substrate 360, and a package colloid 362 covering the semiconductor chip 361.

[0048] Therefore, in the manufacturing method of this embodiment, the electronic component 21 has a first electrode pad 210 and a second electrode pad 213 on opposite sides to form a double-sided power supply structure, so that the electrical functional pad 291 can be electrically connected to the second electrode pad 213 through a plurality of conductive blind holes 290. Therefore, compared with the prior art, when both the electrical functional pad 291 and the second electrode pad 213 are power supply pads, the electronic package 2, 3a, 3b of the present invention can reduce power loss.

[0049] Figure 3 is a cross-sectional schematic diagram of the manufacturing method of the second embodiment of the electronic package 4 of the present invention. The difference between this embodiment and the first embodiment lies in the packaging method, so the similarities will not be repeated below.

[0050] As shown in Figure 3, electronic components 21 and 41 are stacked on a circuit structure 40.

[0051] The circuit structure 40 has a silicon-containing board, such as a functional chip, a silicon interposer (TSI), or a glass substrate, and the board is equipped with conductive lines.

[0052] In this embodiment, the circuit structure 40 is a TSI, which has a through-silicon via (TSV) and a circuit portion 42. For example, the circuit portion 42 includes at least one dielectric layer and a redistribution layer (RDL) bonded to the dielectric layer, and the redistribution layer is electrically connected to the TSV.

[0053] It should be understood that the form of the relevant circuit structure 40 can be designed according to requirements and is not limited to the above.

[0054] On the other hand, a plurality of conductive elements 44 may be formed on the underside of the circuit structure 40, such as including metal pillars (e.g., copper pillars) and / or solder material, so that the plurality of conductive elements 44 are attached to the end face of the plurality of conductive through holes for connection on a substrate structure 43.

[0055] The substrate structure 43 is, for example, a package substrate with a core layer or a coreless package substrate, which is provided with at least one wiring layer 430 so that the plurality of conductive elements 44 are electrically connected to the wiring layer 430.

[0056] In this embodiment, an adhesive 440 may be formed on the substrate structure 43 so that the adhesive 440 covers the plurality of conductive elements 44.

[0057] The electronic components 21 and 41 are disposed on the circuit structure 40 and electrically connected to the circuit section 42.

[0058] In this embodiment, the electronic components 21 and 41 are semiconductor wafers, with a plurality of first electrode pads 210 and 410 on their first side, and a plurality of conductive bumps 47, such as solder material, are disposed on the circuit structure 40 in a flip-chip manner and electrically connected to the circuit portion 42, and then the conductive bumps 47 are covered with a base adhesive 411.

[0059] Furthermore, one of the electronic components 21 has a plurality of second electrode pads 213 on its second side, and a wiring structure 49 is formed on its second side. The wiring structure 49 includes an insulating layer 490, an electrical functional pad 291 formed on the insulating layer 490, and a plurality of conductive blind holes 290 formed in the insulating layer 490 and electrically connecting the second electrode pads 213 and the electrical functional pads 291, so that a single second electrode pad 213 and a single electrical functional pad 291 are connected to a plurality of (e.g., three) conductive blind holes 290.

[0060] Furthermore, at least one electronic device 46 may be disposed on the wiring structure 49 so that the electronic device 46 is electrically connected to the electrical functional pad 291. In this embodiment, the electronic device 46 is a passive component, such as a resistor, capacitor, and inductor.

[0061] Furthermore, an encapsulation layer 45 is formed on the support structure 40 to cover the electronic components 21, 41, for attaching the heat sink 48 to the encapsulation layer 45. For example, the encapsulation layer 45 is a thermal adhesive, and the heat sink 48 is a frame with its support legs mounted on the substrate structure 43, so that the heat sink is attached to the encapsulation layer 45.

[0062] Therefore, in the manufacturing method of this embodiment, the electronic component 21 has a first electrode pad 210 and a second electrode pad 213 on opposite sides to form a double-sided power supply structure, so that the electrical functional pad 291 can be electrically connected to the second electrode pad 213 through a plurality of conductive blind holes 290. Therefore, compared with the prior art, when both the electrical functional pad 291 and the second electrode pad 213 are power pads, the electronic package 4 of the present invention can reduce power loss.

[0063] The present invention also provides an electronic package 2,3a,3b,4, which includes: a package layer 25,45, an electronic component 21, a circuit structure 20,40 and a wiring structure 29,49.

[0064] The electronic component 21 is embedded in the encapsulation layer 25, 45, and the electronic component 21 has a first side 21a and a second side 21b opposite to each other. The first side 21a has a plurality of first electrode pads 210, and the second side 21b has a plurality of second electrode pads 213.

[0065] The circuit structures 20 and 40 are disposed on the first side 21a of the electronic component 21 and the encapsulation layer 25 and 45 and are electrically connected to the plurality of first electrode pads 210.

[0066] The wiring structures 29 and 49 are disposed on the second side 21b of the electronic component 21 and electrically connected to the plurality of second electrode pads 213. The wiring structures 29 and 49 have a plurality of electrical functional pads 291 and a plurality of conductive blind holes 290, so that a single electrical functional pad 291 is electrically connected to a single second electrode pad 213 through the plurality of conductive blind holes 290.

[0067] In one embodiment, the function of the first electrode pad 210 is different from the function of the second electrode pad 213.

[0068] In one embodiment, the first electrode pad 210 is a signal pad, and the second electrode pad 213 is a power pad. Alternatively, the second electrode pad 213 is a signal pad, and the first electrode pad 210 is a power pad. Furthermore, the width D2 of the power pad is different from the width D1 of the signal pad. For example, the width D2 of the power pad is greater than the width D1 of the signal pad.

[0069] In one embodiment, the electronic package 2, 3a, 3b further includes at least one conductive post 23 embedded in the package layer 25, which electrically connects the circuit structure 20 and the wiring structure 29.

[0070] In one embodiment, the electronic package 3a, 3b further includes at least one electronic device 26, 36 disposed on the circuit structure 20 and electrically connected to the circuit structure 20.

[0071] In one embodiment, the electronic package 2, 3a, 3b further includes a covering layer 28 formed on the circuit structure 20.

[0072] In one embodiment, the electronic package 4 further includes at least one electronic device 46 disposed on the wiring structure 49 and electrically connected to the wiring structure 49.

[0073] In summary, the electronic package and its manufacturing method of the present invention form a double-sided power supply structure by having a first electrode pad and a second electrode pad on opposite sides of the electronic component. The electrical functional pad is electrically connected to the second electrode pad through a plurality of conductive blind holes. Therefore, when both the electrical functional pad and the second electrode pad are power supply pads, the present invention can reduce power loss.

[0074] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.

[0075] 20, 40: Line Structure 24,44: Conductive elements 2,3a,3b,4: Electronic packages 200, 490: Insulation layer 201: Line Layer 202: Electrical contact pad 21,41: Electronic components 21a: First side 21b: Second side 210, 410: First electrode pad 211: Protective film 212: Bonding layer 213: Second electrode pad 22: Conductor 22a, 23a: End face 23: Conductive column 25, 45: Encapsulation layer 25a: First surface 25b: Second surface 26, 36, 46: Electronic devices 260, 411, 440: Base rubber 27,47: Conductive bumps 270: Metal layer under the bump 28: Covering layer 29, 49: Wiring Structure 290: Conductive blind hole 291: Electrical Functional Pad 360: Packaging substrate 361: Semiconductor wafers 362: Encapsulating colloid 42: Line Department 43: Substrate Structure 430: Wiring layer 48: Heat sink 9: Support plate 9a: Seed layer 9b: Metal layer 90: Release layer 91,490: Insulation layer D1, D2: Width L: Cutting path

Claims

1. An electronic package, comprising: Encapsulation layer; An electronic component is embedded in the encapsulation layer, wherein the electronic component has a first side and a second side opposite to each other, the first side has a plurality of first electrode pads, and the second side has a plurality of second electrode pads, forming a structure that provides bi-directional power supply to a single electronic component; a circuit structure is disposed on the first side of the electronic component and electrically connected to the plurality of first electrode pads; and a wiring structure is disposed on the second side of the electronic component and electrically connected to the plurality of second electrode pads, wherein the wiring structure includes an insulating layer and has a plurality of electrical functional pads partially embedded in the insulating layer and partially exposed on the outer surface of the insulating layer and a plurality of conductive blind holes, so that each individual electrical functional pad is electrically connected to a single second electrode pad through its portion embedded in the insulating layer and the plurality of conductive blind holes.

2. The electronic package as described in claim 1, wherein, The second electrode pad is a power supply pad.

3. The electronic package as described in claim 1, wherein, The first electrode pad is a power supply pad.

4. The electronic package as described in claim 1 further includes a plurality of conductive pillars embedded in the package layer, which electrically connect the circuit structure and the wiring structure.

5. The electronic package as described in claim 1 further includes an electronic device disposed on the circuit structure and electrically connected to the circuit structure.

6. The electronic package as described in claim 1 further includes a covering layer formed on the circuit structure.

7. The electronic package as claimed in claim 1 further includes an electronic device disposed on the wiring structure and electrically connected to the wiring structure.

8. A method for manufacturing an electronic package, comprising: An electronic component is encapsulated by an encapsulation layer. The electronic component has a first side and a second side, the first side having a plurality of first electrode pads and the second side having a plurality of second electrode pads, forming a structure that provides bi-directional power to a single electronic component. A circuit structure is formed on the first side of the electronic component to electrically connect the circuit structure to the plurality of first electrode pads. A wiring structure is formed on the second side of the electronic component to electrically connect the wiring structure to the plurality of second electrode pads. The wiring structure includes an insulating layer and has a plurality of electrical functional pads partially embedded in the insulating layer and partially exposed on the outer surface of the insulating layer, and a plurality of conductive blind vias, so that each individual electrical functional pad is electrically connected to a single second electrode pad through its portion embedded in the insulating layer and the plurality of conductive blind vias.

9. The method for manufacturing an electronic package as described in claim 8, wherein, The second electrode pad is a power supply pad.

10. The method for manufacturing an electronic package as described in claim 8, wherein, The first electrode pad is a power supply pad.

11. The method of manufacturing an electronic package as described in claim 8 further includes embedding a plurality of conductive pillars in the package layer so that the plurality of conductive pillars electrically connect the circuit structure and the wiring structure.

12. The method of manufacturing an electronic package as described in claim 8 further includes disposing an electronic device on the circuit structure so that the electronic device is electrically connected to the circuit structure.

13. The method of manufacturing an electronic package as described in claim 8 further includes forming an overlay layer on the circuit structure.

14. The method of manufacturing an electronic package as described in claim 8 further includes disposing an electronic device on the wiring structure so that the electronic device is electrically connected to the wiring structure.

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