Switched capacitor charging circuit

Abstract

This invention discloses a switched capacitor charging circuit. By adding an additional first transistor, and combining it with three transistors on the low-voltage side and a flying capacitor to form a 2:1 switched capacitor unit, which is connected in parallel with a 2:1 switched capacitor unit on the high-voltage side, the charging current and power are improved, and the efficiency is increased, in the second mode where the voltage conversion ratio between the input voltage and the output voltage is 2:1.

Description

Technical Field

[0001] []The present invention relates to the field of power electronics technology, and more specifically, to a switched capacitor charging circuit. Prior Art

[0002] The widespread use of mobile phones, tablets, Bluetooth headsets, and other end devices has led to higher demands for charging efficiency. Compared to traditional converter topologies, switched-capacitor circuits (i.e., charge pumps) are widely used in mainstream fast-charging solutions due to their superior efficiency. The current high-power single-battery fast charging solution consists of a switched capacitor converter with an input-output voltage conversion ratio compatible with 4:1 and 2:1. When using a 4:1 switched capacitor converter solution, the 2:1 mode can be supported simultaneously through topology transformation. Referring to Figure 1, which is a schematic diagram of a switched capacitor charging circuit in the prior art, the switched capacitor charging circuit is composed of a 4:1 switched capacitor converter with a series-parallel topology. When the input-output voltage conversion ratio is 4:1, transistors Q21, Q22, Q23, Q24, and transistors Q31, Q41, Q32, Q42, Q33, and Q43 all participate in the operation, and together with the flying capacitor CFIY1, the flying capacitor CFIY2, and the flying capacitor CFIY3, they form a 4:1 switched capacitor converter. When the input-output voltage conversion ratio is 2:1, transistors Q23, Q24, and transistors Q33, Q43 participate in the operation, and together with the flying capacitor CFIY3, they form a 2:1 switched capacitor converter, and at this time, transistor Q32 remains in the on state. In this way, although the input-output voltage conversion ratio can be switched between 4:1 and 2:1, when the input-output voltage conversion ratio is 2:1, the 2:1 switched capacitor converter composed of only switching transistors close to the high-voltage side is used to work, which will make the efficiency of the switched capacitor charging circuit low. Summary of the Invention

[0003] [] In view of this, the present invention provides a switched capacitor charging circuit to improve the efficiency when the input-output voltage conversion ratio is 2:1. The present invention provides a switched capacitor charging circuit, characterized by comprising: The first port is configured to be coupled to a first voltage source; The second port is configured to be coupled to a first terminal of a first battery, wherein a second terminal of the first battery is coupled to a ground terminal; a switched capacitor circuit, comprising N-1 switched capacitor units sequentially coupled between the second port and the first port, the switched capacitor circuit being configured to charge the first battery, with the N-1th switched capacitor unit coupled to the first port and the first switched capacitor unit coupled to the second port; A first transistor has a first end coupled to the first port and a second end coupled to one end of a flying capacitor in the first switch capacitor unit. Preferably, when the switched capacitor circuit operates in the first mode, its voltage conversion ratio is N:1, and when operating in the second mode, its voltage conversion ratio is 2:1, and in the second mode, at least the first switched capacitor unit participates in the operation, and N is a natural number greater than or equal to 3. Preferably, the first transistor is used to be turned on in the second mode to enable the first switched capacitor unit to participate in the operation, thereby improving the efficiency of the switched capacitor charging circuit. Preferably, when the switched capacitor circuit operates in the first mode, all of the N-1 switched capacitor units participate in the operation. Preferably, when N is greater than or equal to 3, and the switched capacitor circuit operates in the second mode, only the first switched capacitor unit participates in the operation. Preferably, when N is greater than or equal to 4, and the switched capacitor circuit operates in the second mode, the N-1th switched capacitor unit is connected in parallel with the first switched capacitor unit and works together. Preferably, each of the switched capacitor units includes a flying capacitor, and the N-1 switched capacitor units switch operating modes so that the flying capacitors are sequentially connected in series between the second port and the first port, or in parallel between the second port and the first port, to charge the first battery. Preferably, the switched capacitor circuit includes: N-1 first structures are sequentially coupled in parallel between the second port and the ground terminal, wherein each first structure includes a third transistor, a flying capacitor, and a fourth transistor, which are sequentially coupled in series between the second port and the ground terminal; and N second transistors are respectively coupled between the second port and the first first structure, between two adjacent first structures, and between the N-1th first structure and the first port. Preferably, the first second transistor is coupled between the second port and the flying capacitor and the fourth transistor in the first first structure; The i-th second transistor is configured to be coupled between a common terminal of the third transistor and the flying capacitor in the i-1-th first structure and a flying capacitor and a fourth transistor in the i-th first structure, wherein i is a positive integer and 2≤i≤N-1; The Nth second transistor is coupled between the common end of the third transistor and the flying capacitor in the N-1th first structure and the first port. Preferably, the kth switching capacitor unit includes a kth first structure, a kth second transistor adjacent to the kth first structure, and a k+1th second transistor, where k is a positive integer less than or equal to N-1. Preferably, when the switched capacitor circuit operates in the second mode, the first transistor, the first first structure, and the first second transistor constitute the first switched capacitor unit. Preferably, when the N-1th switching capacitor unit is connected in parallel with the first switching capacitor unit and works together, the third transistor in the N-2th switching capacitor unit remains in an on state and the fourth transistor remains in an off state. Preferably, the control signals of the third transistor and the fourth transistor are the same, the control signals of the second transistor and the control signals of the third transistor have the same duty cycle, and the phase difference is 180°. Preferably, a switching transistor is further provided between the first port and the switched capacitor circuit to prevent current from flowing back into the first voltage source. The present invention aims to provide a switched capacitor charging circuit. By adding an additional first transistor, three transistors on the low-voltage side, and a flying capacitor to form a group of 2:1 switched capacitor units, which are connected in parallel with a group of 2:1 switched capacitor units on the high-voltage side to operate. In this way, when the voltage conversion ratio between the input voltage and the output voltage is 2:1, the charging current and power can be increased, and the efficiency can be improved. Simple diagram description

[0004] [] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For those with ordinary knowledge in the relevant technical field, other drawings can be obtained based on the provided drawings without any creative work. [Figure 1] is a schematic diagram of a switched capacitor charging circuit of the prior art; [Figure 2] is a schematic diagram of a switched capacitor charging circuit according to a first embodiment of the present invention; [Figure 3 (a)] is an equivalent circuit diagram of the first working stage of the switched capacitor charging circuit of the first embodiment of the present invention under the first embodiment; [Figure 3 (b)] is an equivalent circuit diagram of the switched capacitor charging circuit of the first embodiment of the present invention in the second working stage under the first embodiment; [Figure 4 (a)] is an equivalent circuit diagram of the first working stage of the switched capacitor charging circuit of the first embodiment of the present invention under the second embodiment; [Figure 4 (b)] is an equivalent circuit diagram of the switched capacitor charging circuit of the first embodiment of the present invention in the second working stage under the second embodiment; FIG5 is a schematic diagram of a switched capacitor charging circuit according to a second embodiment of the present invention. Implementation Method

[0005] The present invention is described below based on examples, but the present invention is not limited to these examples. Certain specific details are described in detail in the following detailed description of the present invention. Those skilled in the art will be able to fully understand the present invention without these details. To avoid obscuring the essence of the present invention, conventional methods, processes, procedures, components, and circuits are not described in detail. Furthermore, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit connected electrically or electromagnetically. When an element or circuit is said to be "connected" to another element, or when an element / circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intervening elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements between the two elements. Unless the context clearly requires otherwise, the words “include”, “comprising” and similar expressions throughout the specification and patent application should be interpreted as inclusive rather than exclusive or exhaustive; that is, as “including but not limited to”. In the description of the present invention, it should be understood that the terms "first," "second," etc. are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise specified, "plurality" means two or more than two. Figure 2 is a schematic diagram of a switched capacitor charging circuit according to a first embodiment of the present invention. As shown in Figure 2 , the switched capacitor charging circuit of this embodiment includes a first port o1, a second port o2, and a switched capacitor circuit 1. The first port o1 is coupled to a first voltage source V BUS and the switched capacitor circuit 1, while the second port o2 is coupled to a first terminal of a first battery B1. The second terminal of the first battery B1 is coupled to ground. In this embodiment, the switched capacitor circuit 1 is configured as a series-parallel switched capacitor converter. A switched capacitor circuit 1 includes N-1 switched capacitor units coupled in series and parallel between a second port o2 and a first port o1. The switched capacitor circuit 1 is configured to charge a first battery B1. The N-1th switched capacitor unit is coupled to the first port o1, i.e., near the high-voltage side of a first voltage source V BUS. The first switched capacitor unit is near the low-voltage side of the first voltage source V BUS and has two transistors coupled to the second port o2. Furthermore, when the switched capacitor circuit 1 operates in the first mode, its voltage conversion ratio is N:1, and when operating in the second mode, its voltage conversion ratio is 2:1, and in the second mode, at least the first switched capacitor unit participates in the operation, where N is a natural number greater than or equal to 3. Specifically, in this embodiment, N=4, and the switched capacitor circuit 1 includes: three first structures 11-13 and four second transistors Q21-Q24, the three first structures 11-13 being coupled in parallel between the second port o2 and the ground terminal, wherein each first structure includes at least two transistors and a flying capacitor; the four second transistors Q21-Q24 being coupled respectively between the second port o2 and the first first structure 11, between the first first structure 11 and the second first structure 12, between the second first structure 12 and the third first structure 13, and between the third first structure 13 and the first port o1. Specifically, the first structure 11 includes a third transistor Q31, a flying capacitor C FIY1, and a fourth transistor Q41, which are sequentially coupled in series between the second port o2 and the ground terminal; the first structure 12 includes a third transistor Q32, a flying capacitor C FIY2, and a fourth transistor Q42, which are sequentially coupled in series between the second port o2 and the ground terminal; and the first structure 13 includes a third transistor Q33, a flying capacitor C FIY3, and a fourth transistor Q43, which are sequentially coupled in series between the second port o2 and the ground terminal. The second transistor Q21 is coupled between the second port o2 and the common end of the flying capacitor C FIY1 and the fourth transistor Q41 in the first structure 11; the second transistor Q22 is coupled between the common end of the third transistor Q31 and the flying capacitor C FIY1 in the first structure 11 and the common end of the flying capacitor C FIY2 and the fourth transistor Q42 in the first structure 12; the second transistor Q23 is coupled between the common end of the third transistor Q32 and the flying capacitor C FIY2 in the first structure 12 and the common end of the flying capacitor C FIY3 and the fourth transistor Q43 in the first structure 13; and the second transistor Q24 is coupled between the common end of the third transistor Q33 and the flying capacitor C FIY3 in the first structure 13 and the first port o1. Here, the i-th switched capacitor unit includes the i-th first structure, the i-th second transistor adjacent to the i-th first structure, and the i+1-th second transistor, where i is less than or equal to N-1. Specifically, in this embodiment, the first switched capacitor unit includes the first structure 11 and the second transistors Q21 and Q22; the second switched capacitor unit includes the first structure 12 and the second transistors Q22 and Q23; and the third switched capacitor unit includes the first structure 13 and the second transistors Q23 and Q24. Furthermore, the switched capacitor charging circuit also includes a first transistor Q1, a first end of which is coupled to the first port o1, and a second end of which is coupled to one end of the flying capacitor C FIY1 in the first switched capacitor unit. The first transistor Q1 is configured to periodically turn on and off in the second mode to enable the first switched capacitor unit to participate in operation, thereby improving the efficiency of the switched capacitor charging circuit. Optionally, the switched capacitor charging circuit further includes a switching transistor QB for preventing leakage to prevent current from flowing back into the first voltage source V BUS. In this embodiment, the charging circuit further includes an input capacitor Cin for filtering the output voltage of the first voltage source V BUS. In this embodiment, the switched capacitor circuit 1 is configured as a switched capacitor circuit with a series-parallel architecture, and the voltage conversion ratio between the input and output ends is 4:1. In other embodiments, the switched capacitor circuit 1 can be a switched capacitor circuit converter with other voltage conversion ratios (such as 3:1, 5:1, 6:1), and the present invention is not limited to this. Specifically, when the switched capacitor circuit 1 operates in the first mode, that is, when the voltage conversion ratio between the input voltage and the output voltage is 4:1, N-1 switched capacitor units all participate in the operation. In this embodiment, N=4, that is, all three switched capacitor units participate in the operation, so that the voltage VBAT on the first battery B1 = = 1 / 4V BUS. Preferably, when the switched capacitor circuit 1 operates in the first mode, in the first interval, GH is at a high level, GL is at a low level, the second transistors Q21~Q24 are turned on, the third transistors Q31~Q33 and the fourth transistors Q41~Q43 are all turned off, at this time the flying capacitors C FIY1~C FIY3 and the first battery B1 are connected in series, and the first voltage source VBUS charges the flying capacitors C FIY1~C FIY3 and the first battery B1, so that the first voltage source VBUS is equal to the sum of the voltages VC FIY1~VC FIY3 on the three flying capacitors C FIY1~C FIY3 and the voltage VBAT on the first battery, that is: VBUS=VC FLY1+VC FLY2+VC FLY3+VBAT; in the second interval, GH is at a low level, GL is at a high level, the third transistors Q31~Q33 and the fourth transistors Q41~Q43 are all turned on, the second transistors Q21~Q24 are all turned off, at this time the flying capacitors C C FIY1 through C FIY3 are connected in parallel with the first battery B1. Therefore, the voltages VC FIY1 through VC FIY3 across the three flying capacitors C FIY1 through C FIY3 are equal to the voltage VBAT across the first battery, namely, VC FLY1 = VC FLY2 = VC FLY3 = VBAT. Therefore, the voltage VBAT across the first battery is equal to one-quarter the voltage of the first voltage source VBUS, namely, VBAT = 1 / 4V BUS. When the switched capacitor circuit 1 operates in the second mode, i.e., when the voltage conversion ratio between the input voltage and the output voltage is 2:1, the first switched capacitor unit participates in operation, or the (N-1)th switched capacitor unit is connected in parallel with the first switched capacitor unit and participates in operation together, i.e., the third switched capacitor unit is connected in parallel with the first switched capacitor unit, so that the voltage VBAT on the first battery B1 is equal to 1 / 2V BUS. The following describes the operation process in two embodiments. Figure 3 is an equivalent circuit diagram of the switched capacitor charging circuit of the first embodiment of the present invention at different operating stages in the first implementation of the second mode. The first implementation here refers to the situation where, when the switched capacitor circuit 1 operates in the second mode, the third switched capacitor unit operates in parallel with the first switched capacitor unit. Referring to FIG. 3( a ), in this embodiment, on the one hand, the third transistor in the N-2th switched capacitor unit remains in an on state, and the fourth transistor remains in an off state. Here, that is, the third transistor Q32 in the second switched capacitor unit remains in an on state, and the fourth transistor Q42 remains in an off state, so that the third switched capacitor unit is directly coupled to the first battery B1. On the other hand, the first transistor Q1, the first first structure 11, and the first second transistor Q21 constitute the first switched capacitor unit, so that the first switched capacitor unit is directly coupled to the first voltage source VBUS. As a result, the third switched capacitor unit and the first switched capacitor unit form a parallel structure, connected in parallel between the first port o1 and the positive terminal of the first battery B1, that is, the second port o2. Preferably, in the first interval, GH is at a high level, GL is at a low level, the second transistors Q21, Q23, and Q24 are turned on, the first transistor Q1 is turned on, and among the third transistors Q31-Q33 and the fourth transistors Q41-Q43, except for the third transistor Q32 which remains on, all other transistors are turned off. At this time, the flying capacitor C FIY1 and the flying capacitor C FIY3 are connected in parallel and then connected in series with the first battery B1. The first voltage source VBUS charges the flying capacitors C FIY1, C FIY3, and the first battery B1, so that the first voltage source VBUS is equal to the sum of the voltage VC FIY3 on the flying capacitor C FIY3 and the voltage VBAT on the first battery, or the first voltage source VBUS is equal to the sum of the voltage VC FIY1 on the flying capacitor C FIY1 and the voltage VBAT on the first battery, that is, VBUS=VC FLY3+VBAT, VBUS=VC FLY1+VBAT; Referring to Figure 3(b), in the second interval, GH is at a low level and GL is at a high level. All of the third transistors Q31-Q33 and the fourth transistors Q41-Q43, except for the fourth transistor Q42, remain off. The first transistor Q1 and all of the second transistors Q21-Q24 are off. At this time, the flying capacitors C FIY1 and C FIY3 are connected in parallel with the first battery B1. Consequently, the voltages VC FIY1 and VC FIY3 across the flying capacitors C FIY1 and C FIY3, respectively, are equal to the voltage VBAT across the first battery, i.e., VC FLY1 = VC FLY3 = VBAT. Therefore, the voltage VBAT across the first battery B1 is equal to half the voltage of the first voltage source VBUS, i.e., VBAT = 1 / 2 VBUS. When this embodiment is used to achieve a 2:1 voltage conversion ratio between the input voltage and the output voltage of the switched capacitor charging circuit, and when the parameters of the two switched capacitor units are exactly the same, especially when the on-resistance of each transistor is the same, since the two switched capacitor units operate in parallel, on the one hand, under the condition that the system output power remains unchanged, the charging current flowing through each of the two switched capacitor units is only half of the charging current of the original switched capacitor unit when it is operating. In the switched capacitor charging circuit, when the charging current exceeds a certain lower threshold, the system charging efficiency and the charging current are inversely correlated, and the smaller the charging current, the higher the charging efficiency. Therefore, the switched capacitor charging circuit of this embodiment can improve the system charging efficiency in the second mode where the voltage conversion ratio between the input voltage and the output voltage is 2:1. On the other hand, if the charging current flowing through each of the two switched capacitor units remains unchanged, that is, equal to the charging current of the original switched capacitor unit when it is operating, then using this technical solution, the load charging current will be doubled, and without considering other effects, the system output power can be doubled. FIG4 is an equivalent circuit diagram of the switched capacitor charging circuit of the first embodiment of the present invention at different operating stages in the second implementation of the second mode. The second implementation here refers to the case where, when the switched capacitor circuit 1 operates in the second mode, only the first switched capacitor unit is operational. Referring to FIG. 4( a ), in this embodiment, the first transistor Q1, the first first structure 11, and the first second transistor Q21 form a first switched capacitor unit, such that the first switched capacitor unit is directly coupled to the first voltage source VBUS. Consequently, the first switched capacitor unit is connected between the first port o1 and the positive terminal of the first battery B1, i.e., the second port o2, and can thus operate independently. Preferably, in the first interval, GH is at a high level, GL is at a low level, the second transistor Q21 is turned on, the first transistor Q1 is turned on, and all other transistors are turned off. At this time, the flying capacitor C FIY1 and the first battery B1 are connected in series, and the first voltage source VBUS charges the flying capacitor C FIY1 and the first battery B1. Thus, the first voltage source VBUS is equal to the sum of the voltage VC FIY1 on the flying capacitor C FIY1 and the voltage VBAT on the first battery, VBUS=VC FLY1+VBAT; Referring to Figure 4(b), in the second interval, GH is low and GL is high. The third transistor Q31 and the fourth transistor Q41 are on, while the first transistor Q1 and all other transistors are off. At this time, the flying capacitor C FIY1 and the first battery B1 are connected in parallel. As a result, the voltage VC FIY1 across the flying capacitor C FIY1 and the voltage VBAT across the first battery are equal, i.e., VC FLY1 = VBAT. Therefore, the voltage VBAT across the first battery B1 is equal to half the voltage of the first voltage source VBUS, i.e., VBAT = 1 / 2V BUS. When this embodiment is used to achieve a voltage conversion ratio of 2:1 between the input voltage and the output voltage of the switched capacitor charging circuit, only the first switched capacitor unit close to the low-voltage side is enabled to operate. In the design of the switched capacitor charging circuit, in order to balance the chip area, the on-resistance of the transistor close to the high-voltage side is generally higher than the on-resistance of the transistor close to the low-voltage side. For example, the on-resistance of the third transistor Q33 and the fourth transistor Q43 is higher than the on-resistance of the third transistor Q31 and the fourth transistor Q41. Therefore, the switching loss of the transistor in the first switched capacitor unit is lower than the switching loss of the transistor in the third switched capacitor unit. Therefore, when the on-resistance value of the first transistor Q1 is reasonable, the technical solution of this embodiment will improve the efficiency of the switched capacitor charging circuit. Figure 5 is a schematic diagram of a switched capacitor charging circuit according to a second embodiment of the present invention. This embodiment differs from the first embodiment in that the switched capacitor circuit 1 is configured to be composed of N-1 switched capacitor units connected in series and parallel. When the switched capacitor circuit 1 operates in a first mode, its voltage conversion ratio is N:1. When operating in a second mode, its voltage conversion ratio is 2:1. In the second mode, at least the first switched capacitor unit is operational, and N is a natural number greater than or equal to 3. Specifically, the switched capacitor circuit 1 includes: N-1 first structures 11-1(N-1) and N second transistors Q21-Q2N. The first structures 11-1(N-1) are coupled in parallel between the second port o2 and the ground terminal, wherein each first structure includes at least two transistors and a flying capacitor; the N second transistors Q21-Q2N are respectively used to couple between the second port o2 and the first first structure 11, between two adjacent first structures in the first structures 11-1(N-1), and between the N-1th first structure 1(N-1) and the first port o1. Each first structure 1k includes a third transistor Q3k, a flying capacitor C FIYk, and a fourth transistor Q4k, which are sequentially coupled in series between the second port o2 and the ground terminal, wherein k is less than N; the first second transistor Q21 is coupled between the second port o2 and the common terminal of the flying capacitor C FIY1 and the fourth transistor Q41 of the first first structure 11; the i-th second transistor Q2i is used to couple between the common terminal of the third transistor Q3(i-1) and the flying capacitor C FIY(i-1) of the i-1-th first structure 1(i-1) and the common terminal of the flying capacitor C FIYi and the fourth transistor Q4i of the i-th first structure 1i, wherein 2≤i≤N-1; the N-th second transistor Q2N is coupled between the third transistor Q3(N-1) and the flying capacitor C FIY1 of the N-1-th first structure 1(N-1) The kth switched capacitor unit includes a kth first structure 1k, a kth second transistor Q2k adjacent to the kth first structure 1k, and a k+1th second transistor Q2(k+1), where k is a positive integer less than or equal to N-1. When the switched capacitor circuit 1 operates in the first mode, that is, when the voltage conversion ratio between the input voltage and the output voltage is N:1, N-1 switched capacitor units all participate in the operation, so that the voltage VBAT on the first battery B1 equals 1 / NV BUS. When the switched capacitor circuit 1 operates in the second mode, that is, when the voltage conversion ratio between the input voltage and the output voltage is 2:1, the first switched capacitor unit participates in the operation, or the N-1th switched capacitor unit is connected in parallel with the first switched capacitor unit and participates in the operation together, so that the voltage VBAT on the first battery B1 equals 1 / 2V BUS. When N is greater than or equal to 4, and the switched capacitor circuit 1 operates in the second mode with a voltage conversion ratio of 2:1 between the input voltage and the output voltage, only the first switched capacitor unit may be operational, or the N-1th switched capacitor unit may be connected in parallel with the first switched capacitor unit and operate together. When the first switched capacitor unit is operational, the first transistor Q1, the first first structure 11, and the first second transistor Q21 constitute the first switched capacitor unit. When the N-1th switched capacitor unit is connected in parallel with the first switched capacitor unit and operate together, the third transistor Q3 (N-2) in the N-2th switched capacitor unit remains in an on state, and the fourth transistor Q4 (N-2) remains in an off state, so that the N-1th switched capacitor unit forms a parallel connection structure with the first switched capacitor unit. It should be noted that when N is equal to 3, since there are only two switched capacitor units and the two switched capacitor units cannot form a parallel connection structure, when the switched capacitor circuit 1 operates in the second mode, only the first switched capacitor unit participates in the operation. The rest of the second embodiment, such as the working conditions, working mode and control method, are similar to those of the first embodiment and will not be described in detail here. Thus, it can be seen that the switched capacitor charging circuit of the present invention, by adding an additional first transistor, and three transistors and a flying capacitor on the low-voltage side to form a group of 2:1 switched capacitor units, which are connected in parallel with a group of 2:1 switched capacitor units on the high-voltage side to operate, can increase the charging current and power, and achieve higher efficiency when the voltage conversion ratio between the input voltage and the output voltage is 2:1 in the second mode. The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0006] 1: Switched capacitor circuit 11: First Structure 12: First Structure 13: First Structure 1(N-1): first structure

Claims

1. A switched capacitor charging circuit, characterized in that it comprises: The first port is configured to be coupled to the first voltage source; The second port is configured to be coupled to a first terminal of a first battery, the second terminal of which is coupled to a ground terminal; a switched capacitor circuit includes N-1 switched capacitor units sequentially coupled between the second port and the first port, the switched capacitor circuit being configured to charge the first battery, with the N-1th switched capacitor unit coupled to the first port and the first switched capacitor unit coupled to the second port; a first transistor, the first terminal of which is coupled to the first port and the second terminal of which is coupled to one end of a flying capacitor in the first switched capacitor unit; wherein, the switched capacitor charging circuit is a buck topology, and its output voltage is less than its input voltage; In this circuit, the voltage conversion ratio is N:1 when the switched capacitor circuit operates in the first mode and 2:1 when it operates in the second mode. In the second mode, at least the first switched capacitor unit participates in the operation. N is a natural number greater than or equal to 3. In the second mode, the first transistor is turned on so that the first port is directly coupled to the first switched capacitor unit through the first transistor to form a charging path in the first switched capacitor unit. This bypasses the second to the (N-1)th switched capacitor units so that the first switched capacitor unit can participate in the operation, thereby improving the efficiency of the switched capacitor charging circuit.

2. The switched capacitor charging circuit according to claim 1, wherein, When the switched capacitor circuit operates in the first mode, all N-1 switched capacitor units participate in the operation.

3. The switched capacitor charging circuit according to claim 1, wherein, When N is greater than or equal to 3, and the switched capacitor circuit is operating in the second mode, only the first switched capacitor unit participates in the operation.

4. The switched capacitor charging circuit according to claim 1, wherein, When N is greater than or equal to 4, and the switched capacitor circuit is operating in the second mode, the (N-1)th switched capacitor unit is connected in parallel with the first switched capacitor unit and works together.

5. The switched capacitor charging circuit according to claim 1, wherein, Each switched capacitor unit includes a flying capacitor. The N-1 switched capacitor units switch operating modes so that the flying capacitor is connected in series between the second port and the first port, or in parallel between the second port and the first port, to charge the first battery.

6. The switched capacitor charging circuit according to claim 5, wherein, The switched capacitor circuit includes: N-1 first structures, which are connected in parallel between the second port and the ground terminal, wherein each first structure includes a third transistor, a flying capacitor and a fourth transistor, which are connected in series between the second port and the ground terminal; and N second transistors, which are respectively coupled between the second port and the first first structure, between two adjacent first structures and between the (N-1)th first structure and the first port.

7. The switched capacitor charging circuit according to claim 6, wherein, The first second transistor is coupled between the second port and the flying capacitor and the fourth transistor in the first first structure; The i-th second transistor is used to couple the common terminal of the third transistor and the flying capacitor in the (i-1)-th first structure to the flying capacitor and the fourth transistor in the i-th first structure, where i is a positive integer and 2≤i≤N-1; The N-th second transistor is coupled to the common terminal of the third transistor and the flying capacitor in the (N-1)-th first structure to the first port.

8. The switched capacitor charging circuit according to claim 7, wherein, The k-th switched capacitor unit includes the k-th first structure, the k-th second transistor adjacent to the k-th first structure, and the (k+1)-th second transistor, where k is a positive integer less than or equal to N-1.

9. The switched capacitor charging circuit according to claim 7, wherein, When the switched capacitor circuit operates in the second mode, the first transistor, the first first structure, and the first second transistor constitute the first switched capacitor unit.

10. The switched capacitor charging circuit according to claim 6, wherein, When the (N-1)th switched capacitor unit is connected in parallel with the first switched capacitor unit and works together, the third transistor in the (N-2)th switched capacitor unit remains in the on state, and the fourth transistor remains in the off state.

11. The switched capacitor charging circuit according to claim 6, wherein, The control signals of the third and fourth transistors are the same, the control signals of the second and third transistors have the same duty cycle, and the phase difference is 180°.

12. The switched capacitor charging circuit according to claim 1, wherein, A switching transistor is also provided between the first port and the switched capacitor circuit to prevent current from flowing back into the first voltage source.

Images