Semiconductor device and method for forming the same

Abstract

A method of forming a semiconductor device includes: forming a nanostructure stack above a substrate; forming a source / drain opening adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain opening; performing ion implantation in the semiconductor layer to form an amorphous semiconductor layer; and forming a recrystallized source / drain by annealing the amorphous semiconductor layer.

Description

Technical Field

[0001] none Prior Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in successive generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC development, functional density (the number of interconnected devices per chip area) has generally increased, while geometry size (the smallest component (or circuit) that can be created using the manufacturing process) has decreased. This process size reduction generally offers advantages by increasing production efficiency and reducing associated costs. However, this reduction in size also increases the complexity of IC processing and manufacturing. Summary of the Invention

[0003] none Simple diagram description

[0004] The following detailed description, when read in conjunction with the accompanying drawings, provides a better understanding of the various embodiments of the present disclosure. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration. FIG. 1A and FIG. 1B are exemplary cross-sectional side views of a portion of an IC device according to an embodiment of the present disclosure; Figures 2A to 12 are views of various embodiments of the IC device at various manufacturing stages according to the present disclosure; FIG. 13 is a flow chart of a method of forming an IC device according to various embodiments; and FIG. 14 is a flow chart illustrating a method of forming an IC device with regrown source / drain according to various embodiments. Implementation Method

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these specific examples are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, for descriptive purposes, spatially relative terms (e.g., "underlying," "beneath," "bottom," "overlying," "above," and the like) may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0007] Terms indicating relative degrees, such as "approximately" and "substantially", etc., should be interpreted according to the opinions of one of ordinary skill in the art taking into account the current technical specifications.

[0008] The terms "first," "second," "third," etc. may be used in this disclosure to describe a sequence of events or a sequential order of elements, but may be interchangeable or varied in some contexts. For example, a second layer may be formed on a first layer (e.g., after the first layer), but in some contexts, the first layer may be referred to as the "second layer," "third layer," "fourth layer," etc., and the second layer may be referred to as the "first layer," "third layer," "fourth layer," etc.

[0009] The term "surrounding" may be used throughout this disclosure to describe a structure that completely or partially surrounds another element or structure, for example, in three dimensions. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) without surrounding the second structure on two vertical sides (e.g., top and bottom). In other examples, a first structure may partially surround a second structure, for example by surrounding three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0010] The present disclosure generally relates to a semiconductor device, and more specifically to a field-effect transistor (FET) (e.g., a planar FET, a three-dimensional fin FET (FinFET)) or a nanostructured FET (e.g., a nanosheet FET (NSFET), a nanowire FET (NWFET), a gate-all-around FET (GAAFET), etc.).

[0011] Defects can relax the source-drain epitaxial strain, leading to a decrease in the on-current relative to the off-current (e.g., I on - I off) in nanosheet devices. One observed defect source is stacking faults in (111) or other orientations. The source / drain material may also have high resistance due to insufficient dopant activation. Therefore, the process configured to form the source / drain may lack the selectivity of process conditions that can restore the source / drain strain and improve dopant activation.

[0012] Embodiments disclosed herein form amorphous source / drain epitaxial layers, followed by solid-phase epitaxy regrowth (SPER). SPER causes the amorphous source / drain epitaxial layers to regrow or recrystallize to form the source / drain. Amorphization of the source / drain epitaxial layers can be achieved through ion implantation or by introducing post-source-drain epitaxial material to form a substantially completely amorphous source-drain material. SPER is then induced through an annealing process to cause the amorphous source / drain material to regrow or recrystallize. SPER can be performed in one or more anneals prior to forming a contact etch stop layer (CESL), an interlayer dielectric (ILD), and / or a replacement gate. Alternatively or additionally, SPER can be performed as part of a thermal budget during or after CESL, ILD, and replacement gate formation.

[0013] Various embodiments disclosed herein have multiple advantages. Because the SPER along the (100) direction is at least an order of magnitude faster than along the (111) direction, defects can be removed and the strain of the source / drain material can be restored through the SPER step. SPER is performed on the amorphous source / drain material to re-grow or recrystallize the amorphous source / drain material so that the source / drain material on the adjacent channel recovers the strain due to the reduction of stacking faults, and this recovery can be performed through a combination of amorphization ion implantation and annealing processes. The amorphization ion implantation can remove or reduce defects (e.g., (111) stacking fault defects) generated during the epitaxial growth prior to the annealing process. Performing SPER can increase dopant activation, thereby further improving the I on-I off performance and source / drain resistance of the nanosheet device. The amorphization ion implantation and annealing process can enhance the strain in the source / drain region, thereby improving the electrical characteristics of the channel.

[0014] FIG1A illustrates an exemplary cross-sectional side view of a portion of a nanostructure device 10 according to various embodiments. FIG1A illustrates a view in the XZ plane. The nanostructure device 10 of FIG1A is described in detail below to provide a context for understanding the technical features and advantages of the various embodiments depicted in FIG2A through FIG12. Nanostructure device 10 includes source / drain regions (or "source / drains") 82P and 82N. Due to SPER performed during and / or after the formation of the source / drain regions, the source / drain regions 82P and 82N may be substantially free of stacking fault defects or have a reduced number of stacking fault defects. Depending on the context, the source / drain regions may be individually or collectively referred to as a source or a drain. Although the nanostructure device 10 is described as a nanosheet transistor (or "nanostructure device" 20A, 20B), it should be understood that embodiments may also include planar field effect transistors (FETs) or fin FETs (FinFETs), and the source / drain regions of each transistor may include source / drain regions that have undergone SPER as described in Figures 2A to 12.

[0015] Referring to FIG. 1A , nanostructure devices 20A and 20B may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). Nanostructure devices 20A and 20B are formed above and / or in substrate 110 . Nanostructure devices 20A and 20B typically include a gate structure 200 (or "nanostructure") that spans and / or surrounds semiconductor channels 22A, 22B, and 22C. Gate structure 200 is located above semiconductor fin 32 and protrudes from and is separated by isolation structure 36 (see FIG. 3B ). Gate structure 200 controls current flow through channels 22A, 22B, and 22C.

[0016] Nanostructure devices 20A and 20B are depicted as including three channels 22A, 22B, and 22C. Channels 22A, 22B, and 22C are laterally adjacent to source / drain elements 82N and 82P and are covered and surrounded by a gate structure 200. Generally, the number of channels 22 is two or more, such as three or four or more. Gate structure 200 controls the flow of current through channels 22A, 22B, and 22C to and from source / drain elements 82N and 82P based on voltages applied to gate structure 200 and source / drain elements 82N and 82P. Source / drain elements 82N and 82P may also be referred to as source / drain elements 82.

[0017] In some embodiments, fin structure 32 comprises silicon. In some embodiments, nanostructure device 20B comprises an NFET, and the source / drain element 82N of the NFET comprises silicon-phosphorus (SiP), SiAs, SiSb, SiPA, SiP:As:Sb, or combinations thereof. In some embodiments, nanostructure device 20A comprises a PFET, and the source / drain element 82P of the PFET comprises undoped or doped silicon-germanium (SiGe), such as SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or other suitable semiconductor materials. In general, source / drain elements 82N and 82P may comprise any combination of suitable semiconductor materials and suitable dopants. In some embodiments, source / drain elements 82N and 82P comprise SixCy, SixGey, SixSby, SixPy, or SixAsy, where, according to various embodiments, 0≤x≤1 and 0≤y≤1.

[0018] In some embodiments, source / drain elements 82N and 82P may include one or more implanted ions, and the implanted ions may be or include one or more species, such as Group III species including B, Al, and Ga, Group IV species including C, Si, Ge, Group V species including P, As, and Sb, Group VIII species including He, Ar, and Xe, or combinations thereof. As shown in Figures 8A to 8H, the ions may be implanted at an implant energy between approximately 1 kiloelectronvolt (keV) and approximately 60 keV. In some embodiments, the ion implantation dose is greater than approximately 1×10 13 cm -2, for example, between approximately 1×10 13 cm -2 and approximately 1×10 22 cm -2. In some embodiments, the dose of the Group III and / or Group V species is between approximately 1×10 19 cm -2 and approximately 1×10 22 cm -2. Such a dose is beneficial for improving the SPER rate. However, above approximately 1×10 22 cm -2, the SPER rate may decrease. The implantation temperature may be between approximately -150°C and approximately 500°C. In some embodiments, the implantation temperature is room temperature. Higher temperatures (e.g., greater than approximately 500°C) may reduce the generation of defects during the implantation process. Temperatures in the low temperature range may enhance the formation of amorphous source / drain material. "High temperature cryogenics" may refer to temperatures between approximately -50°C and approximately -195.79°C, and "low temperature cryogenics" may refer to temperatures below approximately -195.79°C. The low temperature range may include high temperature cryogenics, low temperature cryogenics, or a combination thereof.

[0019] Each channel 22A, 22B, 22C comprises a semiconductor material, such as silicon or a silicon compound (e.g., silicon germanium). Channels 22A, 22B, 22C are nanostructures (e.g., with dimensions in the range of a few nanometers), and each channel 22A, 22B, 22C may have an elongated shape and extend in the X-direction. In some embodiments, each channel 22A, 22B, 22C may have a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profile of channels 22A, 22B, 22C may be rectangular, circular, square, round, elliptical, hexagonal, or a combination thereof.

[0020] In some embodiments, the lengths of channels 22A, 22B, and 22C (e.g., measured in the X-direction) may vary from one another, for example due to tapering during a fin etching process (see FIGS. 3A and 3B ). In some embodiments, the length of channel 22C may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22A. For example, due to a channel trimming process configured to increase the spacing between channels 22A, 22B, and 22C (e.g., measured in the Z-direction) to increase the process window for gate structure fabrication, each channel 22A, 22B, and 22C may not have a uniform thickness (e.g., along the X-direction). For example, the middle portion of each channel 22A, 22B, and 22C may be thinner than the ends of each channel 22A, 22B, and 22C, and this shape may be collectively referred to as a "dogbone" shape.

[0021] In some embodiments, the spacing between channels 22A, 22B, and 22C (e.g., between channels 22B and 22A, or between channels 22B and 22C) is between about 8 nanometers (nm) and about 12 nm, but may also exceed or fall below this range. In some embodiments, the thickness of each channel 22A, 22B, and 22C (e.g., measured in the Z direction) is between about 5 nm and about 8 nm, but may also exceed or fall below this range. In some embodiments, the width of each channel 22A, 22B, and 22C (e.g., measured in the Y direction, as shown in FIG. 3A , perpendicular to the XZ plane) is at least about 8 nm, but in some embodiments, this width may be less than 8 nm.

[0022] The gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, respectively. In some embodiments, the gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, and the channels 22A, 22B, and 22C are silicon channels configured for an N-type device or silicon-germanium channels configured for a P-type device. In some embodiments, the gate structure 200 includes an interfacial layer (IL) 210, one or more gate dielectric layers 600 disposed on the interfacial layer 210, optionally one or more work function adjustment layers 900 disposed on the gate dielectric layer 600 (see FIG. 12 ), and optionally a metal core layer 290 disposed on the gate dielectric layer 600 or on the work function adjustment layer 900.

[0023] The interfacial layer 210 can be an oxide of the material of the channels 22A, 22B, and 22C, and is formed on the exposed areas of the channels 22A, 22B, and 22C and the top surface of the fin 32. The interfacial layer 210 can facilitate the bonding between the gate dielectric layer 600 and the channels 22A, 22B, and 22C. In some embodiments, the thickness of the interfacial layer 210 ranges from approximately 5 angstroms (Å) to approximately 50 angstroms (Å). In some embodiments, the thickness of the interfacial layer 210 is approximately 10 Å. An interfacial layer 210 that is too thin may result in voids or poor adhesion. An interfacial layer 210 that is too thick may deplete the gate fill window, which is related to threshold voltage adjustment and resistance. In some embodiments, the interfacial layer 210 is doped with a dipole (e.g., lanthanum) to adjust the threshold voltage.

[0024] In some embodiments, gate dielectric layer 600 includes at least one high-k gate dielectric material. A high-k gate dielectric material may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In some embodiments, gate dielectric layer 600 has a thickness ranging from approximately 5 angstroms to approximately 100 angstroms. Gate dielectric layer 600 may be a single layer or multiple layers.

[0025] The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may include a conductive material such as Co, W, Ru, or a combination thereof. In some embodiments, the metal core layer 290 is or includes a Co-based, W-based, or Ru-based compound or alloy, and the Co-based, W-based, or Ru-based compound or alloy includes one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, or a combination thereof. Between the channels 22A, 22B, and 22C, the metal core layer 290 is surrounded by one or more work function metal layers 900 (in the cross-sectional view). The work function metal layers 900 are then surrounded by a gate dielectric layer 600. The gate structure 200 may further include a glue layer formed between the one or more work function layers 900 and the metal core layer 290 to enhance adhesion. For simplicity, the glue layer is not specifically shown in FIG. 1A .

[0026] Nanostructure devices 20A, 20B may further include source / drain contacts 120 formed over source / drain elements 82N, 82P. Source / drain contacts 120 may include a core layer that is or includes a conductive material, such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. The core layer may be surrounded by one or more liner (or "barrier") layers, such as SiN or TiN, that help prevent or reduce diffusion of material from or into source / drain contacts 120. In some embodiments, source / drain contacts 120 may be between approximately 1 nm and approximately 50 nm.

[0027] A silicide layer 118 is located between the source / drain elements 82N and 82P and the source / drain contacts 120. The silicide layer 118 is configured to reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, or YbSi. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, or OsSi. The thickness of the silicide layer 118 may be between approximately 1 nm and approximately 10 nm. A thickness of less than approximately 1 nm may not be sufficient to reduce the contact resistance. When the thickness of the silicide layer 118 is greater than about 10 nm, an electrical short circuit may be caused with the nanostructure 22. In some embodiments, the silicide layer 118 is located below the etch stop layer 131 and contacts the etch stop layer 131.

[0028] Nanostructure devices 20A and 20B may further include an interlayer dielectric layer 130 (ILD; see FIGS. 9A and 9B ). ILD 130 provides electrical isolation between various components of nanostructure devices 20A and 20B, such as between adjacent pairs of source / drain contacts 120. Prior to forming ILD 130, an etch stop layer 131 (see FIG. 11 ) may be formed. Etch stop layer 131 is laterally positioned between ILD 130 and gate spacers 41 and vertically positioned between ILD 130 and source / drain components 82N and 82P. In some embodiments, etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO₂, ZrO₂, ZrAlO₂, HfAlO₂, HfSiO₂, Al₂O₃, or other suitable materials. In some embodiments, the thickness of the etch stop layer 131 is between about 1 nm and about 5 nm. In some embodiments, in some embodiments where the ILD 130 is not present (e.g., the ILD 130 is completely removed before forming the source / drain contacts 120), the etch stop layer 131 may contact the source / drain contacts 120. Before forming the source / drain contacts 120, the etch stop layer 131 may be trimmed, for example, in the X direction, to improve the fill quality of the source / drain contacts 120.

[0029] Nanostructure devices 20A and 20B include gate spacers 41 and inner spacers 74. Gate spacers 41 are located on the sidewalls of the metal core layer 290, gate dielectric layer 600, and IL 210 above channel 22A. Inner spacers 74 are located on the sidewalls of IL 210 and / or gate dielectric layer 600 between channels 22A, 22B, and 22C. Inner spacers 74 are also located between channels 22A, 22B, and 22C. In the embodiment shown in FIG. 1A , gate spacers 41 include a first spacer layer 41A and a second spacer layer 41B located on the first spacer layer 41A. Both the first spacer layer 41A and the second spacer layer 41B may include a dielectric material, such as a low-k material (e.g., SiOCN, SiON, SiN, SiCN, or SiOC). In some embodiments, gate spacers 41 do not include the second spacer layer 41B. The material of the first spacer layer 41A and the material of the second spacer layer 41B can be the same or different. In some embodiments, the upper portion of the second spacer layer 41B (or the first spacer layer 41A when the gate spacer 41 does not include the second spacer layer 41B) can be partially or completely removed to increase the aspect ratio of the openings forming the source / drain regions 82N and 82P. FIG. 1A illustrates an embodiment in which the upper portions of 82N and 82P have not been thinned.

[0030] Isolation structure 90 can be located on either side of a corresponding nanostructure device 20A, 20B. In some embodiments, isolation structure 90 extends horizontally from below the bottom surface of source / drain 82N, 82P to above the top surface of source / drain 82N, 82P. Isolation structure 90 can include one or more dielectric layers. Isolation structure 90 provides physical and / or electrical isolation between nanostructure device 20A, 20B and adjacent devices. In some embodiments, nanostructure device 20A, 20B does not include isolation structure 90.

[0031] In FIG. 1A , nanostructure devices 20A and 20B are depicted as being located on the same substrate 110 but on different regions of the substrate 110. For example, nanostructure devices 20A and 20B are offset from each other on the substrate 110. Nanostructure device 20A is a p-type field-effect transistor (PFET), while nanostructure device 20B is an n-type field-effect transistor (NFET). In some embodiments, nanostructure device 20B includes a dielectric layer 800, which isolates the underlying substrate 110 or fin 32 from the source / drain 82N. Dielectric layer 800 may be referred to as a flexible bottom insulator (FBI) or bottom dielectric isolation (BDI), among other things.

[0032] In FIG. 1A , the source / drain 82P may include a first source / drain portion 82P1 and a second source / drain portion 82P2 located above the first source / drain portion 82P1. The first source / drain portion 82P1 is adjacent to the undoped semiconductor layer 110A located below the source / drain 82P and the channel 22. The second source / drain portion 82P2 is located above the first source / drain portion 82P1. A visible interface may be included between the first source / drain portion 82P1 and the second source / drain portion 82P2. In some embodiments, the first source / drain portion 82P1 and the second source / drain portion 82P2 may differ in one or more characteristics. For example, the material of the first source / drain portion 82P1 may be different from the material of the second source / drain portion 82P2. For example, the dopant concentration of the first source / drain portion 82P1 may be different from the dopant concentration of the second source / drain portion 82P2. In some embodiments, the material of the first source / drain portion 82P1 and the material of the second source / drain portion 82P2 may be substantially the same, but have different lattice directions due to being formed in different epitaxial growth steps.

[0033] The source / drain 82N may include a first source / drain portion 82N1 and a second source / drain portion 82N2 located on the first source / drain portion 82N1. The first source / drain portion 82N1 is adjacent to the channel 22. The second source / drain portion 82N2 is located on the first source / drain portion 82N1 and the dielectric layer 800. A visible interface may be included between the first portion 82N1 and the second source / drain portion 82N2. In some embodiments, the first source / drain portion 82N1 and the second source / drain portion 82N2 may differ in one or more characteristics. For example, the material of the first source / drain portion 82N1 may be different from the material of the second source / drain portion 82N2. For example, the dopant concentration of the first source / drain portion 82N1 may differ from the dopant concentration of the second source / drain portion 82N2. In some embodiments, the material of the first source / drain portion 82N1 and the material of the second source / drain portion 82N2 may be substantially the same, but have different lattice directions due to being formed in different epitaxial growth steps.

[0034] FIG. 1B illustrates a simplified diagram of a process 400 configured to regrow or recrystallize the source / drain 82 , according to various embodiments.

[0035] In FIG1B , the source / drain 82 includes a first portion 82_1 and a second portion 82_2 located above the first portion 82_1. The first portion 82_1 may be an embodiment of the first source / drain portions 82N1 and 82P1, and the second portion 82_2 may be an embodiment of the second source / drain portions 82N2 and 82P2. FIG1B illustrates a dielectric layer 800, but in some embodiments, the dielectric layer 800 may be omitted.

[0036] The source / drain 82 may include one or more stacking faults 82F, and the stacking faults 82F may be in a (111) orientation. The stacking faults 82F may be arranged at an offset angle θ, which may form an angle of approximately 54.7° with the horizontal direction or an angle of approximately 35.3° with the vertical direction.

[0037] In process 400 , the source / drain 82 may be amorphized, and then solid phase epitaxial regrowth (SPER) may be performed through one or more anneals to recrystallize the source / drain 82 and remove the stacking faults 82F.

[0038] As shown in Figures 13 and 14, methods 1000, 2000 illustrate an embodiment of process 400 in more detail, along with Figures 2A to 12 of apparatus 10 at intermediate stages of the process.

[0039] Figures 13 and 14 illustrate flow charts of methods 1000 and 2000 for forming an IC device or a portion thereof from a workpiece, according to one or more embodiments of the present disclosure. Methods 1000 and 2000 are merely examples and are not intended to limit the present disclosure to the specific disclosures of methods 1000 and 2000. Additional steps may be provided before, during, and after methods 1000 and 2000, and some of the steps described may be replaced, deleted, or moved to other embodiments of the methods. For the sake of simplicity, not all steps are described in detail. Methods 1000 and 2000 are described below with partial perspective and / or cross-sectional views of the workpiece at various stages of fabrication, as shown in the embodiments of Figures 2A through 12. Figures 2A, 3A, and 4A depict section line BB', and Figure 4A depicts section line CC'. For the avoidance of doubt, in all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions. It should be noted that since the workpiece can be manufactured into a semiconductor device, the workpiece can be referred to as a semiconductor device depending on the context.

[0040] 2A through 12 are diagrams of various embodiments of a FET (eg, a nanostructured FET) at various stages of fabrication according to embodiments of the present disclosure.

[0041] See Figures 2A and 2B. A substrate 110 is provided. Substrate 110 can be a semiconductor substrate, such as a bulk semiconductor. Substrate 110 can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of substrate 110 can include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates can be used, such as single-layer, multi-layer, or gradient substrates.

[0042] Furthermore, as shown in FIG2A and FIG2B , a multilayer stack 25 or "lattice" is formed over substrate 110, comprising alternating layers of first semiconductor layers 21A, 21B, and 21C (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23. In some embodiments, first semiconductor layers 21 may be formed of a first semiconductor material suitable for n-type nanoFETs, such as silicon or silicon carbide, and second semiconductor layers 23 may be formed of a second semiconductor material suitable for p-type nanoFETs, such as silicon germanium. The first and second semiconductor layers 21, 23 of multilayer stack 25 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE).

[0043] Taking the example of the first semiconductor layer 21 and the second semiconductor layer 23 each having three layers, in some embodiments, the multilayer stack 25 may include fewer or more pairs of first semiconductor layers 21 and second semiconductor layers 23. Although the multilayer stack 25 is illustrated with the second semiconductor layer 23 as the bottom layer, in some embodiments, the bottom layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0044] Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby enabling the first semiconductor layer 21 to be patterned to form the channel region of the nanoFET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region of the nanoFET. The high etch selectivity enables the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby enabling the second semiconductor layer 23 to be patterned to form the channel region of the nanoFET.

[0045] As shown in Figures 3A and 3B, corresponding to step 1100 in Figure 13, fins 32 are formed in substrate 110, and nanostructures 22 and 24 are formed in multilayer stack 25. In some embodiments, nanostructures 22 and 24 and fins 32 are formed by etching trenches in multilayer stack 25 and substrate 110. The etching process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching process can be anisotropic. First nanostructures 22A, 22B, and 22C (hereinafter referred to as "channels 22") are formed from first semiconductor layer 21, and second nanostructure 24 is formed from second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22 can be between approximately 18 nm and approximately 100 nm. However, in some embodiments, a distance CD1 less than 18 nm may be advantageous. For simplicity, the portion of the device 10 depicted in Figures 3A and 3B includes only two fins 32. Corresponding to the method 1000 of Figure 13, the number of fins can be any number and is not limited to the two fins 32 shown in Figures 3A to 12.

[0046] Fins 32 and nanostructures 22 and 24 can be patterned using any suitable method. For example, one or more lithographic processes, including double or multi-patterning processes, can be used to form fins 32 and nanostructures 22 and 24. Generally, double or multi-patterning processes combine lithography with self-aligned processes, which can achieve a finer pitch than can be achieved using a single direct lithographic process. As an example of a multi-patterning process, a sacrificial layer can be formed over a substrate and patterned using a lithographic process. Spacers can then be formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern fins 32.

[0047] 3A and 3B illustrate fins 32 having tapered sidewalls, such that the width of each fin 32 and / or nanostructures 22, 24 continuously increases in a direction toward substrate 110. In such embodiments, each nanostructure 22, 24 may have a different width and may be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the fins 32 and nanostructures 22, 24 are substantially similar, and each nanostructure 22, 24 is rectangular in shape.

[0048] As shown in Figures 3A and 3B, isolation regions or elements 36 may be shallow trench isolation (STI) regions or elements formed adjacent to fins 32. Isolation regions 36 may be formed by depositing an insulating material over substrate 110, fins 32, and nanostructures 22 and 24, and between adjacent fins 32 and nanostructures 22 and 24. The insulating material may be an oxide, such as silicon oxide, nitride, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. In some embodiments, a liner (not separately shown) may be formed along the surfaces of substrate 110, fins 32, and nanostructures 22 and 24. A core material, such as that described above, may then be formed over the liner.

[0049] The insulating material is processed by a removal process, such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof, to remove excess insulating material above the nanostructures 22 and 24. After the removal process is completed, the top surfaces of the nanostructures 22 and 24 can be exposed and flush with the insulating material.

[0050] The insulating material is then recessed to form isolation regions 36. After the recessing, the upper portions of nanostructures 22, 24 and fins 32 may protrude from between adjacent isolation regions 36. The top surface of isolation regions 36 may be flat (as shown), convex, concave, or a combination thereof. In some embodiments, isolation regions 36 are recessed using an acceptable etching process, such as dilute hydrofluoric acid (dHF), to remove oxide. Due to the etch selectivity to the insulating material, fins 32 and nanostructures 22, 24 are left substantially unchanged.

[0051] Figures 2A through 3B illustrate one embodiment of forming fin 32 and nanostructures 22 and 24 (e.g., etching last). In some embodiments, fin 32 and / or nanostructures 22 and 24 are epitaxially grown in trenches in a dielectric layer (e.g., etching first). The epitaxial structure may include the aforementioned alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material.

[0052] As shown in Figures 3A and 3B, suitable wells (not separately shown) can be formed in fin 32, nanostructures 22, 24, and / or isolation region 36. Through a mask, n-type impurities can be implanted in the p-type region of substrate 110, and p-type impurities can be implanted in the n-type region of substrate 110. For example, n-type impurities may include phosphorus, arsenic, or antimony. For example, p-type impurities may include boron, boron fluoride, or indium. Annealing can be performed after the impurity implantation to repair damage caused by the implantation and activate the p-type and / or n-type impurities. In some embodiments, in-situ doping during the epitaxial growth of fin 32 and nanostructures 22, 24 can be performed separately from implantation doping, but in-situ doping and implantation doping can also be performed together.

[0053] As shown in Figures 4A to 4C , corresponding to step 1200 of Figure 13 , a sacrificial or dummy gate structure 40 is formed over the fin 32 and / or nanostructures 22 and 24. A sacrificial or dummy gate layer 45 is formed over the fin 32 and / or nanostructures 22 and 24. The dummy gate layer 45 may be or include a material having a high etch selectivity relative to the isolation region 36. The dummy gate layer 45 may be a conductive, semiconducting, or non-conductive material, and may be or include amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, or metal. The dummy gate layer 45 may be deposited using physical vapor deposition (PVD), CVD, sputtering, or other techniques. A mask layer 47 is formed over the dummy gate layer 45, and the mask layer 47 may be, for example, silicon nitride or silicon oxynitride. In some embodiments, before forming the dummy gate layer 45, a gate dielectric layer 43 is formed between the dummy gate layer 45 and the fins 32 and / or nanostructures 22 and 24. In some embodiments, the mask layer 47 includes a first mask layer 47A in contact with the dummy gate layer 45 and a second mask layer 47B covering the first mask layer 47A, with the second mask layer 47B in contact with the first mask layer 47A. The first mask layer 47A may be or include a material that is the same as or different from that of the second mask layer 47B.

[0054] A spacer layer 41 is formed over the sidewalls of the mask layer 47 and the dummy gate layer 45. In some embodiments, the spacer layer 41 is or includes an insulating material such as SiOCN, SiOC, SiCN (or any of the materials described in FIG. 1A ), and can have a single-layer structure or a multi-layer structure including multiple dielectric layers. The spacer layer 41 can be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. In some embodiments, the portion of the spacer material layer between the dummy gate structures 40 is removed by an anisotropic etching process. In some embodiments, as shown in detail in FIG. 4B and FIG. 4C , the spacer layer 41 includes a first spacer layer 41A in contact with the nanostructure 22C, the gate dielectric layer 43, the dummy gate layer 45, the first mask layer 47A, and the second mask layer 47B. The second spacer layer 41B of the spacer layer 41 can be in contact with the first spacer layer 41A. The first spacer layer 41A may be or include a material that is the same as or different from that of the second spacer layer 41B.

[0055] As shown in Figures 5A and 5B , corresponding to step 1300 of Figure 13 , an etching process is performed to etch the portions of the protruding fins 32 and / or nanostructures 22 and 24 not covered by the dummy gate structure 40, thereby forming source / drain openings 59. The recess can be formed anisotropically, such that the portion of the fin 32 directly beneath the dummy gate structure 40 and the spacer layer 41 is protected and substantially unetched. According to some embodiments, the top surface of the recessed fin 32 can be substantially coplanar with the top surface of the isolation region 36. According to some other embodiments, as shown in Figure 5B , the top surface of the recessed fin 32 can be lower than the top surface of the isolation region 36. For simplicity, Figure 5A illustrates three vertical stacks of nanostructures 22 and 24 after the etching process. In general, the etching process can be configured to form fewer or more vertical stacks of nanostructures 22 and 24 above the fin 32 than shown. In some embodiments, after the etching process, the second mask layer 47B is exposed, for example due to removal of upper portions of the spacer layers 41A and 41B during the etching process. FIG. 5B illustrates a fin spacer 41F, which is a portion of the first spacer layer 41A and / or the second spacer layer 41B located above the isolation region 36 of the adjacent corresponding fin 32.

[0056] 6A-7B illustrate the formation of inner spacers 74 according to various embodiments.

[0057] As shown in Figures 6A and 6B, a selective etching process is performed to recess the end of nanostructure 24 exposed through the opening in spacer layer 41 while substantially not etching nanostructure 22. After the selective etching process, a recess is formed at the end of nanostructure 24. Subsequently, after the recess is formed, an inner spacer layer 74L is formed to fill (partially or completely) the recess in nanostructure 22 formed in the previous step through the selective etching process. Inner spacer layer 74L can be formed of a suitable dielectric material using a suitable deposition method such as PVD, CVD, or ALD. The dielectric material may be, for example, silicon carbonitride (SiCN) or silicon oxycarbonitride (SiOCN).

[0058] As shown in FIG. 7A and FIG. 7B , after forming the inner spacer layer 74L, an etching process (e.g., an anisotropic etching process) is performed to remove the portion of the inner spacer layer 74L located outside the recess (e.g., the portion on the sidewall of the nanostructure 22). The remaining portion of the inner spacer layer 74L (e.g., the portion located inside the recess in the nanostructure 24) forms the inner spacer 74, as shown in FIG. 7A .

[0059] 8A-8H illustrate the formation of recrystallized source / drain 82 according to various embodiments.

[0060] As shown in Figures 8A, 8B, 8C, and 8D, corresponding to step 1400 in Figure 13, a first material layer 110A is formed in the source / drain opening 59. The first material layer 110A may be or include an undoped semiconductor, such as undoped silicon. Deposition may include one or more steps, such as CVD, which may be ultra-high vacuum chemical vapor deposition (UHV-CVD). UHV-CVD can improve control over the deposition rate and purity of the first material layer 110A. The first material layer 110A may extend to or slightly above the upper surface of the fin 32. In some embodiments, the first material layer 110A is not formed.

[0061] Then, corresponding to steps 1500 and 1600 of FIG. 13 , a bottom insulator 800 and source / drain layer 82L may or may not be formed. The bottom insulator 800 may be formed on the first material layer 110A. In some embodiments, the bottom insulator 800 is formed in the region of the substrate 110 associated with the n-type source / drain 82N. Although FIG. 8A and FIG. 8B illustrate the formation of a single type of source / drain 82, the first source / drain 82N and the second source / drain 82P as shown in FIG. 1A may also be formed in step 1600. For example, a device 10 including an n-type source / drain 82N may advantageously include the bottom insulator 800, while a device 10 including a p-type source / drain 82P may advantageously not include the bottom insulator 800.

[0062] The first source / drain 82N and the second source / drain 82P can be formed in separate steps. For example, while forming the first source / drain 82N, the area on the substrate 110 where the second source / drain 82P will be formed can be shielded. Then, while forming the second source / drain 82P, the area on the substrate 110 where the first source / drain 82N will be formed can be shielded. The order of forming the first source / drain 82N and the second source / drain 82P can be reversed. That is, the second source / drain 82P can be formed before the first source / drain 82N. In some embodiments, a first source / drain layer can be formed to be recrystallized to form the first source / drain 82N, and then a second source / drain layer can be formed to be recrystallized to form the second source / drain 82P, or vice versa.

[0063] In some embodiments, a bottom insulator 800 may or may not be formed in the source / drain openings 59 associated with the n-type nanostructure device before or after forming the source / drain regions 82P. The bottom insulator 800 may be formed by a suitable deposition process, such as low-pressure CVD (LPCVD), PECVD, or ALD. The bottom insulator 800 may be or include SiN or another suitable dielectric material. The thickness of the bottom insulator 800 may be between approximately 2 nm and approximately 4 nm.

[0064] After forming the bottom insulator 800, the source / drain region 82N (or n-type source / drain layer) is epitaxially grown using an epitaxial material. Due to the bottom insulator 800, the source / drain layer 82L can be grown from the channel 22 rather than from the first semiconductor layer 110A. For example, as shown in FIG. 8C , the source / drain layer 82L can have a first portion 82_1 that grows outward from the channel 22, and a second portion 82_2 that grows from the first portion 82_1.

[0065] As shown in FIG. 8D , epitaxial growth can be performed using epitaxial material in a source / drain layer 82L associated with a p-type nanostructure device. Because a bottom insulator 800 is absent, the source / drain layer 82L can be grown from the channel 22 and the undoped silicon layer 110A. For example, a first portion 82_1 of the source / drain layer 82L can be grown outward from the channel 22 and upward from the undoped silicon layer 110A, and a second portion 82_2 of the source / drain layer 82L can be grown from the first portion 82_1.

[0066] In some embodiments, the source / drain layers 82L associated with n-type and p-type nanostructure devices can be formed directly on the first material layer 110A. That is, the bottom insulator 800 can be omitted for n-type nanostructure devices. For example, the source / drain layers 82L can be formed simultaneously in the same process for both n-type and p-type nanostructure devices. This can simplify the manufacturing process by eliminating one or more masking and patterning steps. In other embodiments, it can be beneficial to perform the amorphization and SPER steps in an existing process that includes forming the bottom insulator 800. This can be achieved by only slightly modifying the existing process to include the additional amorphization and SPER steps without changing the underlying structure (e.g., including the bottom insulator 800).

[0067] The source / drain layer 82L is formed such that each dummy gate structure 40 is located between adjacent pairs of source / drain layers 82L. In some embodiments, the source / drain layer 82L is separated from the dummy gate layer 45 by a suitable lateral distance through a spacer layer 41 to prevent electrical bridging of the gate of the ultimately formed device. The source / drain layer 82L may have a surface that is raised from the corresponding surface of the fin 32 and may have facets. In some embodiments, adjacent source / drain layers 82L may be merged to form a single source / drain layer 82L adjacent to two adjacent fins 32.

[0068] As shown in FIG. 8E and FIG. 8F , corresponding to step 1700 of FIG. 13 and step 2100 of FIG. 14 , an amorphous source / drain layer 82A is formed by amorphizing the source / drain layer 82L.

[0069] Forming the amorphous source / drain layer 82A or "amorphized source / drain layer 82A" may include one or more steps. Amorphizing the source / drain layer 82A may be performed using one or more ion implantation steps. In some embodiments, the ion implantation step includes implanting one or more ion species, which may include group III, group IV, group V, group VIII, or combinations thereof. Group III ions may include B, Al, or Ga ions; group IV ions may include C, Si, or Ge ions; group V ions may include P, As, or Sb ions; and group VIII ions may include He, Ar, or Xe ions. The ions may be implanted at an implant energy between approximately 1 keV and 60 keV. The ions may be implanted at a dose greater than approximately 1×10 13 cm -2 . In some embodiments, the concentration of the ion dopant in the source / drain layer 82A is between approximately 1×10 19 cm -3 and approximately 1×10 22 cm -3 . The SPER rate may be increased (or adjusted) by introducing the aforementioned concentrations of group III and group V species. Within the aforementioned concentration range, the SPER rate can be improved. When the ion dopant concentration is greater than approximately 1×10 22 cm -3 , the SPER rate may decrease. The implanted ions can be implanted at a temperature between approximately -150°C and approximately 500°C, such as room temperature. Higher temperatures, such as above approximately 400°C, can reduce the generation of defects during the implantation process, while lower temperatures can enhance the amorphization of the source / drain layer 82L.

[0070] Amorphization can be performed in two or more separate steps, for example to subsequently form the source / drain 82P and 82N of p-type and n-type nanostructure devices, respectively. That is, a first ion implantation step can be performed on the source / drain layer 82A associated with the p-type nanostructure device, followed by a second ion implantation step on the source / drain layer 82A associated with the n-type nanostructure device, or vice versa. In some embodiments, the first ion implantation step can be performed to implant Group III ions into the p-type region of the substrate 110 associated with the p-type nanostructure device. Before or after the first ion implantation step, a second ion implantation step can be performed to implant Group V ions into the n-type region of the substrate 110 associated with the n-type nanostructure device.

[0071] In some embodiments, Group IV and / or Group VIII materials are simultaneously implanted into the source / drain layer 82A associated with both p-type and n-type nanostructure devices. For example, because Group IV and / or Group VIII materials essentially do not generate excess carriers in the crystal lattice of the source / drain layer 82A, ion implantation can be performed simultaneously on both the n-type and p-type regions without masking either region. This simplifies the manufacturing process while achieving amorphization of the source / drain layer 82L.

[0072] As shown in Figures 8A to 8F, the source / drain layer 82L is shown as being formed in a crystalline state and then amorphized. In some embodiments, as shown in Figures 8A to 8D, the source / drain layer 82L is formed in an amorphous state. This avoids further or additional amorphization of the source / drain layer 82L, as shown in Figures 8E and 8F. That is, in some embodiments, steps 1600 and 1700 can be performed simultaneously. In some embodiments, it is advantageous to form the source / drain layer 82L in an amorphous state and then perform ion implantation on the source / drain layer 82L, as shown in Figures 8E and 8F.

[0073] Figures 8G, 8H, 9A, 9B, 10A, and 10B illustrate the formation of recrystallized or regrown source / drain 82 according to various embodiments. The embodiments described in Figures 8G through 10B can be combined. It should be understood that "recrystallization" and "regrowth" do not require an initial crystallization or growth followed by a second (or third, etc.) crystallization or growth. For example, when source / drain layer 82L is initially formed in an amorphous state, the "recrystallized" source / drain 82 may be crystallized for the first time. That is, "recrystallization" includes "the first crystallization."

[0074] As shown in FIG. 8G and FIG. 8H , corresponding to step 1800 of FIG. 13 and step 2200 and optional step 2300 of FIG. 14 , recrystallization of the amorphized source / drain layer 82A may be performed to form recrystallized source / drain 82. Recrystallization may include performing one or more solid phase epitaxial regrowth (SPER) steps. The thermal budget for SPER may be the original thermal budget in the process or may include additional annealing, which facilitates increased flexibility in implementing SPER in existing processes. The original thermal budget may, for example, include a thermal budget configured to form the CESL 131, ILD 130, or gate structure 200. For example, SPER may be performed after forming the CESL 131, ILD 130, or gate structure 200. In some embodiments, the thermal budget configured to form the CESL 131 and / or ILD 130 may include a temperature between approximately 400° C. and approximately 800° C. for a time interval between approximately 10 minutes and approximately 12 hours. In some embodiments, the thermal budget configured to form the gate structure 200 or "replacement gate" 200 may include a temperature between about 600° C. and about 1100° C. for a time interval between about 0.5 minutes and about 20 minutes.

[0075] The thermal budget after forming the gate structure 200 may be more constrained (e.g., lower temperature) to improve control of the threshold voltage (Vt). In some embodiments, instead of or in addition to the original thermal budget, one or more additional anneals may be performed before forming the CESL 131, for example, when the source / drain layer 82A is exposed in the source / drain opening 59.

[0076] In some embodiments, as shown in FIG. 8G and FIG. 8H , SPER can be performed by additional annealing when the source / drain layer 82A is exposed (e.g., before forming the CESL 131). The annealing can include one or more of rapid thermal annealing (RTA), furnace annealing, millisecond annealing, microsecond annealing, flash annealing, laser annealing, melt laser annealing, or a combination thereof. Performing the annealing can repair or prevent (111) or other directional stacking faults and restore or improve the strain of the recrystallized source / drain 82. For example, because the SPER along the (100) direction is about one order of magnitude faster than the SPER along the (111) direction, in some annealing steps including higher temperatures and shorter times (e.g., laser annealing), interstitial clusters can be dissolved to increase dopant activation, for example, through dopant substitution. In some embodiments, the annealing is performed at a temperature between about 600°C and about 1200°C, and for a time between about 1×10-10 seconds and about 1×10-6 seconds. The dopant solubility limit is the maximum concentration that can be achieved in equilibrium with the host lattice. Performing one or more SPERs can increase the active concentration significantly above the dopant solubility limit, thereby reducing the resistance of the recrystallized source / drain 82.

[0077] In some embodiments, prior to forming the CESL 131, an annealing step may be performed to partially or fully recrystallize the source / drain 82. FIG. 8G and FIG. 8H illustrate forming partially recrystallized source / drain 82 by performing one or more anneals while exposing the source / drain layer 82A. In some embodiments, forming the recrystallized source / drain 82 is accomplished by performing SPER while exposing the source / drain layer 82A.

[0078] As shown in FIG8G and FIG8H , because the source / drain layer 82A without the bottom insulator 800 has an additional height, recrystallization of the source / drain layer 82A overlying the bottom insulator 800 (as shown in FIG8G ) is completed before recrystallization of the source / drain layer 82A without the bottom insulator 800 (as shown in FIG8H ). In other words, the source / drain layer 82A without the bottom insulator 800 can have an additional height approximately equal to the thickness of the bottom insulator 800. Therefore, recrystallization of the source / drain layer 82A with the additional height can be completed before recrystallization of the source / drain layer 82A overlying the bottom insulator 800. In some embodiments, recrystallization of the source / drain 82 above the bottom insulator 800 can be completed by a first SPER. In embodiments where the bottom insulator 800 is not present, recrystallization of the source / drain 82 can be completed by performing a first SPER followed by a second SPER.

[0079] Recrystallization to partially or fully form the source / drain 82 may include performing a single SPER or two or more SPERs prior to forming the CESL 131 (eg, when exposing the source / drain layer 82A).

[0080] In some embodiments, SPER is omitted in FIG. 8G and FIG. 8H . Such embodiments may correspond to performing recrystallization of the source / drain layer 82A within the original thermal budget, as previously described. This is illustrated in FIG. 14 by the dashed boxes in steps 2200 and 2300.

[0081] 9A and 9B illustrate the formation of CESL 131 and ILD 130. ILD 130 may be formed to overlie source / drain layer 82A and / or the recrystallized source / drain 82, with ILD 130 abutting spacer layer 41. In some embodiments, CESL 131 is formed before forming ILD 130. CESL 131 may be formed by depositing a conformal thin layer of a dielectric material different from that of ILD 130, such as one or more of SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlOx, HfAlOx, HfSiOx, Al2O3, or other suitable materials. After depositing CESL 131, ILD 130 may be deposited using a suitable process, such as a blanket deposition process including PVD, CVD, or ALD. The material of ILD 130 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (approximately 3.9)). Low-k dielectric materials may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y), spin-on-glass (SOG), or combinations thereof. The ILD may be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD, or other deposition processes.

[0082] In some embodiments, corresponding to step 2400 of FIG. 14 , completing recrystallization of the source / drain layer 82A to form the recrystallized source / drain 82 can be performed simultaneously with and / or after forming the CESL 131 and the ILD 130, for example, utilizing a thermal budget associated with each process. In some embodiments, the source / drain layer 82A is not fully recrystallized during the formation of the CESL 131 and / or the ILD 130, but rather partially recrystallized. In some embodiments, the thermal budget configured to form the CESL 131 and / or the ILD 130 can include a time between about 10 minutes and about 12 hours at a temperature between about 400°C and about 800°C. As indicated by the dashed box in FIG. 14 , step 2400 can be optional. For example, in embodiments where the recrystallized source / drain 82 is completed before forming the CESL 131, step 2400 can be omitted.

[0083] As shown in FIG10A and FIG10B , an active gate structure 200 is formed. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the ILD 130 and ESL 131. During the planarization process, hard masks 47A and 47B and portions of the gate spacers 41 are also removed. After the planarization process, the dummy gate layer 45 is exposed. The top surfaces of the ILD 130 and ESL 131 can be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacers 41.

[0084] Next, the dummy gate layer 45 is removed in an etching process, thereby forming a recess. In some embodiments, the dummy gate layer 45 is removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas. The dry etching process selectively etches the dummy gate layer 45 while not etching the spacer layer 41. If a dummy gate dielectric layer 43 is present, the dummy gate dielectric layer 43 can serve as an etch stop layer when etching the dummy gate layer 45. After removing the dummy gate layer 45, the dummy gate dielectric layer 43 can be removed.

[0085] Nanostructure 24 is removed to release nanostructure 22. After removal of nanostructure 24, nanostructure 22 forms a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of substrate 110). In some embodiments, nanostructure 24 is removed by a selective etching process using an etchant that is selective for the material of nanostructure 24, such that nanostructure 24 is removed without substantially etching nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and / or a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, or a combination thereof.

[0086] In some embodiments, nanostructure 24 is removed and nanostructure 22 is patterned to form the channel regions of the PFET and the NFET. However, in some embodiments, nanostructure 24 may be removed and nanostructure 22 may be patterned to form the channel region of the NFET, and nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of the PFET. In some embodiments, nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of the NFET, and nanostructure 24 may be removed and nanostructure 22 may be patterned to form the channel region of the PFET. In some embodiments, nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of both the PFET and the NFET.

[0087] In some embodiments, nanosheet 22 is reshaped (e.g., thinned) by a further etching process to improve gate fill window. Reshaping can be performed by an isotropic etching process selectively applied to nanosheet 22. After reshaping, nanosheet 22 may have a dog-bone shape, where the center portion of nanosheet 22 is thinner than the surrounding portions of nanosheet 22 along the X-direction (e.g., as shown in FIG. 10A and FIG. 10B ).

[0088] Then, a replacement gate 200 is formed. The gate structure 200 can be formed by a series of deposition steps (eg, ALD cycles) that deposit various layers of the gate structure 200 in the opening, as described later in FIG. 12 .

[0089] In some embodiments, a thermal budget configured to form the gate structure 200 or "replacement gate" 200 may include a time between about 0.5 minutes and about 20 minutes and a temperature between about 600°C and about 1100°C.

[0090] FIG12 is a detailed view of a portion of a gate structure 200. The gate structure 200 typically includes an interfacial layer (IL, or "first IL" below) 210, at least one gate dielectric layer 600, a functional metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interfacial layer 240 or a second work function layer 700.

[0091] Referring to FIG. 12 , in some embodiments, the first IL 210 comprises an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the first IL 210 may comprise other suitable types of dielectric materials. The thickness of the first IL 210 is between approximately 5 angstroms and approximately 50 angstroms.

[0092] Continuing with FIG. 12 , a gate dielectric layer 600 is formed over the first IL 210. In some embodiments, an atomic layer deposition (ALD) process is used to precisely control the thickness of the gate dielectric layer 600. In some embodiments, the ALD process is performed at a temperature between about 200°C and about 300°C using about 40 to 80 deposition cycles. In some embodiments, the ALD process uses HfCl₄ and / or H₂O as precursors. This type of ALD process can form the first gate dielectric layer 600 with a thickness between about 10 angstroms and about 100 angstroms.

[0093] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or combinations thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, or yttrium, and at least one of which can be triggered by an annealing process to adjust the threshold voltage of the nanostructure devices 20A and 20B.

[0094] Referring further to FIG. 12 , a second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 can improve the adhesion of the metal gate to the gate dielectric layer 600. In many embodiments, the second IL 240 can also improve the thermal stability of the gate structure 200. The second IL 240 is configured to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is accomplished by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. The high-k capping layer includes one or more of the following: in various embodiments, HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO, or other suitable materials. In a specific embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, a high-k capping layer is deposited using ALD at a temperature of about 400°C to about 450°C using about 40 to about 100 cycles. A thermal anneal is then performed to form a second IL 240. In some embodiments, the second IL 240 may be or include TiSiNO. After forming the second IL 240 via thermal annealing, cyclic atomic layer etching (ALE) can be controlled using artificial intelligence (AI) control to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle can include a first pulse of WCl 5, followed by an Ar purge, a second pulse of O 2, and another Ar purge. Removing the high-k capping layer increases the gate fill window, allowing for further adjustment of multiple threshold voltages via metal gate patterning. In some embodiments, the thermal anneal includes SPER to partially or completely complete the recrystallization of the source / drain layer 82A.

[0095] Furthermore, in FIG. 12 , according to some embodiments, after forming the second IL 240 and removing the high-k capping layer, a work function blocking layer 700 may be optionally formed on the gate structure 200. The work function blocking layer 700 is or includes a metal nitride, such as TiN, WN, MoN, or TaN. In a specific embodiment, the work function blocking layer 700 is TiN. The thickness of the work function blocking layer 700 may be between approximately 5 Å and approximately 20 Å. The inclusion of the work function blocking layer 700 provides additional threshold voltage adjustment flexibility. Generally speaking, the work function blocking layer 700 increases the threshold voltage of NFET transistors and decreases the threshold voltage (magnitude) of PFET transistors.

[0096] A work function metal layer 900 is formed on the work function blocking layer 700. The work function blocking layer 700 may include at least one of an N-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer. In some embodiments, the N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, or TaAl. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, electroplating, and / or other suitable methods, and the thickness of the N-type work function metal layer is between approximately 10 Å and 20 Å. An in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN, or other suitable materials, and the thickness of the in-situ capping layer is between approximately 10 Å and 20 Å. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, which could cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed from a dielectric material capable of preventing oxygen from diffusing into the N-type work function metal layer and protecting the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness ranging from approximately 10 Å to approximately 20 Å.

[0097] FIG. 12 further illustrates the metal core layer 290. In some embodiments, a glue layer (not separately shown) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The glue layer can be configured to promote and / or enhance adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the glue layer can be formed of a metal nitride, such as TiN, TaN, MoN, WN, or another suitable material, and formed using ALD. In some embodiments, the glue layer has a thickness between approximately 10 Å and approximately 25 Å. The metal core layer 290 can be formed on the glue layer and can include a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, the metal core layer 290 can be deposited using methods such as CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, a seam 510 (air gap) is formed in the metal core layer 290 between the vertical channels 22A, 22B, and 22C. In some embodiments, the metal core layer 290 is conformally deposited on the work function metal layer 900. Since the deposited films on the sidewalls merge during conformal deposition, a seam 510 may be formed. In some embodiments, no seam 510 exists between adjacent channels 22A, 22B, 22C.

[0098] Referring again to FIG. 10A and FIG. 10B , corresponding to step 2500 in FIG. 14 , after forming the gate structure 200, source / drain contact openings may be formed in the ILD 130, and source / drain contacts 120 may be formed in the source / drain contact openings, as shown in FIG. 10A and FIG. Silicide regions 118 (as shown in FIG. 1A and FIG. 11 ) and source / drain contacts 120 are formed on the source / drain regions 82N and 82P.

[0099] In some embodiments, the silicide layer 118 is formed before forming the source / drain contacts 120. For example, an N-type or P-type metal layer can be formed as a thin, conformal layer over the exposed portions of the source / drain regions 82N and 82P. The metal layer can be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, and the like. In some embodiments, the metal layer is or includes one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or another suitable material. After forming the metal layer, the silicide layer 118 can be formed by annealing the device 10. After annealing, the silicide layer 118 may be or include NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, or YbSi. The silicide of the silicide layer 118 may diffuse into the area below the ESL 131. The thickness of the silicide layer 118 may be between about 1 nm and about 10 nm. When the thickness of the silicide layer 118 is less than 1 nm, the contact resistance may be too high. When the thickness of the silicide layer 118 is greater than 10 nm, the silicide layer 118 may short to the channel 22B. In some embodiments, the annealing to form the silicide layer 118 includes a SPER that partially or completely completes the recrystallization of the source / drain layer 82A.

[0100] After forming the silicide layer 118, source / drain contacts 120 are formed by filling the openings above the source / drain regions 82N and 82P with, for example, a liner layer and a filler layer. In some embodiments, the source / drain contacts 120 are formed by depositing a material that is or includes a conductive material such as Co, W, Ru, or a combination thereof. In some embodiments, the source / drain contacts 120 are or include a Co-based, W-based, or Ru-based compound or alloy and include one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, or a combination thereof. The source / drain contacts 120 are located on the silicide layer 118 and in contact with the ESL 131. A description of the device 10 is provided with reference to the drawings, which include a vertically stacked GAAFET of a nanostructure 22. In some embodiments, a silicide layer 118 and source / drain contacts 120 are formed in and over the source / drain regions 82N, 82P of a FinFET or planar device.

[0101] FIG. 11 illustrates a schematic cross-sectional view of an IC device 10 including nanostructure devices 20A, 20B, and 20C according to various embodiments. IC device 10 may be the device embodiments illustrated in FIG. 1A , FIG. 10A , and FIG. 10B , and like reference numerals in IC device 10 represent like features.

[0102] In FIG. 11 , an IC device 10 includes a recrystallized source / drain 82. In some embodiments, one or more visible interfaces 82I1 and 82I2 may exist between a first portion 820A, a second portion 820B, and a third portion 820C of the recrystallized source / drain 82 of the IC device 10. For example, a first visible interface 82I1 may exist between the first portion 820A and the second portion 820B, and a second visible interface 82I2 may exist between the second portion 820B and the third portion 820C. Visible interfaces 82I1 and 82I2 may exist because SPER is stopped midway during the recrystallization process of the source / drain layer 82A.

[0103] When the SPER of a continuous amorphous layer (e.g., source / drain layer 82A) is stopped and later resumed, certain properties around the interfaces between the recrystallized portions may be affected. Measurable properties that may be affected may include one or more of crystal defect density, dopant distribution, strain and / or stress, electrical properties, interface sharpness, material composition, optical properties, mechanical properties, and the like. For example, the crystal defect density may increase at the interface where the process is stopped and then resumed. For example, the crystal defect density at visible interfaces 82I1 and 82I2 may be greater than that of the first, second, and / or third portions 820A, 820B, and 820C. Defects may include dislocations, stacking faults, point defects, and the like. The dopant concentration may vary across visible interfaces 82I1 and 82I2, resulting in one or more dopant accumulation or depletion regions. For example, the dopant concentration in first portion 820A may differ from the dopant concentration in second portion 820B, or the dopant concentration in second portion 820B may differ from the dopant concentration in third portion 820C. Thermal cycling can induce strain or stress around visible interfaces 82I1 and 82I2, potentially leading to lattice distortions. Changes in dopant distribution and defect density can cause changes in electrical properties, such as carrier mobility, carrier lifetime, and resistivity. Transmission electron microscopy (TEM) or high-resolution X-ray reflectivity (XRR) can visualize interface abrupt changes, which may be less clear due to the process stoppage. During the stoppage, impurities or secondary phases may form at visible interfaces 82I1 and 82I2. Changes in defect density and strain at the interfaces can alter the optical properties of the material. Visible interfaces 82I1 and 82I2 may have different mechanical properties, such as hardness or brittleness, than the first portion 820A, the second portion 820B, and the third portion 820C.

[0104] 14 , an additional SPER may be performed after forming the gate structure 200 and / or the source / drain contacts 120. In many embodiments, the thermal budget after forming the gate structure 200 is more constrained (e.g., lower temperature) to improve Vt control.

[0105] In the foregoing, the recrystallized source / drain 82 of a P-type device and the recrystallized source / drain 82 of an N-type device may differ. For example, differences in dopant types and / or ion implantation processes for implanting different dopant types may result in different concentrations or numbers of stacking faults in the recrystallized source / drain 82. For example, the number of stacking faults in a first recrystallized source / drain 82 associated with a P-type device and including a Group III dopant may be greater than the number of stacking faults in a second recrystallized source / drain 82 associated with an N-type device and including a Group V dopant. In another example, the number of stacking faults in the second recrystallized source / drain 82 may be greater than the number of stacking faults in the first recrystallized source / drain 82. Other such differences may include the concentration and / or distribution of stacking faults or the concentration, number, and / or distribution of dislocations. Thus, the device may include a substrate (e.g., substrate 110 or fin 32), a first stack of semiconductor channels 22 located on the substrate, and a second stack of semiconductor channels 22 located on the substrate. A first recrystallized source / drain 82 of a first type (e.g., p-type) can be adjacent to the first stack of semiconductor channels 22, and a second recrystallized source / drain 82 of a second type (e.g., n-type) can be adjacent to the second stack of semiconductor channels 22, where the first type (e.g., p-type) is different from the second type (e.g., n-type). As previously described, the first number of stacking faults of the first recrystallized source / drain 82 can exceed the second number of stacking faults of the second recrystallized source / drain 82.

[0106] After forming the source / drain contacts 120, gate contacts (or gate vias; not separately shown) can be formed to electrically couple to the gate structure 200. An interconnect structure can then be formed over the source / drain contacts 120 and the gate contacts. The interconnect structure can include a plurality of dielectric layers (including, for example, a second ILD) with metal elements embedded in the dielectric layers, including conductive traces and conductive vias. The metal elements can be positioned between devices on the substrate 110 (e.g., nanostructure devices 20A, 20B, 20C) and can also form electrical connections with IC devices external to the IC device 10.

[0107] Embodiments can provide multiple advantages. Amorphization through ion implantation, followed by one or more SPER steps, can reduce dislocation and / or stacking fault defects and improve dopant activation, thereby reducing source / drain resistance and improving strain in the channel. The SPER step offers flexibility in the choice of ion implant type, number of annealing steps, and sequence, facilitating the integration of the disclosed embodiments into existing manufacturing processes.

[0108] According to at least one embodiment, a method includes: forming a nanostructure stack above a substrate; forming source / drain openings adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain openings; performing ion implantation in the semiconductor layer to form an amorphous semiconductor layer; and annealing the amorphous semiconductor layer to form recrystallized source / drain electrodes.

[0109] According to at least one embodiment, a method includes: forming a nanostructure stack above a substrate; forming source / drain openings adjacent to the nanostructure stack; forming a semiconductor layer in the source / drain openings; forming an amorphous semiconductor layer by amorphizing the semiconductor layer; and solid phase epitaxially regrowing the amorphous semiconductor layer to form source / drain electrodes.

[0110] According to at least one embodiment, a device includes: a substrate; a first semiconductor channel stack located on the substrate; a second semiconductor channel stack located on the substrate; a first recrystallized source / drain of a first type adjacent to the first semiconductor channel stack; and a second recrystallized source / drain of a second type adjacent to the second semiconductor channel stack, wherein the second recrystallized source / drain of the second type is different from the first type, the first recrystallized source / drain having a first number of stacking faults, and the second recrystallized source / drain having a second number of stacking faults, and the first number exceeds the second number.

[0111] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various embodiments of the present disclosure. Those skilled in the art will understand that they can simply use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0112] 10: Installation 110:Substrate 110A: first material layer 118: Silicide layer 120: Source / drain contact 130: Dielectric layer / ILD 131: Etch stop layer / CESL / ESL 20A, 20B, 20C: Nanostructured devices 21A, 21B, 21C: first semiconductor layer 22,22A,22B,22C:Semiconductor channel / channel 23: Second semiconductor layer 22,24:Nanostructure 25: Multi-layer stacking 200: Gate structure 210,240:Interface layer / IL 290:Metal core layer 32: Fins 36: Quarantine 40: Virtual gate structure 41: Gate spacer / spacer layer 41A: First spacer layer 41B: Second spacer layer 41F: Fin spacer 43: Gate dielectric layer 45: Virtual gate layer 47: Mask layer 47A: First mask layer 47B: Second mask layer 400:Process 510:Seam 59: Source / Drain Opening 600: Gate dielectric layer 700: second work function layer 74: Inner spacer 74L: Inner spacer layer 82: Source / Drain 82A, 82L: Source / Drain layer 82,82N,82P: Source / Drain / Source / Drain Region 82N, 82P: Source / Drain components 82_1: Part 1 82_2: Part 2 82F: Stacking fault 82N1, 82P1: First source / drain part 82N2, 82P2: Second source / drain part 800: Dielectric layer / bottom insulator 820A: Part 1 820B: Part 2 820C: Part 3 82I1,82I2: Visible interface 900: Metal core layer / work function metal layer 1000,2000:Method 1100,1200,1300,1400,1500,1600,1700,1800,2100,2200,2300,2400,2500,2600:Steps BB',CC': hatch line BDI: Bottom Dielectric Isolation CD1: Distance X, Y, Z: direction θ: offset angle

[0113] Domestic storage information (please note the order of storage institution, date, and number) none Overseas deposit information (please note the order of deposit country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: A nanostructure stack is formed above a substrate, wherein the nanostructure stack includes a plurality of channels and a plurality of gate structures surrounding the channels; a source / drain opening is formed adjacent to the nanostructure stack; a semiconductor layer is formed in the source / drain opening, wherein the semiconductor layer includes a plurality of first portions grown outwardly from the channels and a second portion grown from each of the first portions, and the second portion includes a plurality of stacking faults; an ion implantation is performed in the semiconductor layer to form an amorphous semiconductor layer; and a recrystallized source / drain is formed by annealing the amorphous semiconductor layer to remove or reduce the stacking faults.

2. The method as described in claim 1, wherein annealing the amorphous semiconductor layer comprises performing an annealing on the exposed upper surface of the amorphous semiconductor layer.

3. The method as described in claim 1, wherein the amorphous semiconductor layer is annealed after at least one of the following steps: forming a contact etch stop layer on the amorphous semiconductor layer; forming an inter-dielectric layer on the contact etch stop layer; or forming an alternative gate for a nanostructure stacked around the nanostructure.

4. A method of forming a semiconductor device, comprising: A nanostructure stack is formed on a substrate, wherein the nanostructure stack includes a plurality of channels and a plurality of gate structures surrounding the channels; a source / drain opening is formed adjacent to the nanostructure stack; a semiconductor layer is formed in the source / drain opening, wherein the semiconductor layer includes a plurality of first portions grown outwardly from the channels and a second portion grown from each of the first portions, and the second portion includes a plurality of stacking faults; an amorphous semiconductor layer is formed by amorphizing the semiconductor layer; and a solid-state epitaxial growth is performed on the amorphous semiconductor layer to remove or reduce the stacking faults to form a source / drain.

5. The method as described in claim 4, wherein amorphizing the semiconductor layer comprises implanting a plurality of ions, wherein the ions are substances belonging to group IV, group III, group V or group VIII.

6. The method as described in claim 5, wherein implanting the ions comprises implanting the ions through an energy between about 1 kiloelectron volt and about 60 kiloelectron volts.

7. A semiconductor device, comprising: One substrate; A first semiconductor channel stack is located on the substrate; A second semiconductor channel stack is located on the substrate; A first recrystallization source / drain of a first type, adjacent to the first semiconductor channel stack, and including a plurality of first portions spaced outward from the first semiconductor channel stack and a second portion grown from each of the first portions; And a second recrystallization source / drain of a second type, adjacent to the second semiconductor channel stack, and the second recrystallization source / drain of the second type is different from the first type, and includes a plurality of third portions grown outwardly from the second semiconductor channel stack and a fourth portion grown from each of the third portions, wherein the first recrystallization source / drain has a first number of stacking faults, the second recrystallization source / drain has a second number of stacking faults, and the first number exceeds the second number.

8. The semiconductor device as described in claim 7, further comprising: A dielectric layer is located between the second recrystallization source / drain and the substrate, wherein the bottom surface of the second recrystallization source / drain is offset from the bottom surface of the first recrystallization source / drain by approximately the thickness of the dielectric layer.

9. The semiconductor device as claimed in claim 7, wherein a visible interface exists between the first portion of the first recrystallization source / drain and the second portion of the first recrystallization source / drain.

10. The semiconductor device as claimed in claim 9, wherein the crystal defect density in the visible interface exceeds the crystal defect density in the first portion and the second portion.

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