Semiconductor structure with gate isolation layer and manufacturing method thereof

Abstract

A method for manufacturing a semiconductor structure includes: forming a lower semiconductor region; forming an upper semiconductor region overlapping the lower semiconductor region; forming a lower gate dielectric layer and an upper gate dielectric layer on the lower semiconductor region and the upper semiconductor region, respectively; forming a lower gate electrode on the lower gate dielectric layer and the upper gate dielectric layer; etching back the lower gate electrode; forming a gate isolation layer on the etched lower gate electrode; and forming an upper gate electrode on the gate isolation layer, wherein the upper gate electrode is on the upper gate dielectric layer.

Description

Semiconductor structure with gate isolation layer and manufacturing method thereof Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers on a semiconductor substrate, and using lithography to pattern the various material layers to form circuit components and devices. The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size. This allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise and need to be solved. The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature over or on a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and does not itself represent a relationship between the various embodiments or configurations discussed. Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. A complementary field-effect transistor (CFET) structure and method for forming the same are provided. Throughout the description, the terms "FET" and "transistor" are used interchangeably. According to some embodiments, the CFET structure includes a lower FET and an upper FET overlapping the lower FET. A gate dielectric isolation layer is formed above the gate electrode of the lower FET and below the gate electrode of the upper FET. Thus, the gate electrode of the lower FET is electrically isolated from the gate electrode of the upper FET. It should be understood that although the discussion is based on a gate-all-around (GAA) transistor (e.g., a nanostructured FET), the concepts disclosed herein can also be applied to the formation of other types of transistors (e.g., planar transistors, fin field-effect transistors (FinFETs), or the like). Figure 1 shows an example of a CFET 10 (including FETs (transistors) 10U and 10L) according to some embodiments. Figure 1 is a three-dimensional view in which some features of the CFET are omitted for ease of illustration. CFET 10 may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type), opposite to the first. The nanostructure FETs (10U and 10L) include a semiconductor nanostructure 26' (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), where the semiconductor nanostructure 26' serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 26'L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26'U is used for the upper nanostructure FET 10U. A gate dielectric layer 78 surrounds the respective semiconductor nanostructures 26 ′. A gate electrode 80 (including a lower gate electrode 80L and an upper gate electrode 80U) is disposed on the gate dielectric layer 78 . Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are disposed on opposite sides of the gate dielectric layer 78 and the respective gate electrodes 80 . Depending on the context, the source / drain regions may be individually or collectively referred to as sources or drains. Isolation features (not shown) may be formed to separate desired portions of the source / drain regions 62 and / or desired portions of the gate electrodes 80 . FIG1 further illustrates reference cross sections used in the following figures. Cross section AA' is a vertical cross section perpendicular to cross section AA' and along the longitudinal axis of the gate electrode 80 of the CFET. Cross section BB' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26' of the CFET and in the direction of current flow, for example, between the source / drain regions 62 of the CFET. For clarity, subsequent figures may refer to these reference cross sections. 2 through 14A, 14B, and 14C illustrate cross-sectional views of intermediate stages in forming a CFET (as schematically shown in FIG. 1 ) according to some embodiments. The corresponding process is also schematically illustrated in process flow 200 , as shown in FIG. 24 . In FIG2 , a wafer 2 including a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate (e.g., a silicon substrate or a glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, a III-V compound semiconductor, or the like, or a combination thereof. A multilayer stack 22 is formed on a substrate 20. Multilayer stack 22 includes alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and dummy semiconductor layers 24B) and semiconductor layers 26 (including lower semiconductor layers 26L and upper semiconductor layers 26U). Lower semiconductor layers 26L and upper semiconductor layers 26U are used to form lower and upper FETs, respectively. Appropriate wells (not separately shown) may be formed in the lower semiconductor layer 26L and the upper semiconductor layer 26U. For example, the semiconductor layers (26L and 26U) may be in-situ doped (during epitaxial growth) and / or implanted to a desired conductivity type. In the example shown, the multilayer stack 22 includes six dummy semiconductor layers 24 and six semiconductor layers 26. It should be understood that the multilayer stack 22 may include any number of dummy semiconductor layers 24 and semiconductor layers 26. Each layer in the multilayer stack 22 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. Dummy semiconductor layer 24A is formed of a first semiconductor material, while dummy semiconductor layer 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of substrate 20. The first and second semiconductor materials have high etching selectivity with respect to each other. Therefore, in subsequent manufacturing processes, dummy semiconductor layer 24B can be removed at a faster rate than dummy semiconductor layer 24A. The semiconductor layer 26 (including the lower semiconductor layer 26L and the upper semiconductor layer 26U) is formed of one or more semiconductor materials. The semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The lower semiconductor layer 26L and the upper semiconductor layer 26U can be formed of the same semiconductor material or different semiconductor materials. In some embodiments, dummy semiconductor layer 24A is formed of or includes silicon germanium, semiconductor layer 26 is formed of silicon, and dummy semiconductor layer 24B may be formed of germanium or silicon germanium having a higher atomic percentage of germanium than dummy semiconductor layer 24A. In FIG3 , multilayer stack 22 and substrate 20 are patterned to form semiconductor strips 28. The corresponding process is shown as process 202 in process flow 200 shown in FIG24 . Each of semiconductor strips 28 includes semiconductor strip 20 ′ (part of the original substrate 20) and multilayer stack 22 ′ (the remaining portion of multilayer stack 22). The remaining portion of multilayer stack 22 ′ is hereinafter referred to as a nanostructure, designated by a symbol followed by a "'" in the corresponding reference numerals. Thus, multilayer stack 22 ′ includes dummy nanostructure 24 ′A, dummy nanostructure 24 ′B, lower semiconductor nanostructure 26 ′L, middle semiconductor nanostructure 26 ′M, and upper semiconductor nanostructure 26 ′U. Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching process can be anisotropic. The dummy nanostructure 24 ′A and the dummy nanostructure 24 ′B may be collectively referred to as dummy nanostructures 24 ′. The lower semiconductor nanostructure 26 ′L and the upper semiconductor nanostructure 26 ′U may be collectively referred to as semiconductor nanostructures 26 ′. Lower semiconductor nanostructure 26'L will serve as the channel region of the lower nanostructure FET of the CFET. Upper semiconductor nanostructure 26'U will serve as the channel region of the upper nanostructure FET of the CFET. Intermediate semiconductor nanostructure 26'M is a semiconductor nanostructure 26' located immediately above or below (e.g., in contact with) dummy nanostructure 24'B. Intermediate semiconductor nanostructure 26'M can be used for isolation and may or may not serve as the channel region of the CFET. Dummy nanostructure 24'B will subsequently be replaced by an isolation structure. The isolation structure and intermediate semiconductor nanostructure 26'M can define the boundary between the lower nanostructure FET and the upper nanostructure FET. 4, isolation regions 32 are formed over substrate 20 and between adjacent semiconductor strips 28. Isolation regions 32 may include a dielectric liner and a dielectric material over the dielectric liner. Isolation regions 32 are then recessed. Some upper portions of semiconductor strips 28 (including multilayer stack 22 ′) protrude above the remaining isolation regions 32 to form protruding fins 34 . A dummy dielectric layer 36 is then formed on the protruding fin 34. The dummy dielectric layer 36 may be formed of or may include, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed on the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a chemical mechanical polishing (CMP) process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), or the like. The mask layer 40 is formed on the planarized dummy gate layer 38 and may include, for example, silicon nitride, silicon oxynitride, or the like. Next, mask layer 40 can be patterned by photolithography and etching processes to form a mask, which is then used to etch and pattern dummy gate layer 38 (and possibly dummy dielectric layer 36). The resulting structure is shown in FIG5 . The remaining portion of mask layer 40 , dummy gate layer 38 , and dummy dielectric layer 36 form dummy gate stack 42 . In FIG5 , a gate spacer 44 is formed above the multilayer stack 22 ′ and on the exposed sidewalls of the dummy gate stack 42 . The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by deposition processes such as CVD, ALD, or the like. Fin spacers 45 are also formed. Source / drain recesses 46 are then formed in semiconductor strips 28. Source / drain recesses 46 are formed by etching and can extend through multilayer stack 22' and into semiconductor strips 20'. The bottom surface of source / drain recesses 46 can be above, below, or flush with the top surface of isolation region 32. During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strips 28. The etching process can include a single etching process or multiple etching processes. A timed etching process can be used to stop etching source / drain recesses 46 when they reach a desired depth. In subsequent manufacturing processes, dummy nanostructure 24'A is laterally recessed, and a dielectric material is filled into the corresponding recess to form inner spacers 54, which are dielectric spacers. The resulting structure is shown in FIG6 . Additionally, dummy nanostructure 24'B is removed and filled with a dielectric material to form dielectric isolation layer 56. Next, a lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46 ( FIG. 5 ). The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26 ′L and does not contact the upper semiconductor nanostructure 26 ′U. Inner spacers 54 electrically insulate the lower epitaxial source / drain region 62L from the dummy nanostructure 24 ′A, which will be replaced with a gate in subsequent fabrication processes. The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type appropriate for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with an n-type dopant, such as phosphorus, arsenic, or the like. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon germanium doped with a p-type dopant, such as boron, indium, or the like. The lower epitaxial source / drain region 62L may be doped in situ and may or may not be implanted with the corresponding p-type or n-type dopant. A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed. The first CESL 66 may be formed of a dielectric material having a high etch selectivity relative to the first ILD 68 (e.g., silicon nitride, silicon oxide, silicon oxynitride, or the like) and may be formed by any suitable deposition process (e.g., CVD, ALD, or the like). The first ILD 68 may be formed of a dielectric material and may be deposited by any suitable method (e.g., CVD, plasma-enhanced CVD (PECVD), or FCVD). Suitable dielectric materials for the first ILD 68 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like. The formation process may include depositing a conformal CESL layer, depositing the material for the first ILD 68, followed by a planarization process, and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etch process is then performed to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After the recess is formed, the sidewalls of the upper semiconductor nanostructure 26'U are exposed. Next, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. Depending on the desired conductivity type of the upper epitaxial source / drain region 62U, the material of the upper epitaxial source / drain region 62U can be selected from the same candidate group of materials used to form the lower epitaxial source / drain region 62L. The conductivity type of the upper epitaxial source / drain region 62U can be opposite to the conductivity type of the lower epitaxial source / drain region 62L. In other words, the upper epitaxial source / drain region 62U can be doped opposite to the lower epitaxial source / drain region 62L. The upper epitaxial source / drain region 62U can be in-situ doped and / or implanted with n-type or p-type dopants. Next, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods may be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail here. The formation process may include depositing layers for the second CESL 70 and the second ILD 72 and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surface of the second ILD 72, the top surface of the gate spacer 44, and the top surface of the dummy gate stack 42 are coplanar within process variation. The planarization process may remove the mask layer 40 or leave the hard mask layer 40 intact. The dummy gate stack 42 is then removed in one or more etching processes, thereby forming recesses 74, as shown in Figures 7A and 7B. A corresponding process is shown as process 204 in the process flow 200 shown in Figure 24. Each of the recesses 74 exposes and / or overlies a portion of the multilayer stack 22'. The cross section shown in FIG7B may be the vertical cross section AA' shown in FIG1. ​​FIG7B shows three device regions 400, 500, and 600. Each of the device regions 400, 500, and 600 is used to form a CFET including an upper FET and a lower FET. Each of the device regions 400, 500, and 600 may also be obtained from the vertical cross section 14A-14A shown in FIG23, where the cross section 14A-14A passes through the metal gate to be formed. The remaining portion of the dummy nanostructure 24'A is then removed by etching (FIG. 6), such that the recess 74 extends between the semiconductor nanostructures 26'. During the etching process, the dummy nanostructure 24'A is etched at a faster rate than the semiconductor nanostructure 26', the dielectric isolation layer 56, and the inner spacer 54. The etching may be isotropic. For example, when the dummy nanostructure 24'A is formed of silicon germanium and the semiconductor nanostructure 26' is formed of silicon, the etching process may include using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4OH) or similar wet etching process. Figures 8A, 8B, 9 through 13, 14A, 14B, and 14C illustrate details of forming a gate dielectric layer 78 and gate electrode 80 (including 80U and 80L) according to some embodiments. In Figures 8A and 8B, gate dielectric layer 78 is formed within recess 74 and over the exposed semiconductor nanostructure 26'. The corresponding process is shown as process 206 in process flow 200 shown in Figure 24. Gate dielectric layer 78 is formed over the exposed surface of semiconductor nanostructure 26', including the exposed features of gate spacers 44. Gate dielectric layer 78 surrounds all (e.g., four) sides of semiconductor nanostructure 26'. Each gate dielectric layer 78 may include an interfacial layer 78IL, which is shown but not separately labeled. Interfacial layer 78IL may include an oxide (e.g., silicon oxide or a metal oxide), a silicate (e.g., a metal silicate), combinations thereof, multiple layers thereof, or the like. Interfacial layer 78IL may be formed by a thermal oxidation process and / or a deposition process. Each gate dielectric layer 78 may also include a high-k dielectric layer 78HK overlying the interfacial layer, having a high-k value greater than, for example, about 7.0, about 21, or higher. High-k dielectric layer 78HK may be formed from or include a metal oxide or silicate of a metal selected from hafnium, zirconium, barium, titanium, lead, and combinations thereof. High-k dielectric layer 78HK may be formed by molecular beam deposition (MBD), ALD, PECVD, or the like. High-k dielectric layer 78HK may have a thickness ranging from about 1 nm to about 5 nm. Gate dielectric layers 78 in device regions 400, 500, and 600 may be formed in a common process. Referring to FIG. 9 , a lower gate electrode 80L is formed. The corresponding process is shown as process 208 in the process flow 200 shown in FIG. 24 . According to some embodiments, the lower gate electrode 80L includes a work function layer and may also include other layers, such as a cap layer below the work function layer, a barrier layer above the work function layer, and may or may not include a metal fill layer above the barrier layer. The formation of the lower gate electrode 80L may include a deposition process such as ALD, metal-organic chemical vapor deposition (MOCVD), PECVD, or the like. After depositing the layers of the lower gate electrode 80L, a planarization process is performed to level the top surface of the lower gate electrode 80L. According to some embodiments, the cap layer and the barrier layer may include TiN or TiSiN, and the material of the work function layer depends on whether the lower FET is an NFET or a PFET. For example, when the lower FET is an NFET, the work function layer may include TiAlN, TiAl, TiN, tungsten, or the like. When the lower FET is a PFET, the work function layer may include TiN, TaN, tungsten, or the like. According to some embodiments, the lower gate electrode 80L may (or may not) include a seam 81. The bottom of the seam 81 is close to the bottom of the lower gate electrode 80L. According to some embodiments, the width W1 of the seam 81 may be in a range from about 1 nm to about 5 nm. 10 , an etch-back process is performed to recess the lower gate electrode 80L. The corresponding process is shown as process 210 in the process flow 200 shown in FIG24 . The top surface of the remaining lower gate electrode 80L is lower than the top surface of the upper one of the intermediate semiconductor nanostructures 26 ′M and higher than the bottom surface of the lower one of the intermediate semiconductor nanostructures 26 ′M. The etch-back process can be performed using a dry etching process or a wet etching process. For example, when dry etching is used, chlorine (Cl 2) As etching gas, Ar and N can be used at the same time 2 or similar carrier gas. The seam 81 may be exposed as a result of the etching process. According to some embodiments, the seam 81 may be exposed by adding some by-product generating gases (such as SiCl 4. O 2. CH 4. N 2. BCl 3 and / or the like) to perform an etch-back process. Consequently, byproducts 84 are generated and fill seams 81 during the etch-back process. Depending on the added gas, byproducts 84 may include inorganic materials (e.g., SiCO, SiCN, BN, or the like), polymeric materials (e.g., polymeric carbon nitride (CN)), or a combination thereof. Byproducts 84 may also be dielectric materials. The byproducts generated to fill seams 81 are also referred to as byproduct regions 84. According to some embodiments, byproduct region 84 completely occupies seam 81. According to alternative embodiments, byproduct region 84 partially occupies seam 81. For example, byproduct region 84 may occupy the lower portion of seam 81, leaving the upper portion unfilled. Byproduct region 84 may also conformally line the sidewalls of seam 81, while leaving the central portion of seam 81 unfilled. Throughout this description, seam 81 and byproduct region 84 are referred to as regions (81 / 84), meaning that the corresponding regions are seam 81 and / or byproduct region 84 in the form of air gaps. FIG11 illustrates the formation of a gate isolation layer 86. The corresponding process is shown as process 212 in the process flow 200 shown in FIG24. According to some embodiments, the gate isolation layer 86 comprises a dielectric material, such as SiO, SiN, SiCN, SiOC, SiOCN, SiON, or the like. The formation process may include depositing the gate isolation layer 86 by a deposition process (e.g., an ALD process, a CVD process, a PVD process, or the like), planarizing the top surface of the gate isolation layer 86 (e.g., by CMP or mechanical polishing), and etching back the dielectric layer. The resulting gate isolation layer 86 has a top surface that is lower than the top surface of the uppermost one of the intermediate semiconductor nanostructures 26'M. FIG12 illustrates the selective patterning of the gate isolation layer 86, which can be performed by forming an etching mask (e.g., a patterned photoresist, not shown) and etching the gate isolation layer 86. The corresponding process is shown as process 214 in the process flow 200 shown in FIG24. After the patterning of the gate isolation layer 86, the region (81 / 84) can be exposed, covered by the gate isolation layer 86, or some portions of the gate isolation layer 86 can be exposed while other portions of the gate isolation layer 86 are covered by the gate isolation layer 86. FIG13 illustrates the formation of an upper gate electrode 80U according to some embodiments. The corresponding process is shown as process 216 in the process flow 200 shown in FIG24 . The formation of the upper gate electrode 80U may include depositing multiple conductive layers and performing a planarization process. The structure and materials of the upper gate electrode 80U may be as described in the discussion of the lower gate electrode 80L, except that the corresponding upper FET may have a conductivity type opposite to that of the lower FET and the material of the work function layer in the upper gate electrode 80U may be selected to suit the conductivity type of the upper FET. According to some embodiments, a seam 81 ′ is formed in the upper gate electrode 80U. The seam 81 ′ may have a width W2 that is smaller than the width W1 ( FIG. 9 ). According to alternative embodiments, the seam 81 ′ is not formed. FIG14A illustrates the formation of isolation regions 88, which electrically and physically isolate the gate electrodes (80L and 80U) in device regions 400, 500, and 600 from each other. The corresponding process is shown as process 218 in the process flow 200 shown in FIG24. The formation process may include etching the upper gate electrode 80U and the lower gate electrode 80L to form openings until the underlying gate dielectric layer 78 is exposed. The gate dielectric layer 78 may be etched to expose the underlying STI region 32, or it may not be etched. In subsequent processes, dielectric material is filled into the openings to form gate isolation regions 88. According to some embodiments, the corresponding region (81 / 84) is completely removed after the formation of gate isolation region 88. According to alternative embodiments, the corresponding region (81 / 84) is partially removed and partially retained after the formation of gate isolation region 88, as shown in FIG14A. According to another alternative embodiment, the entire region (81 / 84) is retained because the corresponding gate isolation region 88 is not formed (while other gate isolation regions 88 may still be formed). According to some embodiments, isolation region 88 may be formed simultaneously with contact etch stop layer (CESL 90) and interlayer dielectric (ILD) 92, with the materials of CESL 90 and ILD 92 filling the openings forming the isolation region. In other embodiments, isolation region 88 is formed by a separate process from the formation of CESL 90 and ILD 92. According to some embodiments, CESL 90 may be formed of a nitride such as SiN, SiC, SiOCN, or the like, while ILD 92 may be formed of an oxide such as SiO, SiOC, SiOCN, or the like. Gate contact plug 94 is formed to extend into ILD 92 to electrically connect to upper gate electrode 80U. Electrical connection to lower gate electrode 80L is also formed, but not shown. Throughout the description, the gate electrode 80L and the underlying gate dielectric layer 78 are collectively referred to as the gate stack 94L, and the gate electrode 80U and the underlying gate dielectric layer 78 are collectively referred to as the gate stack 94U. This forms a CFET 10 that includes a lower FET 10L (including the gate stack 94L and the source / drain regions 62L ( FIG. 14B )) and an upper FET 10U (including the gate stack 94U and the source / drain regions 62U ( FIG. 14B )). The gate isolation layer 86 may be at the same level as the dielectric isolation layer 56. According to an alternative embodiment, as shown in FIG14A , the gate isolation layer 86 may have a top surface that is flush with the top surface of the upper one of the intermediate semiconductor nanostructures 26 'M, and the corresponding gate isolation layer 86 is marked with a dotted line 86 '. According to an alternative embodiment, the bottom surface of the gate isolation layer 86 may be flush with the bottom surface of the lower one of the intermediate semiconductor nanostructures 26 'M, and the corresponding gate isolation layer 86 is marked with a dotted line 86 ''. The gate isolation layer 86 may also be located at any position between the positions marked by the dotted lines 86 ' and 86 ''. 23 shows a perspective view of CFET 10 according to some embodiments, with source / drain regions ( 62L and 62U), gate electrodes ( 80L and 80U), gate isolation layer 86 , STI region 32 , etc. labeled. The cross-sectional view shown in FIG14A is obtained from vertical cross-section 14A-14A shown in FIG23 (and vertical cross-section AA' shown in FIG1), wherein the cross-section passes through the metal gate electrode. FIG14B shows vertical cross-section 14B-14B shown in FIG23 (and vertical cross-section BB' shown in FIG1), wherein the cross-section passes through the nanostructure (26U and 26L) (channel region) and the source / drain regions (62U and 62L). FIG14C shows vertical cross-section 14C-14C shown in FIG23, wherein the cross-section passes through the STI region 32 and the gate isolation region 88 used to separate the adjacent gate electrodes (80U and 80L) from each other. As shown in FIG14A , in some embodiments, regions (81 / 84) may be completely removed during the formation of gate isolation regions 88. Also as shown in FIG14A , depending on the width of regions (81 / 84) and the width of gate isolation regions 88, some or all of regions (81 / 84) may have portions remaining. According to some embodiments, some gate isolation regions 88 are not formed, so regions (81 / 84) as shown in FIG13 will remain in the final structure. Figures 15 to 22 illustrate structures formed according to alternative embodiments. It should be understood that the structures formed according to these embodiments and the structures shown in Figures 14A, 14B, and 14C can coexist in the same device die and the same device wafer and be formed using the same formation process. 15 and 16 illustrate the formation of a lower gate electrode 80L, a gate isolation layer 86, and an upper gate electrode 80U according to some embodiments. A byproduct region 84 is shown. By forming the byproduct region 84, the gate isolation layer 86 can more easily seal the underlying seam 81. Figures 17 and 18 illustrate the formation of a lower gate electrode 80L, a gate isolation layer 86, and an upper gate electrode 80U according to alternative embodiments. The illustrated seam 81 is not filled with the byproduct region 84, or may be partially filled with the byproduct region 84 (e.g., filling the lower portion). Alternatively, the byproduct region 84 may be formed as a conformal liner. This structure can be achieved when no byproduct-generating gas is added during the etch-back process of the lower gate electrode 80L. Alternatively, this structure can result when byproducts are generated but do not fill the illustrated seam 81 or fill it in an insufficient amount. Consequently, the gate isolation layer 86 will have portions that extend to and fill the upper portion of the underlying seam 81. Figures 19 and 20 illustrate the formation of a lower gate electrode 80L, a gate isolation layer 86, and an upper gate electrode 80U according to another alternative embodiment. The illustrated seam 81 is not filled with byproduct region 84, or may be partially filled (e.g., filling a lower portion). According to some embodiments, the gate isolation layer 86 is deposited using a bottom-up deposition process. Therefore, the gate isolation layer 86 will fill the remaining underlying seam 81. The seam 81 may or may not contain byproducts, and if byproducts are generated, the remaining seam 81 not filled with byproducts will be completely filled with the gate isolation layer 86. FIG21 illustrates the formation of a lower gate electrode 80L, a gate isolation layer 86, and an upper gate electrode 80U according to some embodiments. The gate isolation layer 86 is patterned, and the underlying seam 81 may be exposed again. Thus, the upper gate electrode 80U seals the underlying seam 81. Furthermore, the upper gate electrode 80U may extend into the underlying seam 81. According to some embodiments, the structure shown in Figure 22 exists in the final structure shown in Figure 23. According to an alternative embodiment, after forming the structure shown in Figure 22, the process shown in Figure 14A is performed and gate isolation regions 88 are formed, which are shown by dashed lines. The disclosed embodiments have several advantageous features. By forming a horizontal gate isolation layer between the upper and lower gate electrodes in a CFET structure, the upper and lower gate electrodes are electrically isolated from each other. The process can also be adjusted to fill any seams that may form in the lower gate electrode. According to some embodiments of the present disclosure, a method includes: forming a lower semiconductor region; forming an upper semiconductor region overlapping the lower semiconductor region; forming a lower gate dielectric layer and an upper gate dielectric layer on the lower semiconductor region and the upper semiconductor region, respectively; forming a lower gate electrode on the lower gate dielectric layer and the upper gate dielectric layer; etching back the lower gate electrode; forming a gate isolation layer on the etched-back lower gate electrode; and forming an upper gate electrode on the gate isolation layer, wherein the upper gate electrode is on the upper gate dielectric layer. In one embodiment, the method further includes patterning the gate isolation layer. In one embodiment, forming the gate isolation layer includes: depositing a dielectric layer; planarizing the dielectric layer; and etching back the dielectric layer, wherein the remaining portion of the dielectric layer forms the gate isolation layer. In one embodiment, a seam is formed in the lower gate electrode, wherein the seam is exposed after the lower gate electrode is etched back. In one embodiment, during the etching back of the lower gate electrode, byproducts are generated to at least partially fill the seam. In one embodiment, a silicon-containing process gas is added during the etching back of the lower gate electrode, and the byproducts include a silicon-containing dielectric. In one embodiment, the byproducts completely fill the seam. In one embodiment, the method further includes: etching the lower gate electrode and the upper gate electrode; and filling the dielectric region in the space left by the etched lower gate electrode and the etched upper gate electrode. In one embodiment, a seam is formed in the lower gate electrode, wherein the gate isolation layer at least partially fills the seam. In one embodiment, the gate isolation layer completely fills the seam. In one embodiment, the lower semiconductor region includes a first semiconductor nanostructure, and the upper semiconductor region includes a second semiconductor nanostructure. The method further includes: forming a first source / drain region connected to the first semiconductor nanostructure; and forming a second source / drain region connected to the second semiconductor nanostructure. According to some embodiments of the present disclosure, a structure includes: a lower transistor including a first semiconductor region; a first gate dielectric layer on the first semiconductor region; and a lower gate electrode on the first gate dielectric layer; and an upper transistor including a second semiconductor region overlapping the first semiconductor region; a second gate dielectric layer on the second semiconductor region; and an upper gate electrode on the second gate dielectric layer; and a gate isolation layer overlying and contacting the lower gate electrode, wherein the gate isolation layer further underlies and contacts the upper gate electrode. In one embodiment, the lower transistor and the upper transistor have opposite conductivity types. In one embodiment, the structure further includes an isolation region, wherein the isolation region includes sidewalls contacting an edge of the lower gate electrode, an edge of the gate isolation layer, and an edge of the upper gate electrode. In one embodiment, the lower gate electrode further includes a silicon-containing dielectric region therein. In one embodiment, the lower gate electrode further includes a seam filled with the same material as the gate isolation layer. In one embodiment, the lower gate electrode further includes a seam serving as an air gap. According to some embodiments of the present disclosure, a structure includes: a first CFET including a first lower FET, the first lower FET including a first lower gate electrode; a first upper FET including a first upper gate electrode overlapping the first lower gate electrode; and a first gate isolation layer between the first lower gate electrode and the first upper gate electrode and connecting the first lower gate electrode and the first upper gate electrode; a second CFET structure including a second lower FET, the second lower FET including a second lower gate electrode; and a second upper transistor including a second upper gate electrode overlapping the second lower gate electrode; and an isolation region including a first sidewall and a second sidewall, the first sidewall contacting a first edge of the first lower gate electrode and the first upper gate electrode, and the second sidewall contacting a second edge of the second lower gate electrode and the second upper gate electrode. In one embodiment, the structure further includes a second gate isolation layer between the second lower gate electrode and the second upper gate electrode and connecting the second lower gate electrode and the second upper gate electrode. In one embodiment, the second lower gate electrode physically contacts the second upper gate electrode. The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. 2: Wafer 10: Complementary Field Effect Transistor (CFET) 10L, 10U: FET 20: Substrate 20', 28: Semiconductor strips 22, 22': Multilayer stack 24, 24A, 24B: Dummy semiconductor layer 24', 24'A, 24'B: Dummy nanostructure 26: Semiconductor layer 26L: Lower semiconductor layer 26U: Upper semiconductor layer 26': Semiconductor nanostructure 26'L: Lower semiconductor nanostructure 26'M: Middle semiconductor nanostructure 26'U: Upper semiconductor nanostructure 32: Isolation region / STI region 34: Protruding fin 36: Dummy dielectric layer 38: Dummy gate layer 40: Mask layer 42: Dummy gate stack 44: Gate spacer 45: Fin spacer 46: Source / drain recess 54: Inner spacer 56: Dielectric isolation layer 62: Source / drain region 62L: Lower epitaxial source / drain region / Source / drain region 62U: Upper epitaxial source / drain region / Source / drain region 66: First contact etch stop layer (CESL) 68: First interlayer dielectric (ILD) 70: Second CESL 72: Second ILD 74: Recess 78: Gate dielectric layer 78HK: High-k dielectric layer 78IL: Interface layer 80: Gate electrode 80L: Lower gate electrode / gate electrode 80U: Upper gate electrode / gate electrode 81, 81': Seam 84: Byproduct / byproduct region 86: Gate isolation layer 86', 86": Dashed line 88: Isolation region / gate isolation region 90: Contact etch stop layer (CESL) 92: Interlayer dielectric (ILD) 94: Gate contact plug 94L, 94U: Gate stack 200: Process flow 202, 204, 206, 208, 210, 212, 214, 216, 218: Processes 400, 500, 600: Device areas AA', BB', 14A-14A, 14B-14B, 14C-14C: Cross sections W1, W2: Width The aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 shows a perspective view of an exemplary complementary field-effect transistor (CFET) according to some embodiments. Figures 2 to 7A, 7B, 8A, 8B, 9 to 13, 14A, 14B, and 14C are views of intermediate stages of CFET fabrication according to some embodiments. Figures 15 to 22 are views of intermediate stages of CFET fabrication according to some embodiments. Figure 23 shows a perspective view of a CFET structure according to some embodiments. Figure 24 shows a flow chart for forming a CFET according to some embodiments. 200:Process flow 202, 204, 206, 208, 210, 212, 214, 216, 218: Process

Claims

1. A method for manufacturing a semiconductor structure, comprising: A lower semiconductor region is formed; an upper semiconductor region is formed that overlaps with the lower semiconductor region; A lower gate dielectric layer and an upper gate dielectric layer are formed on the lower semiconductor region and the upper semiconductor region, respectively; a lower gate electrode is formed on the lower gate dielectric layer and the upper gate dielectric layer; the lower gate electrode is etched back; a gate isolation layer is formed on the etched lower gate electrode; and an upper gate electrode is formed on the gate isolation layer, wherein the upper gate electrode is on the upper gate dielectric layer.

2. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein a seam is formed in the lower gate electrode, and wherein the seam is exposed after the lower gate electrode is etched back.

3. A semiconductor structure, comprising: The lower transistor includes: a first semiconductor region; a first gate dielectric layer on the first semiconductor region; and a lower gate electrode on the first gate dielectric layer; and the upper transistor includes: a second semiconductor region overlapping the first semiconductor region; a second gate dielectric layer on the second semiconductor region; and an upper gate electrode on the second gate dielectric layer; and a gate isolation layer covering the lower gate electrode and contacting the lower gate electrode, wherein the gate isolation layer is further below the upper gate electrode and contacts the upper gate electrode.

4. The semiconductor structure as described in claim 3, further comprising: The isolation zone includes a sidewall that contacts the edge of the lower gate electrode, the edge of the gate isolation layer, and the edge of the upper gate electrode.

5. The semiconductor structure as claimed in claim 3, wherein the lower gate electrode further includes a silicon-containing dielectric region therein.

6. The semiconductor structure of claim 3, wherein the lower gate electrode further includes a seam filled with the same material as the gate isolation layer.

7. The semiconductor structure as claimed in claim 3, wherein the lower gate electrode further includes a seam as an air gap.

8. A semiconductor structure, comprising: A first complementary field-effect transistor (CFPT) structure includes: a first lower CFPT, including a first lower gate electrode; a first upper CFPT, including a first upper gate electrode adjacent to the first lower gate electrode; and a first gate isolation layer between and connecting the first lower gate electrode and the first upper gate electrode; a second complementary field-effect transistor (CFPT) structure includes: a second lower CFPT, including a second lower gate electrode; and a second upper CFPT, including a second upper gate electrode overlapping the second lower gate electrode; and an isolation region including: a first sidewall contacting a first edge of the first lower gate electrode and the first upper gate electrode; and a second sidewall contacting a second edge of the second lower gate electrode and the second upper gate electrode.

9. The semiconductor structure of claim 8 further includes a second gate isolation layer between the second lower gate electrode and the second upper gate electrode and connected to the second lower gate electrode and the second upper gate electrode.

10. The semiconductor structure of claim 8, wherein the second lower gate electrode is in physical contact with the second upper gate electrode.

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