Manufacturing method of semiconductor device and semiconductor device

Abstract

The object of this invention is to provide a method for manufacturing a semiconductor device that can reduce the width of the terminal region and mitigate the electric field in the terminal region. This invention is a method for manufacturing a semiconductor device having a terminal region around an effective region. On the front side of a first semiconductor region having a first conductivity type, a plurality of second semiconductor regions having a second conductivity type are formed. These second semiconductor regions function as RESURF regions. The method, as a mask for forming the second semiconductor regions, uses a mask where, when the distance from the outermost reference window is set to x, the distance between the injection window at position x and the injection window on the effective region side is approximately equal to a value defined by the following formula. Impurities of the second conductivity type are injected to form the second semiconductor regions.

Description

Method for manufacturing semiconductor device and semiconductor device The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. In recent years, price competition in the field of power semiconductor devices has been relatively intense, and cost reduction is sought. To reduce costs, it is necessary to increase the wafer diameter, lower the process temperature, and miniaturize the chip. Therefore, it is necessary to achieve shallow junction formation in the terminal region, reduce the width of the terminal region, and relax the electric field in the terminal region. As prior art related to the structure of the terminal region, for example, there are Patent Document 1 and Patent Document 2. In Patent Document 1, it is described that the terminal structure (32) provided on the outer peripheral portion of the semiconductor element includes an N-type drift region (1) formed in the semiconductor substrate (30) and a P-type impurity region (2) formed on the upper surface portion in the N-type drift region (1); when the P-type impurity region (2) is observed macroscopically, the P-type impurity concentration decreases from the inner peripheral portion to the outer peripheral portion of the terminal structure (32); when the P-type impurity region (2) is observed microscopically, it is composed of a plurality of P-type high-concentration regions (2b) and low-concentration regions (2a) surrounding them; there are separated portions between the low-concentration regions (2a) (Abstract, FIG. 2). Here, in Patent Document 1, it is described that the impurity concentration of the low-concentration region (2a) is set to a value that satisfies the condition (RESURF condition) for completely depleting the low-concentration region (2a), and the impurity concentration of the high-concentration region (2b) is set to a value that determines whether the high-concentration region (2b) is depleted according to the deviation of the wafer process (paragraph 0020). Also, in Patent Document 1, it is described that the aperture ratio of the implantation mask (20) used in the ion implantation for forming such a P-type impurity region (2) is reduced toward the outside of the terminal structure (32) (paragraph 0042). The function for reducing the aperture ratio is listed as a linear function or the like, but an exponential function or the like with a higher reduction rate is desired. For example, it is described that macroscopically observed, if a convex-down exponential function or a function that decreases with a polynomial is used, local concentration of the electric field can be relaxed (paragraph 0043). In Patent Document 2, it is described that a P RESURF layer (3) (electric field relaxation layer) having a lower concentration than the P base layer (2) is formed so as to surround the P base layer (2). The P RESURF layer (3) is composed of high-concentration P RESURF layers (7a, 8a, 9a, 10a) and low-concentration P RESURF layers (8b, 9b, 10b, 11b) arranged alternately. While maintaining the sum of the widths of each group of the high-concentration P RESURF layer and the low-concentration P RESURF layer to be equal, i.e., w(7a) = w(8b) + w(8a) = w(9b) + w(9a) = w(10b) + w(10a) = w(11b), the width of the high-concentration P RESURF layer (7a, 8a, 9a, 10a) is gradually narrowed toward the outside, and the width of the low-concentration P RESURF layer (8b, 9b, 10b, 11b) is gradually widened toward the outside (paragraphs 0027 to 0039, FIGS. 3 to 4). [Prior Art Documents] [Patent Documents] [Patent Document 1] International Publication No. 2014 / 054319 [Patent Document 2] International Publication No. 2013 / 136550 [Problems to be Solved by the Invention] In Patent Document 1, as a function for reducing the aperture ratio of the injection mask (20), a linear function, a convex-down exponential function (a x ) and a function that decreases with a polynomial are described. In Patent Document 2, it is described that while maintaining the sum of the widths of each group of the high-concentration P RESURF layer and the low-concentration P RESURF layer to be equal, the width of the high-concentration P RESURF layer is gradually narrowed toward the outside, and the width of the low-concentration P RESURF layer is gradually widened toward the outside, that is, the concentration decreases quasi-linearly. However, through simulation by the inventors of the present application, it was found that the shape of the mask expected to achieve the reduction of the width of the terminal region and the relaxation of the electric field in the terminal region is a different shape. The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device that can achieve the reduction of the width of the terminal region and the relaxation of the electric field in the terminal region. [Technical Means for Solving the Problem] In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention is characterized in that it is a method for manufacturing a semiconductor device. The semiconductor device has, for example, a terminal region around an active region. On the front surface of a first semiconductor region having a first conductivity type in the terminal region, a plurality of second semiconductor regions having a second conductivity type and a depletion layer that extends to the first semiconductor region when a voltage is applied and is continuous with the active region are formed. When a voltage is applied, at least one second semiconductor region among the plurality of second semiconductor regions, which includes the second semiconductor region formed at the position farthest from the active region, is completely depleted and functions as a RESURF region; and in the method for manufacturing the semiconductor device, a mask is used to implant impurities of the second conductivity type to form the second semiconductor regions. The mask is used to form the second semiconductor regions, and with the injection window corresponding to the second semiconductor region formed at the position farthest from the active region among the second semiconductor regions that are continuous with the active region and extend to the first semiconductor region in a thermally balanced state as a reference window, the position on the active region side of the reference window is set as X0, the distance between the position on the active region side of the injection window adjacent to the active region and X0 is set as XN, the interval between the reference window and the injection window on the active region side is set as Smax, the interval between the end of the active region and the injection window adjacent to the active region is set as Smin, the distance from X0 is set as x, and when the power coefficient is set as β, the interval S(x) between the injection window at the position of the distance x and the injection window on the active region side is approximately equal to the value defined by the following formula, Furthermore, a semiconductor device according to the present invention is characterized in that it has, for example, an active region and a terminal region formed around the active region; and the terminal region has: a first semiconductor region having a first conductivity type; and a plurality of second semiconductor regions formed on the surface of the first semiconductor region having a second conductivity type and having a depletion layer that extends to the first semiconductor region when a voltage is applied and is continuous with the active region. When a voltage is applied, at least one second semiconductor region among the plurality of second semiconductor regions, which includes the second semiconductor region formed at the position farthest from the active region, is completely depleted and functions as a RESURF region; and the second semiconductor regions formed by using the method for manufacturing the semiconductor device are provided in the terminal region. [Effects of the Invention] According to the present invention, a method for manufacturing a semiconductor device and a semiconductor device that can reduce the width of the terminal region and mitigate the electric field in the terminal region can be realized. Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and repeated descriptions are omitted. [Embodiment 1] FIG. 1 is a cross-sectional view of the semiconductor device of Example 1. The semiconductor device 10 of Example 1 has a terminal region 12 around the active region 11. In the front surface of the first semiconductor region 1 having a first conductivity type (e.g., n-type), a plurality of second semiconductor regions 2 having a second conductivity type (e.g., p-type) are formed in the terminal region 12. Here, the first conductivity type is set to n-type and the second conductivity type is set to p-type for explanation, but the first conductivity type may be set to p-type and the second conductivity type may be set to n-type. In the active region 11, for example, semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor), or MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or diodes are formed, but the illustration is omitted. As the semiconductor substrate for forming the semiconductor device 10, Si or SiC etc. can be used, but it is not limited thereto. In the active region 11, the first semiconductor region 1 and the second semiconductor region 2 are also formed. Here, the second semiconductor region 2 in the active region 11 is referred to as the second semiconductor region 2a. Furthermore, the semiconductor device 10 has: a channel stopper 6, which is formed in the terminal region 12 and has a first conductivity type with a higher concentration than the first semiconductor region 1; an oxide film 4, which is formed to cover the first semiconductor region 1, the second semiconductor region 2, and the channel stopper 6; and an electrode 5, which is formed in the active region 11. The electrode 5 is, for example, a gate electrode or an emitter electrode in the case of an IGBT, a gate electrode or a source electrode in the case of a MOSFET, and an anode electrode in the case of a diode. In addition, only the front side of the semiconductor device 10 is illustrated in FIG. 1, and the illustration of the back side is omitted. An electrode (not shown) is provided on the back side of the semiconductor device 10. For example, a collector electrode is provided in the case of an IGBT, a drain electrode is provided in the case of a MOSFET, and a cathode electrode is provided in the case of a diode. In the semiconductor device 10 of Example 1, in the thermal equilibrium state, the depletion layer 3 extending to the first semiconductor region 1 is continuous from the active region 11 to each second semiconductor region 2, and each second semiconductor region 2 almost becomes an intrinsic region 7. And, one of the features is that the depletion of each second semiconductor region 2 (the shrinkage of the intrinsic region 7) caused by the applied voltage starts from the second semiconductor region 2 on the outer peripheral side (the side away from the active region 11) of the terminal region 12. Furthermore, when a voltage is applied to the semiconductor device 10 of Example 1, the depletion layer 3 extending to the first semiconductor region 1 is continuous with the active region 11 up to a plurality of second semiconductor regions 2 in the terminal region 12. Also, in the semiconductor device 10 of Example 1, when a voltage is applied, at least one of the plurality of second semiconductor regions 2, including the second semiconductor region 2 (2b to be described later) formed at the position farthest from the active region 11, is completely depleted and functions as a RESURF region 8, which is also one of the features. The RESURF region 8 has a function of relaxing the electric field and improving the breakdown voltage by RESURF (Reduced Surface Field). In the RESURF region 8, a state is formed in which the second semiconductor region 2 is completely depleted and does not have an intrinsic region 7. When the impurity concentration of the second semiconductor region 2 is high, the intrinsic region 7 remains without being completely depleted. Therefore, the impurity concentration of the second semiconductor region 2 is set to a value low enough to completely deplete the second semiconductor region 2 when a voltage is applied. As shown in FIG. 1, it is desirable that the second semiconductor regions 2 in the terminal region 12 overlap from the side close to the active region 11 to the side far from it. Thereby, the width of the terminal region 12 can be reduced. Alternatively, not limited thereto, the second semiconductor regions 2 may overlap on the side close to the active region 11 in the second semiconductor regions 2 in the terminal region 12, and the second semiconductor regions 2 may be separated from each other on the side far from the active region 11. In either case, the second semiconductor regions 2 in the terminal region 12 are continuous with the second semiconductor region 2a of the active region 11 on the side close to the active region 11. The second semiconductor region 2 formed at the position farthest from the active region 11 among the second semiconductor regions 2 where the depletion layer 3 extending to the first semiconductor region 1 is continuous with the active region 11 in the thermal equilibrium state is referred to as the outermost second semiconductor region 2b continuous with the depletion layer 3. FIG. 2 is a plan view illustrating the shape of the mask of Example 1. FIG. 3 is a diagram illustrating the interval between the implantation window of the mask of Example 1 and the implantation window on one active region side, and the width of the implantation window. In addition, to easily observe the figure, the number of implantation windows 22 in FIG. 2 is simplified to be less than the number of second semiconductor regions 2 in FIG. 1. The horizontal axis in FIG. 3 represents the position POS, the left vertical axis represents the interval S (corresponding to the width of the shielding portion 21) between the implantation window 22 of the mask 20 and the implantation window 22 on one active region 11 side, and the right vertical axis represents the width W of the implantation window 22. Using the mask 20 shown in FIG. 2, impurities of the second conductivity type are implanted to form the second semiconductor region 2. The mask 20 has a shielding portion 21 for shielding impurities and an opening through which impurities pass, i.e., an implantation window 22. Further, due to the diffusion of the implanted impurities, the size of the second semiconductor region 2 is larger than the size of the implantation window 22. Here, the implantation window 22 corresponding to the second semiconductor region 2a of the active region 11 in the implantation window 22 is referred to as the active region implantation window 22a, and the implantation window 22 corresponding to the outermost peripheral second semiconductor region 2b continuous with the depletion layer 3 is referred to as the reference window 22b. The shape of the mask 20 in the first embodiment is set as follows: Let the position on the active region 11 side of the reference window 22b be X0, the distance between the position on the active region 11 side of the implantation window 22 adjacent to the active region 11 and X0 be XN, the interval between the reference window 22b and the implantation window 22 on the active region 11 side be Smax, the interval between the end of the active region 11 and the implantation window 22 adjacent to the active region 11 be Smin, the distance from X0 be x, and when the power coefficient is β, the interval S(x) between the implantation window 22 at the position of the distance x and the implantation window 22 on the active region 11 side is substantially equal to the value defined by the following formula (1). As the range of β, it is desirable that 0.3 ≤ β ≤ 0.5 as described later. Thereby, it is possible to reduce the width of the terminal region 12 in the terminal region 12 and to relax the electric field in the terminal region 12. Details of this effect will be described later. Further, the shape of the mask 20 in the first embodiment is set such that the width W(x) of the implantation window 22 at the position of the distance x decreases as it moves away from the active region 11. Thereby, compared with the case where the width W(x) of the implantation window 22 is constant regardless of the position of the distance x, the width of the second semiconductor region 2 can be reduced, so that the width of the terminal region 12 can be reduced. In the first embodiment, as shown in FIG. 3, it is assumed that the width W(x) of the implantation window at the position of the distance x decreases linearly as it moves away from the active region 11. FIG. 4 is a diagram for explaining the dose distribution in the first embodiment. The horizontal axis in FIG. 4 represents the position POS, and the vertical axis represents the dose DO. To form the RESURF region 8, the impurity concentration of the second semiconductor region 2 needs to be set to a value low enough that at least on the side far from the active region 11, the second semiconductor region 2 is completely depleted when a voltage is applied. Therefore, it is desirable that the dose in the second semiconductor region 2 of the terminal region 12 when implanting impurities of the second conductivity type using the mask 20 is 4×10 12 cm -2 above and 3×10 13 cm -2 as follows. Also, in order to fully utilize the function of the electric field relaxation effect in the RESURF region 8, it is desired that when a voltage is applied up to the breakdown voltage, at least the second semiconductor region 2 corresponding to the range of 0 ≤ x ≤ XN / 2 is completely depleted and functions as the RESURF region 8. Furthermore, it is more desired that at least the second semiconductor region 2 corresponding to the range of 0 ≤ x ≤ 2XN / 3 is completely depleted. In addition, it is not necessary to completely deplete the second semiconductor region 2 corresponding to x = XN. In the first embodiment, when the impurity of the second conductivity type is implanted using the mask 20, the dose distribution is set such that the dose in the second semiconductor region 2a of the active region 11 is approximately equal to the dose in the second semiconductor region 2 of the terminal region 12. Thereby, the impurity of the second conductivity type can be implanted using one mask 20 to form the second semiconductor region 2. In addition, the dose can be made smaller than the above range. However, since the second semiconductor region 2a in the active region 11 is used for the main body region of the semiconductor element formed in the active region 11, etc., there may be a case where the dose required for the second semiconductor region 2a in the active region 11 is insufficient. Therefore, although two masks 20 are required, as needed, the following configuration can be adopted: when the impurity of the second conductivity type is implanted using the mask 20, the dose in the second semiconductor region 2 of the terminal region 12 is made smaller than the dose in the second semiconductor region 2a of the active region 11. Next, a detailed description will be given of the effect of reducing the width of the terminal region 12 and relaxing the electric field in the terminal region 12, which can be achieved by the shape of the mask 20 in the first embodiment. FIG. 5 is a diagram for explaining the effect of reducing the width of the terminal region when β is changed. The horizontal axis in FIG. 5 represents the position POS, and the vertical axis represents the interval S (corresponding to the width of the shielding portion 21) between the implantation window 22 of the mask 20 and the implantation window 22 on the side of one active region 11. It is assumed that the interval S(x) between the implantation window 22 at a position separated from X0 by a distance x and the implantation window 22 on the side of the one active region 11 can be described by the following formula (2). When Lx(β) = XN, it is the same as formula (1). Here, when the number of implantation windows 22 is set to 19 and the distance between the position on the side of the active region 11 of the implantation window 22 adjacent to the active region 11 and X0 is set to Lx(β), for each of β = 0.3, 0.4, 0.5, 1.0, 2.0, the intervals S(x) and Lx(0.3), Lx(0.4), Lx(0.5), Lx(1.0), Lx(2.0) are calculated and shown in FIG. 5. As a result, it can be seen that the smaller β is, the smaller Lx(β) is, that is, the width of the terminal region 12 can be reduced. Here, β = 1.0 corresponds to the case where the interval S(x) increases linearly as it approaches the periphery of the terminal region 12 (x approaches 0). Although it is not exactly the same, in Patent Document 1, it roughly corresponds to the case where the aperture ratio of the implantation mask (20) decreases linearly as it approaches the outside of the terminal structure (32), or the case where the concentration decreases pseudo-linearly towards the outside as in Patent Document 2. Also, in Patent Document 1, β = 2.0 roughly corresponds to the case where the aperture ratio of the implantation mask (20) decreases polynomially as it approaches the outside of the terminal structure (32). However, in the case of β = 1.0 or β = 2.0, Lx(1.0) or Lx(2.0) becomes larger compared to Lx(0.3) to Lx(0.5), and it can be seen that it is not suitable for reducing the width of the terminal region 12. Also, although not shown in FIG. 5, as an example of an exponential function, an attempt was also made for the case where the interval S(x) depends on e x changes (in Patent Document 1, it roughly corresponds to the case where the aperture ratio of the implantation mask (20) decreases exponentially as it approaches the outside of the terminal structure (32)) and calculations were performed, which is roughly a case close to β = 2.0. Therefore, it can be seen that this case is also not suitable for reducing the width of the terminal region 12. FIG. 6 is a graph showing the change in breakdown voltage when β is changed. The horizontal axis of FIG. 6 represents β, and the vertical axis represents the breakdown voltage V. In FIG. 6, assuming that the interface charge density Qss is 0 cm -2 , considering a diode with a nominal breakdown voltage of 750 V and attempting to calculate the breakdown voltage V, as a result, if β is less than 0.3, the slope of the decrease in the breakdown voltage V becomes larger. When β ≤ 0.3, the breakdown voltage V is 850 V or more, and a breakdown voltage sufficiently greater than the nominal breakdown voltage of 750 V can be obtained. FIG. 7 is a graph showing the change in the breakdown voltage reduction amount when β is changed. The horizontal axis of FIG. 7 represents β, and the vertical axis represents the breakdown voltage reduction amount ΔV. Since it is assumed that the interface charge density Qss is 0 cm -2, the breakdown voltage V shown in FIG. 6 is equivalent to the initial breakdown voltage. However, during the pressure test or actual use, the interface charge density Qss changes, and as a result, the breakdown voltage V also changes. The change amount of the breakdown voltage V is the breakdown voltage reduction amount ΔV shown in FIG. 7. The uppermost part of the vertical axis is 0 V, and the lowermost part of the vertical axis is a negative value. When β = 0.4, since the absolute value of the maximum breakdown voltage reduction amount ΔV (negative value) is the smallest (becoming a peak in the graph of FIG. 7), it can be known that the performance is the best. Also, within the range where β is less than 0.3 or β is greater than 0.5, the slope of the breakdown voltage reduction amount ΔV becomes larger, and it can be known that the performance is likely to decrease. Therefore, it is desirable that 0.3 ≤ β ≤ 0.5. FIG. 8 is a cross-sectional view of a semiconductor device having a non-RESURF structure as a comparative example. In the case of the non-RESURF structure of the comparative example, the impurity concentration of the second semiconductor region 2 in the terminal region 12 is set relatively high. Even when a voltage is applied up to the breakdown voltage, the second semiconductor region 2 in the terminal region 12 is not completely depleted, and an intrinsic region 7 remains. Therefore, only the part of the intrinsic region 7 that remains undepleted becomes a dead space, and there is a useless region in reducing the width of the terminal region 12. FIG. 9 is a graph for explaining the characteristic difference in the electric field strength between the RESURF structure and the non-RESURF structure. The horizontal axis of FIG. 9 represents the position POS, and the vertical axis represents the electric field strength E. The dotted-line graph indicated by "Non RESURF" in FIG. 9 represents the characteristic of the electric field strength E of the non-RESURF structure of the comparative example. It can be seen that the electric field strength E changes significantly in the valley part corresponding to the shielding portion 21 and the mountain part corresponding to the implantation window 22. In contrast, the solid-line graph indicated by "RESURF" in FIG. 9 represents the characteristic of the electric field strength E of the RESURF structure of the present embodiment. It can be seen that since the change in the electric field strength E is small, the electric field concentration is suppressed, and thus the electric field is relaxed. Thereby, the breakdown voltage can be ensured. As described above, according to Embodiment 1, by adopting the RESURF structure in the terminal region 12 and setting the mask 20 to have a shape such that the interval S(x) between the implantation window 22 at the position of the distance x and the implantation window 22 on the side of the one active region 11 is substantially equal to the value defined by Equation (1) and 0.3 ≤ β ≤ 0.5, it is possible to reduce the width of the terminal region 12 and relax the electric field in the terminal region 12. [Embodiment 2] FIG. 10 is a graph for explaining the dose distribution of Embodiment 2. FIG. 10 is a graph corresponding to FIG. 4 of Embodiment 1. Example 2 is different from Example 1 in terms of the dose distribution. As shown in FIG. 10, the dose distribution in Example 2 is set to the following dose distribution: in the terminal region 12, the dose of the second semiconductor region 2 in the terminal region 12a on the side closer to the active region 11 is larger than the dose of the second semiconductor region 2 in the terminal region 12b on the side farther from the active region 11. Thereby, there is an effect of suppressing the breakdown voltage reduction caused by positive interface charges. Among them, in Example 2, in order to make the dose vary according to the region, it is necessary to use two masks 20 to implant impurities of the second conductivity type, which is also different from Example 1 in this regard. Except for the above, it is the same as Example 1, so the repeated description is omitted. [Example 3] FIG. 11 is a diagram for explaining the interval between the implantation window of the mask in Example 3 and the implantation window on one active region side, and the width of the implantation window. FIG. 11 is a diagram corresponding to FIG. 3 of Example 1. Example 3 is different from Example 1 in the width W(x) of the implantation window 22 at the position of the distance x. The shape of the mask 20 in Example 3 is set to the following shape: the width W(x) of the implantation window 22 at the position of the distance x linearly decreases as it moves away from the active region 11, and the slope of the decrease on the side closer to the active region 11 (x>XN') is larger than the slope of the decrease on the side farther from the active region 11 (x≤XN'). In addition, in FIG. 11, Wmax' is the value of the width W(x) of the implantation window 22 at the position where the distance x is XN'. Next, the reason for changing the slope of the decrease in the width W(x) of the implantation window 22 will be described. By heat treatment after implanting impurities of the second conductivity type, the width of the second semiconductor region 2 expands, and the peak concentration also decreases. The amount of decrease in the peak concentration is larger when the width W(x) of the implantation window 22 is narrower, and smaller when it is wider. In contrast, since the width of the implantation window 22 of the second semiconductor region 2a in the active region 11 is particularly wide compared to the width W(x) of the implantation window in the terminal region 12, the decrease in the peak concentration of the second semiconductor region 2a in the active region 11 is smaller than that of the second semiconductor region 2 in the terminal region 12. Therefore, a difference in peak concentration occurs between the active region 11 and the adjacent second semiconductor region 2. Here, when there is a large concentration difference, there is a risk of electric field concentration at the end of the active region 11, leading to a reduction in breakdown voltage. Therefore, near the active region 11, it is preferable that the width W(x) of the implantation window 22 is wider. On the other hand, when the width W(x) of the implantation window 22 is wider, the overall width of the terminal region 12 becomes larger, so it is preferably as narrow as possible. As a countermeasure against the electric field concentration at the end of the active region 11, since it is sufficient only near the active region 11, as shown in FIG. 11, by making the slope of the decrease in the side closer to the active region 11 (x > XN') larger than the slope of the decrease in the side farther from the active region 11 (x ≤ XN'), a countermeasure against the electric field concentration at the end of the active region 11 can be taken, and the overall width of the terminal region 12 can be made narrower compared to the case of FIG. 3. This is the reason for changing the slope of the decrease in the width W(x) of the implantation window 22. Also, thereby, when forming the second semiconductor region 2 by implanting impurities of the second conductivity type with the same dose distribution as in FIG. 4 of Example 1 using one mask 20, there is also an effect of suppressing the reduction in breakdown voltage caused by positive interface charges in the same manner as in Example 2. Except for the above, it is the same as Example 1, so the repeated description is omitted. [Example 4] FIG. 12 is a diagram for explaining the interval between the implantation window of the mask of Example 4 and the implantation window on one active region side, and the width of the implantation window. FIG. 12 is a diagram corresponding to FIG. 3 of Example 1. The difference between Example 4 and Example 1 and Example 3 lies in the width W(x) of the implantation window 22 at the position of the distance x. The shape of the mask 20 in Example 4 is set to the following shape: when the width of the implantation window 22 at the position of the distance XN is set to Wmax and the width of the implantation window 22 of the reference window 22b is set to Wmin, the width W(x) of the implantation window 22 at the position of the distance x is approximately equal to the value defined by the following formula (3). In Example 4, the change in the width W(x) of the implantation window 22 can be smoothed and not linear, and the reduction in breakdown voltage caused by positive interface charges can be suppressed. Except as described above, it is the same as Example 1 and Example 3, and thus the repeated description is omitted. [Example 5] FIG. 13 is a cross-sectional view of the semiconductor device of Example 5. Example 5 is an example in which a part of the second semiconductor region 2a in the effective region 11 of the semiconductor device 10 has a high-concentration second semiconductor region 2c in which the impurity concentration of the second conductivity type is higher than that of the surroundings. The high-concentration second semiconductor region 2c is provided, for example, in a part of the front surface of the second semiconductor region 2a in the effective region 11. Thereby, the depletion layer 3 in the effective region 11 can be further suppressed from expanding toward the front surface side. Further, the high-concentration second semiconductor region 2c is provided, for example, at a position in contact with the electrode 5. Thereby, for example, the contact resistance between the second semiconductor region 2a of the effective region 11 that functions as a main body region and the electrode 5 can be further reduced. It is desirable that the impurity concentration of the second conductivity type in the high-concentration second semiconductor region 2c is 1×10 14 cm -3 or so, or a higher concentration. That is, it is desirable that the impurity concentration of the second conductivity type in the high-concentration second semiconductor region 2c is more than one order of magnitude higher than the impurity concentration of the second conductivity type in the second semiconductor region 2a of the effective region 11 around the high-concentration second semiconductor region 2c or the second semiconductor region 2 of the terminal region 12. In this embodiment, the impurity concentration of the second conductivity type in the high-concentration second semiconductor region 2c is set to 2×10 14 cm -3 . Except as described above, it is the same as Examples 1 to 4, and thus the repeated description is omitted. [Example 6] FIG. 14 is a cross-sectional view of the semiconductor device of Example 6. Example 6 is an example in which a channel stop electrode 9 is provided. The semiconductor device 10 of this embodiment has a channel stop electrode 9 formed on the oxide film 4 and connected to the channel stop 6 through an opening provided in the oxide film 4. The end portion of the channel stop electrode 9 on the side close to the effective region 11 is located closer to the effective region 11 than the end portion of the channel stop 6 on the side close to the effective region 11. That is, the channel stop electrode 9 has a shape that extends more toward the effective region 11 than the channel stop 6. To reduce the width of the terminal region 12, it is necessary not only to reduce the size of the entire second semiconductor region 2 in the terminal region 12, but also to reduce the interval DCSP between the outermost second semiconductor region 2b continuous with the depletion layer 3 and the channel stopper 6. In the region between the outermost second semiconductor region 2b continuous with the depletion layer 3 and the channel stopper 6, the equipotential lines also expand. When the interval DCSP is wide, the equipotential lines do not expand to the channel stopper 6. In contrast, when the interval DCSP is narrow, a plurality of equipotential lines reach the channel stopper 6. Since the channel stopper 6 has a high concentration, the equipotential lines do not expand into the channel stopper 6. As a result, a plurality of equipotential lines concentrate on the end portion of the channel stopper 6 on the side close to the active region 11, and the electric field intensity locally becomes extremely high. Therefore, there is a lower limit value for the interval DCSP. Therefore, in this embodiment, the following configuration is adopted: a channel stopper electrode 9 is provided, and the end portion of the channel stopper electrode 9 on the side close to the active region 11 is located at a position closer to the active region 11 than the end portion of the channel stopper 6 on the side close to the active region 11. Thereby, the field plate effect of the channel stopper electrode 9 is generated. Since the equipotential lines concentrated at the end portion of the channel stopper 6 on the side close to the active region 11 move to the end portion of the channel stopper electrode 9 on the side close to the active region 11 at a constant ratio, the increase in the local electric field intensity generated at the end portion of the channel stopper 6 on the side close to the active region 11 is alleviated. This alleviating effect is determined by the interval LFP between the end portion of the channel stopper electrode 9 on the side close to the active region 11 and the end portion of the channel stopper 6 on the side close to the active region 11. A large alleviating effect can be obtained when the interval LFP is increased. On the other hand, however, the electric field intensity in the oxide film 4 below the end portion of the channel stopper electrode 9 on the side close to the active region 11 increases. The appropriate value of the interval LFP depends on the breakdown voltage and the concentration of the first semiconductor region 1 with a low concentration, but it may be set to several μm to several tens of μm. In this embodiment, the interval LFP is set to 20 μm. Thereby, compared with the case where the field plate effect of the channel stopper electrode 9 is not used, the interval DCSP can be shortened by more than 10%. Since the rest is the same as in Embodiments 1 to 4, the repeated description is omitted. As described above, the embodiments of the present invention have been described, but the present invention is not limited to the configurations described in the embodiments, and various changes can be made within the scope of the technical idea of the present invention. Also, a part or all of the configurations described in each embodiment can be combined and applied. 1: First semiconductor region 2: Second semiconductor region 2a: Second semiconductor region of the active region 2b: Outermost second semiconductor region continuous with the depletion layer 2c: High-concentration second semiconductor region 3: Depletion layer 4: Oxide film 5: Electrode 6: Channel stopper 7: Intrinsic region 8: RESURF region 9: Channel stopper electrode 10: Semiconductor device 11: Active region 12, 12a, 12b: Terminal region 20: Mask 21: Masking portion 22: Implantation window 22a: Implantation window of the active region 22b: Reference window DCSP: Interval DO: Dose E: Electric field strength LFP: Interval Lx: Distance POS: Position Qss: Interface charge density S: Interval between the implantation window and the implantation window on one active region side Smax: Interval Smin: Interval S(x): Interval V: Breakdown voltage W: Width of the implantation window Wmax: Width Wmax’: Width Wmin: Width W(x): Width x: Distance X0: Position XN: Distance XN’: Distance β: Power coefficient ΔV: Reduction amount of breakdown voltage FIG. 1 is a cross-sectional view of the semiconductor device of Example 1. FIG. 2 is a plan view for explaining the shape of the mask of Example 1. FIG. 3 is a diagram for explaining the interval between the implantation window of the mask of Example 1 and the implantation window on one active region side, and the width of the implantation window. FIG. 4 is a diagram for explaining the dose distribution of Example 1. FIG. 5 is a diagram for explaining the effect of reducing the width of the terminal region when β is changed. FIG. 6 is a diagram for explaining the change in breakdown voltage when β is changed. FIG. 7 is a diagram for explaining the change in the reduction amount of breakdown voltage when β is changed. FIG. 8 is a cross-sectional view of the semiconductor device of the non-RESURF structure of the comparative example. FIG. 9 is a diagram for explaining the characteristic difference in electric field strength between the RESURF structure and the non-RESURF structure. FIG. 10 is a diagram for explaining the dose distribution of Example 2. FIG. 11 is a diagram for explaining the interval between the implantation window of the mask of Example 3 and the implantation window on one active region side, and the width of the implantation window. FIG. 12 is a diagram for explaining the interval between the implantation window of the mask of Example 4 and the implantation window on one active region side, and the width of the implantation window. FIG. 13 is a cross-sectional view of the semiconductor device of Example 5. FIG. 14 is a cross-sectional view of the semiconductor device of Example 6. POS: Position S: Interval between the implantation window and the implantation window on one active region side Smax: Interval Smin: Interval S(x): Interval W: Width of the implantation window Wmax: Width Wmin: Width W(x): Width X0: Position XN: Distance x: Distance β: Power coefficient

Claims

1. A method for manufacturing a semiconductor device, characterized in that it is a method for manufacturing a semiconductor device having a terminal region around an effective region, wherein the terminal region is formed on the front side of a first semiconductor region having a first conductivity type, comprising a plurality of second semiconductor regions having a second conductivity type and extending to a depletion layer of the first semiconductor region and continuous with the effective region when a voltage is applied, wherein when a voltage is applied, at least one of the plurality of second semiconductor regions, including the second semiconductor region formed at the position furthest from the effective region, is completely depleted and functions as a RESURF region; and the method for manufacturing the semiconductor device uses a mask to implant impurities of the second conductivity type to form the second semiconductor region, the mask being used to form the second semiconductor region and being connected to... In thermal equilibrium, the injection window corresponding to the second semiconductor region at the position furthest from the effective region, which extends to the depletion layer of the first semiconductor region and is continuous with the effective region, is designated as the reference window. The position of the reference window on the effective region side is designated as X0. The distance between the position of the injection window on the effective region side adjacent to the effective region and X0 is designated as XN. The interval between the reference window and the adjacent injection window closer to the effective region side is designated as Smax. The interval between the end of the effective region and the injection window adjacent to the effective region is designated as Smin. The distance from X0 is designated as x. When the power factor is designated as β, the interval S(x) between the injection window at the position at distance x and the adjacent injection window closer to the effective region side is approximately equal to the value specified by the following formula.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the width W(x) of the injection window at the position of the aforementioned distance x of the aforementioned mask decreases as it moves away from the aforementioned effective region.

3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein the width W(x) of the injection window at the location of the aforementioned distance x of the aforementioned mask decreases linearly with distance from the aforementioned effective region.

4. The method of manufacturing a semiconductor device as claimed in claim 2, wherein the width W(x) of the injection window at the position of the aforementioned distance x of the aforementioned mask decreases linearly with distance from the aforementioned effective region, and the slope of the decrease is greater on the side closer to the aforementioned effective region than on the side farther from the aforementioned effective region.

5. A method for manufacturing a semiconductor device as claimed in claim 2, wherein the mask is a mask in which the width of the injection window at the location at a distance XN is set to Wmax and the width of the injection window of the reference window is set to Wmin, the width W(x) of the injection window at the location at a distance x is approximately equal to the value specified by the following formula.

6. A method for manufacturing a semiconductor device as claimed in claim 1, wherein when the impurity of the second conductivity type is injected using the aforementioned mask, the dose in the second semiconductor region of the effective region is substantially equal to the dose in the second semiconductor region of the terminal region.

7. A method for manufacturing a semiconductor device as claimed in claim 1, wherein when the impurity of the second conductivity type is injected using the aforementioned mask, the dose in the second semiconductor region of the effective region is smaller than the dose in the second semiconductor region of the terminal region.

8. A method for manufacturing a semiconductor device as claimed in claim 1, wherein when the impurity of the second conductivity type is injected using the aforementioned mask, in the aforementioned terminal region, the dose of the second semiconductor region on the side closer to the aforementioned effective region is greater than the dose of the second semiconductor region on the side farther from the aforementioned effective region.

9. A method for manufacturing a semiconductor device as claimed in claim 1, wherein when the impurity of the second conductivity type is injected using the aforementioned mask, the dose in the second semiconductor region of the terminal region is 4×10¹² cm⁻² or more and 3×10¹³ cm⁻² or less.

10. A method for manufacturing a semiconductor device as claimed in claim 1, wherein when a voltage is applied to a withstand voltage, the second semiconductor region corresponding to at least the range of 0≤x≤XN / 2 is completely depleted and functions as the RESURF region.

11. A semiconductor device, characterized in that it has an effective region and a terminal region formed around the effective region; and the terminal region has: a first semiconductor region having a first conductivity type; and a plurality of second semiconductor regions formed on the front side of the first semiconductor region having a second conductivity type, and extending to a depletion layer of the first semiconductor region and continuous with the effective region when a voltage is applied; when a voltage is applied, at least one of the second semiconductor regions, including the second semiconductor region formed at the position furthest from the effective region, is completely depleted and functions as a RESURF region; the terminal region has the second semiconductor region formed using a manufacturing method of a semiconductor device as claimed in any one of claims 1 to 10.

12. The semiconductor device of claim 11, wherein in the second semiconductor region, the depletion layer that diffuses into the first semiconductor region from the second semiconductor region formed by the injection window adjacent to the effective region to the second semiconductor region formed by the reference window is continuous from the effective region under thermal equilibrium, and each second semiconductor region is almost an intrinsic region, and the depletion of each of the second semiconductor regions caused by the applied voltage begins from the second semiconductor region formed by the reference window.

13. The semiconductor device of claim 11, wherein the second semiconductor region formed by an injection window adjacent to the effective region overlaps with the second semiconductor region formed by the reference window.

14. The semiconductor device of claim 11, wherein in the second semiconductor region, from the second semiconductor region formed by the injection window adjacent to the effective region to the second semiconductor region formed by the reference window, a plurality of the second semiconductor regions overlap on the side close to the effective region, and the second semiconductor regions are separated from each other on the side away from the effective region.

15. The semiconductor device of claim 11, wherein a portion of the second semiconductor region of the effective region has a high-concentration second semiconductor region with a higher impurity concentration of the second conductivity type than the surrounding area.

16. The semiconductor device of claim 11, comprising: a channel baffle formed in the terminal region and having a first conductivity type with a higher concentration than that of the first semiconductor region; an oxide film formed covering the first semiconductor region, the second semiconductor region, and the channel baffle; and a channel baffle electrode formed on the oxide film and connected to the channel baffle via an opening provided in the oxide film; wherein the end of the channel baffle electrode on the side near the effective region is located closer to the effective region than the end of the channel baffle on the side near the effective region.

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