Display device

Abstract

The display device includes multiple channels, including at least one virtual channel; multiple first sampling circuits that sample multiple virtual voltages corresponding to each of the at least one virtual channel; and hold / scale circuitry including a first input node, a second input node, a first output node, a second output node, a first feedback capacitor connected between the first input node and the first output node, and a second feedback capacitor connected between the second input node and the second output node.

Description

Technical Field

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2023-0126568, filed with the Korean Intellectual Property Office on September 21, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present invention relates to a display device. Prior Art

[0003] A display device may include a display panel for displaying an image and a display driving circuit for driving the display panel. The display driving circuit may drive the display panel by receiving image data from the outside and applying an image signal corresponding to the received image data to the data lines of the display panel. Recently, the use of organic light-emitting diode (OLED) display panels has been increasing, in which each of a plurality of pixels in a pixel array is equipped with an OLED. The OLED display panel has electrical characteristics, such as the threshold voltage or mobility of a driving transistor configured in a pixel may be non-uniform between pixels, or the electrical characteristics may change due to pixel degradation. Therefore, the image quality displayed on the OLED display panel may be low. Summary of the Invention

[0004] Generally, in some aspects, the present invention relates to display devices and systems having precise sensing of active channel outputs.

[0005] According to some aspects of the present invention, a display device includes: a plurality of channels including at least one virtual channel; a plurality of first sampling circuits sampling a plurality of virtual voltages corresponding to each of the at least one virtual channel; and a hold / scale circuit including a first input node, a second input node, a first output node, a second output node, a first feedback capacitor connected between the first input node and the first output node, and a second feedback capacitor connected between the second input node and the second output node, the hold / scale circuit being configured to store voltages of substantially the same magnitude in the first and second feedback capacitors, receive the plurality of sampled virtual voltages from the first input node and the second input node, and output a plurality of virtual output voltages obtained by amplifying the plurality of sampled virtual voltages to the first output node and the second output node.

[0006] According to some aspects of the present invention, a display device includes: a first input node and a second input node; a first output node and a second output node; a first feedback capacitor connected between the first input node and the first output node; a second feedback capacitor connected between the second input node and the second output node; a differential amplifier including a first input terminal, a second input terminal, a first output terminal connected to the first output node, and a second output terminal connected to the second output node; a plurality of offset capacitors respectively connected to the first input terminal and the second input terminal and respectively storing offset voltages of the first input terminal and the second input terminal; a first switch having one end connected to the first output node and the other end connected to the first feedback capacitor; a second switch having one end connected to the second output node and the other end connected to the second feedback capacitor; a third switch having one end connected to the other end of the first switch and the other end connected to an input terminal for inputting a predetermined first voltage; a fourth switch having one end connected to the other end of the second switch and the other end connected to an input terminal for inputting a predetermined first voltage; a fifth switch having one end connected to the other end of the first switch and the other end connected to an input terminal for inputting a first reference voltage; and a sixth switch having one end connected to the other end of the second switch and the other end connected to an input terminal for inputting a second reference voltage different from the first reference voltage.

[0007] According to some aspects of the present invention, a display system includes: a display panel including a plurality of gate lines, a plurality of data lines, a plurality of sensing lines including at least one virtual channel, and a plurality of pixels; a host processor configured to generate image data to be displayed on the display panel and transmit the image data to a timing controller; a data driver including a first input node, a second input node, a first output node, a second output node, a first feedback capacitor connected between the first input node and the first output node, and a second feedback capacitor connected between the second input node and the second output node, the data driver being configured to store voltages of substantially the same magnitude in the first and second feedback capacitors, sample each of a plurality of virtual voltages corresponding to at least one virtual channel, receive a plurality of sampled virtual voltages from the first input node and the second input node, output a plurality of virtual output voltages obtained by amplifying the plurality of sampled virtual voltages to the first output node and the second output node, and receive the plurality of virtual output voltages and a plurality of active output voltages to generate data sensing signals indicating electrical characteristics of each of the plurality of pixels; and a timing controller configured to receive the image data, compensate the image data based on the data sensing signals, and generate compensated image data. Brief Description of the Drawings

[0008] FIG. 1 is an exemplary block diagram showing a display system according to some embodiments. FIG. 2 is an exemplary circuit diagram of a pixel according to some embodiments. FIG. 3 is an exemplary block diagram showing a sensing block according to some embodiments. FIG. 4 is a flowchart showing an example of a method of operating a sensing block according to some embodiments. FIG. 5 is a diagram showing an example of an analog front end according to some embodiments. FIG. 6 is a diagram showing each output of a plurality of analog-to-digital converters (ADCs) in an example of a display system including the analog front end of FIG. 5 according to some embodiments. FIG. 7 is a diagram showing an example of an analog front end according to some embodiments. FIG. 8 is a diagram showing each output of a plurality of ADCs in an example of a display system including the analog front end of FIG. 7 according to some embodiments. FIG. 9 is a diagram showing an example of an analog front end according to some embodiments. FIG. 10 is a timing diagram showing an example of a signal for controlling a switch in the analog front end of FIG. 9 according to some embodiments. FIG. 11 is a diagram showing each output of a plurality of ADCs in an example of a display system including the analog front end of FIG. 9 according to some embodiments. FIG. 12 is a block diagram showing an example of an electronic system according to some embodiments. Embodiments

[0009] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0010] FIG. 1 is an exemplary block diagram showing a display system 10 according to some embodiments. In some embodiments, the display system 10 may be installed on an electronic device having an image display function. For example, the electronic device may include a smartphone, a tablet personal computer, a portable multimedia player (PMP), a camera, a wearable device, a television, a digital versatile disc (DVD) player, a refrigerator, an air conditioner, an air purifier, a set-top box, various medical devices, a navigation device, a global positioning system (GPS) receiver, a vehicle device, furniture, various measurement devices, and the like.

[0011] In FIG. 1, the display system 10 may include a host processor 20, a display driving circuit 30, and a display panel 40. In addition, the display driving circuit 30 may include a timing controller 31, a data driver 33, and a gate driver 35. The display driving circuit 30 and the display panel 40 may be implemented as one module and may be referred to as a display device.

[0012] The host processor 20 can comprehensively control the display system 10. The host processor 20 can generate image data to be displayed on the display panel 40 and transmit the image data and control commands to the display driving circuit 30. The host processor 20 can be a graphics processing unit. However, in some embodiments, the host processor 20 can be implemented as various types of processors, such as a central processing unit (CPU), a microprocessor, a multimedia processor, or an application processor. In some embodiments, the host processor 20 can be implemented as an integrated circuit (IC) or a system-on-chip (SoC).

[0013] The timing controller 31 can control the driving timings of the data driver 33 and the gate driver 35 based on the control commands received from the host processor 20. The timing controller 31 can perform various image processes on the image data received from the host processor 20 to change the format of the image data, reduce power consumption, etc.

[0014] The timing controller 31 can transmit a data control signal D_CTRL to the data driver 33. The data control signal D_CTRL can include a clock signal and image data. The timing controller 31 can transmit a gate control signal G_CTRL to the gate driver 35.

[0015] In addition, the timing controller 31 can receive a data sensing signal DS from the data driver 33. The data sensing signal DS can be a signal indicating the electrical characteristics of each of the pixels PX or a plurality of pixels PX arranged on the display panel 40.

[0016] In addition, the timing controller 31 can perform data compensation on the image data, such as external compensation, and provide the compensated image data to the data driver 33. The timing controller 31 can calculate a compensation value based on the received data sensing signal DS to compensate for the deviation of the electrical characteristics between the pixels PX or the change in the electrical characteristics due to their deterioration. For example, the electrical characteristics can include the threshold voltage of the driving transistor arranged in the pixel PX, the mobility of the driving transistor, the threshold voltage of the light-emitting device, etc. The timing controller 31 can store the calculated compensation value in the memory. The compensation value stored in the memory can be updated each time the electrical characteristics sensing operation of the pixel PX is performed. The timing controller 31 can perform data compensation on the image data based on the compensation value.

[0017] The data driver 33 can process the image data based on the data control signal D_CTRL received from the timing controller 31 and generate a data sensing signal DS. The data sensing signal DS can be a signal indicating the electrical characteristics of each of the plurality of pixels PX. For example, the data driver 33 can process the image data synchronously with the clock signal received from the timing controller 31. The data driver 33 can drive the plurality of pixels PX through a plurality of data lines DL and measure the electrical characteristics of the plurality of pixels PX through the sensing line SL.

[0018] In some embodiments, the data driver 33 can include a driving block 301 and a sensing block 303. The driving block 301 can perform digital-to-analog conversion on the received image data and provide the analog-converted data signal to the display panel 40 through a plurality of data lines DL. Each data signal can be provided to each of the plurality of pixels PX. The driving block 301 can convert the image data provided by the timing controller 31 into a data signal, such as a data voltage, in the display mode and output the data voltage to the display panel 40 through the data lines DL. The driving block 301 can convert the internally set sensing data into a data signal in the sensing mode and output the data signal to the display panel 40 through the data lines DL. In some embodiments, the driving block 301 can include a plurality of digital-to-analog converters DAC, and each of the plurality of DACs can convert the input image data into a data voltage.

[0019] The sensing block 303 can receive the sensing signal from the display panel 40 that operates in response to the data signal through the sensing line SL. Then, the sensing block 303 can transmit the received sensing signal as the data sensing signal DS to the timing controller 31.

[0020] The sensing block 303 can periodically or non-periodically measure the electrical characteristics of the plurality of pixels PX in the sensing mode. In some embodiments, the sensing mode can be set during the manufacturing stage of the display device, during the startup period after the display system 10 is powered on, during the end period when the display system 10 is powered off, or during the virtual period (or vertical blanking period) between the frame display periods of the display panel 40. In some embodiments, the sensing mode can be executed in a state where only the screen of the display device is turned off while the power is still supplied to the display system 10, such as in the standby mode, sleep mode, low power consumption mode, or similar modes. The timing controller 31 can detect the standby mode, sleep mode, low power consumption mode, or similar modes based on a predetermined control process and control the overall operation of the sensing mode.

[0021] The sensing block 303 can receive sensing signals indicating the electrical characteristics of the respective pixels PX through a plurality of sensing lines SL, and generate sensing values by performing analog-to-digital conversion on the sensing signals. When the display driving circuit 30 operates in the display mode, the sensing signals can include pixel voltages or pixel currents of the pixels PX corresponding to the image data, and when the display driving circuit 30 operates in the sensing mode, the sensing signals can include sensing currents. The sensing current can be the sensing current of the pixel PX corresponding to the sensing data, or a current based on the voltage generated in the sensing block 303.

[0022] The sensing block 303 can simultaneously sample a plurality of sensing signals received through the plurality of sensing lines SL, and sequentially perform analog-to-digital conversion on the sampled sensing values. The sensing block 303 can be equipped with a plurality of sampling circuits to simultaneously sample the plurality of sensing signals, and a hold / scale circuit to scale and hold the sampled signals. The sensing block 303 can include one or more analog-to-digital converters (ADCs) to perform analog-to-digital conversion on the plurality of sampled sensing signals. In some embodiments, the ADC can be implemented as a pipelined analog-to-digital converter (ADC). The pipelined ADC can share a current sensing scheme through parallel sensing and serial amplification processes, thereby minimizing sensing errors and maximizing sensing capabilities. In some embodiments, the ADC can operate based on the clock signal in the data control signal D_CTRL.

[0023] The gate driver 35 can drive a plurality of gate lines GL of the display panel 40 based on the gate control signal G_CTRL received from the timing controller 31. The gate driver 35 can provide a gate-on voltage pulse to the corresponding gate line GL for each of the plurality of gate lines GL during the corresponding driving period based on the gate control signal G_CTRL. For example, the gate-on voltage can be a scan voltage or a sense-on voltage. The gate driver 35 can output the gate driving signal G_CTRL to the display panel 40 through the gate lines GL.

[0024] The display panel 40 may include a plurality of signal lines, such as a plurality of gate lines GL, a plurality of data lines DL, or a plurality of sensing lines SL, and a plurality of pixels PX connected to the plurality of signal lines and arranged in a matrix form. The display panel 40 may display an image based on a data signal received from the data driver 33 or a gate driving signal received from the gate driver 35. In some embodiments, the display panel 40 may include pixels implemented using organic light-emitting diode (OLED) units. Accordingly, the OLED units may receive the data signal of the data line DL and the gate driving signal of the gate line GL, and may perform an operation of displaying an image in response to the operation of the organic light-emitting diode OLED. However, in some embodiments, the display panel 40 may be implemented as another type of flat panel display or a flexible display panel.

[0025] In some embodiments, the pixel PX may have a red, green, blue (RGB) structure. However, in some embodiments, the pixel PX may have an RGBW structure, further including a white (W) sub-pixel for improving its brightness. In some embodiments, the pixel PX may be implemented as a combination of different color sub-pixels.

[0026] FIG. 2 is an exemplary circuit diagram of a pixel according to some embodiments. In FIG. 2, the pixel PX may include a switching transistor SWT, a driving transistor DT, an organic light-emitting diode (OLED) 25, a storage capacitor Cst, and a sensing transistor SST. In some embodiments, the pixel PX may have various structures.

[0027] A first driving voltage ELVDD and a second driving voltage ELVSS may be applied to the pixel PX. The first driving voltage ELVDD may be relatively higher than the second driving voltage ELVSS.

[0028] The switching transistor SWT, the sensing transistor SST, or the driving transistor DT may be formed as an amorphous silicon (a-Si) thin film transistor (TFT), a polycrystalline silicon (poly-Si) TFT, an oxide TFT, or an organic TFT, etc.

[0029] The gate line GL connected to the pixel PX may include a first gate line GL1 and a second gate line GL2.

[0030] The switching transistor SWT can be connected to the first gate line GL1 and the data line DL. The switching transistor SWT can be turned on in response to a scan voltage Vsc applied through the first gate line GL1. When turned on, the switching transistor SWT can provide a data signal, such as a data voltage Vd, provided through the data line DL, to the gate node N1 of the driving transistor DT. The data voltage Vd can be generated by a digital-to-analog converter DAC of the data driver 33. Multiple digital-to-analog converters DAC for generating data voltages provided to multiple data lines DL (Figure 1) can be configured in the driving block 301.

[0031] The sensing transistor SST can be connected to the second gate line GL2 and the sensing line SL, and can be turned on by a sensing turn-on voltage Vso applied through the second gate line GL2. The sensing transistor SST can be turned on when operating in the sensing mode. When operating in the sensing mode, the sensing transistor SST can output a current from the driving transistor DT or the organic light-emitting diode 25 through the sensing line SL.

[0032] The storage capacitor Cst can store the difference between the data voltage Vd applied to the gate node N1 of the driving transistor DT through the switching transistor SWT and the initialization voltage Vint provided to the source node N2 of the driving transistor DT through the sensing transistor SST, so as to provide a constant driving voltage Vgs to the driving transistor DT within a predetermined period (e.g., one frame).

[0033] The first driving voltage ELVDD can be applied to the drain node of the driving transistor DT, and the driving transistor DT can provide a driving current IDT proportional to the driving voltage Vgs to the organic light-emitting diode 25.

[0034] The organic light-emitting diode 25 can include an anode connected to the source node N2 of the driving transistor DT, a cathode to which a second driving voltage ELVSS is applied, and an organic light-emitting layer located between the cathode and the anode. The cathode can be a common electrode shared by multiple pixels PX. The organic light-emitting layer of the organic light-emitting diode 25 can emit light when receiving the driving current IDT from the driving transistor DT. The light intensity can be proportional to the driving current IDT. The driving current IDT can be expressed as Equation 1:

[0035] <Equation 1>

[0036] Here, β represents a constant value determined by the mobility of the driving transistor DT, and Vth represents the threshold voltage of the driving transistor DT.

[0037] In the display mode, the switching transistor SWT can supply the driving transistor DT with a data voltage Vd applied through the data line DL. At this time, the sensing transistor SST can be turned on. A current IDT proportional to the driving voltage Vgs, which is the difference between the voltage of the gate node N1 of the driving transistor DT and the voltage of the source node N2 of the driving transistor DT, can flow to the organic light-emitting diode 25. The organic light-emitting diode 25 can output light based on the driving current IDT corresponding to the image data.

[0038] In the sensing mode, the electrical characteristics of the pixel PX can be measured. The switching transistor SWT can supply the driving transistor DT with a sensing data voltage Vd applied through the data line DL. The sensing transistor SST can be turned on, and a current IDT proportional to the driving voltage Vgs, which is the difference between the voltage of the gate node N1 of the driving transistor DT and the voltage of the source node N2 of the driving transistor DT, can flow to the sensing line SL to charge the parasitic capacitor of the sensing line SL, i.e., the line capacitor Cli.

[0039] In some embodiments, the analog-to-digital converter can measure the voltage on the sensing line SL at the time point when the voltage of the source node N2 of the driving transistor DT reaches saturation or at the time point when the voltage of the source node N2 linearly increases. The sensing signal, i.e., the pixel voltage Vps measured at the time point when the voltage of the source node N2 reaches saturation, can include information about the threshold voltage Vth of the driving transistor DT, and the pixel voltage Vps measured at the time point when the voltage of the source node N2 linearly increases can include information about the mobility of the driving transistor DT. For example, when the threshold voltage Vth of the pixel PX increases, even if the same data voltage Vd is supplied to the pixel PX, the amount of light output by the organic light-emitting diode 25 may decrease due to the decrease in the driving current IDT.

[0040] The timing controller 31 (in FIG. 1) can detect an increase in the threshold voltage Vth of the driving transistor DT by measuring the electrical characteristics of the pixel PX through the sensing block 303, to compensate for the increase in the threshold voltage Vth of the pixel PX, and compensate the image data value based on the detected increase. The driving block 301 (in FIG. 1) can generate an increased data signal, i.e., an increased data voltage Vd, based on the image data value adjusted by the timing controller 31. Therefore, the decrease in the driving current IDT caused by the increase in the threshold voltage Vth can be offset by an increase in the driving voltage Vgs. In addition, the display driving circuit 30 can measure the electrical characteristics of each of the plurality of pixels PX, and perform external compensation based on the measured values, thereby compensating for the change in electrical characteristics caused by the deviation or deterioration of the electrical characteristics of the plurality of pixels PX.

[0041] FIG. 3 is an exemplary block diagram showing a sensing block according to some embodiments. In FIG. 3, the sensing block 303 can include an analog front end (AFE) 3007 and a plurality of analog-to-digital converters (ADCs) 3005. The analog front end 3007 can include a plurality of sampling circuits 3001 or 3001a, 3001b,..., and 3001n, and a hold / scale circuit 3003.

[0042] The plurality of sampling circuits 3001 can be respectively connected to the plurality of pixels PX included in the display panel 40 (in FIG. 1) through a plurality of sensing lines SL. Each of the plurality of sampling circuits 3001 can detect the characteristics of the corresponding pixel PX based on the sensing signals received through the connected sensing lines SL.

[0043] In some embodiments, the plurality of channels can be implemented in different ways. For example, two signal lines receiving a pair of input voltages (e.g., VIP1 and VIN1) can form one channel. Here, one of the pair of input voltages (e.g., VIP1) can be the high voltage actually input from the display panel 40. For example, the plurality of input voltages VIP can be the first to the m-th sensing signals (here, m is a natural number of 2 or greater). The other of the input voltages (e.g., VIN1) can be a reference voltage for implementing different ways.

[0044] In FIG. 3, "n" channels (here, "n" is a natural number of 2 or greater) are depicted for convenience of explanation, and the number of channels can be changed. In some embodiments, one channel can be connected to at least one sensing line SL.

[0045] Multiple sampling circuits 3001 can sample the first to the m-th sensing signals simultaneously based on multiple input voltages VIN, and transmit the sampled signals to the hold / scale circuit 3003. For example, multiple sensing signals, such as the first to the m-th sensing signals, can be received through the first to the n-th sensing lines SL1 to SLn, and each of the multiple sampling circuits 3001 can provide the sensing signal selected from the first to the m-th sensing signals to the hold / scale circuit 3003. In some embodiments, the sensing signals sampled by the multiple sampling circuits 3001 can be provided to the hold / scale circuit 3003 in sequence.

[0046] The hold / scale circuit 3003 can amplify the signals received from the multiple sampling circuits 3001, and sequentially transmit the amplified signals to the multiple analog-to-digital converters 3005. The hold / scale circuit 3003 can amplify and provide the signals received from the multiple sampling circuits 3001 to enable high-speed operation of the multiple analog-to-digital converters 3005 connected thereto. In some embodiments, the hold / scale circuit 3003 can include an amplifier. For example, the hold / scale circuit 3003 can include an amplifier and a feedback capacitor. The hold / scale circuit 3003 can include multiple hold switches and multiple reset switches.

[0047] In some embodiments, the amplifier can also be implemented in different ways. For example, the amplifier can include two input terminals and two output terminals. One of the two input terminals can be selectively connected to a signal line group of multiple channels (e.g., the signal lines receiving the input voltages VIP1, VIP2,... and VIPn), and the other can be selectively connected to another signal line group of multiple channels (e.g., the signal lines receiving the input voltages VIN1,... and VINn). The amplifier can sequentially receive multiple sampled input voltages VIP and VIN, and generate corresponding first output voltage Vop and second output voltage Von.

[0048] An offset voltage may be formed at the input terminal of the amplifier. When the number of sampling circuits to be connected to the hold / scale circuit 3003 increases, the parasitic capacitance caused by the parasitic capacitors formed on the lines of the input signal to the amplifier may increase. The increase in parasitic capacitance may increase the offset voltage generated at the input terminal of the amplifier. Therefore, it may be difficult to accurately sense the critical voltage of the pixel PX, and the image data may not be accurately compensated.

[0049] A plurality of analog-to-digital converters 3005 can sequentially receive a first output voltage Vop and a corresponding second output voltage Von from the hold / scale circuit 3003, amplify the received voltages, and convert the amplified voltages into digital signals. In some embodiments, each of the plurality of analog-to-digital converters 3005 can be implemented in a different manner. In some embodiments, each of the plurality of analog-to-digital converters 3005 can include a common-mode feedback circuit (CMFB). The CMFB can operate using switches, capacitors, clocks, or similar elements at its output to maintain the common mode of different output voltages, thereby facilitating low-voltage or low-power operation of each of the plurality of analog-to-digital converters 3005.

[0050] As shown in FIG. 3, the plurality of analog-to-digital converters 3005 can include four analog-to-digital converters 3005a, 3005b, and 3005c. In some embodiments, the plurality of analog-to-digital converters 3005 can be interconnected in a pipeline manner. For example, the analog-to-digital converter 3005a of the first stage (or stage #1) can digitize the first output voltage Vop and the second output voltage Von into 3 bits, and analogize the digitized output to generate a first output voltage Vop_2 and a second output voltage Von_2. For example, the analog-to-digital converter 3005a can subtract the analogized first output voltage Vop_2 and the second output voltage Von_2 from the first input voltage VIP1 and the second input voltage VIN1, and transmit the resulting values back to the analog-to-digital converter 3005b of the second stage (or stage #2). Similarly, the output values of the previous stage can be transmitted through the analog-to-digital converter 3005b to the analog-to-digital converter 3005c of the third stage (or stage #3). The bits of each stage can be output sequentially with a time difference. Therefore, all the bits extracted based on the same first input voltage VIP and second input voltage VIN can be arranged in chronological order in a shift register (not shown) before being transmitted to the timing controller 31. The analog-to-digital converter of the currently ongoing stage can determine the bits by fully digitizing the first input voltage and the second input voltage, and can transmit the result of re-analogizing the digitized output and the difference between the first input voltage and the second input voltage to the next stage. At the same time, the next input voltage can be digitized at the current stage.

[0051] In some embodiments, each of the plurality of analog-to-digital converters 3005 can generate a 10-bit data sense signal DS, and each of the plurality of analog-to-digital converters 3005 can transmit the generated data sense signal DS to the timing controller 31. In some embodiments, the plurality of analog-to-digital converters 3005 can be implemented in another suitable manner. For example, each of the plurality of analog-to-digital converters 3005 can generate a 12-bit data sense signal DS.

[0052] Some of the multiple sensing lines SL may operate as active channels, while the remaining portions of the multiple sensing lines SL may operate as virtual channels. When operating in the display mode, the display panel 40 may first sense the output of the virtual channels and then sense the output of the active channels to accurately sense the output of each channel from the pixel PX. Here, when the display panel 40 operates in the display mode, the active channels may be the sensing lines that output pixel voltages or pixel signals from the pixel PX to the sensing block 303. In addition, when the display panel 40 operates in the sensing mode, the virtual channels may be the sensing lines that output a floating voltage rather than a pixel voltage or a pixel signal to the sensing block 303 as a sensing signal. In some embodiments, the virtual channels may not actually be connected to the display panel 40 and may be the sensing lines that output a floating voltage as a sensing signal. Among the multiple sensing lines SL, the sensing lines operating as virtual channels may be predetermined. For example, the first sampling circuit 3001a or the second sampling circuit 3001b may be connected to the sensing lines operating as virtual channels, while the remaining sampling circuits 3001c,... or 3001n may be connected to the sensing lines operating as active channels. In addition, the sensing block 303 may sense the sensing signal of the virtual channels before sensing the sensing signal of the active channels to accurately sense the sensing signal of the active channels.

[0053] In some embodiments, the virtual channels may output a floating voltage as a sensing signal, and thus the sensing signal may be amplified when passing through the multiple analog-to-digital converters 3005 and may exceed the normal operating range of the analog-to-digital converters. For example, the output of the third-stage (or stage #3) analog-to-digital converter 3005c may exceed the normal operating range of the analog-to-digital converters. The multiple analog-to-digital converters 3005 may be driven in a pipelined manner, and thus the operating range of the analog-to-digital converters deviated by the virtual channels may also affect the situation of sensing the output of the active channels.

[0054] FIG. 4 is a flowchart showing an example of a method of operating a sensing block according to some embodiments. In FIG. 4, the multiple sampling circuits 3001 may sample multiple input voltages respectively to generate sensing signals (S401). Hereinafter, the sampling period may refer to the period in which each of the multiple sampling circuits 3001 samples the first input voltage VIPi (here, "i" is a natural number equal to or less than "n").

[0055] The hold / scale circuit 3003 may generate a first output voltage Vop and a second output voltage Von by performing a scale and hold operation on the sensing signals (S403).

[0056] Hereinafter, the hold period may refer to the period during which the hold / scale circuit 3003 performs the scaling and holding operations. The scaling operation may be an operation in which the hold / scale circuit 3003 sequentially scales the sampled sense signal into a plurality of output voltages by using an amplifier and a feedback capacitor.

[0057] The holding operation may be an operation in which the hold / scale circuit 3003 sequentially outputs the scaled sense signal to a plurality of analog-to-digital converters by using an amplifier and a capacitor.

[0058] A plurality of analog-to-digital converters 3005 may generate a data sense signal DS (S405) by performing a conversion operation on the first output voltage Vop and the second output voltage Von.

[0059] Then, each of the plurality of analog-to-digital converters 3005 may transmit the generated data sense signal DS to the timing controller 31.

[0060] The timing controller 31 may compensate the image data based on the data sense signal DS (S407). The timing controller 31 may then transmit the compensated image data to the data driver 33, and the data driver 33 may generate a data voltage based on the compensated image data.

[0061] FIG. 5 is a diagram showing an example of an analog front end according to some embodiments. In FIG. 5, the analog front end 500 may include a plurality of sampling circuits 5001 or 5001a, 5001b,..., and 5001n and a hold / scale circuit 5003. Hereinafter, a description will be provided based on the sampling circuit 5001a, and it can be understood that the corresponding hold signals QH1 to QHn are respectively applied to the sampling circuits 5001a, 5001b,..., and 5001n.

[0062] The sampling circuit 5001a may include a plurality of sampling capacitors CSP1 and CSN1, a plurality of sampling switches SSP1 and SSN1, a differential switch SD1, a plurality of common-mode switches SCP1 and SCN1, and a plurality of hold switches SHP1 and SHN1.

[0063] The first sampling switch SSP1 may be connected between the first channel receiving the first input voltage VIP1 and the first node N501. In addition, the second sampling switch SSN1 may be connected between the first channel receiving the second input voltage VIN1 and the ninth node N509.

[0064] The first sampling capacitor CSP1 can be connected between the first node N501 and the second node N502. In addition, the second sampling capacitor CSN1 can be connected between the ninth node N509 and the eleventh node N511.

[0065] The plurality of sampling switches SSP1 and SSN1 can be turned on substantially simultaneously in response to the first sampling signal QS, such that the plurality of sampling capacitors CSP1 and CSN1 sample the plurality of input voltages VIP1 and VIN1 substantially simultaneously. The plurality of sampling switches SSP1 and SSN1 can be turned on to transmit the first input voltage VIP1 to the first node N501 and transmit the second input voltage VIN1 to the ninth node N509. Therefore, the plurality of sampling switches SSP1 and SSN1 can control their connection relationship with the plurality of sensing lines SL in response to the sampling signal QS.

[0066] The differential switch SD1 can have one end connected to the first node N501 and the other end connected to the ninth node N509. The differential switch SD1 can operate in response to the first hold signal QH1.

[0067] The plurality of common-mode switches SCP1 and SCN1 can be connected in series with each other between the second node N502 and the eleventh node N511. For example, the first common-mode switch SCP1 can have one end connected to the second node N502 and the other end connected to the fifth node N505, and the second common-mode switch SCN1 can have one end connected to the fifth node 505 and the other end connected to the eleventh node N511. The first common-mode switch SCP1 and the second common-mode switch SCN1 can connect the common-mode voltage Vref2 to the second node N502 and the eleventh node N511 in response to the second sampling signal QSP.

[0068] The first hold switch SHP1 can have one end connected to the second node N502 and the other end connected to the third node N503. The second hold switch SHN1 can have one end connected to the eleventh node N511 and the other end connected to the thirteenth node N513. The first hold switch SHP1 and the second hold switch SHN1 can be turned on substantially simultaneously in response to the first hold signal QH1. The plurality of hold switches SHP1 and SHN1 can be turned on to transmit the voltage of the second node N502 to the third node N503 and transmit the voltage of the eleventh node N511 to the thirteenth node N513.

[0069] For example, when multiple sampling circuits 5001 activate the first sampling signal QS during a sampling period, multiple sampling switches SSP1, SSN1, ..., SSPn, and SSNn can conduct substantially simultaneously, and multiple sampling capacitors CSP1, CSN1, ..., CSPn, and CSNn can each have one end electrically connected to multiple channels, thereby substantially simultaneously sampling multiple input voltages VIP1, VIN1, ..., VIPn, and VINn received from the multiple channels.

[0070] In addition, when multiple sampling circuits 5001 activate the second sampling signal QSP during a sampling period, multiple common-mode switches SCP1, SCN1, ..., SCPn, and SCNn can conduct substantially simultaneously, and the common-mode voltage Vref2 can be provided to the other end of each of the multiple sampling capacitors CSP1, CSN1, ..., CSPn, and CSNn.

[0071] In some embodiments, the second sampling signal QSP can be activated simultaneously with the first sampling signal QS and deactivated before the first sampling signal QS. For example, multiple common-mode switches SCP1, SCN1, ..., SCPn, and SCNn can be turned off before multiple sampling switches SSP1, SSN1, ..., SSPn, and SSNn, thereby preventing charge injection that may occur when the sampling capacitors CSP1, CSN1, ..., CSPn, and CSNn switch from a sampling operation to a hold operation. During the sampling period, each of the multiple hold signals QH1 to QHn can be at a disabled level.

[0072] When multiple hold signals QH1 to QHn are sequentially activated during a hold period after the sampling period, multiple hold switches SHP1, SHN1, ..., SHPn, and SHNn and multiple differential switches SD1, ..., and SDn can be sequentially activated, and the sampled multiple input voltages VIP1, VIN1, ..., VIPn, and VINn can be sequentially held and scaled.

[0073] When the first hold signal QH1 is activated, the hold switches SHP1 and SHN1 and the differential switch SD1 can conduct, one end of the sampling capacitor CSP1 and one end of the sampling capacitor CSN1 can be electrically connected to each other, and the other ends of the sampling capacitors CSP1 and CSN1 can each be electrically connected to the amplifier 503a.

[0074] The hold / scale circuit 5003 may include a plurality of common-mode switches SW14 and SW24, a plurality of offset capacitors C01 and C02, an amplifier 503a, a plurality of feedback capacitors Cf1 and Cf2, and a plurality of switches SW11, SW12, SW13, SW21, SW22, and SW23.

[0075] The plurality of common-mode switches SW14 and SW24 may be connected in series between a third node N503 and a thirteenth node N513. For example, the first common-mode switch SW14 may have one end connected to the third node N503 and the other end connected to the sixth node N506. The second common-mode switch SW24 may have one end connected to the sixth node N506 and the other end connected to the thirteenth node N513. The first common-mode switch SW14 and the second common-mode switch SW24 may connect the common-mode voltage Vref2 to the third node N503 and the thirteenth node N513 in response to a third sampling signal QSPE. At the same time, the second sampling signal QSP and the third sampling signal QSPE may be the same signal, and the present invention is not limited thereto.

[0076] The plurality of offset capacitors C01 and C02 and the plurality of feedback capacitors Cf1 and Cf2 may be arranged in consideration of the first input voltage VIP1 and the second input voltage VIN1 being input to the first input terminal (+) and the second input terminal (-) of the amplifier 503a as differential signals through the sampling circuit 5001a, respectively. The first offset capacitor C01 may be connected between the third node N503 and the seventh node N507. The second offset capacitor C02 may be connected between the thirteenth node N513 and the fourteenth node N514.

[0077] The amplifier 503a may generate a plurality of output voltages Vop and Von by sequentially receiving a plurality of input voltages VIP1 and VIN1 sampled by the sampling capacitors CSP1 and CSN1. As described above, the amplifier 503a may be excited in different ways. For example, the amplifier 503a may include two input terminals and two output terminals. One of the two input terminals may be selectively connected to a signal line receiving one of the plurality of first input voltages VIP, and the other may be selectively connected to a signal line receiving one of the plurality of second input voltages VIN. In addition, the two output terminals may output the plurality of output voltages Vop and Von in different ways sequentially.

[0078] The first input terminal (+) of the amplifier 503a may be connected to the seventh node N507, and the second input terminal (-) of the amplifier 503a may be connected to the fourteenth node N514.

[0079] The first offset capacitor C01 can store a voltage corresponding to the offset voltage generated at the first input terminal (+) of the amplifier 503a. In addition, the second offset capacitor C02 can store a voltage corresponding to the offset voltage generated at the second input terminal (-) of the amplifier 503a. When the output signal of the sampling circuit 5001a is input to the amplifier 503a, the plurality of offset capacitors C01 and C02 can store the offset voltages at the input terminals of the amplifier 503a. Therefore, the output voltages Vop and Von of the amplifier 503a can be output without being affected by the offset voltages.

[0080] The plurality of feedback capacitors Cf1 and Cf2 can be connected between the input terminal and the output terminal of the amplifier 503a. For example, the feedback capacitor Cf1 can be connected between the first input terminal and the first output terminal of the amplifier 132a, and the feedback capacitor Cf2 can be connected between the second input terminal and the second output terminal of the amplifier 132a. The feedback capacitors Cf1 and Cf2 can be shared by a plurality of channels.

[0081] In some embodiments, the plurality of switches SW11, SW12, SW13, SW21, SW22, and SW23 can be metal oxide semiconductor (MOS) transistors.

[0082] Each of the switches SW12 and SW22 can have one end connected to the output terminal of the amplifier 503a and the other end connected to the input terminal of the amplifier 503a. For example, the switch SW12 can control the transfer of the voltage of the eighth node N508 to the seventh node N507 according to the switch control signal QS2. The switch SW22 can control the transfer of the voltage of the fifteenth node N515 to the fourteenth node N514 according to the switch control signal QS2.

[0083] Each of the switches SW13 and SW23 can have one end connected to the output terminal of the amplifier 503a and the other end connected to one end of each of the feedback capacitors Cf1 and Cf2. For example, the switch SW13 can control the transfer of the voltage of the eighth node N508 to the fourth node N504 (i.e., one end of the feedback capacitor Cf1) according to the switch control signal QS3. The switch SW23 can control the transfer of the voltage of the fifteenth node N515 to the sixteenth node N516 (i.e., one end of the feedback capacitor Cf2) according to the switch control signal QS3.

[0084] Each of switches SW12 and SW22 may have one end connected to the respective input terminals of reference voltages REFB and REFT, and the other end connected to one end of feedback capacitors Cf1 and Cf2 respectively. For example, switch SW11 may control the transmission of reference voltage REFB to the fourth node N504 according to switch control signal QS1. Switch SW21 may control the transmission of reference voltage REFT to the sixteenth node N516 according to switch control signal QS1.

[0085] Switches SW13 and SW23 and switches SW11 and SW21 may be connected in parallel to feedback capacitors Cf1 and Cf2 to each other.

[0086] Amplifier 503a and feedback capacitors Cf1 and Cf2 may generate first output voltage Vop and second output voltage Von by substantially simultaneously scaling and holding the input voltages VIP1 and VIN1 received and sampled from the first channel. For example, feedback capacitors Cf1 and Cf2 may be used by the first channel. Feedback capacitors Cf1 and Cf2 may be reset immediately after the first hold signal QH1 is deactivated.

[0087] In some embodiments, hold / scaling circuit 5003 may perform hold and scale operations on the first input voltage VIP during scaling and holding. When sampling circuit 5001a performs a sampling operation, hold / scaling circuit 5003 may turn on switches SW11, SW12, and SW14 and turn off switch SW13.

[0088] When switch SW12 is turned on, amplifier 503a may act as a unity buffer, and the voltage of the seventh node N507 of amplifier 503a may be completely transmitted to the output terminal. For example, when the seventh node N507 as the input terminal of amplifier 503a and the eighth node N508 as the output terminal are connected to each other, bias capacitor C01 may store the voltage output from the eighth node N508 of amplifier 503a. For example, offset capacitor C01 may store an offset voltage having the same magnitude and opposite sign as the offset voltage generated at the seventh node N507. For example, 1 may be the set amplification ratio of amplifier 503a.

[0089] In addition, when switch SW13 is turned off and switch SW11 is turned on, feedback capacitor Cf1 may be disconnected from the eighth node N508 of amplifier 503a and connected to reference voltage REFB. Therefore, feedback capacitor Cf1 may store reference voltage REFB.

[0090] For example, the offset capacitor C01 can store an offset voltage having the same magnitude and opposite sign as the offset voltage generated at the seventh node N507, i.e., the input terminal (+) of the amplifier 503a.

[0091] The hold / scale circuit 5003 can also perform an operation similar to that performed on the first input voltage VIP on the second input voltage VIN during the scale and hold periods.

[0092] The reference voltage REFB and the reference voltage REFT can be applied differently depending on the configuration of the circuit. When configured as a differential amplifier circuit, the reference voltage REFB and the reference voltage REFT can use the same voltage. For example, the reference voltage REFB and the reference voltage REFT can each have a value of 1 / 2 of the power supply voltage. The reason is to prevent distortion due to signal saturation caused by a low power supply voltage.

[0093] Next, when the amplifier 503a generates an output voltage for sampling the input voltage, the hold / scale circuit 5003 can turn off the switches SW11, SW12, and SW14 and turn on the switch SW13.

[0094] When the switch SW12 is turned off, the seventh node N507 and the eighth node N508 can be disconnected from each other, and the unity buffer function of the amplifier 503a can be released. For example, the amplifier 503a can amplify the signal applied to the seventh node N507 by a predetermined amplification ratio and then output the signal.

[0095] When the switch SW11 is turned off and the switch SW13 is turned on, the feedback capacitor Cf1 can be disconnected from the reference voltage REFB. In addition, the feedback capacitor Cf1 can be connected to the sampling capacitor CSP1 to form a feedback loop.

[0096] The offset voltage stored in the offset capacitor C01 can have the same amount and opposite polarity as the offset voltage Vos1 at the seventh node N507 of the amplifier 503a, and the offset voltage stored in the offset capacitor C01 and the offset voltage at the seventh node N507 can cancel each other out. For example, the amplifier 503a can amplify and output the signal without being affected by the offset voltage generated at the seventh node N507. In addition, the voltage charged in the sampling capacitor CSP1 can be transferred to the feedback capacitor Cf1. Therefore, the first input voltage VIP1 can be amplified and output from the amplifier 503a based on the ratio of the sampling capacitor CSP1 to the feedback capacitor Cf1.

[0097] In some embodiments, the signal input to amplifier 503a can be amplified by the amplification ratio of CSP1 / Cf1 and can be unaffected by the offset voltage. Additionally, the ratio Cs / Cf of the sampling capacitor CSP1 or Cs2 to the feedback capacitor Cf1 or Cf2 can be predetermined.

[0098] Similarly, when the second hold signal QH2 is activated, amplifier 503a and feedback capacitors Cf1 and Cf2 can perform scaling and holding operations on the input voltages VIP2 and VIN2 received and sampled from the second channel substantially simultaneously, thereby generating a first output voltage Vop and a second output voltage Von. In some embodiments, feedback capacitors Cf1 and Cf2 can be used by the second channel. For example, when the i-th hold signal QHi is activated, amplifier 503a and feedback capacitors Cf1 and Cf2 can perform scaling and holding operations on the input voltages VIPn and VINn received and sampled from the i-th channel substantially simultaneously, thereby generating a scaled sensing signal VSENM. For example, feedback capacitors Cf1 and Cf2 can be used by the i-th channel.

[0099] As described above, feedback capacitors Cf1 and Cf2 can be shared by multiple channels so that the feedback capacitors are used sequentially by multiple channels.

[0100] In some embodiments, some sampling circuits 5001a can be implemented to include high-voltage components, and the hold / scaling circuit 5003 can be implemented to include low-voltage components.

[0101] For example, multiple input voltages VIP1 and VIN1 can be relatively high high voltages. Thus, each of the multiple sampling switches SSP1 and SSN1 and the multiple differential switches SD1 included in the sampling circuit 5001a can include high-voltage switch elements that can withstand high voltages (i.e., switch elements that will not be damaged by high voltages). In some embodiments, the high-voltage switch elements can include high-voltage transistors having a relatively high threshold voltage.

[0102] Furthermore, each of the multiple sampling capacitors CSP1 and CSN1 included in the sampling circuit 5001a can also include high-voltage capacitors that can withstand high voltages.

[0103] Some components of the sampling circuit 5001a and the hold / scale circuit 5003 can operate using a relatively low low voltage. A plurality of hold switches SHP1 and SHN1 and a plurality of common-mode switches SCP1 and SCN1 included in the sampling circuit 5001a, and a plurality of switches SW14, SW24, SW12, SW22, SW11, SW21, SW13, and SW23 included in the hold / scale circuit 5003 can include low-voltage switch elements. In some embodiments, the low-voltage switch elements can include low-voltage transistors having a relatively low threshold voltage. In addition, each of the feedback capacitors Cf1 and Cf2 included in the hold / scale circuit 5003 can also include a low-voltage capacitor.

[0104] The following equations represent a first output voltage Vop and a second output voltage Von of a first input voltage VIP input to the AFE 500 (in FIG. 5) based on the above configuration. Similar equations can be applied to the second input voltage VIN.

[0105] <Equation 2>

[0106] For ease of explanation, the sampling circuit 5001a is described with reference to FIG. 5, and each of the plurality of sampling circuits 5001 can include a structure similar to that of the sampling circuit 5001a.

[0107] Although FIG. 5 illustrates that the common-mode voltage Vref2 is input to the fifth node N505 and the sixth node N506, some embodiments are not limited thereto, and the voltage input to the fifth node N505 and the voltage input to the sixth node N506 may be different from each other.

[0108] FIG. 6 is a diagram showing the output of each of a plurality of analog-to-digital converters (ADCs) in an example of a display system including the analog front end of FIG. 5 according to some embodiments. FIG. 6 assumes a case where each of the plurality of ADCs generates a 10-bit data sensing signal DS.

[0109] In FIG. 6, a plurality of hold signals QH, first and second output voltages Vop and Von, and voltages Vop, Von, Vop_2, Von_2, Vop_3, and Von_3 are output when passing through a plurality of stages of the plurality of ADCs 3005 (FIG. 3).

[0110] In some embodiments, the first input voltage VIP may be the same as the second input voltage VIN, or may be greater than the second input voltage VIN by a first value. For example, the first value may range from zero V to 4 V. The sampling circuit 5001 and the hold / scale circuit 5003 may perform voltage scaling to process the voltage difference of the first value using multiple ADCs 3005 (Figure 3). For example, Cf1 = 2CSP1 may be set and the difference between the first reference voltage REFT and the second reference voltage REFB is 1 V. Therefore, the output value of the first input voltage VIP and the second input voltage VIN (i.e., the first output voltage Vop - the second output voltage Von) may be -1 V when the first value is zero, and may be 1 V when the first value is 4 V. These values may fall within the range where the input range of the ADC can be maximally utilized.

[0111] In Figure 6, the active period of sensing the active channel output may be performed after a virtual period that operates outside the operating range of the ADC 3005c multiple times. The first part 601 may be the initial active period, in which the voltage input through CMFB is unstable due to the influence of the virtual period. For example, a voltage outside the operating range of the ADC in the virtual period (e.g., a voltage below -1 V or above 1 V) may be amplified by the amplifier 503a and multiple stages (e.g., the first stage (or stage #1) and the second stage (or stage #2)), and may saturate in the second stage (stage #2). The voltage input through CMFB in the second stage (or stage #2) may become unstable, thereby also changing the outputs Vop_3 and Von_3 in the second stage (or stage #2) as shown in Figure 6. Therefore, multiple ADCs 3005 may not be able to generate accurate data sensing signals DS.

[0112] Figure 7 is a diagram showing an example of an analog front end according to some embodiments. Descriptions overlapping with those provided with reference to Figure 5 are omitted below.

[0113] In Figure 7, the analog front end 700 may include multiple sampling circuits 7001 or 7001a, 7001b,... and 7001n, and a hold / scale circuit 7003.

[0114] The sampling circuit 7001a may include multiple sampling capacitors CSP1 and CSN1, multiple sampling switches SSP1 and SSN1, a differential switch SD1, multiple common-mode switches SCP1 and SCN1, multiple hold switches SHP1 and SHN1, and multiple channel selection switches CSW1 and CSW1'.

[0115] The sampling circuit 7001a may be substantially the same as the sampling circuit 5001a of FIG. 5, except that the sampling circuit 7001a includes a plurality of channel selection switches CSW1 and CSW1'.

[0116] The first channel selection switch CSW1 may have one end connected between the first channel receiving the first input voltage VIP1 and the seventeenth node N717. The first channel selection switch CSW1 may operate in response to a first channel selection signal CHSEL. For example, the first channel selection signal CHSEL may be a signal that controls the connection between a random channel in a plurality of sampling circuits 7001 and the sampling circuit corresponding to the random channel.

[0117] The first channel selection switch CSW1' may have one end connected to the first channel receiving the second input voltage VIN1 and the other end connected between the seventeenth node N717. The first channel selection switch CSW1' may operate in response to an inverted first channel selection signal CHSEL'.

[0118] For example, when a plurality of sampling circuits 7001 activate a first sampling signal QS during a sampling period, a plurality of sampling switches SSP1, SSN1,..., SSPn and SSNn may conduct substantially simultaneously, and a plurality of sampling capacitors CSP1, CSN1,..., CSPn and CSNn may each have one end electrically connected to a plurality of channels, thereby substantially simultaneously sampling a plurality of input voltages VIP1, VIN1,..., VIPn and VINn received from the plurality of channels.

[0119] In addition, when a plurality of sampling circuits 7001 activate a second sampling signal QSP during a sampling period, a plurality of common-mode switches SCP1, SCN1,..., SCPn and SCNn may conduct substantially simultaneously, and a common-mode voltage Vref2 may be provided to the other end of each of the plurality of sampling capacitors CSP1, CSN1,..., CSPn and CSNn.

[0120] In some embodiments, the second sampling signal QSP may be activated simultaneously with the first sampling signal QS and deactivated before the first sampling signal QS. For example, a plurality of common-mode switches SCP1, SCN1,..., SCPn and SCNn may be turned off before a plurality of sampling switches SSP1, SSN1,..., SSPn and SSNn, thereby preventing charge injection that may occur when the sampling capacitors CSP1, CSN1,..., CSPn and CSNn switch from a sampling operation to a holding operation.

[0121] When multiple hold signals QH1 to QHn are sequentially activated during the hold period after the sampling period, multiple hold switches SHP1, SHN1, ..., SHPn and SHNn and multiple differential switches SD1, ..., and SDn can be sequentially activated, and the sampled multiple input voltages VIP1, VIN1, ..., VIPn and VINn can be sequentially held and scaled.

[0122] When the first hold signal QH1 is activated, the hold switches SHP1 and SHN1 and the differential switch SD1 can be turned on, one end of the sampling capacitor CSP1 and one end of the sampling capacitor CSN1 can be electrically connected to each other, and the other ends of the sampling capacitors CSP1 and CSN1 can be electrically connected to the amplifier 703a respectively.

[0123] The hold / scaling circuit 7003 can include multiple common-mode switches SW14 and SW24, multiple offset capacitors C01 and C02, an amplifier 703a, multiple feedback capacitors Cf1 and Cf2, and multiple switches SW11, SW12, SW13, SW21, SW22 and SW23. The hold / scaling circuit 7003 can be substantially the same as the hold / scaling circuit 5003 in FIG. 5.

[0124] In the case of the active channel, the sampling circuit 7001a can turn off the first channel selection switch CSW1 through the disabled-level first channel selection signal CHSEL, and at the same time turn on the first channel selection switch CSW1' through the inverted first channel selection signal CHSEL'. Therefore, the operation of the AFE 700 may be substantially similar to the operation of the AFE 500 in FIG. 5.

[0125] However, in the case of the virtual channel, the sampling circuit 7001a can turn on the first channel selection switch CSW1 through the first channel selection signal CHSEL of the enable level, and at the same time turn off the first channel selection switch CSW1' through the inverted first channel selection signal CHSEL'. Therefore, the first input voltage VIP1 can be transmitted to the seventeenth node N717. For example, a voltage identical to the first input voltage VIP1 can be input as the second input voltage VIN1. Therefore, referring to Equation 2, the output value (i.e., the first output voltage Vop - the second output voltage Von) can be expressed as the difference between the first reference voltage REFT and the second reference voltage REFB. For example, when the first reference voltage REFT - the second reference voltage REFB = 1 V, the output value can be -1 V. The operation range of the analog-to-digital converter can be from -1 V to 1 V, and the sensing block 303 (FIG. 1) can generate data corresponding to zero gray level. However, the sensing block 303 (FIG. 1) can generate data corresponding to the threshold value (-1 V) of the operation range of the analog-to-digital converter. Therefore, if there is a slight error, the data may be outside the operation range of the analog-to-digital converter. For example, if an error occurs between the ratios of the sampling capacitors CSP1 and CSN1 to the feedback capacitors Cf1 and Cf2 and a predetermined value, the data may be outside the operation range of the analog-to-digital converter.

[0126] For ease of explanation, the sampling circuit 7001a is described with reference to FIG. 7, and each of the plurality of sampling circuits 7001 may include a structure similar to that of the sampling circuit 7001a.

[0127] FIG. 8 is a diagram showing the outputs of each of a plurality of ADCs in an example of a display system including the analog front end of FIG. 7 according to some embodiments. FIG. 8 assumes a case where each of the plurality of analog-to-digital converters generates a 10-bit data sensing signal DS.

[0128] In FIG. 8, the first output voltages Vop_2 and Vop_3, the second output voltages Von_2 and Von_3, the CMFB voltage, and the data sensing signal DS are output when passing through the first output voltage Vop, the second output voltage Von, and multiple stages of the plurality of analog-to-digital converters 3005 (FIG. 3).

[0129] In some embodiments, the first input voltage VIP may be the same as the second input voltage VIN, or may have a value that is greater than the second input voltage VIN by a first value. For example, the first value may be 4 V. Thus, the sampling circuit 7001 and the hold / scale circuit 7003 may perform voltage scaling to process a voltage difference of 4 V using the plurality of analog-to-digital converters 3005 (FIG. 3). For example, Cf1 may be set to 2Cs and the difference between the first reference voltage REFT and the second reference voltage REFB may be 1 V. Thus, the output value of the first input voltage VIP and the second input voltage VIN (i.e., the first output voltage Vop - the second output voltage Von) may range from -1 V to 1 V. These values may fall within a range where the input range of the analog-to-digital converter can be utilized to the maximum extent.

[0130] The sensing block 303 (FIG. 1) may generate data corresponding to zero gray level. The active period of the output of the sensing active channel may occur after the virtual period. As described above, the input voltages VIP and VIN may be amplified by the amplifier 703a and the plurality of analog-to-digital converters 3005 (FIG. 3). Thus, the first output voltage Vop_3 and the second output voltage Von_3 may saturate, thereby changing the CMFB voltage of the amplifier (AMP) in the second stage (or stage #2) analog-to-digital converter 3005b. For example, as shown in the first part 801 of FIG. 8, the voltage input to the AMP through the CMFB in the second stage analog-to-digital converter 3005b may change.

[0131] When the CMFB of the second stage is unstable during the virtual period, the CMFB may require at least one clock to return to the stable state. Thus, the analog-to-digital converter 3005b may be affected by the unstable CMFB during the initial active period. The unstable CMFB in the virtual period may cause an error in the code of the initial active period. For example, as shown in FIG. 8, a code error may occur in the second period 803. The unstable CMFB occurring in the virtual channel may affect the code value of the active channel.

[0132] FIG. 9 is a diagram showing an example of an analog front end according to some embodiments. Descriptions overlapping those provided with reference to FIG. 5 are omitted below.

[0133] In FIG. 9, the analog front end 900 may include a plurality of sampling circuits 9001 or 9001a, 9001b,... and 9001n and a hold / scale circuit 9003.

[0134] The sampling circuit 9001a may include a plurality of sampling capacitors CSP1 and CSN1, a plurality of sampling switches SSP1 and SSN1, a differential switch SD1, a plurality of common-mode switches SCP1 and SCN1, and a plurality of hold switches SHP1 and SHN1.

[0135] The plurality of sampling switches SSP1 and SSN1 may be substantially simultaneously turned on in response to a first sampling signal QS and a channel selection signal CHSELb. The plurality of sampling switches SSP1 and SSN1 may be turned on to transmit a first input voltage VIP1 to a first node N501 and a second input voltage VIN1 to a ninth node N509.

[0136] The differential switch SD1 may have one end connected to the first node N501 and the other end connected to the ninth node N509. The differential switch SD1 may operate in response to a first hold signal QH1 or a channel selection signal CHSEL. The channel selection signal CHSEL may be a signal indicating whether the channel connected to the sampling circuit 9001a is a virtual channel or an active channel. The channel selection signal CHSELb may be an inverted signal of the channel selection signal CHSEL. When the channel selection signal CHSEL indicates a virtual channel, that is, when the value of the inverted channel selection signal CHSELb is zero, the plurality of sampling switches SSP1 and SSN1 may be turned off regardless of whether the first sampling signal QS is activated. When the channel selection signal CHSEL indicates a virtual channel or when the first hold signal QH1 is activated, the differential switch SD1 may be turned on.

[0137] For example, when the plurality of sampling circuits 9001 activate the first sampling signal QS during a sampling period, the plurality of sampling switches SSP1, SSN1,..., SSPn and SSNn may be substantially simultaneously turned on, and each of the plurality of sampling capacitors CSP1, CSN1,..., CSPn and CSNn may have one end electrically connected to the plurality of channels, thereby substantially simultaneously sampling the plurality of input voltages VIP1, VIN1,..., VIPn and VINn received from the plurality of channels.

[0138] In addition, when the plurality of sampling circuits 9001 activate a second sampling signal QSP during a sampling period, the plurality of common-mode switches SCP1, SCN1,..., SCPn and SCNn may be substantially simultaneously turned on, and a common-mode voltage Vref2 may be provided to the other ends of the plurality of sampling capacitors CSP1, CSN1,..., CSPn and CSNn.

[0139] In some embodiments, the second sampling signal QSP may be activated simultaneously with the first sampling signal QS and deactivated before the first sampling signal QS. For example, a plurality of common-mode switches SCP1, SCN1, ..., SCPn, and SCNn may be turned off before a plurality of sampling switches SSP1, SSN1, ..., SSPn, and SSNn, thereby preventing charge injection that may occur when the sampling capacitors CSP1, CSN1, ..., CSPn, and CSNn switch from the sampling operation to the hold operation. During the sampling period, a plurality of hold signals QH1 to QHn may be at a disabled level.

[0140] When a plurality of hold signals QH1 to QHn are sequentially activated during the hold period after the sampling period, a plurality of hold switches SHP1, SHN1, ..., SHPn, and SHNn, and a plurality of differential switches SD1, ..., and SDn may be sequentially activated, and a plurality of sampled input voltages VIP1, VIN1, ..., VIPn, and VINn may be sequentially held and scaled.

[0141] When the first hold signal QH1 is activated, the hold switches SHP1 and SHN1 and the differential switch SD1 may be turned on, one end of the sampling capacitor CSP1 and one end of the sampling capacitor CSN1 may be electrically connected to each other, and the respective other ends of the sampling capacitors CSP1 and CSN1 may be electrically connected to the amplifier 903a.

[0142] The hold / scale circuit 9003 may include a plurality of common-mode switches SW14 and SW24, a plurality of offset capacitors C01 and C02, an amplifier 903a, a plurality of feedback capacitors Cf1 and Cf2, a plurality of switches SW11, SW12, SW13, SW21, SW22, and SW23, and a plurality of virtual channel switches SW1_DUM1 and SW2_DUM1.

[0143] The hold / scale circuit 9003 may be substantially the same as the hold / scale circuit 5003 of FIG. 5, except that the hold / scale circuit 9003 includes a plurality of virtual channel switches SW1_DUM1 and SW2_DUM1, and the switches SW12 and SW22 are controlled by an active control signal ASW1.

[0144] The first virtual channel switch SW1_DUM1 may have one end connected to the input terminal of the common-mode voltage Vref2 and the other end connected to the fourth node N904. The first virtual channel switch SW1_DUM1 may operate in response to a virtual selection signal DSW1.

[0145] One end of the second virtual channel switch SW2_DUM1 may be connected to the input terminal of the common mode voltage Vref2, and the other end may be connected to the sixteenth node N916. The second virtual channel switch SW2_DUM1 may operate in response to the virtual selection signal DSW1.

[0146] Although FIG. 9 shows that one end of the first virtual channel switch SW1_DUM1 and one end of the second virtual channel switch SW2_DUM1 are connected to the input terminal of the common mode voltage Vref2, some embodiments are not limited thereto. The first virtual channel switch SW1_DUM1 and the second virtual channel switch SW2_DUM1 may be connected to any input terminal for receiving the same voltage.

[0147] Respective ends of the switches SW12 and SW22 may be connected to the input terminals of the reference voltages REFB and REFT respectively, and the other ends may be connected to respective ends of the feedback capacitors Cf1 and Cf2. For example, the switch SW11 may control the transmission of the reference voltage REFB to the fourth node N904 based on the active selection signal ASW1. The switch SW21 may control the transmission of the reference voltage REFT to the sixteenth node N916 based on the active selection signal ASW1.

[0148] The hold / scale circuit 9003 may perform hold and scale operations on the first input voltage VIP during the scale and hold periods. For example, the hold / scale circuit 9003 may turn on the switches SW11 and SW12 and turn off the switches SW12 and SW14.

[0149] When the switch SW12 is turned on, the amplifier 903a may act as a unity buffer, and the voltage of the seventh node N907 of the amplifier 903a may be completely transmitted to the output terminal. For example, when the seventh node N907 serving as the input terminal of the amplifier 903a and the eighth node N908 serving as the output terminal are connected to each other, the offset capacitor C01 may store the voltage output from the eighth node N908 of the amplifier 903a. Therefore, the offset capacitor C01 may store an offset voltage having the same magnitude and opposite sign as the offset voltage generated at the seventh node N907. Here, 1 may be the set amplification ratio of the amplifier 903a.

[0150] In addition, when the switch SW13 is turned off and the switch SW11 is turned on, the feedback capacitor Cf1 may be disconnected from the eighth node N908 of the amplifier 903a and connected to the reference voltage REFB. Therefore, the feedback capacitor Cf1 may store the reference voltage REFB.

[0151] For example, the offset capacitor C01 can store an offset voltage having the same magnitude and opposite sign as the offset voltage generated at the seventh node N907, i.e., the input terminal (+) of the amplifier 903a.

[0152] The hold / scale circuit 9003 can also perform operations similar to those performed on the first input voltage VIP on the second input voltage VIN during the scale and hold periods.

[0153] Next, the hold / scale circuit 9003 can disconnect the switches SW11, SW12, and SW14 and connect the switch SW13 during the scale and hold periods.

[0154] When the switch SW12 is disconnected, the seventh node N907 and the eighth node N908 can be disconnected from each other, and the unity buffer function of the amplifier 903a can be released. For example, the amplifier 903a can amplify the signal applied to the seventh node N907 by a predetermined amplification ratio and then output it.

[0155] When the switch SW11 is disconnected and the switch SW13 is connected, the feedback capacitor Cf1 can be disconnected from the reference voltage REFB. In addition, the feedback capacitor Cf1 can be connected to the sampling capacitor CSP1 to form a feedback loop.

[0156] The offset voltage stored in the offset capacitor C01 can have the same magnitude and opposite polarity as the offset voltage Vos1 at the seventh node N907 of the amplifier 903a, and the offset voltage stored in the offset capacitor C01 and the offset voltage at the seventh node N507 can cancel each other out. For example, the amplifier 903a can amplify and output the signal without being affected by the offset voltage generated at the seventh node N907. In addition, the voltage charged in the sampling capacitor CSP1 can be transferred to the feedback capacitor Cf1. Therefore, the first input voltage VIP1 can be amplified and output from the amplifier 903a based on the ratio of the sampling capacitor CSP1 to the feedback capacitor Cf1.

[0157] The signal input to the amplifier 903a can be amplified by the amplification ratio of CSP1 / Cf1 and can be unaffected by the offset voltage. In addition, the ratio Cs / Cf of the sampling capacitor CSP1 or Cs2 to the feedback capacitor Cf1 or Cf2 can be predetermined.

[0158] This description together with FIG. 10 illustrates a method of operating the AFE 900 shown in FIG. 9.

[0159] FIG. 10 is a timing diagram showing an example of signals for controlling switches in the AFE in FIG. 9 according to some embodiments. FIG. 10 shows a clock signal ADC_CLK, a first sampling signal QS, a second sampling signal QSP, a third sampling signal QSPE, a switch control signal QS3, a virtual selection signal DSW1, an active selection signal ASW1, and a plurality of hold signals QH1_DUM1, QH1_DUM2, QH1_ACT1, and QH1_ACT2, which operate the ADC 3005 (FIG. 3). The first sampling signal QS, the second sampling signal QSP, the third sampling signal QSPE, the switch control signal QS3, the virtual selection signal DSW1, the active selection signal ASW1, and the plurality of hold signals QH1_DUM1, QH1_DUM2, QH1_ACT1, and QH1_ACT2 can be generated based on the clock signal ADC_CLK.

[0160] In FIG. 10, the operation of the AFE 900 can be divided into operations in a sampling period Ts, a plurality of reset periods Tr1, Tr2, Tr3, and Tr4, and a plurality of hold periods Th1, Th2, Th3, and Th4. The plurality of reset periods Tr1, Tr2, Tr3, and Tr4 and the plurality of hold periods Th1, Th2, Th3, and Th4 can alternate. The sampling period Ts can be a period for sampling each of the plurality of sensing signals of a plurality of channels. Each of the reset periods Tr1, Tr2, Tr3, and Tr4 can be a period for resetting the value stored in the hold / scale circuit 9003 to accurately read the value sampled from the sensing signal. Each of the hold periods Th1, Th2, Th3, and Th4 can be a period for scaling and holding the value transmitted from the sampling circuit 9001. The AFE 900 can measure each charge of the sensing signals stored in the sampling capacitors CSP1 and CSN1 respectively connected to the plurality of channels by alternately performing the reset periods Tr1, Tr2, Tr3, and Tr4 and the hold periods Th1, Th2, Th3, and Th4 for each of the plurality of channels.

[0161] For ease of explanation, FIG. 10 assumes two virtual channels and two active channels. For example, a first virtual channel DUM1, a second virtual channel DUM2, a first active channel ACT1, and a second active channel ACT2 can be sequentially connected to the hold / scale circuit 9003. The reset period Tr1 or Tr2 and the hold period Th1 or Th2 can be the reset period and the hold period of the virtual channel. In addition, the reset period Tr3 or Tr4 and the hold period Th3 or Th4 can be the reset period and the hold period of the active channel.

[0162] At time point t101, the second sampling signal QSP can transition from a high level to a low level.

[0163] From time point t101 to time point t103, the first sampling signal QS, the third sampling signal QSPE, the switch control signal QS3, the virtual selection signal DSW1, the active selection signal ASW1, and multiple hold signals QH1_DUM1, QH1_DUM2, QH1_ACT1, and QH1_ACT2 can be at a low level.

[0164] At time point t103, the first sampling signal QS transitions to a high level.

[0165] Time points t103 to t105 can belong to the sampling period Ts. During the sampling period Ts, charges can be stored in the sampling capacitors CSP1 or CSN1 through the sensing signals of each of the multiple channels.

[0166] During the sampling period Ts, the first sampling signal QS can be at a high level, and the second sampling signal QSP, the third sampling signal QSPE, the switch control signal QS3, the virtual selection signal DSW1, the active selection signal ASW1, and multiple hold signals QH1_DUM1, QH1_DUM2, QH1_ACT1, and QH1_ACT2 can be maintained at a low level.

[0167] After the sampling period Ts, the reset periods and the hold periods can be arranged alternately.

[0168] During multiple reset periods Tr1, Tr2, Tr3, and Tr4 and multiple hold periods Th1, Th2, Th3, and Th4, the first sampling signal QS can be maintained at a low level, while the second sampling signal QSP can be maintained at a high level. In addition, during each of the multiple hold periods Th1, Th2, Th3, and Th4, the hold signal corresponding to each channel can be maintained at a high level. For example, during the hold period Th1 of the first virtual channel DUM1, the hold signal QH1_DUM1 can be at a high level; during the hold period Th2 of the second virtual channel DUM2, the hold signal QH1_DUM2 can be at a high level; during the hold period Th3 of the first active channel ACT1, the hold signal QH1_ACT1 can be at a high level; during the hold period Th4 of the second active channel ACT2, the hold signal QH1_ACT2 can be at a high level.

[0169] At time point t107, the first sampling signal QS can transition from a high level to a low level, while the third sampling signal QSPE and the virtual selection signal DSW1 can transition from a low level to a high level.

[0170] The time points t107 to t109 can belong to the reset period Tr1 of the first virtual channel DUM1.

[0171] During the time points t107 to t109, the third sampling signal QSPE and the virtual selection signal DSW1 can be at a high level, while the switch control signal QS3 and the active selection signal ASW1 can be at a low level.

[0172] At time point t109, the third sampling signal QSPE and the virtual selection signal DSW1 can transition from a high level to a low level. The switch control signal QS3 and the hold signal QH1_DUM1 corresponding to the first virtual channel DUM1 can transition from a low level to a high level.

[0173] The time points t109 to t111 can belong to the hold period Th1 of the first virtual channel DUM1.

[0174] During the time points t109 to t111, the third sampling signal QSPE, the virtual selection signal DSW1, and the active selection signal ASW1 can be at a low level. In addition, the switch control signal QS3 can be at a high level, and the hold signal QH1_DUM1 can be at a high level.

[0175] From time point t111 to time point t113, the reset period Tr2 and the hold period Th2 of the second virtual channel DUM2 can be carried out. The reset period Tr2 can be similar to the reset period Tr1, and the hold period Th2 can be similar to the hold period Th1.

[0176] At time point t113, the third sampling signal QSPE and the active selection signal ASW1 can transition from a low level to a high level. The switch control signal QS3 can transition from a high level to a low level.

[0177] The time points t113 to t115 can belong to the reset period Tr3 of the first active channel ACT1.

[0178] During the time points from t113 to t115, the third sampling signal QSPE and the active selection signal ASW1 can be at a high level, and the switch control signal QS3 and the virtual selection signal DSW1 can be at a low level.

[0179] At time point t115, the third sampling signal QSPE and the active selection signal ASW1 can change from a high level to a low level. The switch control signal QS3 and the hold signal QH1_ACT1 corresponding to the first active channel ACT1 can change from a low level to a high level.

[0180] The time points from t115 to t117 can belong to the hold period Th3 of the first active channel ACT1.

[0181] During the time points from t115 to t117, the third sampling signal QSPE, the virtual selection signal DSW1 and the active selection signal ASW1 can be at a low level, and the switch control signal QS3 and the hold signal QH1_ACT1 can be at a high level.

[0182] In summary, the virtual selection signal DSW1 can maintain a high level during the reset period of the virtual channel, so that the common-mode voltage Vref2 of the same voltage can be input to the node N904 and the node N916.

[0183] During the hold periods Th1 and Th2 of the virtual channel, the above equation 2 can be expressed as equation 3.

[0184] <Equation 3>

[0185] In addition, the active selection signal ASW1 can maintain a high level during the reset period of the active channel. Therefore, the reference voltage REFB can be input to the node N904 and the reference voltage REFT can be input to the node N916. During the hold periods Th3 and Th4 of the active channel, the above equation 2 can be expressed as equation 4.

[0186] As described above, the first input voltage VIP can be the same as the second input voltage VIN, or can have a value that is larger than the second input voltage VIN by a first value. For example, the first value can range from 0 V to 4 V. It can be set that Cf1 = 2CSP1 and the difference between the first reference voltage REFT and the second reference voltage REFB is 1 V.

[0187] <Equation 4>

[0188] As shown in Equation 4, the output value for the first input voltage VIP and the second input voltage VIN (i.e., the first output voltage Vop minus the second output voltage Von) can be -1 V when the first value is zero and 1 V when the first value is 4 V. These values can fall within the range where the input range of the analog-to-digital converter can be maximally utilized.

[0189] As a result, when sensing the virtual channel, both the first output voltage Vop and the second output voltage Von may have a value of zero V. Thus, the sensing block 303 (FIG. 1) can generate data corresponding to the middle gray scale (here, the operating range of the analog-to-digital converter can be from -1 to 1). Thus, by sensing the virtual channel, the output voltage may not exceed the operating range of the analog-to-digital converter and may not even affect the subsequent sensing of the active channel output.

[0190] FIG. 11 is a diagram showing the output of each of multiple ADCs in an example of a display system including the analog front end of FIG. 9 according to some embodiments. FIG. 11 assumes a case where each of the multiple ADCs generates a 10-bit data sensing signal DS.

[0191] In FIG. 11, the first output voltages Vop and Vop_3, the second output voltages Von_2 and Von_3, the CMFB voltage, and the data sensing signal DS are output while passing through the first output voltage Vop, the second output voltage Von, and multiple stages of the multiple ADCs 3005 (FIG. 3).

[0192] In some embodiments, the first input voltage VIP can be the same as the second input voltage VIN or can have a value that is a first value greater than the second input voltage VIN. For example, the first value can be 4 V. For example, the sampling circuit 9001 and the hold / scale circuit 9003 can perform voltage scaling to process a voltage difference of 4 V using the multiple ADCs 3005 (FIG. 3). For example, Cf1 can be set to 2Cs and the difference between the first reference voltage REFT and the second reference voltage REFB can be 1 V. For example, the output value for the first input voltage VIP and the second input voltage VIN (i.e., the first output voltage Vop minus the second output voltage Von) can range from -1 V to 1 V. These values can fall within the range where the input range of the analog-to-digital converter can be maximally utilized.

[0193] The sensing block 303 (FIG. 1) can generate data corresponding to zero gray scale. The active period of the output of the sensing active channel can be after the virtual period. As described above, the input voltages VIP and VIN can be amplified by the amplifier 903a and the plurality of ADCs 3005 (FIG. 3). Therefore, the first output voltage Vop_3 and the second output voltage Von_3 may saturate, thereby changing the CMFB voltage of the amplifier (AMP) in the ADC 3005b in the second stage (or stage #2). However, during the hold period of the virtual channel, the same common-mode voltage Vref2 can be input to the input of the AMP, so as shown in the first part 1101 of FIG. 11, the voltage input to the AMP is not changed by the CMFB of the ADC 3005b in the second stage (or stage #2). Therefore, no code error may occur due to the source output measurement of the virtual channel, and the virtual channel sensing may not affect the output value of the active channel. In addition, the display driving circuit including the source block with the AFE 900 can sense the channel data without error and accurately correct the image data based on this.

[0194] FIG. 12 is a block diagram showing an example of an electronic system according to some embodiments. In FIG. 12, the electronic system 1200 may include a processor 1210, a memory device 1220, a communication link 1230, an input / output device 1240, a power supply device 1250, and a display device 1260. The electronic system 1200 may further include several ports that can communicate with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc. or other systems.

[0195] The processor 1210 can control the overall operation of the electronic system 1200 and execute an operating system, application programs, etc. The memory device 1220 can store data required to operate the electronic system 1200. The communication link 1230 can perform communication with external devices. The input / output device 1240 may include input devices such as a keyboard, a numeric keypad, a touchpad, a touch screen, a mouse, and a remote controller, etc., and output devices such as a speaker or a printer. The power supply device 1250 can supply the power required to operate the electronic system 1200. The display device 1260 may include a display panel and a display driving integrated circuit, and may be a display device according to some embodiments.

[0196] The display driving integrated circuit may be a display driving integrated circuit according to some embodiments. The display device 1260 may include sensing circuitry 1261 for detecting a plurality of pixel characteristics. The sensing circuitry 1261 may include a sampling circuit connected to a plurality of channels in the display panel, a hold / scale circuit connected to the sampling circuit, and a plurality of analog-to-digital converters connected to the hold / scale circuit to generate data signals. The display device 1260 may compensate the image data displayed on the display panel based on the data signals. The sensing circuitry 1261 may control a plurality of switches in the sampling circuit and perform control when the sampling circuit is connected to a virtual channel, such that the input voltage received from the channel and a reference voltage as a reference have the same value. In addition, the sensing circuitry 1261 may control the hold / scale circuit such that when a sampled signal is transmitted from the sampling circuit connected to the virtual channel, the same voltage is input to the input terminal of the amplifier in the hold / scale circuit. For example, the amplifier may operate in a differential manner. Accordingly, a zero-volt voltage may be input to the plurality of analog-to-digital converters, and this value may not be outside the operating range of each of the plurality of analog-to-digital converters.

[0197] Although the present invention includes many specific implementation details, these should not be construed as limitations on the claimed scope. Certain features described in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although the above features may be described as acting in certain combinations, in some cases, one or more features may be excluded from the combination, and the combination may be directed to a sub-combination or a variant of the sub-combination.

[0198] 10: Display system 20: Host processor 25: Organic light-emitting diode 30: Display driving circuit 31: Timing controller 33: Data driver 35: Gate driver 40: Display panel 132a, 503a, 703a, 903a: Amplifier 301: Driving block 303: Sensing block 500, 700, 900, 3007: Analog front end 803: Second period 1101, 601, 801: First part 1200: Electronic system 1210: Processor 1220: Memory device 1230: Communication link 1240: Input / output device 1250: Power supply device 1260: Display device 1261: Sensing circuit 3001, 3001a, 3001b - 3001n, 5001, 5001a, 5001b - 5001n, 7001, 7,001a, 7001b, 7001n, 9001, 9001a, 9001b, 9001n: Sampling circuit 3003, 5003, 7003, 9003: Hold / scale circuit 3005, 3005a, 3005b, 3005c: Analog - to - digital converter ACT1: First active channel ACT2: Second active channel ADC_CLK: Clock signal ASW1: Active control signal C01, C02: Offset capacitor CHSEL, CHSELb: Channel selection signal CHSEL': Inverted first channel selection signal Cli: Line capacitor CSP1, CSN1, CSPn, CSNn: First sampling capacitor CSW1, CSW1': Channel selection switch Cf1, Cf2: Feedback capacitor Cst: Storage capacitor DL: Data line DS: Data sensing signal DSW1: Virtual selection signal DT: Drive transistor DUM1: First virtual channel DUM2: Second virtual channel D_CTRL: Data control signal ELVDD: First drive voltage ELVSS: Second drive voltage GL: Gate line GL1: First gate line GL2: Second gate line G_CTRL: Gate control signal IDT: Drive Current N1: Gate Node N2: Source Node N501: First Node N502: Second Node N503: Third Node N504, N904: Fourth Node N505: Fifth Node N506: Sixth Node N507, N907: Seventh Node N508, N908: Eighth Node N509: Ninth Node N511: Eleventh Node N513: Thirteenth Node N514: Fourteenth Node N515: Fifteenth Node N516, N916: Sixteenth Node N717: Seventeenth Node PX: Pixel QH1 - QHn, QH1_ACT1, QH1_ACT2, QH1_DUM1, QH1_DUM2: Hold Signal QS: First Sampling Signal QS1, QS2, QS3: Switch Control Signal QSP: Second Sampling Signal QSPE: Third Sampling Signal REFB, REFT: Reference Voltage SCN1, SCP1, SCNn, SCPn, SW14, SW24: Common - Mode Switch SD1, SDn: Differential Switch SHN1, SHP1: Hold Switch SL, SL1 - SLn: Sense Line SSN1, SSP1, SSPn, SSNn: Sampling Switch SST: Sense Transistor SW1_DUM1, SW2_DUM1: Virtual Channel Switch SW11, SW12, SW13, SW14, SW21, SW22, SW23, SW24: Switch SWT: Switch Transistor Th1, Th2, Th3, Th4: Hold Period Tr1, Tr2, Tr3, Tr4: Reset Period Tr1, Tr2, Tr3: Reset Period Ts: Sampling Period Vd: Data Voltage Vgs: Drive Voltage VIN, VIN1, VIN2, VIP, VIP1, VIP2, VIPn, VINn: Input Voltage Vint: Initialization Voltage VIPi, Vop, Von, Vop_2, Von_2, Vop_3, Von_3: Output Voltage Vos1: Offset Voltage Vps: Pixel Voltage Vref2: Common-Mode Voltage Vsc: Scan Voltage Vso: Sense Conduction Voltage Vth: Threshold Voltage t101, t103, t107, t109, t111, t113, t115: Time Points

Claims

1. A display device, comprising: Multiple channels, wherein the multiple channels include at least one virtual channel; A plurality of first sampling circuits, each configured to sample one of a plurality of virtual voltages corresponding to each of the at least one virtual channel, wherein each of the plurality of virtual voltages includes a corresponding floating virtual voltage different from the pixel voltage; and a hold / scaling circuit, including a first input node, a second input node, a first output node, a second output node, a first feedback capacitor connected between the first input node and the first output node, and a second feedback capacitor connected between the second input node and the second output node, wherein the hold / scaling circuit is configured to: store voltages of substantially the same magnitude in the first feedback capacitor and the second feedback capacitor, receive the plurality of sampled virtual voltages from the first input node and the second input node, and output a plurality of virtual output voltages obtained by amplifying the plurality of sampled virtual voltages to the first output node and the second output node.

2. The display device of claim 1, wherein the plurality of channels includes at least one active channel, wherein the device further includes a plurality of second sampling circuits, each configured to sample an active voltage corresponding to the at least one active channel, wherein the first feedback capacitor and the second feedback capacitor are configured to store voltages of different magnitudes, and wherein the hold / scaling circuit is configured to receive the sampled active voltage from the first input node and the second input node, and output a plurality of active output voltages obtained by amplifying the sampled active voltage to the first output node and the second output node.

3. The display device as claimed in claim 2, wherein the holding / scaling circuit comprises: A differential amplifier includes a first input terminal, a second input terminal, a first output terminal connected to the first output node, and a second output terminal connected to the second output node; Multiple offset capacitors are respectively connected to the first input terminal and the second input terminal, and are configured to store the offset voltage of the first input terminal and the second input terminal; A first switch has a first end connected to the first output node and a second end connected to the first feedback capacitor; And a second switch having a first end connected to the second output node and a second end connected to the second feedback capacitor.

4. The display device as claimed in claim 3, wherein the hold / scaling circuit further comprises: The third switch has a first end connected to the second end of the first switch, and a second end connected to the input end configured to receive a predetermined first voltage; And a fourth switch having a first end connected to the second end of the second switch, and a second end connected to the input end configured to receive the predetermined first voltage.

5. The display device as claimed in claim 4, wherein the hold / scaling circuit further comprises: A fifth switch has a first terminal connected to the second terminal of the first switch and a second terminal connected to the input terminal configured to receive a first reference voltage; a sixth switch has a first terminal connected to the second terminal of the second switch and a second terminal connected to the input terminal configured to receive a second reference voltage different from the first reference voltage; a seventh switch is connected between the first input terminal and the first output terminal of the differential amplifier. And an eighth switch, connected between the second input terminal and the second output terminal of the differential amplifier.

6. The display device as claimed in claim 5, wherein when the first sampling circuit samples the plurality of virtual voltages, the third switch, the fourth switch, the seventh switch, and the eighth switch are turned on, while the first switch and the second switch are turned off.

7. The display device as claimed in claim 5, wherein when the hold / scaling circuit outputs the plurality of virtual output voltages to the first output node and the second output node, the first switch and the second switch are turned on, while the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the eighth switch are turned off.

8. The display device as claimed in claim 2, wherein each of the plurality of first sampling circuits and the plurality of second sampling circuits comprises: A plurality of sampling capacitors are connected to a first channel of the plurality of channels, each of the plurality of sampling capacitors being configured to sample a plurality of first active voltages or a plurality of first virtual voltages; a plurality of sampling switches are disposed between the plurality of channels and the plurality of sampling capacitors, each of the plurality of sampling switches being configured to operate based on an inverting channel selection signal; And a differential switch, connected between the plurality of sampling switches and the plurality of sampling capacitors, the differential switch being configured to operate based on a channel selection signal.

9. The display device of claim 8, wherein during the period of sampling the plurality of virtual voltages and the plurality of active voltages, the plurality of sampling switches are turned on, and a corresponding virtual voltage of the plurality of virtual voltages and a corresponding active voltage of the plurality of active voltages are respectively stored in the plurality of sampling capacitors.

10. The display device of claim 9, wherein each of the plurality of first sampling circuits and the plurality of second sampling circuits further comprises: Multiple hold switches are disposed between the multiple sampling capacitors and the first input node, and between the multiple sampling capacitors and the second input node, and are configured to operate in response to a corresponding hold signal among multiple hold signals.

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