Semiconductor device and method of fabrication thereof

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; an isolation region disposed on the substrate and adjacent to the base structure; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion; a gate structure; and a gate spacer disposed along a sidewall of the gate structure and between the gate structure and the isolation region. The gate structure includes an outer gate portion and an inner gate portion, the outer gate portion having a tapered cross-sectional profile and being disposed on the isolation region, and the inner gate portion having a non-tapered cross-sectional profile and being disposed on the nanostructure channel region.

Description

Technical Field

[0001] This disclosure relates to the outline of a gate structure in a semiconductor device. Prior Technology

[0002] With the development of semiconductor technology, the demand for larger storage capacity, faster processing systems, higher efficiency, and lower costs is growing. To meet these demands, the semiconductor industry is constantly shrinking the size of semiconductor devices (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)), including planar MOSFETs, fin field-effect transistors (finFETs), and all-gate field-effect transistors (GAA FETs). This shrinking size increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] Some embodiments disclosed herein provide a semiconductor device comprising: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; an isolation region disposed on the substrate and adjacent to the base structure; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion; a gate structure comprising: an outer gate portion having a tapered cross-sectional profile and disposed on the isolation region; and an inner gate portion having a non-tapered cross-sectional profile and disposed on the nanostructure channel region; and a gate spacer disposed along a plurality of sidewalls of the gate structure and between the gate structure and the isolation region.

[0004] Other embodiments disclosed herein provide a semiconductor device comprising: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; a shallow channel isolation (STI) region disposed on the substrate; a nanostructured channel region disposed on the first base portion; a source / drain region disposed on the second base portion; and a gate structure comprising: a top gate portion disposed on the nanostructured channel region; and a bottom gate portion comprising: a first gate portion having a rectangular cross-sectional profile disposed on the first base portion; and a second gate portion having a tapered cross-sectional profile disposed on the first base portion.

[0005] Further embodiments of this disclosure provide a method comprising: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a base structure on a substrate; forming a shallow trench isolation (STI) region on the substrate; forming a sacrificial gate structure on the superlattice structure, the sacrificial gate structure having a second gate portion and a first gate portion suspended on the STI region; forming a gate spacer along a plurality of sidewalls of the sacrificial gate structure and between the sacrificial gate structure and the STI region; and replacing the sacrificial gate structure and the sacrificial nanostructure layer with a gate structure. Simple Explanation of the Diagram

[0006] When read in conjunction with the accompanying drawings, the various aspects of this disclosure can be best understood through the following detailed description.

[0007] Figure 1A shows an isometric view of a semiconductor device with a gate structure having a tapered cross-sectional profile according to some embodiments.

[0008] Figure 1B shows a top view of a semiconductor device with a gate structure having a tapered profile according to some embodiments.

[0009] Figures 2A-2C, 3A-3C, and 4A-4C show different cross-sectional views of a semiconductor device including a gate structure with a tapered profile, according to some embodiments.

[0010] Figure 5 is a flowchart of a method for manufacturing a semiconductor device with a gate structure having a tapered cross-sectional profile according to some embodiments.

[0011] Figures 6, 7A-7D, 8A-8D, 9A-9D, 10A-10D, 11A-11D, 12A-12C, 13A-13C, 14A-14C, and 15A-15C illustrate isometric and cross-sectional views of a semiconductor device including a gate structure with a tapered profile, according to some embodiments, at different stages of its manufacturing process.

[0012] Figure 16 is a flowchart of a method for manufacturing another semiconductor device including a gate structure with a tapered cross-sectional profile according to some embodiments.

[0013] Figures 17A-17D, 18A-18D, 19A-19D, 20A-20D, 21A-21C, 22A-22C, 23A-23C, 24A-24C, and 25A-25C illustrate isometric and cross-sectional views of a semiconductor device, including a gate structure with a tapered profile, at different stages of its manufacturing process, according to some embodiments.

[0014] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features may not be in direct contact. As used herein, forming a first feature over a second feature means that the first and second features are formed in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. This repetition, in itself, does not indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatially related terms (e.g., "below," "under," "lower part," "above," "upper part," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are also intended to cover different orientations of the apparatus in use or operation other than those shown in the figures. The apparatus may be oriented in other directions (rotated 90 degrees or otherwise), and the spatially related descriptors used herein can be interpreted similarly.

[0017] It should be noted that references to "an embodiment," "embodiment," "example embodiment," "exemplary," etc., in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, this phrase does not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing that feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0018] It should be understood that the wording or terminology used herein is for descriptive rather than limiting purposes, and that the terminology or terminology used herein shall be interpreted by one or more persons skilled in the art based on the teachings herein.

[0019] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given quantity varies within 5-20% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10-15%, ±15-20%). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to percentages of values ​​as interpreted by one or more persons skilled in the art in accordance with the teachings herein.

[0020] GAA transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more lithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing patterns to be created with, for example, a smaller pitch than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA transistor structure.

[0021] The fin structures disclosed herein can be patterned using any suitable method. For example, the fin structures can be patterned using one or more lithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing patterns to be created with a smaller pitch than that achievable using a single direct lithography process. For example, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the fin structure.

[0022] A GAA FET may include: a substrate structure (also referred to as a "plate substrate" and a "fin substrate") disposed on a substrate, a shallow channel isolation (STI) region disposed adjacent to the substrate structure and on the substrate, a source / drain (S / D) region disposed on the substrate, a nanostructure channel region disposed on the substrate structure and between the S / D regions, and a gate structure (also referred to as a "GAA structure") surrounding each nanostructure channel region. The GAA structure includes an outer gate portion disposed on the STI region and an inner gate portion disposed on the nanostructure channel region. The inner gate portion includes a top gate portion disposed on the topmost nanostructure channel region and a bottom gate portion disposed between the substrate structure and the bottommost nanostructure channel region.

[0023] One of the challenges in forming a GAA structure is preventing the bottom gate portion from extending into the base structure during GAA structure formation. This causes the bottom gate portion to be close to the S / D region and increases the parasitic capacitance in the GAA FET. The bottom gate portion extends into the base structure because a trench is formed in the base structure during the gate replacement process to form the GAA structure. The gate replacement process includes: forming a sacrificial gate structure (also known as a "dummy gate structure"), a portion of which is located on the STI region; etching the sacrificial gate structure to form a gate opening; and forming the GAA structure within the gate opening. During the etching of the sacrificial gate structure, the STI region below the sacrificial gate structure is etched, which etches the base structure adjacent to the STI region and forms a trench in the base structure.

[0024] To overcome the aforementioned challenges, this disclosure provides example structures and methods for improving the bottom surface profile of the bottom gate portion of a GAA structure, which increases the spacing between the bottom gate portion and the S / D region. Increasing the spacing between the bottom gate portion and the S / D region can reduce or minimize parasitic capacitance in the GAA FET, which can improve the reliability and performance of the GAA FET. In some embodiments, the portion of the sacrificial gate structure on the STI region can be separated by spacers to prevent etching of the STI region during removal of the sacrificial gate structure. Preventing etching of the STI region can prevent etching of the base structure and the formation of trenches in the base structure. Therefore, the bottom gate portion can form a substantially flat bottom surface profile. In some embodiments, the portion of the sacrificial gate structure directly on the STI region can form a tapered profile to prevent or minimize etching of the STI region during removal of the sacrificial gate structure. Therefore, trenches can be prevented from forming in the base structure, or narrow trenches can be formed in the base structure. In some embodiments, the trench can be narrower than a trench formed by a sacrificial gate structure having a non-tapered (e.g., rectangular) cross-sectional profile on the STI region. Therefore, by modifying the profile of the sacrificial gate structure portion on the STI region, the bottom surface profile of the bottom gate portion can be improved to reduce or minimize the parasitic capacitance in the GAA FET.

[0025] Figure 1A shows an isometric view of a semiconductor device 100 according to some embodiments, which may represent a GAA FET 100. Figure 1B shows a top view of a GAA FET 100 according to some embodiments. Figures 2A, 3A, and 4A show different cross-sectional views of a GAA FET 100 according to some embodiments along line AA of Figures 1A and 1B, having additional structures not shown in Figures 1A and 1B for simplicity. Figures 2B, 3B, and 4B show different cross-sectional views of a GAA FET 100 according to some embodiments along line BB of Figures 1A and 1B, having additional structures not shown in Figures 1A and 1B for simplicity. Figures 2C, 3C, and 4C show different cross-sectional views of a GAA FET 100 according to some embodiments along line CC of Figures 1A and 1B, having additional structures not shown in Figures 1A and 1B for simplicity. Unless otherwise mentioned, the discussion of elements with the same annotations in Figures 1A, 1B, 2A-2C, 3A-3C and 4A-4C applies to each other.

[0026] Referring to Figures 1A, 1B, and 2A-2C, in some embodiments, the GAA FET 100 may include (i) a substrate 102, (ii) an STI region 104 disposed on the substrate 102, (iii) a fin-shaped substrate structure 106 disposed on the substrate 102 (also referred to as "sheet substrate 106" or "fin substrate 106"), (iv) a nanostructure channel region 208 disposed on the substrate structure 106, (v) an S / D region 110 disposed adjacent to the nanostructure channel region 208, (vi) an isolation structure 111, (vii) a gate structure 112 surrounding the nanostructure channel region 208 (also referred to as "GAA structure 112"), (viii) an external gate spacer 114, (ix) a barrier layer 115, (x) an internal gate spacer 216, (xi) an etch stop layer (ESL) 118 directly disposed on the S / D region 110, and (xii) a retrieval stop layer (ESL) directly disposed on the ESL. Interlayer dielectric (ILD) layer 120 on 118. Depending on the context, each region in S / D region 110 may individually or collectively refer to the source or drain. For simplicity, barrier layer 115, ESL 118 and ILD layer 120 are not shown in Figure 1B.

[0027] In some embodiments, substrate 102 may be a semiconductor material, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-insulator (SOI) structures, and combinations thereof. Furthermore, substrate 102 may be doped with p-type dopant (e.g., boron, indium, aluminum, or gallium) or n-type dopant (e.g., phosphorus or arsenic). In some embodiments, STI region 104 may include an insulating material, such as silicon oxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon carbonitride oxycarbonate (SiOCN), and silicon-germanium oxide (SiGeOx). In some embodiments, base structure 106 may include a material similar to substrate 102. Base structure 106 may have an elongated side extending along the X-axis.

[0028] In some embodiments, the nanostructure channel region 208 may be a nanosheet, nanowire, nanorod, nanotube, or other suitable nanostructure shape. As used herein, the term "nanostructure" defines a structure, layer, and / or region such that its horizontal dimensions (e.g., along the X-axis and / or Y-axis) and / or vertical dimensions (e.g., along the Z-axis) are less than about 100 nanometers, such as about 90 nanometers, about 50 nanometers, about 10 nanometers, or other values ​​less than about 100 nanometers. The nanostructure channel region 208 may include semiconductor materials similar to or different from the substrate 102. In some embodiments, the nanostructure channel region 208 may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbide carbon (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium antimony boron (SiGeSnB), group III-V semiconductor compounds, or other suitable semiconductor materials. In some embodiments, the thickness of each nanostructured channel region 208 along the Z-axis can be from about 3 nanometers to about 15 nanometers. Although three nanostructured channel regions 208 are shown below each gate structure 112, the GAA FET 100 can have any number of nanostructured channel regions 208. Although a rectangular cross-section of the nanostructured channel region 208 is shown, the cross-section of the nanostructured channel region 208 can be other geometries (e.g., circular, elliptical, triangular, or polygonal).

[0029] In some embodiments, the S / D region 110 may be disposed above the base structure 106 and electrically isolated from the base structure 106 by an isolation structure 111. In some embodiments, each S / D region 110 may include S / D sub-regions 110A and 110B, which may also be epitaxially grown on the sidewalls of the nanostructure channel region 208. In some embodiments, each S / D sub-region 110A may have a D-shaped cross-sectional profile and curved sidewalls in contact with the S / D sub-region 110B. The number of S / D sub-regions 110A in each S / D region 110 may be equal to the number of nanostructure channel regions 208 facing each S / D region 110. For example, as shown in FIG2A, each S / D region 110 includes six S / D sub-regions 110A, which is equal to the six nanostructure channel regions 208 facing each S / D region 110.

[0030] In some embodiments, each S / D sub-region 110B may include: (i) a first portion epitaxially grown directly on the S / D sub-region 110A, and (ii) a second portion disposed directly on the sidewall of the internal gate spacer 216 and located between adjacent S / D sub-regions 110A. The second portion of the S / D sub-region 110B may be formed by merging the first portions of adjacent S / D sub-regions 110B. In some embodiments, an air gap (not shown) may exist between the sidewall of the internal gate spacer 216 and the second portion of the S / D sub-region 110B.

[0031] In some embodiments, for an n-type GAA FET 100, S / D subregions 110A and 110B may comprise epitaxially grown Si without any Ge atoms and may differ from each other based on the concentration of an n-type dopant (e.g., phosphorus atoms). For example, the n-type dopant concentration in S / D subregion 110B may be higher than that in S / D subregion 110A. A higher dopant concentration in S / D subregion 110B can reduce the contact resistance between S / D region 110 and the S / D contact structure (not shown). In some embodiments, S / D subregion 110A may be undoped. In some embodiments, S / D subregion 110B may comprise a phosphorus doping concentration of about 1 × 10²¹ atoms / cm³ to about 4 × 10²¹ atoms / cm³.

[0032] In some embodiments, for a p-type GAA FET 100, S / D subregion 110A may comprise epitaxially grown Si without any Ge atoms, and S / D subregion 110B may comprise epitaxially grown SiGe. In some embodiments, S / D subregion 110B may comprise a Ge atom concentration of about 45 atomic% to about 60 atomic% with any remaining atomic% being Si atoms. In some embodiments, for a p-type GAA FET 100, S / D subregions 110A and 110B may differ from each other based on the concentration of a p-type dopant (e.g., boron atoms). For example, the p-type dopant concentration in S / D subregion 110B may be higher than that in S / D subregion 110A. In some embodiments, S / D subregion 110A may be undoped. In some embodiments, S / D subregion 110B may comprise a boron doping concentration of about 8 × 10²⁰ atoms / cm³ to about 3 × 10²¹ atoms / cm³.

[0033] In some embodiments, isolation structures 111 may be disposed below the S / D region 110 and in a recessed region of the substrate structure 106. The recessed region in the substrate structure 106 may be formed during the formation of the S / D region 110, as described in detail below. Isolation structures 111 prevent epitaxial growth of the S / D region 110 on the substrate structure 106 and prevent dopant from diffusing from the S / D region 110 to the substrate structure 106, thereby preventing current leakage between adjacent S / D regions 110 and short-channel effects in the GAA FET 100. In some embodiments, each isolation structure 111 may include an undoped semiconductor layer 111A and a dielectric layer 111B.

[0034] In some embodiments, an undoped semiconductor layer 111A may be disposed in a recessed region of the substrate structure 106. In some embodiments, the undoped semiconductor layer 111A may comprise undoped silicon or other suitable undoped semiconductor material. In some embodiments, the undoped semiconductor layer 111A may extend to a distance of about 20 nanometers to about 40 nanometers in the substrate structure 106. In some embodiments, if the distance is less than about 20 nanometers, the undoped semiconductor layer 111A may not adequately prevent dopant from diffusing from the S / D region 110 to the substrate structure 106. On the other hand, if the distance is greater than about 40 nanometers, the processing time (e.g., etching time, deposition time) for forming the undoped semiconductor layer 111A increases, thereby increasing the manufacturing cost of the GAA FET 100.

[0035] In some embodiments, the dielectric layer 111B may be directly disposed on the undoped semiconductor layer 111A and disposed along the sidewalls of the recessed region in the substrate structure 106. In some embodiments, each dielectric layer 111B may include a nitride material, such as SiN, SiON, SiCON, and SiCN. In some embodiments, each dielectric layer 111B may include a silicon-rich dielectric material. In some embodiments, silicon-rich dielectric materials may include: (i) silicon-rich nitrides (Si xN y) with a silicon atom concentration higher than that of nitrogen atoms; (ii) silicon-rich oxide nitrides (Si xO yN z) with a silicon atom concentration higher than that of oxygen atoms and nitrogen atoms; (iii) silicon-rich carbon oxides (Si xO yC z) with a silicon atom concentration higher than that of oxygen atoms and carbon atoms; (iv) silicon-rich carbon nitrides (Si wO xC yN z) with a silicon atom concentration higher than that of oxygen atoms, carbon atoms and nitrogen atoms; (v) silicon-rich boron nitrides (Si wB xO yN z) with a silicon atom concentration higher than that of oxygen atoms, boron atoms and nitrogen atoms; (vi) silicon-rich boron carbon oxynitrides (Si wB xO yC z) with a silicon atom concentration higher than that of oxygen atoms, boron atoms and carbon atoms; or (vii) other suitable silicon-rich nitride or carbide-based dielectric materials. The silicon-rich dielectric material of dielectric layer 111B can provide high etch resistance to dielectric layer 111B during its formation.

[0036] Each gate structure 112 may be a multilayer structure and may include: (i) an interface oxide (IL) layer 112A, (ii) a high-k (HK) gate dielectric layer 112B, (iii) a work function metal (WFM) layer 112C, and (iv) a gate metal filling layer 112D. In some embodiments, the IL layer 112A may be directly disposed on the topmost nanostructure channel region 208. In some embodiments, the IL layer 112A may include SiO2, SiGeOx, or germanium oxide (GeOx) and may have a thickness of about 0.5 nanometers to about 1 nanometer. In some embodiments, the HK gate dielectric layer 112B can be directly disposed on the IL layer 112A and can include a high-k dielectric material, such as hafnium oxide (HfO 2), titanium oxide (TiO 2), zirconium hafnium oxide (HfZrO), tantalum oxide (Ta 2O 3), hafnium silicate (HfSiO 4), zirconium oxide (ZrO 2), and zirconium silicate (ZrSiO 2). In some embodiments, the sidewall of the HK gate dielectric layer 112B can contact the sidewall of the external gate spacer 114.

[0037] WFM layer 112C may be disposed on HK gate dielectric layer 112B. In some embodiments, for p-type GAA FET 100, WFM layer 112C may comprise a substantially Al-free (e.g., Al-free) Ti-based or Ta-based nitride or alloy, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, for n-type GAA FET 100, WFM layer 112C may comprise titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), titanium aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. Gate metal filling layer 112D may be disposed on WFM layer 112C. In some embodiments, the gate metal filling layer 112D may include a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0038] Each gate structure 112 may have a pair of outer gate portions 112S (as shown in Figures 1A, 1B, 2B, and 2C; not visible in the cross-sectional view of Figure 2A) and an inner gate portion 112N between the pair of outer gate portions 112S (as shown in Figures 1A, 1B, 2A, and 2C; not visible in the cross-sectional view of Figure 2B). In some embodiments, each outer gate portion 112S may be disposed on the STI region 104 but not in direct contact with the STI region 104. The outer gate portions 112S may be separated from the STI region 104 by a portion of the outer gate spacer 114. Each outer gate portion 112S may have an upper gate portion 112SU and a lower gate portion 112SL. In some embodiments, each upper gate portion 112SU may have: (i) a rectangular cross-sectional profile along the X-axis (as shown in FIG. 2B); (ii) substantially linear sidewalls; and (iii) a width W1 of approximately 9 nm to approximately 12 nm. In some embodiments, each lower gate portion 112SL may have: (i) a tapered cross-sectional profile along the X-axis (e.g., a V-shaped cross-sectional profile); (ii) sloping sidewalls; (iii) an angle of approximately 70 degrees to approximately 80 degrees between the sloping sidewalls and the top surface 104t of the STI region 104; and (iv) a width W2 of approximately 5 nm to approximately 8 nm in the middle region of the lower gate portion 112SL. In some embodiments, the portion of the HK gate dielectric layer 112B in the upper gate portion 112SU may have substantially linear sidewalls, and the portion of the HK gate dielectric layer 112B in the lower gate portion 112SL may have sloping sidewalls and a V-shaped cross-sectional profile along the X-axis.

[0039] In some embodiments, as shown in FIG2A, each inner gate portion 112N may have a top gate portion 212Nt and a bottom gate portion 212Nb. The top gate portion 212Nt may be disposed on and in contact with the topmost nanostructure channel region 208. In some embodiments, each top gate portion 212Nt may have (i) a rectangular cross-sectional profile along the X-axis, (ii) substantially linear sidewalls, and (iii) a width W1 of about 9 nanometers to about 12 nanometers. The bottom gate portion 212Nb may be disposed between the bottommost nanostructure channel region 208 and the base structure 106. In some embodiments, each bottom gate portion 212Nb may have (i) a rectangular cross-sectional profile along the X-axis and (ii) a substantially linear bottom surface in contact with the top surface of the base structure 106. The substantially linear profile of the bottom surface of the bottom gate portion 212Nb may depend on the structural profile of the lower gate portion 112SL.

[0040] Forming a lower gate portion 112SL with a tapered profile and separated from the STI region 104 prevents the formation of trenches (e.g., trench 122 indicated by dashed lines in FIG. 2A) in the base structure 106 during the formation of the gate structure 112 in the gate replacement process, as discussed in detail below. Trenches (e.g., trench 122 in the base structure of other GAA FETs) are formed during the formation of a gate portion with a non-tapered profile (e.g., rectangular profile) on the STI region. Preventing the formation of such trenches in the region of the base structure 106 below the nanostructure channel region 208 prevents the bottom gate portion 212Nb from extending into the base structure 106, thereby reducing the spacing between the gate structure 112 and the S / D region 110 and increasing the parasitic capacitance of the GAA FET 100. Therefore, forming a lower gate portion 112SL with a tapered profile and separated from the STI region 104 facilitates the formation of a substantially linear profile of the bottom surface of the bottom gate portion 212Nb.

[0041] In some embodiments, the portion of the HK gate dielectric layer 112B in the top gate portion 212Nt may have a U-shaped cross-sectional profile along the X-axis. In some embodiments, the portion of the HK gate dielectric layer 112B in the bottom gate portion 212Nb may have a rectangular annular cross-sectional profile along the X-axis. In some embodiments, the portion of the HK gate dielectric layer 112B in the inner gate portion 212Nb may have a rectangular annular cross-sectional profile along the Y-axis. In some embodiments, as shown in FIG2C, the portion of the HK gate dielectric layer 112B on the base structure 106 in the inner gate portion 112N may be disposed at a lower surface plane than the portion of the HK gate dielectric layer 112B disposed on the STI region 104 in the outer gate portion 112S. In some embodiments, as shown in FIG2C, the top surface of the base structure 106 region below the nanostructure channel region 208 and the top surface 104t of the STI region 104 may be substantially coplanar with each other.

[0042] External gate spacers 114 electrically isolate the gate structure 112 from the adjacent S / D region 110 and other adjacent structures (e.g., S / D contact structures (not shown)). In some embodiments, each external gate spacer 114 may include a dielectric material such as SiO2, SiN, SiON, SiCN, and SiOCN. In some embodiments, each external gate spacer 114 may have an outer sidewall with a substantially linear profile facing away from the gate structure 112 and an inner sidewall with a V-shaped cross-sectional profile facing the gate structure 112. In some embodiments, each external gate spacer 114 may have a pair of external spacer portions 114S (shown in Figures 1A, 1B, 2B, and 2C; not visible in the cross-sectional view of Figure 2A) and an inner spacer portion 114N located between the pair of external spacer portions 112S (shown in Figures 1A, 1B, 2A, and 2C; not visible in the cross-sectional view of Figure 2B).

[0043] In some embodiments, each inner spacer portion 114N may be disposed along the sidewall of the top gate portion 212Nt and on the topmost nanostructure channel region 208, and may have a thickness T1 of about 6 nanometers to about 8 nanometers. In some embodiments, each outer spacer portion 114S may be disposed directly on the STI region 104 and may surround the outer gate portion 112S. Each outer spacer portion 114S may have an upper spacer portion 114SU and a lower spacer portion 114SL. In some embodiments, each upper spacer portion 114SU may have: (i) a rectangular cross-sectional profile along the X-axis (as shown in FIG. 2B); (ii) substantially linear sidewalls disposed along the sidewalls of the upper gate portion 112SU; and (iii) a thickness T1 of about 6 nanometers to about 8 nanometers. In some embodiments, each lower spacer portion 114SL may have (i) a substantially linear outer sidewall facing away from and in contact with the lower gate portion 112SL, (ii) an inclined inner sidewall facing and in contact with the lower gate portion 112SL, and (iii) a thickness T2 of about 30 nanometers to about 35 nanometers. This profile and dimensions of the outer spacer portion 114S facilitate the formation of a lower gate portion 112SL with a tapered cross-sectional profile, as discussed in detail below.

[0044] The internal gate spacer 216 electrically isolates the gate portion and the bottom gate portion 212Nb between the nanostructure channel regions 208 from the adjacent S / D region 110. In some embodiments, each internal gate spacer 216 may have a height of about 3 nanometers to about 20 nanometers and a thickness of about 1 nanometer to about 10 nanometers. Within these height and thickness ranges, the internal gate spacer 216 can adequately electrically isolate the gate portion from the adjacent S / D region 110 without affecting device size and manufacturing cost.

[0045] In some embodiments, ESL 118 can be directly disposed on S / D region 110. In some embodiments, the dielectric constant of ESL 118 can be from about 4 to about 7, and may include dielectric materials such as lanthanum oxide (LaO), aluminum oxide (Al₂O₃), yttrium oxide (Y₂O₃), tantalum carbon nitride (TaCN), zirconium silicon silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), aluminum zirconium oxide (ZrAlO), TiO₂, Ta₂O₃, ZrO₂, HfO₂, SiN, hafnium silicon silicide (HfSi), aluminum oxynitride (AlON), SiO₂, SiC, SiN, and zinc oxide (ZnO). In some embodiments, ILD layer 120 can be directly disposed on ESL 118. In some embodiments, ILD layer 120 may include insulating materials such as SiO₂, SiN, SiON, SiCN, and SiOCN.

[0046] Referring to Figures 3A-3C, in some embodiments, the GAA FET 100 may have a gate structure 312 and an external gate spacer 314 instead of a gate structure 112 and an external gate spacer 114. Unless otherwise mentioned, the discussion regarding the gate structure 112 and the external gate spacer 114 applies to the gate structure 312 and the external gate spacer 314. Similar to the gate structure 112, each gate structure 312 may be a multilayer structure and may include (i) an IL layer 312A, (ii) an HK gate dielectric layer 312B, (iii) a WFM layer 312C, and (iv) a gate metal filler layer 312D. Unless otherwise mentioned, the discussion of IL layer 112A, HK gate dielectric layer 112B, WFM layer 112C and gate metal fill layer 112D applies to IL layer 312A, HK gate dielectric layer 312B, WFM layer 312C and gate metal fill layer 312D, respectively.

[0047] Each gate structure 312 may have a pair of outer gate portions 312S and an inner gate portion 312N located between the pair of outer gate portions 312S. In some embodiments, each outer gate portion 312S may be directly disposed on the STI region 104. Each outer gate portion 312S may have an upper gate portion 312SU and a lower gate portion 312SL. In some embodiments, each upper gate portion 312SU may have (i) a rectangular cross-sectional profile along the X-axis (as shown in FIG. 3B), (ii) substantially linear sidewalls, and (iii) a width W1 of approximately 9 nm to approximately 12 nm. In some embodiments, each lower gate portion 312SL may have: (i) a tapered cross-sectional profile along the X-axis; (ii) sloping sidewalls; (iii) an angle of approximately 70 to approximately 80 degrees between the sloping sidewalls and the top surface 104t of the STI region 104; (iv) a substantially linear bottom surface 312Bs in contact with the top surface 104t of the STI region 104; (v) a width W2 of approximately 5 to approximately 8 nanometers in the middle region of the lower gate portion 312SL; and (vi) a width W3 of approximately 0 to approximately 3 nanometers in the bottom surface 312Bs. In some embodiments, the portion of the HK gate dielectric layer 312B in the upper gate portion 312SU may have substantially linear sidewalls, and the portion of the HK gate dielectric layer 312B in the lower gate portion 312SL may have sloping sidewalls and a substantially linear bottom surface in contact with the top surface 104t of the STI region 104.

[0048] In some embodiments, each inner gate portion 312N may have a top gate portion 312Nt and a bottom gate portion 312Nb. Unless otherwise mentioned, the discussion concerning the top gate portion 212Nt and the bottom gate portion 212Nb applies to both the top gate portion 312Nt and the bottom gate portion 312Nb. Similar to the bottom gate portion 212Nb, the substantially linear profile of the bottom surface of the bottom gate portion 312Nb may depend on the structural profile of the lower gate portion 312SL. Even though the lower gate portion 312SL contacts the STI region 104, unlike the lower gate portion 112SL, the tapered profile of the lower gate portion 312SL prevents the formation of trenches (e.g., trench 122 indicated by dashed lines in FIG. 3A) in the base structure 106 during the formation of the gate structure 312 in the gate replacement process, as discussed in detail below. In some embodiments, a gate structure 312 having a lower gate portion 312SL contacting the STI region 104 can be formed in the GAA FET 100 instead of a gate structure 112 to reduce etch time during the gate replacement process, thereby reducing the manufacturing cost of the GAA FET 100, as discussed in detail below.

[0049] In some embodiments, as shown in FIG3C, the portion of the HK gate dielectric layer 312B on the base structure 106 in the inner gate portion 312N and the portion of the HK gate dielectric layer 312B on the STI region 104 in the outer gate portion 312S can be substantially coplanar with each other. In some embodiments, as shown in FIG3C, the top surface of the base structure 106 region below the nanostructure channel region 208 and the top surface 104t of the STI region 104 can be substantially coplanar.

[0050] In some embodiments, each external gate spacer 314 may have a pair of external spacer portions 314S and an internal spacer portion 314N between the pair of external spacer portions 312S. In some embodiments, each internal spacer portion 314N may be disposed along the sidewall of the top gate portion 312Nt and in the topmost nanostructure channel region 208, and may have a thickness T1 of about 6 nanometers to about 8 nanometers. In some embodiments, each external spacer portion 314S may be disposed directly on the STI region 104 and along the sidewall of the external gate portion 312S. Each external spacer portion 314S may have an upper spacer portion 314SU and a lower spacer portion 314SL. In some embodiments, each upper spacer portion 314SU may have (i) a rectangular cross-sectional profile along the X-axis (as shown in FIG. 3B), (ii) substantially linear sidewalls disposed along the sidewall of the upper gate portion 312SU, and (iii) a thickness T1 of about 6 nanometers to about 8 nanometers. In some embodiments, each lower spacer portion 314SL may have (i) a substantially linear outer sidewall facing away from the lower gate portion 312SL, (ii) an inclined inner sidewall facing and contacting the lower gate portion 312SL, and (iii) a thickness T3 of about 15 nanometers to about 17 nanometers. This profile and dimensions of the outer spacer portion 314S facilitate the formation of a lower gate portion 312SL with a tapered cross-sectional profile, as described in detail below.

[0051] Referring to Figures 4A-4C, in some embodiments, the GAA FET 100 may have a gate structure 412 instead of gate structures 112 or 312. Unless otherwise mentioned, the discussion regarding gate structure 112 applies to gate structure 412 and external gate spacer 314. Similar to gate structure 112, each gate structure 412 may be a multilayer structure and may include: (i) an IL layer 412A, (ii) an HK gate dielectric layer 412B, (iii) a WFM layer 412C, and (iv) a gate metal fill layer 412D. Unless otherwise mentioned, the discussion regarding IL layer 112A, HK gate dielectric layer 112B, WFM layer 112C, and gate metal fill layer 112D applies to IL layer 412A, HK gate dielectric layer 412B, WFM layer 412C, and gate metal fill layer 412D, respectively.

[0052] Each gate structure 412 may have a pair of outer gate portions 412S and an inner gate portion 412N between the pair of outer gate portions 412S. In some embodiments, as shown in FIG4B, each outer gate portion 412S may extend a distance D1 into the STI region 104. Each outer gate portion 412S may have an upper gate portion 412SU and a lower gate portion 412SL. In some embodiments, each upper gate portion 412SU may have: (i) a rectangular cross-sectional profile along the X-axis (as shown in FIG4B); (ii) substantially linear sidewalls; and (iii) a width W1 of approximately 9 nm to approximately 12 nm. In some embodiments, each lower gate portion 412SL may have a V-shaped cross-sectional profile along the X-axis, which extends a distance D1 into the STI region 104. In some embodiments, each lower gate portion 412SL may have: (i) a first portion 412S1 having a tapered profile along the X-axis, the first portion 412S1 being disposed on the top surface 104t of the STI region 104; (ii) a second portion 412S2 having a V-shaped profile along the X-axis; (iii) inclined sidewalls of the first portion 412S1 and the second portion 412S2; (iv) an angle of about 70 degrees to about 80 degrees between the inclined sidewalls and the top surface 104t of the STI region 104; and (iv) a width W2 of about 5 nanometers to about 8 nanometers in the middle region of the lower gate portion 412SL. In some embodiments, the portion of the HK gate dielectric layer 412B in the upper gate portion 412SU may have substantially linear sidewalls, the portion of the HK gate dielectric layer 412B in the lower gate portion 412SL may have sloping sidewalls, and may extend a distance D1 into the STI region 104.

[0053] In some embodiments, each inner gate portion 412N may have a top gate portion 412Nt and a bottom gate portion 412Nb. Unless otherwise mentioned, the discussion concerning the top gate portion 212Nt applies to the top gate portion 412Nt. Unlike the bottom gate portion 212Nb, each bottom gate portion 412Nb may have: (i) a first portion 412Nb1 having a rectangular cross-sectional profile along the X-axis, the first portion 412Nb1 being disposed on the top surface of the base structure 106; and (ii) a second portion 412Nb2 having a U-shaped cross-sectional profile (as shown in FIG. 4A) or a V-shaped cross-sectional profile (not shown) along the X-axis, the second portion 412Nb2 extending below the top surface of the base structure 106 to a distance D2 of about 2 nanometers to about 4 nanometers. In some embodiments, the distance D2 may be equal to or greater than the distance D1. The structural profile of the second portion 412Nb2 may depend on the structural profile of the lower gate portion 412SL.

[0054] Because the lower gate portion 412SL is formed with a tapered cross-sectional profile, the second portion 412Nb2 formed in the base structure 106 has a narrower cross-sectional profile along the X-axis (as shown in Figure 4A) compared to the gate portion formed in the base structure during the formation of a gate structure with a non-tapered cross-sectional profile in other GAA FETs (e.g., gate portion 422 shown by the dashed line in Figure 4A). This narrower cross-sectional profile of the second portion 412Nb2 allows the horizontal spacing S1 between the second portion 412Nb2 and the adjacent S / D region to reach approximately 9 to approximately 14 nanometers, which is greater than the approximately 3 to approximately 8 nanometer horizontal spacing S1 between the gate portion 422 and the S / D region in other GAA FETs. This increase in horizontal spacing S1 can lead to a reduction in parasitic capacitance in the GAA FET 100.

[0055] In addition to a narrower cross-sectional profile, the second portion 412Nb2 in the substrate structure 106 can form a shallower depth profile than the gate portion 422 due to the formation of a lower gate portion 412SL with a tapered cross-sectional profile. The second portion 412Nb2 extends into the substrate structure 106 by a distance D2 of approximately 2 nm to approximately 4 nm, while the gate portion 422 extends into the substrate structure of other GAA FETs by a distance of approximately 8 nm to approximately 10 nm. Therefore, by using a gate structure 412 with a tapered gate portion (e.g., the lower gate portion 412SL) in the STI region 104, the volume of the gate portion (e.g., the second portion 412Nb2) in the substrate structure 106 can be reduced, thereby reducing the parasitic capacitance of the GAA FET 100. In some embodiments, a gate structure 412 with a lower gate portion 412SL extending into the STI region 104 may be formed in the GAA FET 100 instead of gate structures 112 or 312. This is a result of forming a gate structure 412 with a higher aspect ratio than gate structures 112 or 312, as discussed in detail below. In some embodiments, as shown in FIG4A, portions of the IL layer 412A, HK gate dielectric layer 412B, WFM layer 412C, and gate metal fill layer 412D in the second portion 412Nb2 may have a U-shaped or V-shaped cross-sectional profile along the X-axis.

[0056] Figure 5 is a flowchart of an example method 500 for manufacturing a GAA FET 100 having isometric views, top views, and cross-sectional views of Figures 1A, 1B, and 2A-2C, according to some embodiments. For illustrative purposes, the operations shown in Figure 5 will be described with reference to the example manufacturing processes for manufacturing the GAA FET 100 shown in Figures 6, 7A-7D, 8A-8D, 9A-9D, 10A-10D, 11A-11D, 12A-12C, 13A-13C, 14A-14C, and 15A-15C. Figures 6, 7A, 8A, 9A, 10A, and 11A are isometric views of the GAA FET 100 at different stages of its manufacturing according to some embodiments. Figures 7B, 8B, 9B, 10B, 11B, 12A, 13A, 14A, and 15A are cross-sectional views of the GAA FET 100 according to some embodiments at different stages of its manufacturing process, along line AA of Figures 1A, 1B, 7A, 8A, 9A, 10A, and 11A. Figures 7C, 8C, 9C, 10C, 11C, 12B, 13B, 14B, and 15B are cross-sectional views of the GAA FET 100 according to some embodiments at different stages of its manufacturing process, along line BB of Figures 1A, 1B, 7A, 8A, 9A, 10A, and 11A. Figures 7D, 8D, 9D, 10D, 11D, 12C, 13C, 14C, and 15C are cross-sectional views of v according to some embodiments at different stages of its manufacturing process along line CC of Figures 1A, 1B, 7A, 8A, 9A, 10A, and 11A. Depending on the specific application, operations may be performed in different sequences or not at all. It should be noted that method 500 may not produce a complete GAA FET 100. Therefore, it is understood that other processes may be provided before, during, and after method 500, and some of these other processes may only be briefly described herein. Unless otherwise mentioned, the discussion of elements with the same annotations in Figures 1A, 1B, 2A-2C, 6, 7A-7D, 8A-8D, 9A-9D, 10A-10D, 11A-11D, 12A-12C, 13A-13C, 14A-14C, and 15A-15C applies to each other.

[0057] Referring to FIG. 5, in operation 505, a superlattice structure having a nanostructure layer and a nanostructure sacrificial layer is formed on a substrate structure. For example, as shown in FIG. 6, a superlattice structure 607 (also referred to as "nanosheet stack 607") is formed on a fin-shaped substrate structure 106 formed on a substrate 102. The superlattice structure 607 may include nanostructure layers 208 and nanostructure sacrificial layers 608 arranged in an alternating configuration. In some embodiments, nanostructure layers 208 may include Si, and nanostructure sacrificial layers 608 may include SiGe.

[0058] Referring to FIG. 5, in operation 510, an STI region adjacent to the base structure is formed on the substrate. For example, as shown with reference to FIG. 6, an STI region 104 adjacent to the base structure 106 is formed on the substrate 102. In some embodiments, the formation of the STI region 104 may include the following sequential operations: (i) depositing a dielectric layer (not shown) of material having the STI region 104 on the substrate 102 and the superlattice structure 607; (ii) performing a chemical mechanical polishing (CMP) process to coplanarize (not shown) the dielectric layer and the top surface of the superlattice structure 607; and (iii) performing an etching process on the dielectric layer to form the structure of FIG. 6. In some embodiments, the STI region 104 and the top surface of the base structure 106 may be substantially coplanar.

[0059] Referring to Figure 5, in operation 515, a sacrificial gate structure is formed, wherein a first portion is located on the superlattice structure and a second portion is suspended on the STI region. For example, as described with reference to Figures 7A-7D, 8A-8D and 9A-9D, a sacrificial gate structure 812 is formed, which has an outer gate portion 812S suspended on the STI region 104 and an inner gate portion 812N on the superlattice structure 607. In some embodiments, the formation of the sacrificial gate structure 812 may include the following sequential operations: (i) substantially conformally depositing an oxide layer 712A on the STI region 104 and the superlattice structure 607 of FIG. 6, as shown in FIG. 7A-7D; (ii) depositing an amorphous, polycrystalline, or monocrystalline polycrystalline silicon layer 712B on the oxide layer 712A, as shown in FIG. 7A-7D; (iii) depositing a nitride masking layer 712C on the polycrystalline silicon layer 712B, as shown in FIG. 7A-7D; (iv) depositing an oxide masking layer 712D (e.g., SiO2) on the nitride masking layer 712C. v) Perform photolithography on the structure in Figures 7A-7D (not shown); vi) Perform a first etching process on the structure in Figures 7A-7D to form a sacrificial gate structure 812 having an IL layer 812A, a polycrystalline silicon structure 812B, a nitride layer 812C, and an oxide layer 812D, as well as a byproduct layer 824, as shown in Figures 8A-8D; and vii) Perform a second etching process (also known as a "cleaning process") on the structure in Figures 8A-8D using hydrofluoric acid gas or solution to remove the byproduct layer 824, forming a sacrificial gate structure 812, with the outer gate portion 812S suspended on the STI region 104 and the inner gate portion 812N directly located on the superlattice structure 607, as shown in Figures 9A-9D.

[0060] Referring to Figures 8A-8D and 9A-9D, in some embodiments, each outer gate portion 812S may have (i) an upper gate portion 812SU having a first portion of a polycrystalline silicon structure 812B, a nitride layer 812C, and an oxide layer 812D; and (ii) a lower gate portion 812SL having a second portion of the polycrystalline silicon structure 812B. In some embodiments, the upper portion of the polycrystalline silicon structure 812B, the nitride layer 812C, and the oxide layer 812D in each upper gate portion 812SU may have (i) a rectangular cross-sectional profile along the X-axis; (ii) substantially linear sidewalls; and (iii) a width W1 of approximately 9 nanometers to approximately 12 nanometers. In some embodiments, the lower portion of the polycrystalline silicon structure 812B in each lower gate portion 812SL may have (i) a tapered profile (e.g., a V-shaped profile) along the X-axis; (ii) sloping sidewalls; (iii) an angle of approximately 70 to approximately 80 degrees between the sloping sidewalls and the top surface 104t of the STI region 104; and (iv) a width W2 of approximately 5 to approximately 8 nanometers in the middle region of the lower portion of the polycrystalline silicon structure 812B. In some embodiments, each inner gate portion 812N may be disposed on and in contact with the topmost nanostructure layer 208 of the superlattice structure 607. In some embodiments, each inner gate portion 812N may have (i) a rectangular profile along the X-axis; (ii) substantially linear sidewalls; and (iii) a width W1 of approximately 9 to approximately 12 nanometers.

[0061] In some embodiments, depositing oxide layer 712A in operation 515 may include: exposing the structure of FIG6 to a precursor, such as tetraethyl orthosilicate (TEOS), at a temperature of about 650°C to about 750°C in a chemical vapor deposition (CVD) process to deposit oxide layer 712A (e.g., SiO2) of about 2 nanometers to about 4 nanometers.

[0062] In some embodiments, after the first etching process of operation 515, as shown in Figures 8A, 8C, and 8D, a portion of the oxide layer 712A under the outer gate portion 812S can be completely removed, while a portion of the oxide layer 712A at the interface between the polycrystalline silicon structure 812B and the superlattice structure 607 is retained to form the IL layer 812A, as shown in Figures 8B and 8D. In some embodiments, during the first etching process, a byproduct layer 824 can be formed on the exposed surfaces of the superlattice structure 607 and the STI region 104, as well as on the sacrificial gate structure 812, as shown in Figures 8A-8D. In some embodiments, the byproduct layer 824 can be formed as an etching byproduct generated from the reaction between the etch-off material of the oxide layer 712A, the polycrystalline silicon layer 712B, the nitride masking layer 712C, and the oxide masking layer 712D and the gas mixture used in the first etching process. In some embodiments, the byproduct layer 824 may include byproducts of silicon monoxide (SiO), SiO and chlorine (Cl), SiO and nitrogen (N), SiO and argon (Ar), and / or SiO and hydrogen bromide (HBr). In some embodiments, as shown in FIG9C and 9D, after removing the byproduct layer 824 during the second etching process, a gap 926 with a height H1 of approximately 2 nm to approximately 5 nm can be formed between the polycrystalline silicon structure 812B and the STI region 104.

[0063] In some embodiments, the first etching process may include a plasma etching process using a mixture of an etching gas and a diluted carrier gas. In some embodiments, the etching gas may include Cl2, HBr, difluoromethane (CH2F2), fluoroform (CHF3), carbon tetrafluoride (CF4), dichlorofluoromethane (CHClF2), fluoromethane (CH3F), hexafluorocyclobutene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), or hydrogen (H2). In some embodiments, the carrier gas may include an inert gas, such as Ar, N2, helium (He), and neon (Ne). Furthermore, the mixture of gases used in the plasma etching process may also include a passivation gas. In some embodiments, the passivation gas may include N2, O2, CO2, CH4, SO2, CO, and / or SiCl4. Passivating gas can be used to vary the etching selectivity of the polysilicon layer 712B along the height of the sacrificial gate structure 812, to achieve a cross-sectional profile of the polysilicon structure 812B with different widths (e.g., widths W1 and W2) along the height of the polysilicon structure 812B in FIG. 8C. In some embodiments, the plasma etching process can be performed at a temperature of about 25°C to about 200°C and a pressure of about 1 mTorr to about 800 mTorr. The flow rates of the etching gas, carrier gas, and passivating gas can be from about 20 standard cubic centimeters (sccm) per minute to about 3000 standard cubic centimeters (sccm). Plasma power of about 10 W to about 4000 W and bias power of about 300 W to about 600 W can be used in the plasma etching process.

[0064] Referring to FIG5, in operation 520, an external gate spacer is formed on the sacrificial gate structure. For example, as described with reference to FIGS. 10A-10D and 11A-11D, an external gate spacer 114 is formed on the sacrificial gate structure 812. In some embodiments, the formation of the external gate spacer 114 may include the following sequential operations: (i) depositing a dielectric layer 1014 having the material of the external gate spacer 114 on the structure of FIG. 9A-9D, as shown in FIG. 10A-10D; (ii) performing an annealing process to densify the dielectric layer 1014; and (iii) performing an etching process on the densified dielectric layer 1014 to form an external gate spacer 114 having a structural profile, as shown in FIG. 11A-11D.

[0065] In some embodiments, the dielectric layer 1014 may be deposited in a plasma-enhanced CVD (PECVD) process using a gas mixture of TEOS, H2, ammonia (NH3), N2, and / or O2 at a temperature of approximately 500°C to approximately 600°C. During the PECVD process, a plasma power of approximately 100W to approximately 300W and a bias power of approximately 200W to approximately 500W may be used. In some embodiments, the bias applied to the substrate 102 during the PECVD process may be controlled to vary the deposition selectivity of the dielectric layer 1014 along the height of the sacrificial gate structure 812, thereby achieving a cross-sectional profile of the dielectric layer 1014 with different thicknesses (e.g., thicknesses T1, T2, and T4) along the height of the polycrystalline silicon structure 812B in FIG. 10C. In some embodiments, the dielectric layer 1014 may have a thickness T1 around the upper portion of the polycrystalline silicon structure 812B in each upper gate portion 812SU. In some embodiments, as shown in Figures 10A and 10C, the thickness T4 of the dielectric layer 1014 around the lower portion of the polysilicon structure 812B in the lower gate portion 812SL can be greater than the thickness T1. In some embodiments, the dielectric layer 1014 around the tip of the polysilicon structure 812B in the lower gate portion 812SL can have a thickness T2 greater than both thicknesses T1 and T4, as shown in Figures 10A and 10C. In some embodiments, the bias voltage applied to the substrate 102 during the PECVD process can be controlled to fill the gap 926 between the polysilicon structure 812B and the STI region 104 (as shown in Figures 9C and 9D), as shown in Figures 10C and 10D.

[0066] Referring to Figure 5, in operation 525, an S / D opening and an internal gate spacer are formed in the superlattice structure. For example, as described with reference to Figures 12A-12C, an S / D opening 1210 and an internal gate spacer 216 are formed in the superlattice structure 607. The formation of the internal gate spacer 216 may include the following sequential operations: (i) performing an etching process on the structure of Figures 11A-11D to etch the portion of the superlattice structure 607 not covered by the sacrificial gate structure 812 and the external gate spacer 114, and forming the opening 1210, as shown in Figure 12A (not visible in the cross-sectional views of Figures 12B and 12C); (ii) performing an etching process on the sidewall of the nanostructure sacrificial layer 608 facing the opening 1210 to form the internal gate spacer. (iii) Depositing a dielectric layer (not shown) to fill the inner gate spacer opening (on the sidewalls of the outer gate spacer 114 and nanostructure layer 208, and on the top surface of the sacrificial gate structure 812, the outer gate spacer 114 and the base structure 106); and (iv) performing an etching process on the dielectric layer to form the inner gate spacer 216 and the barrier layer 115, as shown in Figures 12A and 12B (the cross-sectional view of Figure 12C is not visible).

[0067] Referring to FIG5, in operation 530, an isolation structure and an S / D region are formed in the S / D opening. For example, as described with reference to FIG13A-13C, an isolation structure 111 and an S / D region 110 are formed in the S / D opening 1210. In some embodiments, the formation of the isolation structure 111 may include the following sequential operations: (i) epitaxially growing an undoped silicon layer on the exposed surface of the base structure 106 in the S / D opening 1210 to form an undoped semiconductor layer 111A, as shown in FIG13A (not visible in the cross-sectional views of FIG13B and FIG13C); (ii) forming a dielectric layer 111A on the undoped semiconductor layer 111A, as shown in FIG13A (not visible in the cross-sectional views of FIG13B and FIG13C). In some embodiments, the formation of the S / D region 110 may include: (i) epitaxially growing an S / D sub-region 110A on the sidewall of the nanostructure layer 208, as shown in FIG13A (not visible in the cross-sectional views of FIG13B and 13C); and (ii) epitaxially growing an S / D sub-region 110B on the S / D sub-region 110A, as shown in FIG13A. After the formation of the S / D region 110, an ESL 118 and an ILD layer 120 may be formed, as shown in FIG13A and 13B (not visible in the cross-sectional view of FIG13C).

[0068] Referring to Figure 5, in operation 535, the sacrificial gate structure and the nanostructure sacrificial layer are replaced with a GAA structure. For example, as described with reference to Figures 14A-14C and 15A-15C, the sacrificial gate structure 812 and the nanostructure sacrificial layer 608 are replaced with a GAA structure 112. The formation of the GAA structure 112 may include the following sequential operations: (i) etching the sacrificial gate structure 812 and the nanostructure sacrificial layer 608 to form a gate opening 1412, as shown in Figures 14A-14C; (ii) oxidizing the exposed area of ​​the nanostructure layer 208 in the gate opening 1412 to form an IL layer 112A, as shown in Figures 15A and 15C (not visible in the cross-sectional view of Figure 15B); (iii) forming an HK gate dielectric layer 112B on the IL layer 112A, as shown in Figures 15A-15C; (iv) forming a WFM layer 112C on the HK gate dielectric layer 112B, as shown in Figures 15A-15C; and (v) forming a conductive layer 112D on the WFM layer 112C, as shown in Figures 15A-15C.

[0069] In some embodiments, as shown in FIG14B, the cross-sectional profile of the gate opening 1412 on the STI region 104 can be similar to the cross-sectional profile of the polysilicon structure 812B. Because the cross-sectional profile of the polysilicon structure 812B is tapered, the volume of the polysilicon structure 812B removed near the STI region 104 is smaller compared to polysilicon structures with non-tapered cross-sectional profiles in other GAA FETs. Therefore, unlike the etching process for non-tapered polysilicon structures, the polysilicon structure 812B is not over-etched to ensure complete removal of the polysilicon structure 812B. Over-etching of non-tapered polysilicon structures results in the formation of trenches in the substrate structure 106 (trench 122 shown by the dashed line in FIG14A), which increases the parasitic capacitance in the GAA FET, as described above. Therefore, due to the tapered profile of the polysilicon structure 812B and the fact that the lower part of the polysilicon structure 812B is separated from the STI region 104 by the external gate spacer 114, the gate opening 1412 can be prevented from extending into the STI region 104 and the base structure 106 during the etching of the sacrificial gate structure 812.

[0070] Figure 16 is a flowchart of an example method 1600 for manufacturing a GAA FET 100 having the top and cross-sectional views of Figures 1A, 1B, 3A-3C, and 4A-4C, according to some embodiments. For illustration, the operation shown in Figure 16 will be described with reference to the example manufacturing process shown in Figures 6, 7A-7D, 17A-17D, 18A-18D, 19A-19D, 20A-20D, 21A-21C, 22A-22C, 23A-23C, 24A-24C, and 25A-25C. Figures 6, 7A, 17A, 18A, 19A, and 20A are isometric views of the GAA FET 100 at different stages of its manufacturing according to some embodiments. Figures 7B, 17B, 18B, 19B, 20B, 21A, 22A, 23A, 24A, and 25A are cross-sectional views of a GAA FET 100 according to some embodiments at different stages of its manufacturing process along line AA of Figures 1A, 1B, 7A, 17A, 18A, 19A, and 20A. Figures 7C, 17C, 18C, 19C, 20C, 21B, 22B, 23B, 24B, and 25B are cross-sectional views of a GAA FET 100 according to some embodiments at different stages of its manufacturing process along line BB of Figures 7A, 17A, 18A, 19A, and 20A. Figures 7D, 17D, 18D, 19D, 20D, 21C, 22C, 23C, 24C, and 25C are cross-sectional views of a GAA FET 100 according to some embodiments at different stages of its fabrication along lines CC of Figures 7A, 17A, 18A, 19A, and 20A. Operations may be performed in different sequences or not, depending on the specific application. It should be noted that method 1600 may not produce a complete GAA FET 100. Therefore, it is understood that other processes may be provided before, during, and after method 1600, and these processes may only be briefly described herein. The discussion of elements with the same annotations in Figures 1A, 1B, 2A-2C, 3A-3C, 4A-4C, 2A-2C, 6, 7A-7D, 8A-8D, 9A-9D, 10A-10D, 11A-11D, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 17A-17D, 18A-18D, 19A-19D, 20A-20D, 21A-21C, 22A-22C, 23A-23C, 24A-24C, and 25A-25C applies to each other unless otherwise stated.

[0071] Referring to Figure 16, operations 1605 and 1610 are similar to operations 505 and 510 in Figure 5. After operation 1610, a structure similar to that in Figure 6 is formed. As described below with reference to Figures 7A-7D, 17A-17D, and 18A-18D, the subsequent operation 1615 of Figure 16 is performed on the structure of Figure 6.

[0072] Referring to Figure 16, in operation 1615, a sacrificial gate structure is formed having a first portion directly located on the superlattice structure and a second portion directly located on the STI region. For example, as described with reference to Figures 7A-7D, 17A-17D, and 18A-18D, a sacrificial gate structure 1712 is formed, wherein the outer gate portion 1712S is directly located on the STI region 104, and the inner gate portion 1712N is located on the superlattice structure 607. In some embodiments, the formation of the sacrificial gate structure 1712 may include the following sequential operations: (i) substantially conformally depositing an oxide layer 712A on the STI region 104 and the superlattice structure 607 of FIG. 6, as shown in FIG. 7A-7D; (ii) depositing an amorphous, polycrystalline, or monocrystalline polycrystalline silicon layer 712B on the oxide layer 712A, as shown in FIG. 7A-7D; (iii) depositing a nitride masking layer 712C (e.g., a SiN layer) on the polycrystalline silicon layer 712B, as shown in FIG. 7A-7D; (iv) depositing an oxide masking layer 712D (e.g., a SiO2 layer) on the nitride masking layer 712C. (v) Perform photolithography on the structure in Figures 7A-7D (not shown); (vi) Perform a first etching process on the structure in Figures 7A-7D to form a sacrificial gate structure 1712 having an IL layer 1712A, a polycrystalline silicon structure 1712B, a nitride layer 1712C, and an oxide layer 1712D, as well as a byproduct layer 1724, as shown in Figures 17A-17D; and (vii) Perform a second etching process on the structure in Figures 17A-17D using HF acid gas or solution to remove the byproduct layer 1724 and form the sacrificial gate structure 1712, as shown in Figures 18A-18D, with the outer gate portion 1712S directly located on the STI region 104 and the inner gate portion 1712N directly located on the superlattice structure 607, as shown in Figures 17A-17D.

[0073] Referring to Figures 17A-17D and 18A-18D, in some embodiments, each outer gate portion 1712S may have (i) an upper gate portion 1712SU having a first portion of a polycrystalline silicon structure 1712B, a nitride layer 1712C, and an oxide layer 1712D, and (ii) a lower gate portion 1712SL having a second portion of a polycrystalline silicon structure 1712B. In some embodiments, the upper portion of the polycrystalline silicon structure 1712B, the nitride layer 1712C, and the oxide layer 1712D in each upper gate portion 1712SU may have (i) a rectangular cross-sectional profile along the X-axis, (ii) substantially linear sidewalls, and (iii) a width W1 of approximately 9 nm to approximately 12 nm. In some embodiments, the lower portion of the polycrystalline silicon structure 1712B in each lower gate portion 1712SL may have: (i) a tapered profile along the X-axis; (ii) sloping sidewalls; (iii) an angle of approximately 70 to approximately 80 degrees between the sloping sidewalls and the top surface 104t of the STI region 104; (iv) a substantially linear bottom surface 1712Bs in contact with the top surface 104t of the STI region 104; (v) a width W2 of approximately 5 to approximately 8 nanometers in the middle region of the lower gate portion 1712SL; and (vi) a width W3 of approximately 0 to approximately 3 nanometers in the bottom surface 1712Bs. In some embodiments, each inner gate portion 1712N may be disposed on and in contact with the topmost nanostructure layer 208 of the superlattice structure 607. In some embodiments, each internal gate portion 1712N may have (i) a rectangular cross-sectional profile along the X-axis, (ii) substantially linear sidewalls, and (iii) a width W1 of about 9 nanometers to about 12 nanometers.

[0074] In some embodiments, unlike the first etching process in operation 515, portions of the oxide layer 712A are retained at the interfaces between the polysilicon structure 812B and the STI region 104, and between the polysilicon structure 812B and the superlattice structure 607, to form the IL layer 1712A after the first etching process in operation 1615, as shown in Figures 17A-17D. In some embodiments, similar to the byproduct layer 824, the byproduct layer 1724 may be formed during the first etching process on the exposed surfaces of the sacrificial gate structure 1712 and the superlattice structure 607, and on the STI region 104, as shown in Figures 17A-17D. The first etching process in operation 1615 may be similar to the first etching process in operation 515, except that the etching duration in the first etching process of operation 1615 may be shorter than that in operation 515.

[0075] Referring to FIG16, in operation 1620, an external gate spacer is formed on the sidewall of the sacrificial gate structure. For example, as described with reference to FIGS. 19A-19D and 20A-20D, an external gate spacer 314 is formed on the sidewall of the sacrificial gate structure 1712. In some embodiments, the formation of the external gate spacer 314 may include the following sequential operations: (i) depositing a dielectric layer 1914 having the material of the external gate spacer 314 on the structure of FIG18A-18D, as shown in FIG19A-19D; (ii) performing an annealing process to densify the dielectric layer 1914; and (iii) performing an etching process on the densified dielectric layer 1914 to form the external gate spacer 314 having a structural profile, as shown in FIG20A-20D.

[0076] In some embodiments, similar to dielectric layer 1014, dielectric layer 1914 can be deposited during a PECVD process. In some embodiments, the bias voltage applied to substrate 102 during the PECVD process can be controlled to vary the deposition selectivity of dielectric layer 1914 along the height of sacrificial gate structure 1712, thereby achieving a cross-sectional profile of dielectric layer 1914 with different thicknesses (e.g., thicknesses T1 and T3) along the height of polysilicon structure 1712B in FIG. 19C. In some embodiments, as shown in FIG. 19C, dielectric layer 1914 may have a thickness T1 around the upper portion of polysilicon structure 1712B in upper gate portion 1712SU. In some embodiments, dielectric layer 1914 may have a thickness T3 greater than thickness T1 around the lower portion of polysilicon structure 1712B in lower gate portion 1712SL, as shown in FIG. 19A and FIG. 19C.

[0077] Referring to Figure 16, operations 1625 and 1630 are similar to operations 525 and 530 in Figure 5 and are performed on the structures of Figures 20A-20D. Following operation 1630, the structures of Figures 21A-21C are formed. As described below with reference to Figures 22A-22C and 23A-23C, subsequent operation 1635 of Figure 16 is performed on the structures of Figures 21A-21C.

[0078] Referring to Figure 16, in operation 1635, the sacrificial gate structure and the nanostructure sacrificial layer are replaced with a GAA structure. For example, as described with reference to Figures 22A-22C and 23A-23C, the sacrificial gate structure 1712 and the nanostructure sacrificial layer 608 are replaced with a GAA structure 312. The formation of the GAA structure 312 may include the following sequential operations: (i) etching the sacrificial gate structure 1712 and the nanostructure sacrificial layer 608 to form a gate opening 2212, as shown in Figures 22A-22C; (ii) oxidizing the exposed area of ​​the nanostructure layer 208 in the gate opening 2212 to form an IL layer 312A, as shown in Figures 23A and 23C (not visible in the cross-sectional view of Figure 23B); (iii) forming an HK gate dielectric layer 312B on the IL layer 312A, as shown in Figures 23A-23C; (iv) forming a WFM layer 312C on the HK gate dielectric layer 312B, as shown in Figures 23A-23C; and (v) forming a conductive layer 312D on the WFM layer 312C, as shown in Figures 23A-23C.

[0079] In some embodiments, as shown in FIG14B, the cross-sectional profile of the gate opening 2212 on the STI region 104 can be similar to the cross-sectional profile of the polysilicon structure 1712B. Similar to the polysilicon structure 812B, due to the tapered cross-sectional profile of the polysilicon structure 1712B, the gate opening 2212 can be prevented from extending into the STI region 104 and the base structure 106 during the etching of the sacrificial gate structure 1712.

[0080] In some embodiments, during operation 1635, the sacrificial gate structure 1712 and the nanostructure sacrificial layer 608 can be replaced by the GAA structure 412, as shown in Figures 25A-25C, instead of the GAA structure 312. The formation of the GAA structure 412 may include the following sequential operations: (i) etching the sacrificial gate structure 1712 and the nanostructure sacrificial layer 608 to form a gate opening 2412, as shown in Figures 24A-24C; (ii) oxidizing the exposed area of ​​the nanostructure layer 208 in the gate opening 2412 to form an IL layer 412A, as shown in Figures 25A and 25C (not visible in the cross-sectional view of Figure 25B); (iii) forming an HK gate dielectric layer 412B on the IL layer 412A, as shown in Figures 25A-25C; (iv) forming a WFM layer 412C on the HK gate dielectric layer 412B, as shown in Figures 25A-25C; and (v) forming a conductive layer 412D on the WFM layer 412C, as shown in Figures 25A-25C.

[0081] In some embodiments, because the sacrificial gate structure 1712 has a high aspect ratio (e.g., an aspect ratio of approximately 3 to 20), the sacrificial gate structure 1712 can be over-etched to ensure the removal of the narrower portion of the sacrificial gate structure 1712 near the STI region 104. The result of this over-etching is that the gate opening 2412 is spaced a distance from the STI region 104 and a distance D2 from the base structure 106, thereby forming a trench 2412Nt in the base structure 106, as shown in FIG. 24A. Because the polysilicon structure 1712B has a tapered profile, the formed trench 2412Nt is narrower than trench 422 (shown as dashed lines in FIG. 24A) formed by over-etching polysilicon structures with non-tapered profiles in other GAA FETs. Similarly, because the polysilicon structure 1712B has a tapered profile, the depth profile of the formed trench 2412Nt is shallower than that of trench 422.

[0082] This disclosure provides example structures and methods for improving the bottom surface profile of the bottom gate portion (e.g., bottom gate portions 212Nb, 312Nb, and 412Nb) of GAA structures (e.g., GAA structures 112, 312, and 412), which increases the spacing (e.g., spacing S1) between the bottom gate portion and the S / D region (e.g., S / D region 110). Increasing the spacing between the bottom gate portion and the S / D region can reduce or minimize parasitic capacitance in the GAA FET (e.g., GAA FET 100), thereby improving the reliability and performance of the GAA FET. In some embodiments, portions of the sacrificial gate structure (e.g., outer gate portion 812S) on the STI region (e.g., STI region 104) may be separated by spacers (e.g., outer gate spacers 114 and 314) to prevent etching of the STI region during removal of the sacrificial gate structure. Preventing etching of the STI region can prevent etching of the base structure (e.g., base structure 106) and the formation of trenches in the base structure. Therefore, the bottom gate portion can form a substantially planar bottom surface profile. In some embodiments, the portion of the sacrificial gate structure directly located on the STI region (e.g., the outer gate portion 1712S) can form a tapered profile to prevent or minimize etching of the STI region during removal of the sacrificial gate structure. Therefore, trench formation in the base structure, or narrow trench formation (e.g., trench 2412Nt), can be prevented. In some embodiments, the trench can be narrower than a trench formed by a sacrificial gate structure having a non-tapered (e.g., rectangular) cross-sectional profile on the STI region. Therefore, by modifying the profile of the sacrificial gate structure, the bottom surface profile of the bottom gate portion can be improved to reduce or minimize parasitic capacitance in the GAA FET.

[0083] In some embodiments, the semiconductor device includes: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; an isolation region disposed on the substrate and adjacent to the base structure; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion; a gate structure; and a gate spacer disposed along a sidewall of the gate structure and between the gate structure and the isolation region. The gate structure includes an outer gate portion and an inner gate portion, the outer gate portion including: an outer gate portion having a tapered cross-sectional profile and disposed on the isolation region, and an inner gate portion having a non-tapered cross-sectional profile and disposed on the nanostructure channel region.

[0084] In some embodiments, the semiconductor device includes: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; a shallow channel isolation (STI) region disposed on the substrate; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion; and a gate structure. The gate structure includes a top gate portion disposed on the nanostructure channel region; and a bottom gate portion. The bottom gate portion includes: a first gate portion having a rectangular cross-sectional profile disposed on the first base portion; and a second gate portion having a tapered cross-sectional profile disposed on the first base portion.

[0085] In some embodiments, a method includes: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a base structure on a substrate; forming a shallow trench isolation (STI) region on the substrate; forming a sacrificial gate structure on the superlattice structure, the sacrificial gate structure having a second gate portion and a first gate portion suspended on the STI region; forming a gate spacer along the sidewall of the sacrificial gate structure and between the sacrificial gate structure and the STI region; and replacing the sacrificial gate structure and the sacrificial nanostructure layer with the gate structure.

[0086] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0087] 100: Semiconductor devices, GAA FET 102:Substrate 104: STI region 104t: Top surface 106: Base structure, plate base, fin base structure, fin base 110: S / D area 110A:S / D sub-region 110B:S / D subregion 111: Isolation Structure 111A: Semiconductor layer 111B: Dielectric layer 112: GAA structure, gate structure 112A: Interfacial oxide (IL) layer 112B: High-K (HK) gate dielectric layer 112C: Work Function Metal (WFM) Layer 112D: Gate metal filler layer, conductive layer 112N: Internal gate section 112S: External gate section 112SL: Lower gate section 112SU: Upper gate section 114: External gate spacer 114N: Internal spacer section 114S: External spacer section 114SL: Lower spacer section 114SU: Upper spacer section 115: Barrier layer 118: Etching Stop Layer (ESL) 120: Interlayer Dielectric (ILD) Layer 122: Trench 208: Nanostructure channel region, nanostructure layer 212N: Internal gate section 212Nb: Bottom gate section 212Nt: Top gate section 216: Internal gate spacer 312: GAA structure, gate structure 312A: IL layer 312B:HK gate dielectric layer 312Bs: Bottom surface 312C:WFM layer 312D: Gate metal filler layer, conductive layer 312N: Internal gate section 312Nb: Bottom gate section 312Nt: Top gate section 312S: External gate section 312SL: Lower gate section 312SU: Upper gate section 314: External gate spacer 314N: Internal spacer section 314S: External spacer section 314SL: Lower spacer section 314SU: Upper spacer section 412: GAA structure, gate structure 412A: IL layer 412B:HK gate dielectric layer 412C:WFM layer 412D: Gate metal filler layer, conductive layer 412N: Internal gate section 412Nb: Bottom gate section 412Nb1: Part 1 412Nb2: Part Two 412Nt: Top gate section 412S: External gate section 412S1: Part 1 412S2: Part Two 412SL: Lower gate section 412SU: Upper gate section 422: Trench 422: Gate section 500: Methods 505: Operation 510: Operation 515: Operation 520: Operation 525: Operation 530: Operation 535: Operation 607: Superlattice structure, nanosheet stacking 608: Nanostructured sacrificial layer 712A: Oxide layer 712B: Polycrystalline silicon layer 712C: Nitride Masking Layer 712D: Oxide Masking Layer 812: Sacrificial gate structure 812A: IL layer 812B: Polycrystalline silicon structure 812C: Nitride layer 812D: Oxide layer 812N: Internal gate section 812S: External gate section 812SL: Lower gate section 812SU: Upper gate section 824: Byproduct layer 926: Gap 1014: Dielectric layer 1210: S / D opening 1210: Opening 1412: Gate Opening 1600: Method 1605: Operation 1610: Operation 1615: Operation 1620: Operation 1625: Operation 1630: Operation 1635: Operation 1712: Sacrificial gate structure 1712A: IL layer 1712B: Polycrystalline silicon structure 1712Bs: Bottom surface 1712C: Nitride layer 1712D: Oxide layer 1712N: Internal gate section 1712S: External gate section 1712SL: Lower gate section 1712SU: Upper gate section 1724: Byproduct layer 1914: Dielectric layer 2212: Gate Opening 2412: Gate Opening 2412Nt: Trench D1: Distance D2: Distance H1: Height S1: Spacing T1: Thickness T2: Thickness T3: Thickness T4: Thickness W1: Width W2: Width W3: Width

Claims

1. A semiconductor device, comprising: a substrate; A base structure having a first base portion and a second base portion disposed on a substrate; an isolation region disposed on the substrate and adjacent to the base structure; a nanostructure channel region disposed on the first base portion; a source / drain region disposed on the second base portion; and a gate structure comprising: an outer gate portion having a tapered cross-sectional profile and disposed on the isolation region, and an inner gate portion having a non-tapered cross-sectional profile and disposed on the nanostructure channel region. and a gate spacer, disposed along a plurality of sidewalls of the gate structure and between the gate structure and the isolation region; wherein the outer gate portion includes: an upper gate portion having a rectangular cross-sectional profile; and a lower gate portion having the conical cross-sectional profile.

2. The semiconductor device according to claim 1, wherein, The gate spacer is located below a conical portion of the outer gate section.

3. The semiconductor device according to claim 1, wherein, The external gate portion includes: an upper gate portion having a first width; and a lower gate portion having a second width smaller than the first width.

4. The semiconductor device according to claim 1, wherein, The gate structure includes a gate dielectric layer having a V-shaped profile and is disposed on the isolation region.

5. The semiconductor device according to claim 1, wherein, The gate structure includes a conductive layer, wherein a portion of the gate spacer is disposed between a bottom surface of the conductive layer and a top surface of the isolation region.

6. The semiconductor device according to claim 1, wherein, The gate spacer includes: an upper spacer portion having a first thickness; and a lower spacer portion having a second thickness greater than the first thickness.

7. The semiconductor device according to claim 1, wherein, The gate spacer includes: an outer sidewall having a substantially linear profile facing away from the gate structure; and an inner sidewall having a V-shaped cross-sectional profile facing the gate structure.

8. The semiconductor device according to claim 1, wherein, A first portion of the gate structure disposed on the gate spacer is on a higher surface plane than a second portion of the gate structure disposed on the first base portion of the base structure.

9. A semiconductor device comprising: a substrate; a base structure having a first base portion and a second base portion disposed on the substrate; a shallow channel isolation (STI) region disposed on the substrate; a nanostructured channel region disposed on the first base portion; a source / drain region disposed on the second base portion; and a gate structure comprising: a top gate portion disposed on the nanostructured channel region; and a bottom gate portion comprising: a first gate portion having a rectangular cross-sectional profile disposed on the first base portion; and a second gate portion having a tapered cross-sectional profile disposed on the first base portion; wherein... The gate structure also includes an external gate portion, which includes: an upper gate portion having a rectangular cross-sectional profile; and a lower gate portion having a V-shaped cross-sectional profile.

10. A method of manufacturing a semiconductor device, comprising: forming a superlattice structure having a nanostructure layer and a sacrificial nanostructure layer on a base structure on a substrate; forming a shallow trench isolation (STI) region on the substrate; forming a sacrificial gate structure on the superlattice structure, the sacrificial gate structure having a second gate portion and a first gate portion suspended on the STI region; forming a gate spacer along a plurality of sidewalls of the sacrificial gate structure and between the sacrificial gate structure and the STI region; and replacing the sacrificial gate structure and the sacrificial nanostructure layer with a gate structure; wherein, Forming the sacrificial gate structure includes: forming a first gate portion having a tapered cross-sectional profile; and forming a second gate portion having a rectangular cross-sectional profile.

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