Semiconductor processing method and method of forming 3D dram device

Abstract

Embodiments of this technology may include semiconductor processing methods and systems. The methods and systems may include: providing a substrate to a processing region of a semiconductor process chamber, wherein the substrate includes one or more alternating pairs of semiconductor material layers and sacrificial material layers. The method includes: forming one or more vertically extending features through one or more alternating pairs of semiconductor material layers and sacrificial material layers, forming one or more sidewalls having lateral ends of alternatingly exposed semiconductor material layers and sacrificial material layers. The method includes: forming a protective material layer over the exposed lateral ends of the semiconductor material layers. The method includes: laterally recessing at least a portion of the sacrificial material layer from one or more vertically extending features, and trimming a portion of the semiconductor material layer adjacent to the one or more vertically extending features.

Description

Technical Field

[0001] This application claims priority under patent law to U.S. patent application No. 63 / 588,931, filed on October 9, 2023, entitled "3D DRAM WITH ENLARGE-LESS TRIM," which is incorporated herein by reference in its entirety.

[0002] The technology relates to semiconductor systems and processes. More specifically, the technology relates to three-dimensional (3D) dynamic random access memory (DRAM) devices (3D DRAM) and methods of forming such devices. Prior Art

[0003] Integrated circuits are fabricated through processes that produce intricately patterned layers of material on a substrate surface. Producing patterned material on a substrate requires controlled methods of forming and removing exposed material. Material properties can affect the operation of the device and can also affect the way films are removed relative to each other. During formation and removal, material can be accidentally removed, which can result in wasted space within the device. As devices continue to shrink, this wasted area within the device becomes an increasingly problematic issue.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high-quality components and structures. The present technology can meet these and other needs. Summary of the invention

[0005] The present technology generally relates to semiconductor components and methods of forming such components. The method includes providing a substrate to a processing area of ​​a semiconductor processing chamber, wherein the substrate includes one or more alternating pairs of semiconductor material layers and sacrificial material layers. The method includes forming one or more vertically extending features through the one or more alternating pairs of semiconductor material layers and sacrificial material layers. The method includes forming one or more sidewalls having alternating exposed lateral ends of the semiconductor material layers and sacrificial material layers. The method includes forming a protective material layer above the exposed lateral ends of the semiconductor material layers. The method includes causing at least a portion of the sacrificial material layer to be laterally recessed from the one or more vertically extending features. The method includes trimming a portion of the semiconductor material layer adjacent to the one or more vertically extending features.

[0006] In an embodiment, the method includes: wherein the protective material layer is formed by selectively oxidizing or nitriding the exposed lateral ends of the semiconductor material. In a further embodiment, the method includes: wherein the sacrificial material is laterally recessed before forming the protective material layer. And, in an embodiment, the method also includes: filling the laterally recessed portion of the sacrificial material with a dielectric material. Additionally or alternatively, the method includes: removing the dielectric material before trimming. In more embodiments, the protective material layer is formed by directional deposition on the exposed lateral ends of the semiconductor material. Further, in an embodiment, the thickness of the protective material layer is from about 5 Å to about 500 Å. In more embodiments, the semiconductor material layer is an optionally doped silicon material, and the sacrificial material layer includes silicon germanium. In an embodiment, one or more vertically extending features have a first width before trimming the semiconductor material layer, and a second width after trimming the semiconductor material layer, wherein the second width is about 10% or less than the first width. In a further embodiment, the thickness of the semiconductor material layer is about 400% or greater than the thickness of the sacrificial material layer. In an embodiment, the method includes: after trimming the semiconductor material layer, removing the protective material layer.

[0007] The present technology also generally relates to a semiconductor processing method. The method includes providing a substrate to a processing area of ​​a semiconductor processing chamber, wherein the substrate includes a plurality of alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. The method includes etching one or more access holes through the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials to expose lateral ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. The method includes etching to form one or more sidewalls, the one or more sidewalls containing alternating exposed lateral ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. The method includes forming a protective material layer over the exposed lateral ends of the silicon-containing materials. The method includes causing at least a portion of the silicon-and-germanium-containing materials to be laterally recessed from the one or more access holes. The method includes trimming a portion of the silicon-containing material adjacent to the access holes.

[0008] In an embodiment, the substrate comprises more than 20 alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. In further embodiments, the thickness of the silicon-and-germanium-containing materials is less than or about 30 nm. Further, in an embodiment, the thickness of the silicon-containing materials is about 400% or greater than the thickness of the silicon-and-germanium-containing materials. Additionally or alternatively, in an embodiment, the method comprises etching one or more vertically extending features at ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials opposite the exposed lateral ends, thereby exposing outer ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials, wherein etching removes at least a portion of the patterned stack and forms one or more outer sidewalls having alternating exposed outer ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. The method comprises forming a second protective layer over the exposed outer ends of the silicon-containing materials. In an embodiment, the method comprises recessing at least a portion of the silicon-and-germanium-containing materials laterally from the one or more vertically extending features. Furthermore, in an embodiment, the method includes trimming a portion of the semiconductor material layer adjacent to the access hole.

[0009] In an embodiment, the method includes: etching one or more vertically extending features at ends of the alternating pairs of silicon-containing material layers and silicon-and-germanium-containing material layers opposite to the exposed lateral ends, thereby exposing the outer ends of the alternating pairs of silicon-containing material layers and silicon-and-germanium-containing material layers. In further embodiments, the method includes: wherein etching removes at least a portion of the patterned stack and forms one or more outer sidewalls, the one or more outer sidewalls having the alternating exposed outer ends of the alternating pairs of silicon-containing material layers and silicon-and-germanium-containing material layers. In an embodiment, the method includes: forming a second protective layer over the exposed outer ends of the silicon-containing material.

[0010] The present technology also generally relates to a method of forming a three-dimensional dynamic random access memory (3D DRAM) device. The method includes providing a substrate to a processing area of ​​a semiconductor processing chamber, wherein the substrate includes one or more alternating pairs of silicon-containing material layers and silicon-and-germanium-containing material layers. The method includes forming one or more access holes through the one or more alternating pairs of silicon-containing material layers and silicon-and-germanium-containing material layers to form one or more sidewalls, the one or more sidewalls including alternating exposed lateral ends of the silicon-containing material layers and the silicon-and-germanium-containing material layers. The method includes forming a protective material layer over the exposed lateral ends of the silicon-containing material layers. The method includes causing at least a portion of the silicon-and-germanium-containing material layer to be laterally recessed from the one or more access holes. The method includes trimming a portion of the silicon-containing material layer adjacent to the one or more access holes.

[0011] Such techniques can provide many benefits over conventional systems and methods for forming 3D-DRAM devices. For example, by forming devices as discussed herein, even when the access aperture defines a high aspect ratio structure, little or no enlargement of the access aperture is required to etch a recess within the access aperture. Thus, the devices and methods discussed herein can provide increased recess dimensions, such as increased channel dimensions in the case of 3D DRAM. Embodiments of the present technology and their many advantages and features are described in more detail in conjunction with the following description and accompanying drawings. Simple diagram description

[0012] The nature and advantages of the technology disclosed in this article can be further understood by referring to the rest of the specification and the drawings.

[0013] FIG. 1A illustrates a top plan view of an example processing system in accordance with some embodiments of the present technology.

[0014] FIG. 1B illustrates a schematic cross-sectional view of an example processing system according to some embodiments of the present technology.

[0015] FIG. 2 illustrates operations of an example method of semiconductor processing in accordance with some embodiments of the present technology.

[0016] 3A-3H illustrate cross-sectional views of example semiconductor structures according to some embodiments of the present technology.

[0017] Several drawings are included in a schematic manner. It should be understood that these drawings are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated to be drawn to scale. In addition, as schematic diagrams, these drawings are used to aid understanding and may not include all aspects or information compared to actual performance, and may include exaggerated materials for illustrative purposes.

[0018] In the drawings, similar components and / or features may have the same reference numeral. Further, components of the same type may be distinguished by appending a letter after the reference numeral that distinguishes the similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference numeral. Implementation

[0019] In a dynamic random access memory (DRAM) device such as a 3D DRAM, alternating layers of material may be formed on a substrate. The alternating layers of material may include alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials. As the number of layers increases, the challenges of forming features also increase, due at least in part to the high aspect ratio of the device. For example, during 3D DRAM processing, a vertically extending access hole may be formed through two or more layers of material. Subsequent processing may require the removal of material extending horizontally away from the access hole. Due to the lack of line of sight to the access hole, such horizontally extending recesses, referred to herein as "blind recesses," are difficult to properly trim, particularly as the size of the device continues to increase while also desiring greater aspect ratios in the features formed. While 3D DRAM is used as an example of such blind recesses, it should be clear that such challenges may be equally applicable to a variety of devices having one or more blind recesses formed by a main channel.

[0020] Initial efforts to improve 3D DRAM devices included increasing the size of the SiGe layer compared to the silicon layer. In this way, it is possible to etch all or part of the SiGe while leaving the silicon. Thus, the controlled silicon layer and the etched portion can be controlled as the layer is deposited. However, such a structure is insufficient for high aspect ratio structures because only a certain percentage of SiGe can exist without causing mechanical failure. Attempts have been made to reduce the germanium concentration without reducing the thickness of the SiGe layer, but these attempts have failed to achieve the required germanium concentration for selective etching compared to silicon. Attempts have been made to use a SiGe layer thinner than silicon and perform silicon recess trimming after the SiGe is removed. However, such efforts result in recessed access holes, which disadvantageously shortens the length of the semiconductor channel. In existing methods, the width of the access hole can be more than twice the width in order to trim an acceptable channel. This phenomenon requires an access hole of insufficient width to properly trim the blind recess, or there is an unacceptable loss of dimensionality, especially as device shrinkage continues.

[0021] Surprisingly, the present technique has discovered that by carefully controlling the deposition and etching operations, excellent trimming can be achieved in one or more blind recesses without increasing the width of the access region (e.g., sidewalls). That is, by carefully depositing one or more protective films, controlled trimming of sacrificial material can be achieved while only little or no non-sacrificial material is removed. Thus, devices formed according to the present technique can exhibit excellent dimensional control (e.g., in blind recesses) without sacrificing the quality of the trimmed sections.

[0022] Having described the general aspects of a chamber configured to perform operations according to embodiments of the present technology, in which plasma processing may be performed, specific methods and component configurations may be discussed. It should be understood that the present technology is not intended to be limited to the specific films and processes discussed, as the techniques described herein may be used to enhance many film formation processes and may be applied to a variety of semiconductor processing chambers and operations.

[0023] FIG. 1A shows a top plan view of one embodiment of a processing system 10 of deposition, treatment, etching, baking and curing chambers according to an embodiment. In the figure, a pair of front-opening unified pods 12 supply substrates of various sizes, which are received by a robot 14 and placed into a low pressure holding area 16, and then placed into one of semiconductor processing chambers 18a to 18f, which are arranged in series blocks 19a to 19c. A second robot 11 can be used to transport substrate wafers from the holding area 16 to the semiconductor processing chambers 18a to 18f and back. Each semiconductor processing chamber 18a to 18f can be equipped to perform a number of substrate processing operations, including the formation of stacks of semiconductor materials described herein, as well as plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation and other substrate processes (including plasma treatment, annealing, ashing, etc.).

[0024] The semiconductor process chambers 18a-18f may include one or more system components for depositing, plasma treating, curing and / or etching dielectric or other films on a substrate. In one configuration, two pairs of semiconductor process chambers (e.g., 18c-18d and 18e-18f) may be used to deposit dielectric materials on a substrate, and a third pair of semiconductor process chambers (e.g., 18a-18b) may be used to process the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 18a-18f) may be configured to deposit and process alternating stacks of dielectric films on a substrate. Any one or more of the processes described herein may be performed in chambers separate from the manufacturing system as shown in the various embodiments. It will be appreciated that other configurations of chambers for the deposition, treatment, etching, annealing and curing of dielectric films are contemplated.

[0025] FIG. 1B illustrates a cross-sectional view of an exemplary semiconductor processing chamber 100 according to some embodiments of the present technology. This figure may illustrate an overview of a system that may incorporate one or more aspects of the present technology and / or may be specifically configured to perform one or more operations according to embodiments of the present technology. Additional details of the chamber 100 or the methods performed therein may be further described below. According to some embodiments of the present technology, the chamber 100 may be utilized to form a tensile nitride film, although it may be appreciated that the methods may similarly be performed in any chamber in which film formation may occur. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 in a processing volume 120. A substrate 103 may be provided to the processing volume 120 via an opening 126, which may be conventionally sealed using a slit valve or door for processing. During processing, the substrate 103 may be positioned on the surface 105 of the substrate support. As indicated by arrow 145, the substrate support 104 may be rotated along an axis 147, and the shaft 144 of the substrate support 104 may be positioned on the axis 147. Alternatively, the substrate support 104 may be raised and rotated as desired during the deposition process.

[0026] A plasma profile modulator 111 may be disposed in the semiconductor processing chamber 100 to control plasma distribution across a substrate 103 disposed on a substrate support 104. The plasma profile modulator 111 may include a first electrode 108, which may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106, or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-like member, and may be a ring electrode. The first electrode 108 may be a continuous loop located about the perimeter of the semiconductor processing chamber 100 surrounding the processing volume 120, or may be discontinuous at selected locations if desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as, for example, a secondary gas distributor.

[0027] One or more isolators 110a, 110b, which may be dielectric materials such as ceramics or metal oxides, such as aluminum oxide and / or aluminum nitride, may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the first electrode 108 from the chamber body 102. The gas distributor 112 may define apertures 118 for distributing process precursors into the processing volume 120. The gas distributor 112 may be coupled to a first electrical power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be coupled to a semiconductor processing chamber. In some embodiments, the first electrical power source 142 may be an RF power source.

[0028] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive or non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the panel of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, for example, by the first electrical power source 142 shown in FIG. 1B , or in some embodiments, the gas distributor 112 may be grounded.

[0029] The first electrode 108 may be coupled to a first tuning circuit 128 that may control a ground path for the semiconductor processing chamber 100. The first tuning circuit 128 may include a first electron sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or may include a variable capacitor or other circuit element. The first tuning circuit 128 may be or may include one or more inductors 132. The first tuning circuit 128 may be any circuit that can achieve a variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some embodiments shown, the first tuning circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electron sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B that is coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit branches to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to the first electronic controller 134, which may provide a degree of closed-loop control of the plasma environment within the processing volume 120.

[0030] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 via a conduit 146, for example, a cable having a selected resistance (e.g., 50 ohms) disposed in a shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to provide further control of the plasma environment in the processing volume 120.

[0031] The third electrode 124 may be coupled to the substrate support 104, and the third electrode 124 may be a bias electrode and / or an electrostatic clamping electrode. The third electrode may be coupled to a second electrical power source 150 via a filter 148, and the filter 148 may be an impedance matching circuit. The second electrical power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second electrical power source 150 may be RF bias power.

[0032] The lid assembly 106 and substrate support 104 of FIG. 1B may be used with any semiconductor processing chamber used for plasma or thermal processing. In operation, the semiconductor processing chamber 100 may provide real-time control of a plasma environment in a processing volume 120. The substrate 103 may be disposed on the substrate support 104, and process gases may be flowed through the lid assembly 106 using the inlet 114 according to any desired flow schedule. The gases may exit the semiconductor processing chamber 100 via the outlet 152. A power source may be coupled to the gas distributor 112 to create a plasma in the processing volume 120. In some embodiments, the substrate may be subjected to an electrical bias using the third electrode 124.

[0033] Once the plasma is ignited in the processing volume 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 may then be used to adjust the flow properties of the ground path represented by the two tuning circuits 128 and 136. Set points may be communicated to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and the uniformity of the plasma density from the center to the edge. In embodiments where the electronic controllers may both be variable capacitors, the electronic sensors may adjust the variable capacitors to independently maximize the deposition rate and minimize the thickness non-uniformity.

[0034] Each tuning circuit 128, 136 may have a variable impedance that may be adjusted using the corresponding electronic controller 134, 140. When the electronic controllers 134, 140 are variable capacitors, the capacitance range of each variable capacitor, as well as the inductance of the first inductor 132A and the second inductor 132B, may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and may have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape with minimum aerial coverage or lateral coverage over the substrate support. When the capacitance of the first electronic controller 134 is close to the value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may be reduced from the chamber wall and the air coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect, increasing or decreasing the air coverage of the plasma above the substrate support as the capacitance of the second electronic controller 140 changes.

[0035] Electronic sensors 130, 138 may be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be built into each sensor, and the sensor may be equipped with control software that determines adjustments to each respective electronic controller 134, 140 to minimize deviations from the set point. Thus, the plasma shape may be selected and dynamically controlled during processing. It should be understood that while the above discussion is based on electronic controllers 134, 140 that may be variable capacitors, any electronic component with adjustable characteristics may be used to provide adjustable impedance for the tuning circuits 128 and 136.

[0036] FIG. 2 shows example operations in a method 200 for forming a semiconductor structure according to an embodiment of the present technology. The method 200 may include one or more operations before the method begins, including front-end processing, deposition, etching, polishing, cleaning, or any other operation that may be performed before the operations described herein. For example, the method may begin after depositing several layers, such as for producing a 3D DRAM structure. However, as explained above, it is understood that the drawings illustrate only one example process in which a process according to an embodiment of the present technology may be employed, and the present description is not intended to limit the technology to only this process or structure. Some or all of these operations may be performed in a chamber or system as described above, or some or all of these operations may be performed in different chambers on the same system tool, which may include a chamber in which the operations of the method 200 may be performed.

[0037] Method 200 may include additional operations before the operations listed herein are initiated. For example, the additional processing operations may include forming structures on the substrate, which operations may include both forming and removing materials. The previous processing operations may be performed in the chamber in which method 200 may be performed, or the substrate may be processed in one or more other semiconductor processing chambers before being transferred to the semiconductor processing chamber in which method 200 may be performed. Regardless, method 200 may optionally include transferring the semiconductor substrate to a processing region of a semiconductor processing chamber such as semiconductor processing chamber 100 described above, or to other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a pedestal such as substrate support 104, and may be located in a processing region of the chamber, such as processing volume 120 described above. Method 200 may describe the operations schematically shown in FIGS. 3A to 3H, and the illustrations of FIGS. 3A to 3H will be described with reference to the operations of method 200. It should be understood that FIGS. 3A-3H illustrate only partial schematic diagrams, and that the substrate may contain any number of structural blocks having the aspects illustrated in the figures, as well as alternative structural aspects that may still benefit from the operation of the present technology. Nevertheless, as depicted in FIG. 3A , semiconductor structure 300 may have a number of material layers deposited over substrate 305. Semiconductor structure 300 may be formed from any number of materials, such as a base wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that may be formed during semiconductor processing to cover the substrate.

[0038] As depicted in FIG. 3A , substrate 305 may be any number of materials, such as a base wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that may be formed during semiconductor processing to cover the substrate. In an embodiment, substrate 305 may include a bulk substrate, an epitaxial growth substrate, and / or a silicon-on-insulator wafer. As used herein, the term "semiconductor substrate" refers to a substrate in which the entirety of the substrate is composed of semiconductor material. The semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials used to form a semiconductor structure. For example, the semiconductor layer may include one or more materials, such as crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes a semiconductor material such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination of the foregoing. In one or more embodiments, the substrate 305 includes one or more of the following: silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials that can form the substrate are described herein, any material that can serve as the basis for passive and active electronic components (such as transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic components, or any other electronic components) can fall within the spirit and scope of the present disclosure.

[0039] In an embodiment, the semiconductor material may be a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In an embodiment, any suitable process, such as an ion implantation process, may be used to dope the substrate. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a greater concentration of holes than electrons. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0040] In an embodiment, a previous process may form one or more materials on the substrate 305. For example, in an embodiment, the substrate may be previously processed with alternating pairs of semiconductor material 310 (which may be a silicon-containing material) and sacrificial material 315 (which may be a silicon- and germanium-containing material), which may be suitable for the formation of the device 300 (such as a 3D DRAM structure). As depicted in FIG. 4A, a film stack may be deposited on the substrate 305. The film stack may include multiple cell stacks (such as a three-cell stack in the depicted example), portions of which are sacrificed for forming a 3D DRAM cell. Obviously, this method forms a three-layer 3D DRAM cell. In other examples, cell stacks of the film stack may be repeated to form additional 3D DRAM cell layers. In addition, using one instance of a cell stack in the film stack can form a 3D DRAM cell layer.

[0041] However, in an embodiment, the alternating pairs of silicon-containing material 310 and silicon-and-germanium-containing material 315 formed on the substrate may include greater than 10 alternating pairs of silicon-containing material 310 and silicon-and-germanium-containing material 315, such as greater than 20 alternating pairs, such as greater than 30 alternating pairs, such as greater than 32 alternating pairs, such as greater than 34 alternating pairs, such as greater than 36 alternating pairs, such as greater than 38 alternating pairs, such as greater than 40 alternating pairs, greater than 44 alternating pairs, greater than 48 alternating pairs, greater than 50 alternating pairs, greater than 52 alternating pairs, greater than 56 alternating pairs, greater than 60 alternating pairs, greater than 64 alternating pairs, greater than 68 alternating pairs, greater than 72 alternating pairs, or any range or value therebetween.

[0042] The thickness of each pair, such as the alternating pairs of silicon- and germanium-containing material 315 and silicon-containing material 31, can be greater than or about 30 nm. In this way, sufficient space is provided for accommodating the volume of the insulator discussed below. Thus, in an embodiment, each pair can have a thickness greater than or about 35 nm, such as greater than or about 40 nm, greater than or about 45 nm, greater than or about 50 nm, greater than or about 55 nm, greater than or about 60 nm, greater than or about 65 nm, greater than or about 70 nm, greater than or about 75 nm, greater than or about 80 nm, greater than or about 85 nm, greater than or about 90 nm, greater than or about 95 nm, greater than or about 100 nm, or any range or value therebetween.

[0043] However, unlike previous units, the present technology can provide an increased ratio of semiconductor material layers to sacrificial material layers. That is, the processes and methods discussed herein can provide deposition and etching that are independent of sacrificial layer selectivity. Therefore, since there can be a reduced amount of weak sacrificial layers while maintaining the overall pair thickness required for robust insulator volume formation, the semiconductor structure 300 according to the present technology can exhibit improved mechanical strength and stability.

[0044] In an embodiment, the semiconductor material may have a thickness that is about 10% or greater than the thickness of the sacrificial material layer, such as about 20% or greater, such as about 30% or greater, such as about 40% or greater, such as about 50% or greater, such as about 60% or greater, such as about 70% or greater, such as about 80% or greater, such as about 90% or greater, such as about 100% or greater, such as about 125% or greater, such as about 150% or greater, such as about 175% or greater, such as about 200% or greater, such as about 250% or greater, such as about 300% or greater, such as about 350% or greater, such as about 400% or greater, such as about 450% or greater, such as about 500% or greater, such as about 550% or greater, such as about 600% or greater, such as about 650% or greater, such as about 700% or greater, or any range or value therebetween.

[0045] Due at least in part to the increased thickness of the semiconductor material, the doping content of the sacrificial layer may not be particularly limited. For example, in an embodiment where the sacrificial material is SiGe, the germanium content may be in the range of from about 1% to about 50% by weight of the layer without negatively affecting the structural integrity of the element, such as less than or about 45%, such as less than or about 40%, such as less than or about 35%, such as less than or about 30%, such as less than or about 25%, such as less than or about 20%, such as less than or about 15%, such as less than or about 10%, such as less than or about 5%, or such as greater than or about 2.5%, such as greater than or about 5%, such as greater than or about 7.5%, such as greater than or about 10%, such as greater than or about 15%, such as greater than or about 20%, such as greater than or about 25%, such as greater than or about 30%, such as greater than or about 35%, such as greater than or about 40%, such as greater than or about 45%, or any range or value therebetween. For example, due at least in part to the reduced thickness of the sacrificial material layer(s), a higher percentage of germanium may be present without negatively affecting the mechanical stability of the structure.

[0046] Regardless of the ratio of semiconductor layer 310 to sacrificial layer 315, as depicted in FIG. 3A , semiconductor device 300 may have an access hole 325 formed therein. Although only one access hole 325 is shown, it should be appreciated that more than one access hole may be provided depending on the device and device orientation. Nevertheless, access hole 325 may be formed through one or more cells of semiconductor device 300 to provide access to various layers of the cell. In embodiments, access hole(s) 325 may be formed by any method known in the art. For example, in embodiments, access hole(s) 325 may be patterned using mask 302 and then etched. As depicted, the etch may be any etch suitable for extending through both semiconductor material 310 and sacrificial material 315.

[0047] As depicted in FIG. 3B , operation 205 may optionally include lateral removal of a portion of the sacrificial material 315. By removing a portion of the sacrificial material, one or more additional deposition operations may be performed to form a protective layer 330 ( FIG. 3C ). Although one or more removal processes may be performed at operation 205 based on the selected semiconductor material and sacrificial material, in some embodiments, the etching process is a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process). In an embodiment, the extent to which the sacrificial material 315 is laterally removed is controlled by the duration of the etching process. For example, in an embodiment, the sacrificial material 315 may be laterally removed based on the desired length of the channel and isolation recess. In some embodiments, the selective wet etching process may include hydrofluoric acid (HF), fluoride (F 2), or NH 4OH etchants.

[0048] Although in embodiments, it may not be necessary to initially remove the sacrificial material at operation 205, as will be discussed in more detail below, when used, it may be desirable to at least partially fill the formed recess 335 at optional operation 210. For example, a dielectric material may be filled into the recess 335 using one or more non-line of sight deposition methods such as atomic layer deposition (ALD) and / or chemical vapor deposition (CVD). In embodiments, suitable dielectric materials may include silicon oxide, silicon nitride, combinations thereof, and other dielectrics known in the art.

[0049] By utilizing the optional operation 210, the protective layer 330 may be formed by oxidizing the sidewalls of the access hole 325 at operation 215. That is, by utilizing the optional filling operation 210, the protective layer 330 may be blocked from forming within the recess 335, and may therefore be formed on the vertically extending sidewalls 340 of the access hole 325. Furthermore, by utilizing the optional filling operation 210, the protective layer 330 may be formed using sidewall oxidation or nitridation as known in the art to which the present invention pertains, without requiring extensive processing. Furthermore, after forming the protective layer 330, the dielectric material filled into the recess 335 may be easily removed by one or more selective etching processes, thereby allowing further processing without damaging the protective layer 330. However, in embodiments, one or more cleaning operations, such as a Siconi™ clean, may be required to remove any surface oxide present prior to forming the protective layer 330.

[0050] However, as discussed above, in embodiments, no optional filling operation 210 may be necessary. Instead, directional deposition may be utilized to deposit the protective layer 330 on the vertically extending sidewalls 340 of the access hole 325. Although various deposition methods known in the art to which the present invention pertains may be utilized, in embodiments, the directional deposition operation may include physical vapor deposition (PVD), ion beam deposition (IBD), electron beam (EB) deposition, electron beam ion assisted deposition (EB-IAD), or a combination thereof. Nevertheless, the protective layer 330 may be formed of one or more materials, such as one or more of the dielectric materials discussed above. That is, by utilizing one or more directional deposition operations at operation 215, the protective layer 330 may be primarily formed on the sidewalls 340 of the access hole 325 due to the selection of one or more line-of-sight deposition methods. As a result, little or no protective layer 330 may be formed within the recess 335.

[0051] However, as discussed above, in embodiments, the protective layer 330 may be formed at operation 215 without removing a portion of the sacrificial material at operation 205 or filling the recess formed at operation 210. For example, in embodiments where the sacrificial material is not susceptible to nitridation, as an example, the access hole 325 may undergo a nitridation operation at operation 215 to form the nitrogen-containing protective layer 330. For example, in this example, the protective layer may include silicon nitride. However, it should be understood that one or more additional dielectric formation processes may be utilized based on the materials selected for the sacrificial material and the semiconductor material, provided that the dielectric is formed on the semiconductor material 310 but not on the sacrificial material 315.

[0052] Although the protective layer 330 is formed using a method(s), the method(s) may be performed for a sufficient time to form a protective layer having a thickness of greater than or about 5 Å, such as greater than or about 6 Å, such as greater than or about 7 Å, such as greater than or about 8 Å, such as greater than or about 9 Å, such as greater than or about 10 Å, such as greater than or about 15 Å, such as greater than or about 20 Å, such as greater than or about 30 Å, such as greater than or about 40 Å, such as greater than or about 50 Å, such as greater than or about 75 Å, such as greater than or about 100 Å, such as greater than or about 125 Å, such as greater than or about 150 Å, such as greater than or about 175 Å, such as greater than or about 200 Å, such as greater than or about 250 Å, such as greater than or about 300 Å, such as greater than or about 350 Å, such as greater than or about 400 Å, such as greater than or about 450 Å, such as greater than or about 500 Å, In this manner, the protective layer 330 can have a sufficient thickness to protect the sidewall 340 of the access hole 325 without hindering subsequent operations.

[0053] Thus, regardless of whether a portion of the sacrificial material is removed in operation 205 or the formed recess is filled in operation 210, a protective layer 330 may be formed on the sidewalls 340 (e.g., vertically extending sidewalls) of the access hole 325 as depicted in FIG. 3C. If not completed at operation 205, or if filled at operation 210, operation 220 may include lateral removal of the sacrificial material from at least a portion of the recess 335, or removal of the dielectric material filled at operation 210. In embodiments, the lateral removal may include any one or more of the embodiments discussed above with respect to optional operation 205.

[0054] In such a manner, an etch process specific to the semiconductor material 310 may be utilized in the trimming operation 225, as depicted in FIG. 3D. That is, by utilizing the protective layer 330 discussed herein, a semiconductor material specific etch process may be utilized without reducing the width w of the access hole 325. Further, as discussed above, surprisingly, such a process is also compatible with a relatively thin sacrificial material layer 315. For example, unlike conventional systems where the sacrificial material is only removed to form the channel (e.g., the thickness of the sacrificial material layer determines the maximum thickness of the isolation recess 350 formed), the semiconductor material is etched during trimming.

[0055] Also, surprisingly, the protective layer 330 protects the vertically extending sidewalls 340 of the access hole 325 (e.g., the lateral edges of the formed channel) without inhibiting etching from the corresponding recess 335. Thus, the protective layer 330 advantageously allows etching from within the recess 335 formed by removing sacrificial material while preventing material removal from the lateral edges. In this manner, the width w of the access hole 325 can be maintained while allowing the channel 345 to be thinned, thereby forming a strong isolated recess 350.

[0056] For example, unlike conventional processes and components, the width w of the access hole can generally maintain its originally etched width. Thus, in embodiments, the width of the access hole after the trimming operation 225 can have a width that is about 10% or less, such as about 9% or less, about 8% or less, about 7% or less, about 6% or less, about 5% or less, about 4% or less, about 3% or less, about 2% or less, about 1% or less, or any range or value therebetween, than the width of the access hole before trimming (e.g., the access hole formed by masking and etching as discussed above). As can be appreciated, in embodiments, some width may be lost due to one or more cleaning or removal operations, but most of the width is maintained during trimming.

[0057] Thus, in embodiments, methods according to the present technology can provide excellent channel 345 and isolation 350 thicknesses while also exhibiting improved mechanical stability and increased channel length. For example, the channel width c can be less than or about 50 nm, such as less than or about 45 nm, such as less than or about 40 nm, such as less than or about 35 nm, such as less than or about 30 nm, such as less than or about 25 nm, such as less than or about 20 nm, or such as greater than or about 10 nm, such as greater than or about 12.5 nm, such as greater than or about 15 nm, such as greater than or about 17.5 nm, such as about 10 nm, or any range or value therebetween.

[0058] Furthermore, the isolation width I may be greater than or about 40 nm, such as greater than or about 45 nm, such as greater than or about 50 nm, such as greater than or about 55 nm, such as greater than or about 60 nm, or such as less than or about 100 nm, such as less than or about 95 nm, such as less than or about 90 nm, such as less than or about 85 nm, such as less than or about 80 nm, such as less than or about 75 nm, such as less than or about 70 nm, such as less than or about 65 nm, such as about 60 nm, or any range or value therebetween.

[0059] Surprisingly, the width w of the entry hole can be less than 150 nm, such as less than or about 140 nm, such as less than or about 135 nm, such as less than or about 130 nm, such as less than or about 125 nm, such as less than or about 120 nm, such as less than or about 115 nm, such as less than or about 110 nm, such as less than or about 105 nm, such as less than or about 100 nm, such as less than or about 95 nm, such as less than or about 90 nm, or greater than or about 50 nm, such as greater than or about 55 nm, such as greater than or about 60 nm, such as greater than or about 65 nm, such as greater than or about 70 nm, such as greater than or about 75 nm, such as greater than or about 80 nm, such as greater than or about 85 nm, such as greater than or about 90 nm, such as greater than or about 95 nm, or any range or value therebetween.

[0060] As shown in FIG. 3E , at operation 230, the protective layer 330 may be removed after trimming the isolation recess 350 to a desired size. The protective layer 330 may be removed by any suitable etching process, such as a wet or dry etching process. For example, when the protective layer 330 is silicon nitride, a hot phosphoric acid etching process may be used to remove the protective layer 330.

[0061] After removing the protective layer 330, the semiconductor device 300 can generally re-enter the standard process flow. For example, in an embodiment, a gate oxide 402, a diffusion barrier 404 (such as TiN in an embodiment), one or more gate metals 406 and one or more isolations 408 can be formed in the isolation recess 350, and one or more insulating dielectric materials 410 are formed in the access hole 325, as can be drawn in FIG. 3F, so as to form the capacitor of the semiconductor device 300 in the isolation recess 350 formed.

[0062] However, surprisingly, the methods discussed herein can also be applied to forming transistors on the opposite side of the semiconductor device 300. Therefore, in an embodiment, one or more second access holes 425 can be formed on the outer side 405 of the semiconductor device 300. In addition, a protective layer 430 can be formed along one or more sidewalls 440 of the one or more second access holes 425. And, in an embodiment, according to any one or more of the above methods, the remaining portion of the sacrificial material 315 (if any) can be removed from the recess.

[0063] By utilizing the protective layer 430, which may be formed according to any one or more of the above methods, the remaining portion of the isolation recess 350 may be selectively etched as discussed above, thereby providing a recess 470 to form one or more transistor components, as depicted in FIG. 3G. Surprisingly, by utilizing the protective layer 430, as discussed above, the lateral edges of the channel 445 may be maintained while trimming the transistor recess 470 (e.g., trimming the recess 335 remaining after forming the isolation recess 350). Thus, there may be little or no channel length loss due to the etching process on the capacitor side or the transistor side of the semiconductor device 300.

[0064] Nevertheless, as depicted in FIG. 3H , after the desired channel width and / or isolation recess width is achieved, the protective layer 430 may be removed using any one or more of the methods discussed above. In embodiments, the thickness may be any one or more of the thicknesses discussed above with respect to the channel, recess, and access hole. After removing the protective layer 430, the semiconductor structure 300 may again enter the standard process flow to form the remainder of the transistor components and 3D DRAM capacitor components, such as one or more source / drain regions 480, bit line 482 patterning and filling, electrode 484 formation, etc., in this example. However, as discussed herein, while 3D DRAM has been used as an example, it should be clear that the methods of the present invention are suitable for forming one or more blind recesses in a variety of devices, including high aspect ratio devices.

[0065] In an embodiment, forming the protective layer 330 / 430 may include one or more plasma precursors to the semiconductor structure 300. In an embodiment, the deposition precursor may include at least one nitrogen-containing precursor, at least one oxygen-containing precursor, at least one silicon-containing precursor, combinations thereof, and other dielectric precursors known in the art. The silicon-containing precursor may be or may include silane and disilane, as well as other silicon-containing precursors useful in semiconductor processing. The nitrogen-containing precursor may be or may include ammonia (NH3) and a mixture of molecular nitrogen and hydrogen (N2+H2), as well as other nitrogen-containing precursors useful in semiconductor processing. The deposition precursor may also include one or more carrier gases. Examples of carrier gases may include molecular nitrogen (N2), helium, xenon, or argon, as well as other carrier gases useful in semiconductor processing. The oxygen-containing precursor may be any oxygen-containing material used or useful in semiconductor processing. For example, the oxygen-containing precursor may be or may include vapor (H 2 O), molecular oxygen (O 2), ozone (O 3), nitrous oxide (N 2 O), hydrogen peroxide (H 2 O 2), oxygen-containing plasma, alcohol-based compounds, or alcohol-based plasma.

[0066] Embodiments of method 200 may further include: at operation 215, and optionally at operation 210, generating a plasma effluent of a deposition precursor in a processing region of a semiconductor processing chamber to form a protective layer. The deposition plasma may be generated by delivering plasma power to the deposition precursor that has flowed into the processing region. In some embodiments, the plasma power may be delivered by a radio frequency (RF) power source electrically coupled to at least one electrode in the semiconductor processing chamber. In embodiments, the RF power source may deliver power to the at least one electrode, which generates an electric field in the processing region of the semiconductor processing chamber, which energizes the deposition precursor to form a deposition plasma. The plasma power delivered to the deposition precursor may be less than or about 60 watts, less than or about 55 watts, less than or about 50 watts, less than or about 45 watts, less than or about 40 watts, less than or about 35 watts, less than or about 30 watts, or less. In a non-limiting example, the frequency of the RF power delivered to the deposition precursor may be 13.56 MHz. In some embodiments, the plasma power delivered to the deposition precursor may be supplied continuously, while in other embodiments, the plasma power may be pulsed. In pulsed embodiments, the RF plasma power delivered may have a pulse frequency of less than or about 10 kHz, and may be less than or about 9 kHz, less than or about 8 kHz, less than or about 7 kHz, less than or about 6 kHz, less than or about 5 kHz, less than or about 4 kHz, less than or about 3 kHz, less than or about 2 kHz, less than or about 1 kHz, or less. In some pulsed embodiments, the off portion of the plasma power duty cycle may allow the plasma effluent to be more diffused in the deposited silicon- and nitrogen-containing material. The longer diffusion time of the plasma effluent may result in a more uniform deposited material.

[0067] In embodiments, deposition of the protective layer(s) into the apertures may be performed at a deposition temperature that affects the deposition rate of the material. For example, a processing region of a semiconductor processing chamber may be characterized by a deposition temperature of less than or about 550°C, less than or about 500°C, less than or about 475°C, less than or about 450°C, less than or about 425°C, less than or about 400°C, less than or about 375°C, less than or about 350°C, or less than or about 300°C or less. By depositing at temperatures less than or about 500°C, the present technique may protect device thermal budgets.

[0068] In the foregoing description, for the purpose of explanation, many details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to a person skilled in the art that some embodiments may be practiced without some of these details or with additional details.

[0069] Having disclosed several embodiments, a person of ordinary skill in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. In addition, in order to avoid unnecessarily obscuring the present technology, several well-known processes and components are not described. Therefore, the above description should not be considered to limit the scope of the present technology. In addition, a method or process may be described as being performed sequentially or in steps, but it should be understood that the operations may be performed simultaneously or in an order different from the order listed.

[0070] Where a range of values ​​is provided, it is understood that every intervening value between the upper and lower limits of that range is also specifically disclosed, to the nearest fraction of a unit of the lower limit, unless expressly specified herein. Any narrower range between any stated value or unstated intervening value in the stated range and any other stated value or intervening value in that stated range will be included. The upper and lower limits of such smaller ranges may be independently included or excluded in this range, and each range in which either, neither, or both limits are included in such smaller ranges is also included in the present technology, each of which is subject to any specifically excluded limits in the stated range. Where the stated range includes one or both of the limits, ranges excluding one or both of the included limits are also included. When referring to a measurable value (e.g., an amount, a duration, etc.), the use of "about" and / or "approximately" herein and in the appended claims encompasses variations of ±20%, ±10%, ±5%, or ±0.1% from the specified value, as such variations are suitable for the systems, components, circuits, methods, and other embodiments described herein. When referring to a measurable value, such as an amount, a duration, a physical property (e.g., a frequency), etc., the use of "substantially" herein and in the appended claims also encompasses variations of ±20%, ±10%, ±5%, or ±0.1% from the specified value, as such variations are suitable for the systems, components, circuits, methods, and other embodiments described herein.

[0071] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors and reference to "the layer" includes reference to one or more layers and equivalents thereof known to those of ordinary skill in the art, and so forth.

[0072] Furthermore, when the words “comprise,” “comprising,” “contain,” “include,” and “including” are used in the specification of this case and the scope of the patent claims below, they are intended to specify the existence of stated features, integers, components, or operations, but these words do not exclude the existence or addition of one or more other features, integers, components, operations, actions, or groups.

[0073] 10: Processing System 11: Robotic Arm 12: Front-opening unified transfer box 14: Robotic Arm 16: Low pressure holding area 18a~18f: Semiconductor process chamber 19a~19c: Serial blocks 100:Semiconductor Processing Chamber 102: Chamber body 103:Substrate 104: substrate support 105: Surface of substrate support 106: Cover assembly 108: first electrode 110a, 110b: Isolator 111: Plasma Profile Modulator 112: Gas distributor 114: Entrance 118: Hole 120: Processing volume 122: Second electrode 124: The third electrode 126: Opening 128,136: Tuning circuit 130,138:Electronic sensor 132A,132B:Inductor 134,140: Electronic controller 142: first electric power source 144: Shaft 145: Arrow 146: Catheter 147: Axis 148:Filter 150: second electric power source 152:Export 200: Method 205~230: Operation 300:Semiconductor substrate 302: Mask 305:Substrate 310: Semiconductor Materials 315: Sacrificial Materials 325:Enter hole 330: Protective layer 335: concave part 340: Side wall 345: Channel 350: Isolation recess 402: Gate oxide 404: Diffusion Barrier 405: Outer side 406: Gate Metal 408: Isolation 410: Insulating dielectric material 425: Second entry hole 430: Protective layer 440: Side wall 470: (transistor) recess 480: Source / Drain Region 482: Bit Line 484: Electrode

Claims

1. A semiconductor processing method comprising the steps of: providing a substrate to a processing region of a semiconductor process chamber, wherein the substrate includes one or more alternating pairs of semiconductor material layers and a sacrificial material layer; forming one or more vertically extending features through the one or more alternating pairs of semiconductor material layers and sacrificial material layers, forming one or more sidewalls, the one or more sidewalls including alternating exposed lateral ends of the semiconductor material layers and the sacrificial material layers; forming a protective material layer over the exposed lateral ends of the semiconductor material layers; causing at least a portion of the sacrificial material layer to be laterally recessed from the one or more vertically extending features; trimming a portion of the semiconductor material layer having the protective material layer adjacent to the one or more vertically extending features; and removing the protective material layer after trimming the semiconductor material layer.

2. The semiconductor processing method as claimed in claim 1, wherein the protective material layer is formed by selectively oxidizing or nitriding the exposed lateral end of the semiconductor material.

3. The semiconductor processing method as described in claim 1, wherein the sacrificial material is laterally recessed before the protective material layer is formed.

4. The semiconductor processing method as described in claim 3 further includes the step of: filling the laterally recessed portion of the sacrificial material with a dielectric material.

5. The semiconductor processing method as described in claim 4 further includes the step of removing the dielectric material before finishing.

6. The semiconductor processing method as claimed in claim 1, wherein the protective material layer is formed by directional deposition on the exposed lateral end of the semiconductor material.

7. The semiconductor processing method as described in claim 1, wherein the thickness of the protective material layer is from about 5 Å to about 500 Å.

8. The semiconductor processing method as claimed in claim 1, wherein the semiconductor material layer is a doped silicon material, and the sacrificial material layer comprises silicon germanium.

9. The semiconductor processing method as claimed in claim 1, wherein the one or more vertically extending features have a first width before trimming the semiconductor material layer and a second width after trimming the semiconductor material layer, wherein the second width is approximately 10% or less than the first width.

10. The semiconductor processing method as claimed in claim 1, wherein the thickness of the semiconductor material is approximately 400% or greater than the thickness of the sacrificial material layer.

11. The semiconductor processing method as described in claim 1 further includes the step of: removing the protective material layer after trimming the semiconductor material layer.

12. A semiconductor processing method comprising the steps of: providing a substrate to a processing region of a semiconductor process chamber, wherein the substrate includes one of a plurality of alternating pairs of silicon-containing materials and a silicon-and-germanium-containing material; etching one or more access holes through the alternating pairs of silicon-containing materials and the silicon-and-germanium-containing material to expose lateral ends of the alternating pairs of silicon-containing materials and the silicon-and-germanium-containing material, wherein the etching forms one or more sidewalls, the one or more sidewalls including alternately exposed lateral ends of the alternating pairs of silicon-containing materials and the silicon-and-germanium-containing material; forming a protective material layer over the exposed lateral ends of the silicon-containing material; causing at least a portion of the silicon-and-germanium-containing material to be laterally recessed from the one or more access holes; trimming a portion of the silicon-containing material having the protective material layer adjacent to the access hole; and removing the protective material layer after trimming the silicon-containing material.

13. The semiconductor processing method as described in claim 12, wherein the substrate comprises more than 20 alternating pairs of the silicon-containing material and the silicon-and-germanium-containing material.

14. The semiconductor processing method as described in claim 12, wherein the thickness of the silicon and germanium-containing material is less than or about 30 nm.

15. The semiconductor processing method as described in claim 12, wherein the thickness of the silicon-containing material is approximately 400% or greater than the thickness of the silicon- and germanium-containing material.

16. The semiconductor processing method of claim 12, further comprising the steps of: etching one or more vertically extending features at one end of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials opposite to the exposed lateral ends, thereby exposing the outer ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials, wherein the etching removes at least a portion of the alternating pairs and forms one or more outer sidewalls, the one or more outer sidewalls including the alternately exposed outer ends of the alternating pairs of silicon-containing materials and silicon-and-germanium-containing materials; and forming a second protective layer over the exposed outer ends of the silicon-containing materials.

17. The semiconductor processing method as claimed in claim 16 further comprises the step of: causing at least a portion of the silicon and germanium-containing material to be laterally recessed from the one or more vertically extending features.

18. The semiconductor processing method as described in claim 17 further includes the step of trimming a portion of the silicon-containing material adjacent to the access hole.

19. A method of forming a three-dimensional dynamic random access memory (3D DRAM) device, comprising the steps of: providing a substrate to a processing region of a semiconductor process chamber, wherein the substrate includes one or more alternating pairs of silicon-containing material layers and a silicon-and-germanium-containing material layer; forming one or more access vias through the one or more alternating pairs of silicon-containing material layers and the silicon-and-germanium-containing material layers to form one or more sidewalls, the one or more sidewalls including alternating exposed lateral ends of the silicon-containing material layers and the silicon-and-germanium-containing material layers; forming a protective material layer over the exposed lateral ends of the silicon-containing material layers; causing at least a portion of the silicon-and-germanium-containing material layers to be laterally recessed from the one or more access vias; trimming a portion of the silicon-containing material layer having the protective material layer adjacent to the one or more access vias; and removing the protective material layer after trimming the silicon-containing material layer.

20. The method of claim 19 further comprises the steps of: etching one or more vertically extending features at one end of the alternating silicon-containing material layer and the silicon-and-germanium-containing material layer opposite to the exposed lateral ends, thereby exposing the outer ends of the alternating silicon-containing material layer and the silicon-and-germanium-containing material layer, wherein the etching removes at least a portion of the alternating pair and forms one or more outer sidewalls, the one or more outer sidewalls including the alternately exposed outer ends of the alternating silicon-containing material layer and the silicon-and-germanium-containing material layer; and forming a second protective layer over the exposed outer ends of the silicon-containing material.

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