Substrate wiring structure, integrated circuit board and electronic equipment

Abstract

This application relates to a substrate wiring structure, an integrated circuit board, and an electronic device. The substrate wiring structure includes a substrate body, on which a plurality of first buried vias and a plurality of second buried vias extending along the thickness direction of the substrate body are formed. The plurality of first buried vias are spaced apart in a first direction; the plurality of second buried vias are spaced apart from the first buried vias in a second direction, and at least one second buried via is located between two adjacent first buried vias in the first direction, wherein the first direction is perpendicular to the second direction. This arrangement effectively increases the distance between two adjacent first buried vias in the first direction and spaces the second buried vias apart from the first buried vias in the second direction, thereby at least partially reducing crosstalk between buried vias on the substrate body.

Description

Technical Field

[0001] This application relates to the technical field of substrate design, and specifically, to a substrate wiring structure, an integrated circuit board, and an electronic device. Prior Art

[0002] This application claims the priority of a Chinese patent application with the application number 202311361794.X and the invention title "Substrate Wiring Structure, Integrated Circuit Board, and Electronic Device" filed on October 19, 2023, and a Chinese patent application with the application number 202322816479.3 and the invention title "Substrate Wiring Structure, Integrated Circuit Board, and Electronic Device" filed on October 19, 2023. The entire content of which is incorporated herein by reference.

[0003] The substrate wiring structure of BGA (Ball Grid Array) packaging is mostly designed with HDI (High Density Interconnection). When the conventional substrate wiring structure is applied to the layout of a compact ballmap (ball pin definition), since it is impossible to increase the distance between adjacent buried vias of high-speed signals, the distance between the buried vias of different signals will be very close. And the crosstalk between buried vias is the main contributing factor to the crosstalk between substrate signal holes. Therefore, the crosstalk between signal holes is relatively large. The higher the signal rate, for example, when the rate is greater than 2.5 Gbps, the greater the impact of the crosstalk between buried vias on the signal quality. Summary of the Invention

[0004] The purpose of this application is to provide a substrate wiring structure, an integrated circuit board, and an electronic device to at least partially solve the related technical problems.

[0005] To achieve the above purpose, in the first aspect of the embodiments of this application, a substrate wiring structure is provided, including a substrate body, the substrate body is formed with a plurality of first buried vias and a plurality of second buried vias extending along the thickness direction of the substrate body, and the plurality of first buried vias are spaced apart in a first direction;

[0006] The plurality of second buried vias are arranged at intervals with the first buried vias in a second direction, and at least one of the second buried vias is located between two adjacent first buried vias in the first direction, where the first direction is perpendicular to the second direction.

[0007] Optionally, in the first direction, the first buried via is located between two adjacent second buried vias and / or the second buried via is located between two adjacent first buried vias.

[0008] Optionally, a plurality of solder ball mounting portions are formed on a first side surface in the thickness direction of the substrate body. The plurality of solder ball mounting portions are used for solder ball connection and are arranged at intervals along the first direction;

[0009] The extension lines of the central axes of the plurality of first buried vias pass through the centers of some of the solder ball mounting portions; and / or,

[0010] The connection line between the first center and the second center is parallel to the second direction, where the first center is the center of the second buried via located between two adjacent first buried vias in the first direction; the second center is the center of the solder ball mounting portion between the solder ball mounting portions corresponding to the two adjacent first buried vias.

[0011] Optionally, the first distance between at least some of the first buried vias and the second buried vias is greater than the second distance between two adjacent solder ball mounting portions in the first direction, where the first distance is the distance between the adjacent second buried via and the first buried via; the second distance is the distance between two adjacent solder ball mounting portions in the first direction.

[0012] Optionally, the distance between two adjacent first buried vias in the first direction is equal to the distance between two adjacent second buried vias.

[0013] Optionally, the plurality of first buried vias are formed into a plurality of first buried via groups arranged at intervals in the first direction. Each first buried via group includes at least two first buried vias arranged at intervals in the second direction;

[0014] The plurality of second buried vias are formed into a plurality of second buried via groups arranged at intervals in the first direction. Each second buried via group includes at least two second buried vias arranged at intervals in the second direction.

[0015] Optionally, the substrate wiring structure further includes a chip, and the chip is connected to the second side surface of the substrate body through a solder bump;

[0016] The solder ball mounting portions on the first side surface of the substrate body are connected with solder balls.

[0017] Optionally, a plurality of micro-holes are further formed in the substrate body, and one end of the first buried hole is connected to the solder ball mounting portion on the first side surface of the substrate body through the micro-holes; the other end of the first buried hole is connected to the welding bumps on the second side surface of the substrate body opposite to the first side surface through the micro-holes.

[0018] One end of the second buried hole is connected to the solder ball mounting portion on the first side surface of the substrate body through the micro-holes; the other end of the second buried hole is connected to the welding bumps on the second side surface of the substrate body opposite to the first side surface through the micro-holes.

[0019] In a second aspect of the embodiments of the present application, an integrated circuit board is provided, and the integrated circuit board includes the substrate wiring structure provided in the first aspect of the embodiments of the present application.

[0020] In a third aspect of the embodiments of the present application, an electronic device is further provided, and the electronic device includes the integrated circuit board provided in the second aspect of the embodiments of the present application.

[0021] Through the above technical solutions, that is, the substrate wiring structure of the present application, by arranging a plurality of first buried holes at intervals in the first direction, and arranging a plurality of second buried holes at intervals from the first buried holes in a second direction perpendicular to the first direction, and at least one second buried hole is located between two adjacent first buried holes in the first direction. It can also be understood that a part of the plurality of first buried holes arranged at intervals in the first direction is moved a certain distance in the second direction to form the second buried hole, and the second buried hole is arranged at intervals from the first buried hole in the second direction. Through the above arrangement, it is equivalent to increasing the distance between two adjacent first buried holes in the first direction, and arranging the second buried hole at intervals from the first buried hole in the second direction, which can at least partially reduce the crosstalk between the buried holes on the substrate body.

[0022] Other features and advantages of the present application will be described in detail in the following specific implementation manners. Brief Description of the Drawings

[0023] The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the specification, and are used to explain the present application together with the following specific implementation manners, but do not constitute a limitation to the present application. In the accompanying drawings:

[0024] FIG. 1 is a schematic diagram of a BGA package substrate wiring structure in the related art.

[0025] FIG. 2 is a schematic diagram of a substrate signal layer-changing structure in the related art, where n is the number of substrate layers.

[0026] FIG. 3 shows the distribution of signal buried vias corresponding to the conventional wiring structure in an embodiment of the related art.

[0027] FIG. 4 shows the distribution of signal buried vias corresponding to the conventional wiring structure in another embodiment of the related art.

[0028] FIG. 5 shows the distribution of signal buried vias corresponding to the wiring structure in the substrate wiring structure provided by an exemplary embodiment of the present application.

[0029] FIG. 6 shows the distribution of signal buried vias corresponding to the wiring structure in the substrate wiring structure provided by another exemplary embodiment of the present application.

[0030] FIG. 7 is a schematic diagram of a substrate signal layer-changing structure in the substrate wiring structure provided by an exemplary embodiment of the present application, where n is the number of substrate layers. Embodiment

[0031] The following describes the specific embodiments of the present application in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining and illustrating the present application, and are not used to limit the present application.

[0032] In the present application, unless otherwise stated, the orientation terms such as "row, column" usually refer to the rows and columns of the corresponding drawings, that is, the first direction is the row and the second direction is the column; "depth, shallowness" refer to the depth and shallowness of the out-layer lines of the corresponding signal vias. In the accompanying drawings of the specification, X represents the first direction, Y represents the second direction, Z represents the thickness direction of the substrate body, and the first direction and the second direction are two mutually perpendicular directions in a plane perpendicular to the thickness direction of the substrate body. In addition, the terms "first", "second", etc. used in the present application are used to distinguish one element from another element, and do not have sequence and importance. In addition, in the following description, when referring to the drawings, unless otherwise explained, the same reference numerals in different drawings represent the same or similar elements. The above definitions are only for explaining and illustrating the present application, and should not be construed as a limitation to the present application.

[0033] The substrate wiring structure 10 of the BGA package is shown in FIG. 1. Among them, the signals on the substrate body 100 need to be connected from the bumps (soldering bumps 110) on the top layer to the balls (solder balls 120) on the bottom layer, so it is necessary to drill holes and change layers on the substrate body 100. The substrates of BGA packages are mostly HDI designs.

[0034] As shown in FIG. 2, the conventional substrate wiring structure is that the bump (solder bump 110) directly leads from the top layer to the solder ball 120 area at the bottom layer, or first drills one or more micro-holes 105 to the inner layer (above L(n / 2)), and then leads the wire to the 120 area, that is, the bump (solder bump 110) is connected to the L(n / 2) layer through the micro-hole 105, and then through the buried hole 101 and the micro-hole 105 to change layers to the Ln layer, and is connected to the solder ball 120, so that the buried hole 101 coincides with the back ball (solder ball 120) in the thickness direction of the substrate. As shown in FIGS. 3 and 4, they are schematic diagrams of the arrangement of the buried holes 101 for single-ended signals and differential signals, respectively.

[0035] This wiring structure is not suitable for the compact signal ball (solder ball) arrangement: it will cause the distance between the buried holes of different signals to be very close, and the crosstalk between the buried holes is the main contributing factor to the crosstalk between the signal holes, that is, the conventional substrate wiring structure will cause large crosstalk between the signal holes in the compact signal ball arrangement. The higher the signal rate, for example, when the rate is greater than 2.5 Gbps, the greater the impact of the crosstalk between the buried holes on the signal quality.

[0036] The purpose of the present application is to provide a substrate wiring structure 10, an integrated circuit board, and an electronic device to at least partially solve the above problems.

[0037] As shown in FIGS. 5 to 7, in order to achieve the above object, in some embodiments of the present application, a substrate wiring structure 10 is provided. The substrate wiring structure 10 includes a substrate body 100. The substrate body 100 is formed with a plurality of first buried holes 102 and a plurality of second buried holes 103 extending along the thickness direction of the substrate body 100. The plurality of first buried holes 102 are arranged at intervals in the first direction X; the plurality of second buried holes 103 are arranged at intervals from the first buried holes 102 in the second direction Y, and at least one second buried hole 103 is located between two adjacent first buried holes 102 in the first direction, wherein the first direction is perpendicular to the second direction.

[0038] Through the above technical solution, that is, the substrate wiring structure 10 of the present application, by arranging a plurality of first buried vias 102 at intervals in the first direction, and arranging a plurality of second buried vias 103 at intervals in the second direction perpendicular to the first direction with respect to the first buried vias 102, and at least one second buried via 103 is located between two adjacent first buried vias 102 in the first direction. It can also be understood that a part of the plurality of first buried vias 102 arranged at intervals in the first direction is moved a certain distance in the second direction to form the second buried vias 103, and the second buried vias 103 and the first buried vias 102 are arranged at intervals in the second direction. Through the above arrangement, it is equivalent to increasing the distance between two adjacent first buried vias 102 in the first direction, and arranging the second buried vias 103 at intervals in the second direction with respect to the first buried vias 102, which can at least partially reduce the crosstalk between the plurality of buried vias.

[0039] In some embodiments of the present application, in the first direction, the first buried via 102 is located between two adjacent second buried vias 103 and / or the second buried via 103 is located between two adjacent first buried vias 102.

[0040] As shown in FIGS. 5 and 6, a plurality of first buried vias 102 are arranged at intervals in the first direction, a plurality of second buried vias 103 are arranged at intervals in the first direction, and the plurality of second buried vias 103 and the plurality of first buried vias 102 are arranged at intervals in the second direction. In other words, the plurality of first buried vias 102 are arranged in a row in the first direction in sequence, and the plurality of second buried vias 103 are also arranged in a row in the first direction in sequence, and the plurality of second buried vias 103 and the plurality of first buried vias 102 are not in the same row, which can be applied to single-ended signals. In the first direction, each second buried via 103 is located between two adjacent first buried vias 102, that is, in the first direction X of the drawing in FIG. 5, each second buried via 103 is located between two adjacent first buried vias 102. Similarly, in the first direction, each first buried via 102 is located between two adjacent second buried vias 103, so that the first buried vias 102 and the second buried vias 103 are arranged alternately in the first direction and at intervals in the second direction, thereby reducing the crosstalk between each other to a certain extent.

[0041] In some embodiments, on the first side 100a in the thickness direction of the substrate body 100, a plurality of solder ball mounting parts 104 for connecting the solder balls 120 are formed at intervals in the first direction; the extension lines of the central axes of the plurality of first buried vias 102 pass through the centers of some of the solder ball mounting parts 104. Among them, on the first side 100a in the thickness direction of the substrate body 100, a plurality of solder ball mounting parts 104 are formed, the plurality of solder ball mounting parts 104 are used for connecting the solder balls 120, and the plurality of solder ball mounting parts 104 are arranged at intervals in the first direction.

[0042] In some embodiments, the line connecting the center of the second buried via 103 between two adjacent first buried vias 102 in the first direction and the center of the solder ball mounting portion 104 between the solder ball mounting portions 104 corresponding to the two adjacent first buried vias 102 is parallel to the second direction. That is to say, the line connecting the first center and the second center is parallel to the second direction, where the first center is the center of the second buried via 103 between two adjacent first buried vias 102 in the first direction; the second center is the center of the solder ball mounting portion 104 between the solder ball mounting portions 104 corresponding to the two adjacent first buried vias 102.

[0043] As shown in FIG. 5, the solder ball mounting portions 104 can be arranged in a row in the first direction, and the distance between two adjacent solder ball mounting portions 104 is equal to half of the distance between two adjacent first buried vias 102 in the first direction. Among them, the first buried vias 102 correspond to the solder ball mounting portions 104 in the odd rows in the thickness direction of the substrate body 100, that is, the extension lines of the central axes of the plurality of first buried vias 102 pass through the centers of the solder ball mounting portions 104 in the odd rows. In addition, the solder ball mounting portions 104 in the even rows are aligned with the second buried vias 103 in the second direction and correspond one by one. Through the above arrangement, a plurality of solder ball mounting portions 104 arranged at intervals in the first direction are formed on the first side 100a of the substrate body 100 for soldering the solder balls 120. By arranging the second buried vias 103 in the even rows at intervals from the first buried vias 102 in the odd rows in the second direction, compared with the related art, the crosstalk between the buried vias 101 can be reduced.

[0044] It should be noted that the extension lines of the central axes of the plurality of first buried vias 102 may not pass through the centers of some solder ball mounting portions 104. The first buried vias 102 can be near the solder balls 120, that is, there is a certain deviation in the distance between the central axis of the first buried via 102 and the center of the solder ball 120.

[0045] In addition, it is exemplary that the line connecting the center of the second buried hole 103 located between two adjacent first buried holes 102 in the first direction and the center of the solder ball mounting portion 104 corresponding to the two adjacent first buried holes 102 is parallel to the second direction. In other embodiments, the second buried holes may be arranged at any suitable position having a certain distance from the first buried holes. For example, all or part of the plurality of second buried holes 103 may be offset upward or downward in the first direction, or the line connecting the center of the second buried hole 103 located between two adjacent first buried holes 102 in the first direction and the center of the solder ball mounting portion 104 corresponding to the two adjacent first buried holes 102 is not parallel to the second direction, such as intersecting.

[0046] In yet another embodiment, the distance between at least some of the adjacent second buried holes 103 and the first buried holes 102 is greater than the distance between two adjacent solder ball mounting portions 104 in the first direction. That is, the first distance L1 between at least some of the first buried holes 102 and the second buried holes 103 is greater than the second distance L2 between two adjacent solder ball mounting portions 104 in the first direction, where the first distance is the distance between the adjacent second buried hole 103 and the first buried hole 102; the second distance is the distance between two adjacent solder ball mounting portions 104 in the first direction. In the related art, each buried hole 101 corresponds to the solder ball mounting portion 104 in the thickness direction of the substrate body 100. In the embodiments of the present application, the second buried holes 103 are arranged at intervals from the first buried holes 102 in the second direction. At the same time, the first distance L1 between some adjacent second buried holes 103 and the first buried holes 102 is greater than the second distance L2 between two adjacent solder ball mounting portions 104 in the first direction. On the one hand, it is equivalent to increasing the center distance between some adjacent first buried holes 102 in the first direction. On the other hand, the center distance between the second buried holes 103 and the first buried holes 102 is also not less than the distance in the conventional wiring structure, which can further reduce the crosstalk between the buried holes 101.

[0047] In still other embodiments, the distance between all adjacent second buried vias 103 and first buried vias 102 is greater than the distance between two adjacent solder ball mounting portions 104 in the first direction, that is, the first distance L1 between the centers of adjacent second buried via 103 and first buried via 102 is greater than the second distance L2 between the centers of two adjacent solder ball mounting portions 104 in the first direction. That is to say, the center distance between the closest second buried via 103 and the first buried via 102 is greater than the center distance between two adjacent solder ball mounting portions 104 in the first direction. Compared with the conventional solution, arranging the distance between the centers of some or all of the second buried vias 103 and the first buried vias 102 to be greater than the center distance between the two solder ball mounting portions 104 can achieve the effect of reducing crosstalk.

[0048] It should be noted that the distance between the buried vias in this application generally refers to the distance between the centers of two adjacent buried vias. For example, L1 refers to the distance between the center of the adjacent second buried via 103 and the center of the first buried via 102; L2 refers to the distance between the centers of two adjacent solder ball mounting portions 104 in the first direction.

[0049] In yet another embodiment, the distance between two adjacent first buried vias 102 in the first direction is equal to the distance between two adjacent second buried vias 103. That is to say, the distance between the centers of two adjacent first buried vias 102 in the first direction is equal to the distance between the centers of two adjacent second buried vias 103.

[0050] Considering that during BGA packaging, a plurality of solder balls 120 on the first side 100a of the substrate body 100 are evenly arranged, and at the same time, ensuring the arrangement between the first buried via 102 and the second buried via 103 can make the crosstalk on the entire substrate more uniform. Therefore, the solder ball mounting portions 104 on the first side 100a of the substrate body 100 are evenly arranged along the first direction. At the same time, the first buried vias 102 and the second buried vias 103 are also evenly arranged in the first direction. The distance between two adjacent first buried vias 102 is equal to the distance between two adjacent second buried vias 103, and the distance L3 between two adjacent first buried vias 102 is equal to twice the second distance L2 between two adjacent solder ball mounting portions 104, that is, L3 = 2L2.

[0051] It can be understood that the multiple solder balls 120 located on the first side 100a of the substrate body 100 can also be arranged in other implementable ways, such that the first buried via 102 corresponds to some of the solder balls 120 in the thickness direction of the substrate body 100. The second buried via 103 can be arranged in other forms to stagger a certain distance from the first buried via 102, so as to at least partially reduce the crosstalk with the first buried via 102. For example, the distance between two adjacent first buried vias 102 can be different from the distance between two adjacent second buried vias 103, or the distance L3 between two adjacent first buried vias 102 is greater than or less than twice the second distance L2 between two adjacent solder ball mounting portions 104, etc.

[0052] It can be understood that considering various limitations of the substrate wiring space, the first buried vias 102 and the second buried vias 103 do not necessarily have to be evenly arranged in the first direction, and at the same time, the second buried vias do not necessarily have to be aligned in the second direction, as long as L1 > L2 is ensured. As long as the center distance between the first buried via 102 and the second buried via 103 is increased compared with the existing solution, it can be considered that it has a better effect compared with the related art.

[0053] As shown in FIGS. 6 and 7, in some other embodiments of the present application, multiple first buried vias 102 form multiple first buried via groups 102a arranged at intervals in the first direction, and each first buried via group 102a includes at least two first buried vias 102 arranged at intervals in the second direction; multiple second buried vias 103 form multiple second buried via groups 103a arranged at intervals in the first direction, and each second buried via group 103a includes at least two second buried vias 103 arranged at intervals in the second direction.

[0054] Among them, in the second direction, there are multiple first buried vias 102 and second buried vias 103. For example, both the first buried vias 102 and the second buried vias 103 are two, corresponding to differential signals. As shown in FIG. 7, in each row, two first buried vias 102 form a first buried via group 102a, and two second buried vias 103 form a second buried via group 103a. Multiple first buried via groups 102a and second buried via groups 103a form two columns in the first direction, and the second buried via groups 103a and the first buried via groups 102a are arranged in a staggered manner in the first direction. At this time, the solder ball mounting portions 104 on the first side 100a of the substrate body 100 are also correspondingly set as solder ball mounting portion groups 104a, and each solder ball mounting portion group 104a includes two solder ball mounting portions 104 arranged at intervals, corresponding to the first buried via group 102a and the second buried via group 103a respectively.

[0055] It should be noted that to ensure the crosstalk effect between multiple first buried vias 102 and second buried vias 103 in the same group, the center-to-center distance of multiple first buried vias 102 in the second direction in each first buried via group 102a is not less than the center-to-center distance between two adjacent solder ball mounting parts 104 in the first direction. Similarly, the center-to-center distance of multiple second buried vias 103 in the second direction in each second buried via group 103a is not less than the center-to-center distance between two adjacent solder ball mounting parts 104 in the first direction. It can be understood that the center-to-center distance of multiple first buried vias 102 in the second direction in each first buried via group 102a refers to the center-to-center distance between two adjacent first buried vias 102 in the second direction included in the first buried via group 102a. The center-to-center distance of multiple second buried vias 103 in the second direction in each second buried via group 103a refers to the center-to-center distance between two adjacent second buried vias 103 in the second direction included in the second buried via group 103a.

[0056] In another embodiment, the substrate wiring structure 10 further includes a chip 20. The chip 20 is connected to the second side 100b of the substrate body 100 through a solder bump 110. The solder ball mounting part 104 on the first side 100a of the substrate body 100 is connected to a solder ball 120. Among them, the substrate body 100 includes a first side 100a and a second side 100b that are oppositely arranged in its thickness direction. The chip 20 is connected to the second side 100b of the substrate body 100 through a solder bump 110. Multiple solder ball mounting parts 104 are provided on the first side 100a of the substrate body 100, and each solder ball mounting part 104 is mounted with a solder ball 120. Among them, multiple solder balls 120 can be multiple arranged along the first direction and one arranged at intervals along the second direction, corresponding to a single-ended signal, or two arranged at intervals along the second direction, corresponding to a differential signal.

[0057] In some embodiments, the substrate body 100 further forms multiple micro vias 105. One end of the first buried via 102 is connected to the solder ball mounting part 104 on the first side 100a of the substrate body 100 through the micro via 105; the other end of the first buried via 102 is connected to the solder bump 110 on the second side 100b of the substrate body 100 opposite to the first side 100a through the micro via 105. One end of the second buried via 103 is connected to the solder ball mounting part 104 on the first side 100a of the substrate body 100 through the micro via 105; the other end of the second buried via 103 is connected to the solder bump 110 on the second side 100b of the substrate body 100 opposite to the first side 100a through the micro via 105.

[0058] As shown in FIG. 6, the solder bump 110 is connected to the L1 layer (the second side 100b) of the substrate body 100 to the La layer through a micro via 105, and then connected to the upper end of the first buried via 102 in the L(n / 2) layer through a micro via 105. The lower end of the first buried via 102 is connected to the solder ball mounting portion 104 and the solder ball 120 of the Ln layer (the first side 100a) of the substrate body 100 through a micro via 105 at the lower end of the first buried via 102 in the L(n / 2 + 1) layer. In addition, the solder bump 110 is connected to the L1 layer (the second side 100b) of the substrate body 100 to the La layer through a micro via 105, and then connected to the upper end of the second buried via 103 in the L(n / 2) layer through a micro via 105. The lower end of the second buried via 103 is connected to the solder ball mounting portion 104 and the solder ball 120 of the Ln layer (the first side 100a) of the substrate body 100 through a micro via 105 at the lower end of the second buried via 103 in the L(n / 2 + 1) layer. Therefore, the first buried via 102 and the second buried via 103 are arranged at intervals in the second direction. Therefore, crosstalk can be reduced compared with the conventional arrangement.

[0059] In the second aspect of the embodiment of the present application, an integrated circuit board is provided. The integrated circuit board includes the above-mentioned substrate wiring structure 10 provided by the embodiment of the present application. Therefore, the integrated circuit board also has all the advantages of the above-mentioned substrate wiring structure 10, which will not be elaborated here.

[0060] It can be understood that the integrated circuit board can be any compact high-speed ballmap arranged circuit board. In addition, the substrate wiring structure 10 can be applied to single-ended signals or differential signals.

[0061] On the third party side of the embodiment of the present application, an electronic device is also provided. The electronic device includes the above-mentioned integrated circuit board provided by the embodiment of the present application. It should be noted that the electronic device includes computers, mobile phones, tablet computers, wearable devices, etc.

[0062] As shown in the distribution diagram of the buried via 101 under the conventional substrate wiring structure in FIG. 3, it can be seen that the distance between adjacent single-ended buried vias 101 is equal to the distance between the balls (solder balls 120). As shown in FIG. 5, in the novel wiring structure of the substrate wiring structure 10 proposed by the present application, half of the single-ended buried vias 101 are moved out of the area of the balls (solder balls 120). These half of the single-ended buried vias 101 can be the odd-row single-ended buried vias 101 in FIG. 5 or the even-single-ended buried vias 101 in FIG. 5.

[0063] As shown in FIG. 4, which is a distribution diagram of blind vias 101 under a conventional substrate wiring structure, it can be seen that the distance between adjacent blind vias 101 of differential pairs is equal to the distance between balls (solder balls 120). As shown in FIG. 7, the novel wiring structure of the substrate wiring structure 10 proposed in this application moves the blind vias 101 of half of the differential pairs out of the area of the balls (solder balls 120). These half of the differential pairs can be the odd-row differential pairs in FIG. 7 or the even-row differential pairs in FIG. 7.

[0064] For the substrate wiring structure 10, integrated circuit board, and electronic device of this application, at least part (half or all) of the blind vias 101 (single-ended signal blind vias 101 or differential signal blind vias 101) are moved out of the signal BALL (solder ball 120) area (solder ball mounting part 104 area) in an equally spaced manner, doubling the distance between the blind vias 101 between differential pairs, so as to achieve the purpose of reducing crosstalk between vias. The preferred embodiments of this application have been described in detail above in conjunction with the accompanying drawings. However, this application is not limited to the specific details in the above embodiments. Within the scope of the technical concept of this application, various simple modifications can be made to the technical solutions of this application, and these simple modifications all fall within the protection scope of this application.

[0065] In addition, it should be noted that, among the various specific technical features described in the above specific embodiments, without conflict, they can be combined in any suitable manner. To avoid unnecessary repetition, this application will not separately describe various possible combination methods.

[0066] In addition, any combination can be made between various different embodiments of this application, as long as it does not violate the idea of this application, and it should also be regarded as the content disclosed in this application.

[0067] 10: Substrate wiring structure 20: Chip 100: Substrate body 100a: First side 100b: Second side 101: Blind via 102: First blind via 102a: First blind via group 103: Second blind via 103a: Second blind via group 104: Solder ball mounting part 105: Micro via 110: Solder bump 120: Solder ball

Claims

1. A substrate wiring structure, wherein, The system includes a substrate body having a plurality of first buried vias and a plurality of second buried vias extending along the thickness direction of the substrate body. The plurality of first buried vias are spaced apart in a first direction. The plurality of second buried vias are spaced apart from the first buried vias in a second direction, and at least one of the second buried vias is located between two adjacent first buried vias in the first direction, wherein the first direction is perpendicular to the second direction. The plurality of first buried vias are formed in a plurality of first buried via groups spaced apart in the first direction, each first buried via group including at least two first buried vias arranged adjacently in the second direction. The plurality of second buried vias are formed in a plurality of second buried via groups spaced apart in the first direction, each second buried via group including at least two second buried vias arranged adjacently in the second direction. The plurality of first buried via groups and the plurality of second buried via groups form two columns in the first direction, and the second buried via groups and the first buried via groups are arranged in an alternating manner in the first direction. A column of second buried via groups and a column of first buried via groups are spaced apart and adjacent in the second direction, and there are neither first buried vias nor second buried vias between a column of second buried via groups and a column of first buried via groups.

2. The substrate wiring structure as described in claim 1, wherein, In the first direction, the first buried hole is located between two adjacent second buried holes and / or the second buried hole is located between two adjacent first buried holes.

3. The substrate wiring structure as described in claim 1 or 2, wherein, The first side surface of the substrate body in the thickness direction has a plurality of solder ball mounting portions, which are used for solder ball connection and are spaced apart along the first direction; the extension line of the central axis of the plurality of first buried vias passes through the center of a portion of the solder ball mounting portion; and / or, the line connecting the first center and the second center is parallel to the second direction, wherein the first center is the center of the second buried via located between two adjacent first buried vias in the first direction; and the second center is the center of the solder ball mounting portion between the solder ball mounting portions corresponding to the two adjacent first buried vias.

4. The substrate wiring structure as described in claim 3, wherein, At least a portion of the first buried via and the second buried via have a first distance greater than a second distance between two adjacent solder ball mounting portions in the first direction, wherein the first distance is the distance between adjacent second buried vias and the first buried via; and the second distance is the distance between two adjacent solder ball mounting portions in the first direction.

5. The substrate wiring structure as described in claim 3, wherein, The distance between two adjacent first buried holes in the first direction is equal to the distance between two adjacent second buried holes.

6. The substrate wiring structure as described in claim 3, wherein, The substrate wiring structure also includes a chip, which is connected to the second side of the substrate body via solder bumps; the solder ball mounting portion on the first side of the substrate body is connected with solder balls.

7. The substrate wiring structure as described in claim 6, wherein, The substrate body also has a plurality of microholes. One end of the first buried hole is connected to the solder ball mounting portion on the first side of the substrate body through the microhole. The other end of the first buried hole is connected to the solder bump on the second side of the substrate body opposite to the first side through the microhole. One end of the second buried hole is connected to the solder ball mounting portion on the first side of the substrate body through the microhole. The other end of the second buried hole is connected to the solder bump on the second side of the substrate body opposite to the first side through the microhole.

8. An integrated circuit board, wherein, The integrated circuit board includes a substrate wiring structure; the substrate wiring structure includes a substrate body, the substrate body having a plurality of first buried vias and a plurality of second buried vias extending along the thickness direction of the substrate body, the plurality of first buried vias being spaced apart in a first direction; the plurality of second buried vias being spaced apart from the first buried vias in a second direction, and at least one second buried via being located between two adjacent first buried vias in the first direction, wherein the first direction is perpendicular to the second direction; wherein the plurality of first buried vias form a plurality of first buried via groups spaced apart in the first direction, each first buried via group including at least two first buried vias arranged adjacently in the second direction; the plurality of second buried vias form a plurality of second buried via groups spaced apart in the first direction, each second buried via group including at least two second buried vias arranged adjacently in the second direction; The plurality of first buried hole groups and the plurality of second buried hole groups form two columns in the first direction, and the second buried hole groups and the first buried hole groups are arranged in an alternating manner in the first direction. A column of second buried hole groups and a column of first buried hole groups are adjacent to each other in the second direction, and there are neither first buried holes nor second buried holes between a column of second buried hole groups and a column of first buried hole groups.

9. An electronic device, wherein, The electronic device includes an integrated circuit board; the integrated circuit board includes a substrate wiring structure; the substrate wiring structure includes a substrate body, the substrate body having a plurality of first buried vias and a plurality of second buried vias extending along the thickness direction of the substrate body, the plurality of first buried vias being spaced apart in a first direction; the plurality of second buried vias being spaced apart from the first buried vias in a second direction, and at least one second buried via being located between two adjacent first buried vias in the first direction, wherein the first direction is perpendicular to the second direction; wherein the plurality of first buried vias form a plurality of first buried via groups spaced apart in the first direction, each first buried via group including at least two first buried vias arranged adjacently in the second direction; the plurality of second buried vias form a plurality of second buried via groups spaced apart in the first direction, each second buried via group including at least two second buried vias arranged adjacently in the second direction; The plurality of first buried hole groups and the plurality of second buried hole groups form two columns in the first direction, and the second buried hole groups and the first buried hole groups are arranged in an alternating manner in the first direction. A column of second buried hole groups and a column of first buried hole groups are adjacent to each other in the second direction, and there are neither first buried holes nor second buried holes between a column of second buried hole groups and a column of first buried hole groups.

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