Integrated device for electrostatic discharge and method for forming the same

Abstract

Some embodiments relate to integrated elements, including: a resistor-capacitor structure coupled in series between a high-voltage line and a low-voltage line, the resistor-capacitor structure having a first node electrically coupled to a resistor and a capacitor; a transistor including a first source / drain terminal coupled to the high-voltage line, a second source / drain terminal coupled to the low-voltage line, and a gate terminal; and a diode coupled between the gate terminal and the high-voltage line or the low-voltage line.

Description

Prior Technology

[0001] An integrated circuit (IC) comprises various circuit elements that perform functions at different points in the circuitry. These elements utilize the voltage difference between high-voltage and low-voltage lines to perform logic operations; store and access memory; and receive and transfer energy. However, external sources of current and voltage (e.g., electrostatic discharge (ESD) or similar conditions) can introduce different voltage levels that may damage the circuit elements. Simple Explanation of the Diagram

[0002] The best understanding of all aspects of this disclosure can be obtained from the detailed description below when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1A, 1B, 1C, and 1D are circuit diagrams illustrating some active power clamps with a diode between a gate terminal and a voltage line, according to some embodiments. Figures 2A and 2B illustrate top views of an active power clamp in which the diode is located between the gate terminal and the low-voltage line, and the first node between the capacitor and the resistor is directly coupled to the gate terminal of the transistor. Figures 3A and 3B illustrate top views of an active power clamp in which a diode is located between a gate terminal and a high-voltage line, and where the first node between a capacitor and a resistor is directly coupled to the gate terminal of a transistor. Figures 4A and 4B illustrate a top view of an active power clamp in which a diode is located between the gate terminal and the low-voltage line, a first node between the capacitor and the resistor is coupled to an inverter circuit, and an odd number of inverter circuits are coupled in series between the first node and the gate terminal. Figures 5A and 5B are top views of an active power clamp in which the diode is located between the gate terminal and the high-voltage line, the first node between the capacitor and the resistor is coupled to the inverter circuit, and an even number of inverter circuits are coupled in series between the first node and the gate terminal. Figure 6 illustrates a cross-sectional view of an active power clamp structure in which a diode is located between the gate terminal and the low-voltage line, a capacitor is located above the resistor, diode, and transistor, and the resistor, diode, and transistor include a channel layer and an active layer. Figure 7 illustrates a cross-sectional view of an active power clamp in an interconnect structure where the diode is located between the gate terminal and the low-voltage line, and the capacitor is located above the resistor, diode, and transistor. Figures 8A to 12 illustrate a series of cross-sectional views showing methods for forming an active power clamp in some embodiments, wherein the diode is located between the gate terminal and the voltage line. Figure 13 illustrates a flowchart showing a method for forming an active power clamp in some embodiments, wherein the diode is located between the gate terminal and the voltage line. Implementation

[0003] This disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these examples are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, but does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0004] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0005] It should be understood that the terms "first," "second," "third," etc., used in this written description and in the following claims are merely general identifiers for ease of explanation, used to distinguish different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements, and are not intended to describe corresponding elements in different illustrated examples and / or examples not shown. For example, "first dielectric layer" illustrated in conjunction with the first figure may not necessarily correspond to "first dielectric layer" illustrated in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in examples not shown.

[0006] The integrated element includes a high-voltage line and a low-voltage line. During operation, the high-voltage line provides a first supply voltage (VDD), and the low-voltage line provides a second supply voltage (VSS) lower than the first supply voltage VDD. The high-voltage and low-voltage lines are coupled to circuit elements (e.g., passive circuit elements, transistors, operational amplifiers, or similar components) within the integrated element. The voltage difference between the high-voltage and low-voltage lines depends on the type of circuit elements used in the device and the integrated element.

[0007] Electrostatic discharge (ESD) from an external energy source of an integrated circuit can cause the affected component, high-voltage line, or low-voltage line to have a voltage much higher or lower than during normal operation. The voltage level caused by ESD may exceed the rated voltage of the circuit elements used in the integrated circuit, thereby damaging the affected component. Damaged components can degrade the performance of the integrated circuit or cause the circuit to malfunction.

[0008] One method to reduce the impact of ESD on the voltage levels of integrated components is to use a power clamp. In some embodiments, the power clamp includes a series resistance-capacitance (RC) or capacitance-resistance (CR) circuit coupled between a high-voltage line and a low-voltage line, and a transistor. A first source / drain terminal of the transistor is coupled to the high-voltage line, and a second source / drain terminal is coupled to the low-voltage line. In some embodiments, the gate terminal of the transistor is directly coupled to a first node coupled between a capacitor and a resistor. In other embodiments, one or more inverter circuits are coupled in series between the first node and the gate terminal.

[0009] A power clamp conducts the unexpected electrostatic discharge current of a positive (e.g., unexpected voltage increase) electrostatic discharge event on a high-voltage line or a low-voltage line, and discharging this current can mitigate damage to circuit components. However, the power clamp circuit configured as described above may be slow to discharge negative (e.g., unexpected voltage decrease) electrostatic discharge events on high-voltage lines. In active voltage clamps using transistors with floating base terminals or n-type high electron mobility transistors (nHEMTs) without a body, the discharge time for negative electrostatic discharge events is further prolonged. Therefore, there is a need for a device that enhances operation during negative electrostatic discharge events while maintaining the effectiveness of an active power clamp.

[0010] This disclosure provides a diode that couples the gate terminal of a transistor to a low-voltage or high-voltage line of a device, depending on the type of transistor used in the end stage of an active power clamp. For an n-type transistor, the diode is configured such that its cathode is coupled to the gate terminal and its anode is coupled to the low-voltage line. For a p-type transistor, the diode is configured such that its cathode is coupled to the high-voltage line and its anode is coupled to the gate terminal. During a negative electrostatic discharge event on the high-voltage line, the high-voltage line is driven to a voltage much lower than that of the low-voltage line (VDD << VSS). The sudden drop in VDD causes a rapid response on the capacitor side of the RC circuit, driving the gate terminal down (for active power clamps using n-type transistors) or up (for active power clamps using p-type transistors). In embodiments without a diode, the voltage change at the gate causes the transistor to remain in a "cut-off" state. The "off" state prevents the transistor from turning on until the gate-to-drain voltage (VGD) rises (for n-type transistors) above the threshold voltage (VTH) or falls (for p-type transistors) below the threshold voltage (VTH). The voltage change following a negative electrostatic discharge event is based on the RC delay of the series RC circuit.

[0011] In embodiments with diodes, a sudden change in VDD activates the diode, causing the voltage at the gate terminals to be equal to VSS minus the diode's threshold voltage (for n-type transistors) or equal to VDD plus the diode's threshold voltage (for p-type transistors). The instantaneous voltage caused by diode activation avoids a portion of the RC delay in the power clamp circuit (e.g., between approximately 20% and 50%), resulting in an increased rate of transistor activation and electrostatic discharge (ESD). This increased ESD rate reduces the amount of damage experienced by the circuit logic elements.

[0012] Figures 1A, 1B, 1C, and 1D are circuit diagrams 100a, 100b, 100c, and 100d illustrating an active power clamp with a diode between a gate terminal and a voltage line, according to some embodiments.

[0013] As shown in the circuit diagram of Figure 1A, a power clamp 102 is coupled between a high-voltage line 104 and a low-voltage line 106. The power clamp 102 includes a capacitor 108 coupled between the high-voltage line 104 and a first node 110, and a resistor 109 coupled between the low-voltage line 106 and the first node 110. The combination of resistor 109 and capacitor 108 is also referred to as a resistor-capacitor structure 111. The power clamp 102 also includes a transistor 112, whose first source / drain terminal 114 is coupled to the high-voltage line 104, its second source / drain terminal 116 is coupled to the low-voltage line 106, and its gate terminal 118 is coupled to the first node 110. The source / drain regions may be referred to individually or collectively as source and drain, depending on the context. The cathode 122 of diode 120 is coupled to the gate terminal 118, and the anode is coupled to the low-voltage line 106.

[0014] Power clamp 102 is configured to prevent the voltage VDD of high-voltage line 104 from rising above a first threshold and to prevent the voltage VSS of low-voltage line 106 from falling below a second threshold. In some embodiments, the first threshold is approximately between 1.5 volts and 5 volts, between 3.5 volts and 7 volts, between 5 volts and 10 volts, or in another similar range, and is selected based on the functional and performance characteristics of the corresponding circuit 126. In some embodiments, the second threshold is approximately 0 volts and is selected based on the functional and performance characteristics of the corresponding circuit 126. If VDD rises above the first threshold for an extended period or VSS falls below the second threshold for an extended period, the circuit elements in the corresponding circuit 126 may operate under increased voltage and current, leading to increased temperature, increased thermal resistance, and potential dielectric breakdown and damage to circuit elements.

[0015] Power clamp 102 discharges voltages exceeding a first or second threshold by activating transistor 112 coupled between high-voltage line 104 and low-voltage line 106 until the difference between VDD and VSS returns to the design value. For example, when a positive electrostatic discharge event occurs on high-voltage line 104 (e.g., a sudden introduction of a voltage higher than the design voltage of the corresponding circuit 126), the voltage at gate terminal 118 will rise above the transistor's threshold voltage (VTH), activating transistor 112 and discharging the electrostatic discharge. As the electrostatic discharge continues, the voltage at gate terminal 118 will decrease until it falls below the threshold voltage (VTH) of transistor 112, returning the transistor to "off" mode.

[0016] During a negative electrostatic discharge event (e.g., when a voltage lower than the design voltage of the corresponding circuit 126 is suddenly introduced into high-voltage line 104), the VDD of high-voltage line 104 is lower than the VSS of low-voltage line 106. The voltage at gate terminal 118 also drops rapidly. Since transistor 112 is an n-type device, the transistor channel turns on when the voltage at gate terminal 118 exceeds the threshold voltage (VTH). In embodiments without diode 120, the voltage at gate terminal 118 will subsequently rise to voltage VSS due to the RC delay of the circuit. This delayed start-up of transistor 112 may damage circuit elements in the corresponding circuit 126.

[0017] In an embodiment with diode 120, a negative electrostatic discharge event on high-voltage line 104 causes the voltage at gate terminal 118 to drop below VSS of the low-voltage line, activating diode 120. Activation of diode 120 causes the voltage at gate terminal 118 to recover and remain at VSS minus the diode's threshold voltage. Due to the drop in VDD, the resulting voltage at the gate terminal activates the transistor after a shorter delay (compared to the delay in an embodiment without a diode). In some embodiments, the delay is reduced by approximately 20% to 50%, approximately 25% to 55%, approximately 15% to 45%, or in another similar range. This reduced delay after the negative electrostatic discharge event results in the discharge of excess charge on the high-voltage line within a faster timeframe, mitigating damage to the circuit elements of the corresponding circuit 126.

[0018] As shown in circuit diagram 100b of Figure 1B, in some embodiments, the transistor 112 in the power clamp 102 is a p-type transistor. Furthermore, a resistor 109 is coupled between the high-voltage line 104 and the first node 110, a capacitor 108 is coupled between the low-voltage line 106 and the first node 110, and a diode 120 is coupled between the high-voltage line 104 and the gate terminal 118. During a negative electrostatic discharge event on the high-voltage line 104, the VDD of the high-voltage line 104 suddenly drops. In embodiments without diode 120, the voltage at the gate terminal 118 requires a longer delay to drop sufficiently to activate the transistor 112, compared to embodiments with diode 120. That is, embodiments with diode 120, when VDD drops, reduce the voltage at the gate terminal 118 to the reduced VDD value plus the threshold voltage of diode 120, causing the transistor 112 to activate after a shorter delay (compared to embodiments without diode 120).

[0019] As shown in circuit diagram 100c of Figure 1C, in some embodiments, the power clamp 102 may further include an odd number of inverter circuits 128 (e.g., one inverter circuit, three inverter circuits, five inverter circuits, seven inverter circuits, etc.). The inverter circuit 128 includes an input node 130 coupled to a first node 110 (or the output node 132 of the preceding inverter circuit 128), and an output node 132 coupled to a gate terminal 118 (or the input node of a subsequent inverter circuit 128). The odd number of inverter circuits 128 are configured to invert the signal from the first node 110 an odd number of times and couple the gate terminal 118 of the transistor 112 to a high-voltage line 104 or a low-voltage line 106 according to the voltage of the first node 110. In an embodiment with an odd number of inverter circuits 128 and capacitor 108 coupled between low-voltage line 106 and first node 110, transistor 112 is an n-type transistor (e.g., conducting current when the voltage between the gate and source / drain terminals is above the threshold voltage (V TH)) and diode coupled between low-voltage line 106 and gate terminal 118.

[0020] During a positive electrostatic discharge event on high-voltage line 104, the RC delay of the resistors and capacitors causes the voltage at input node 130 of the first inverter circuit 128 to be lower than the voltage of the high-voltage line. This activates the p-type transistor 134 of the first inverter circuit, coupling gate terminal 118 to the high voltage VDD and conducting excess current through transistor 112. During a negative electrostatic discharge event on high-voltage line 104, the first source / drain terminal 114 of transistor 112 is driven to a new VDD, which is lower than VSS. Since diode 120 maintains the voltage at gate terminal 118 at at least VSS minus the diode threshold voltage, transistor 112 is turned on, conducting current from low-voltage line 106 to high-voltage line 104.

[0021] As shown in the circuit diagram of Figure 1D, in some embodiments, the power clamp 102 may further include an even number of inverter circuits 128 (e.g., two inverter circuits, four inverter circuits, six inverter circuits, eight inverter circuits, etc.). In embodiments with an even number of inverter circuits 128 and capacitor 108 coupled between low-voltage line 106 and first node 110, transistor 112 is a p-type transistor (e.g., conducting current when the voltage between the gate and source / drain terminals is below the threshold voltage (VTH)), and the diode is coupled between low-voltage line 106 and gate terminal 118.

[0022] During a positive electrostatic discharge event on high-voltage line 104, the RC delay of resistor 109 and capacitor 108 causes the voltage at input node 130 of the first inverter circuit 128 to be lower than the voltage of the high-voltage line. This activates the p-type transistor 134 of the first inverter circuit. Due to the even number of inverters in the circuit 128, gate terminal 118 is coupled to low-voltage line 106, activating transistor 112 and conducting current from high-voltage line 104 to low-voltage line 106. During a negative electrostatic discharge event on high-voltage line 104, the first source / drain terminal 114 of transistor 112 is driven to a new VDD, which is lower than VSS. Because diode 120 maintains the voltage at gate terminal 118 at no more than VDD plus the diode threshold voltage, transistor 112 is turned on, conducting current from low-voltage line 106 to high-voltage line 104.

[0023] Figures 2A and 2B illustrate top views 200a and 200b of an active power clamp having a diode between the gate terminal and the low-voltage line, wherein the first node between the capacitor and the resistor is directly coupled to the gate terminal of the transistor.

[0024] As shown in the top view 200a of Figure 2A, in some embodiments, the transistor 112 in the circuit shown in Figure 1A is a high electron mobility transistor (HEMT) on substrate 204. Interconnect structure 202 includes a high-voltage line 104 and a low-voltage line 106, and multiple contacts 203 coupled to terminals of diode 120, transistor 112, capacitor 108, and resistor 109. Interconnect structure 202 further couples the first node 110 and diode 120 to gate terminal 118. In some embodiments, diode 120, capacitor 108, and resistor 109 are formed using the same active layer 206 and metal layer 208 as transistor 112. For example, in some embodiments, resistor 109 is a two-dimensional electron gas (2DEG) type resistor, and capacitor 108 is a HEMT device in which source / drain terminals 216 are coupled together to form one terminal of capacitor 108.

[0025] In some embodiments, diode 120 includes a HEMT transistor whose third source / drain terminal 210 and gate terminal 212 are coupled together to form an anode 124, while a fourth source / drain terminal 214 forms a cathode 122. The third source / drain terminal 210 and the fourth source / drain terminal 214 may include about 2 to 100 finger structures. The aspect ratio (e.g., the ratio of the length to the width of the active region of the diode) may be between 0.02 and 100. In some embodiments, the active layer 206 of diode 120 is or includes a combination of two or more of binary III / V semiconductor materials, ternary III / V semiconductor materials, silicon carbide (SiC), or similar materials. The active layer 206 is configured to form a two-dimensional electron gas extending beneath the finger structures of the third source / drain terminal 210 and the fourth source / drain terminal 214.

[0026] As shown in the top view 200b of Figure 2B, in some embodiments, the transistor 112 shown in the circuit diagram 100a of Figure 1A is a metal-oxide-semiconductor field-effect transistor (MOSFET) or other types of transistors. Furthermore, in some embodiments, the capacitor 108 is a metal-oxide-semiconductor (MOS) device, whose source / drain terminals 216 are coupled together to form one terminal of the capacitor. In other embodiments, the capacitor 108 is a varactor diode, a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, or other variant capacitors.

[0027] In some embodiments, diode 120 is a silicon-based diode, wherein anode 124 and cathode 122 include a plurality of first doped regions 218 surrounded by a second doped region 220 in doped well 222. In some embodiments, the plurality of first doped regions 218 are positively doped, the second doped regions 220 are negatively doped, and the doped well 222 is negatively doped. In other embodiments, the plurality of first doped regions 218 are negatively doped, the second doped regions 220 are positively doped, and the doped well 222 is positively doped. In yet another embodiment, the first doped regions 218 and the second doped regions 220 are of a first doping type, and the doped well 222 is of a second doping type different from the first doping type, and a first terminal of diode 120 (e.g., one of cathode 122 or anode 124) is coupled to doped well 222, while a second terminal (e.g., the other of cathode 122 or anode 124) is coupled to one of the first doped regions 218 or the second doped region 220.

[0028] In some embodiments, resistor 109 is a chip resistor, a thin-film resistor, or other types of resistor. In some embodiments, resistor 109 includes a plurality of conductive segments 224 extending between a plurality of insulating segments 226. In some embodiments, resistor 109 includes one or more of tantalum nitride (TaN), titanium nitride (TiN), an oxide diffusion (OD) region covered by a resistive protective oxide (RPO), a polysilicon (PO) region covered by a resistive protective oxide, a doped well, silicon chromium (SiCr), or similar materials.

[0029] Figures 3A and 3B illustrate top views 300a and 300b of an active power clamp having a first node between the diode and the high-voltage line, and between the capacitor and the resistor, directly coupled to the gate terminal of the transistor (see circuit diagram 100b of Figure 1B). As shown in top view 300a of Figure 3A, in some embodiments, diode 120, capacitor 108, and resistor 109 are high electron mobility transistor (HEMT) devices, or are fabricated using the same active layer 206 and metal layer 208 as HEMT devices (as described in Figure 2A). Transistor 112 is a p-type transistor and therefore not an HEMT device, but is formed using a different technique. As shown in top view 300b of Figure 3B, in some embodiments, transistor 112, diode 120, capacitor 108, and resistor 109 are not HEMT devices, as described with reference to Figure 2B.

[0030] Figures 4A and 4B illustrate top views 400a and 400b of an active power clamp in which a first node, between the diode and the voltage line, and between the capacitor and the resistor, is coupled to an inverter circuit, and where an odd number of inverter circuits are coupled in series between the first node and the gate terminal (see circuit diagram 100c of Figure 1C). As shown in top view 400a of Figure 4A, in some embodiments, transistor 112, diode 120, capacitor 108, and resistor 109 are high electron mobility transistor (HEMT) devices, or are fabricated using the same active layer 206 and metal layer 208 as HEMT devices (as described with reference to Figure 2A). Furthermore, in some embodiments, inverter circuit 128 includes an n-type HEMT transistor and a p-type transistor formed using different techniques, or neither an n-type nor a p-type HEMT transistor. As shown in the top view 400b of Figure 4B, in some embodiments, the transistors 112, 120, 108, 109, and the inverter circuit are not HEMT devices (as described with reference to Figure 2B).

[0031] Figures 5A and 5B illustrate top views 500a and 500b of an active power clamp in which a diode is coupled to an inverter circuit at a first node between the gate terminal and the high-voltage line, where the capacitor and resistor are connected in series, and where an even number of inverter circuits are coupled in series between the first node and the gate terminal. As shown in top view 500a of Figure 5A, in some embodiments, transistor 112, diode 120, capacitor 108, and resistor 109 are high electron mobility transistor (HEMT) devices, or are fabricated using the same active layer 206 and metal layer 208 as HEMT devices (as described with reference to Figure 2A). Furthermore, in some embodiments, inverter circuit 128 includes an n-type HEMT transistor and a p-type transistor formed using different technologies, or neither an n-type nor a p-type HEMT transistor. As shown in the top view 500b of Figure 5B, in some embodiments, the transistors 112, 120, 108, 109, and the inverter circuit are not HEMT devices, as described with reference to Figure 2B.

[0032] Figure 6 illustrates a cross-sectional view 600 of an interconnect structure in which a diode is located between a gate terminal and a voltage line, a capacitor is located above a resistor, a diode, and a transistor, and the resistor, diode, and transistor include a high electron mobility transistor (HEMT) device, or an active power clamp formed using the same active layer and metal layer as a HEMT device.

[0033] In some embodiments, capacitor 108 is or includes a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, or another type of capacitor in interconnect structure 202. In some embodiments, capacitor 108 is separated from substrate 204 by a portion of interconnect structure 202 and an interlayer dielectric layer 602 surrounding interconnect structure 202. Interconnect structure 202 includes a plurality of conductor levels 606 and a plurality of via levels 604 configured to form a plurality of conductive paths extending between circuit elements in a corresponding circuit (see corresponding circuit 126 in FIG. 1A). In some embodiments, resistor 109, diode 120, and transistor 112 are all high electron mobility transistor (HEMT) devices, or include an active layer 206 and a metal layer 208 formed concurrently with a HEMT device. In a further embodiment, the inverter circuit (see inverter circuit 128 in Figures 1C and 1D) is also located on the substrate 204, and the n-type transistor in the inverter circuit (see inverter circuit 128 in Figures 1C and 1D) is a HEMT device, whose active layer 206 and metal layer 208 are formed simultaneously with the transistor 112.

[0034] In some embodiments, the active layer 206 includes a channel layer 608, which is or includes silicon carbide (SiC) or a binary III / V semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or the like); and a barrier layer 610, which includes a ternary III / V semiconductor material (e.g., aluminum gallium nitride (AlGaN), aluminum gallium arsenide (AlGaAs), or the like). In some embodiments, the metal layer 208 includes a first metal layer 612, which includes source / drain terminals of a transistor 112, a diode 120, and a resistor 109; and a second metal layer 614, which includes gate terminals of the transistor 112, the diode 120, and the resistor. The second source / drain terminal 116 is coupled to the low-voltage line 106 via a first conductive path 615 extending through the first conductor layer 606.

[0035] Transistor 112 and diode 120 also include a p-type gallium nitride layer 616 (e.g., a layer of positively doped gallium nitride (GaN) or similar material). The p-type gallium nitride layer 616 enables transistor 112 and diode 120 to have a "normally off" function, meaning the device is not conductive when the gate terminal voltage is 0 volts. The p-type gallium nitride layer 616 is omitted in resistor 109, enabling resistor 109 to have a "normally on" function. In some embodiments, the gate terminal of resistor 109 remains floating or is omitted to maintain the "normally on" function. In other embodiments, the gate terminal of resistor 109 is coupled to ground.

[0036] Figure 7 illustrates a cross-sectional view 700 of the power clamp 102, wherein a diode 120 is located between a gate terminal 118 and a low-voltage line 106, and a capacitor 108 is located in an interconnect structure 202 above a resistor 109, a diode 120, and a transistor 112. In some embodiments, the transistor 112, resistor 109, diode 120, and / or capacitor 108 do not include high electron mobility transistor devices or use the same active layer 206 or metal layer 208 as high electron mobility transistor devices. Instead, the transistor 112 may include a metal-oxide-semiconductor field-effect transistor or the like, the diode 120 may include multiple doped regions or other variations, and / or the resistor may include one or more thin-film resistors, pinched resistors, well resistors, or the like.

[0037] Figures 8A, 8B, and 9 through 12 illustrate a series of cross-sectional views 800a, 800b, 900, 1000, 1100, and 1200, demonstrating methods for forming an active power clamp in some embodiments, the power clamp having a diode between the gate terminal and the voltage line. While Figures 8A, 8B, and 9 through 12 are depicted as a series of actions, it should be understood that these actions are not limiting; the order of actions may be changed in other embodiments, and the disclosed methods are applicable to other configurations. In other embodiments, some illustrated and / or described actions may be omitted in whole or in part.

[0038] As shown in cross-sectional view 800a of FIG8A, transistor 112, resistor 109, and diode 120 are formed on substrate 204. In some embodiments, the transistor, resistor 109, and diode 120 are formed by etching channel layer 608 and barrier layer 610 to form openings corresponding to the spaces between channel layer 608 and barrier layer 610 of transistor 112, resistor 109, and diode 120. The openings are then filled with an insulating layer (e.g., silicon dioxide (SiO2) or the like). A first metal layer 612 is then deposited on barrier layer 610, followed by removal of portions of the first metal layer 612 corresponding to the space between the source / drain terminals of the circuit element. The gate terminal is then formed by depositing a second metal layer 614 on the substrate and then removing portions of the second metal layer 614 that do not correspond to the gate terminal. In some embodiments, the channel layer 608 and the barrier layer 610, the first metal layer 612 and the second metal layer 614 are formed independently using one or more of physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), mosaic process or similar methods.

[0039] As shown in cross-sectional view 800b of Figure 8B, in some embodiments, capacitor 108 and transistor 112 are simultaneously formed as a high electron mobility transistor device. In other embodiments, capacitor 108 is formed on the substrate using different front-end-of-line (FEOL) techniques before or after transistor 112. In still other embodiments, capacitor 108 is formed as part of a back-end-of-line (BEOL) process (see Figures 10 and 11). Figures 9 through 12 continue to assume that the capacitor will be formed as part of a BEOL process. It should be understood that the embodiments discussed in relation to Figures 2A through 5B may use FEOL techniques to form capacitor 108, and the formation of capacitor 108 as shown in Figures 10 and 11 is omitted.

[0040] As shown in cross-sectional view 900 of FIG9, a first portion of interconnect structure 202 is formed on substrate 204. Interconnect structure 202 is configured to couple circuit elements 901 to each other using multiple conductive paths and further includes a high-voltage line 104 and a low-voltage line 106. In some embodiments, the low-voltage line 106 is formed in the first portion of interconnect structure 202, while the high-voltage line 104 is formed in a second portion of interconnect structure 202 after capacitor formation (see FIGS. 11 and 12). Interconnect structure 202 is coupled to circuit elements 901 (e.g., resistor 109, diode 120, and transistor 112) using multiple contacts 203.

[0041] In some embodiments, the interconnect structure 202 is formed by: depositing an interlayer dielectric layer 602 on a substrate; depositing an etch stop layer 902; forming openings in the interlayer dielectric layer 602 and the etch stop layer 902; depositing a metal layer in the openings; and removing portions of the metal layer outside the openings to leave via layers (or contact layers) and conductor layers on the substrate 204. This process is repeated to complete the conductor level 606 and via level 604 in the first portion of the interconnect structure 202. In some embodiments, the conductor level 606 and via level 604 are formed using multiple damascene or dual damascene processes. In some embodiments, the interlayer dielectric layer 602 is or includes an insulating material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or the like. In some embodiments, the conductors and vias of the multiple conductor levels 606 and multiple via levels 604 are or include one or more of aluminum, copper, aluminum-copper, or the like.

[0042] As shown in the cross-sectional view 1000 of FIG10, a first masking layer 1004 is formed on a first portion of the interconnect structure 202. In some embodiments, the first masking layer 1004 is formed by depositing photoresist on a substrate 204 (e.g., via deposition, spin coating, dipping, or similar processes) and then patterning the photoresist using lithography. After forming the first masking layer 1004, a first opening 1002 is formed in the interlayer dielectric layer 602. In some embodiments, the first opening 1002 is formed by etching through the interlayer dielectric layer 602 and the etch stop layer 902 using a dry etching process 1006. In some embodiments, the dry etching process 1006 ends after exposing one of the plurality of conductor levels 606. The first masking layer 1004 is then removed.

[0043] As shown in the cross-sectional view 1100 of FIG11, in some embodiments, a capacitor 108 is formed in a first opening 1002. The capacitor 108 formed in the first opening 1002 is a metal-insulator-metal (MIM), metal-oxide-metal (MOM), or other type of capacitor. In some embodiments, the capacitor 108 is formed by depositing a bottom metal layer, a conformal dielectric layer, and a top metal layer on a first portion of the interconnect structure 202. The bottom metal layer, conformal dielectric layer, and top metal layer are etched to remove portions that do not correspond to the capacitor 108, leaving the capacitor bottom metal 1102, capacitor dielectric 1104, and capacitor top metal 1106 remaining in the first opening 1002. In some embodiments, the bottom metal layer, conformal dielectric layer, and top metal layer are patterned using a single masking layer. In other embodiments, the capacitor is patterned using one or more additional masking layers to have two terminals on the upper surfaces of the capacitor bottom metal 1102 and the capacitor top metal 1106, or the conductor layer 606 is patterned simultaneously with the patterning of the capacitor bottom metal 1102. In some embodiments, the portion of capacitor 108 outside the first opening 1002 is perpendicularly spaced from the conductor layer 606 of the first portion of the interconnect structure. After forming the capacitor 108, a protective layer 1108 is formed on the capacitor 108.

[0044] As shown in the cross-sectional view 1200 of FIG12, a second portion of the interconnect structure 202 is formed over the capacitor 108 and the first portion of the interconnect structure 202. In some embodiments, the second portion of the interconnect structure 202 is formed in the same manner as the first portion of the interconnect structure (see FIG9). In some embodiments, the second portion of the interconnect structure 202 includes a high-voltage line 104. In other embodiments, the high-voltage line 104 is located in the first portion of the interconnect structure 202, and a conductive path extending through the first and second portions of the interconnect structure couples the high-voltage line to the capacitor 108.

[0045] Figure 13 illustrates a flowchart 1300 of a partial embodiment of a method for forming an active power clamp having a diode disposed between a gate terminal and a voltage line. While this method and other methods illustrated and / or described herein are depicted as a series of actions or events, it should be understood that this disclosure is not limited to the illustrated sequence or actions. Therefore, in some embodiments, these actions may be performed in a different order than depicted, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included. [, , ]

[0046] At operation 1302, a first transistor is formed on the substrate. The first transistor includes a gate terminal, a first source / drain terminal, and a second source / drain terminal. A diagram illustrating this step can be seen, for example, in Figure 8.

[0047] At operation 1304, a diode is formed on the substrate, the diode comprising an anode and a cathode. A illustrative example illustrating this step can be found in Figure 8, for example.

[0048] At operation 1306, a resistor is formed on the substrate. A diagram illustrating this step can be seen, for example, in Figure 8.

[0049] At operation 1308, a first portion of an interconnect structure is formed on the substrate, including contacts coupled to a resistor, a diode, and a first transistor. A graphical example illustrating this step can be found, for example, in Figure 9.

[0050] At operation 1310, a capacitor is formed on the substrate before the first portion of the interconnect structure is formed, or after the first portion of the interconnect structure is formed, a capacitor is formed on the substrate. An example illustration of this step can be found in Figures 10 and 11, for example.

[0051] At operation 1312, a second part of the interconnect structure is formed, wherein the interconnect structure includes a high-voltage line and a low-voltage line. The interconnect structure is configured to couple a first source / drain terminal to the high-voltage line, couple a second source / drain terminal to the low-voltage line, couple a capacitor to a resistor at a first node, couple a first node to a gate terminal or the input node of a first inverter circuit, couple the cathode of a diode to a gate terminal or the high-voltage line, and couple the anode of a diode to the low-voltage line or the gate terminal. A graphical example illustrating this step can be found, for example, in Figure 12.

[0052] Some embodiments relate to an integrated element comprising: a resistor-capacitor structure coupled in series between a high-voltage line and a low-voltage line, the resistor-capacitor structure having a first node electrically coupled to a resistor and a capacitor; a transistor including a first source / drain terminal coupled to the high-voltage line, a second source / drain terminal coupled to the low-voltage line, and a gate terminal; and a diode coupled between the gate terminal and the high-voltage line or the low-voltage line.

[0053] Other embodiments relate to an integrated element comprising: a first transistor, located on a substrate and including a gate terminal, a first source / drain terminal, and a second source / drain terminal; an interconnect structure coupled to the gate terminal, the first source / drain terminal, and the second source / drain terminal; a high-voltage line extending through the interconnect structure and coupled to the first source / drain terminal; a low-voltage line extending through the interconnect structure and coupled to the second source / drain terminal; a diode coupled via the interconnect structure to the gate terminal and one of the high-voltage line or the low-voltage line; a resistor coupled to a first node of the interconnect structure and one of the high-voltage line or the low-voltage line; and a capacitor coupled to the first node and the other of the high-voltage line or the low-voltage line, wherein the first node is coupled to the gate terminal or coupled to a first inverter circuit.

[0054] Other embodiments relate to a method of forming an integrated element, including: forming a first transistor on a substrate, wherein the first transistor includes a gate terminal, a first source / drain terminal, and a second source / drain terminal; forming a diode on the substrate, wherein the diode includes an anode and a cathode; forming a resistor on the substrate; forming a first portion of an interconnect structure on the substrate, including contacts coupled to the resistor, the diode, and the first transistor; forming a capacitor on the substrate before or after forming the first portion of the interconnect structure; and forming a second portion of the interconnect structure, wherein the interconnect structure includes a high-voltage line and a low-voltage line, wherein the interconnect structure is configured to couple the first source / drain terminal to the high-voltage line, couple the second source / drain terminal to the low-voltage line, couple the capacitor to the resistor at a first node, couple the first node to the gate terminal or an input node of a first inverter circuit, couple the cathode of the diode to the gate terminal or the high-voltage line, and couple the anode of the diode to the low-voltage line or the gate terminal.

[0055] It should be understood that in this written description, and in the following claims, the terms "first," "second," "third," etc., are merely general identifiers used for ease of explanation to distinguish different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" illustrated in conjunction with the first figure may not necessarily correspond to "first dielectric layer" illustrated in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0056] The features of the above embodiments are beneficial for those skilled in the art to understand various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis to design or modify other processes and structures to achieve the same purpose and / or the same advantages as the above embodiments. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

[0057] 100a, 100b, 100c, 100d: Circuit diagrams 102: Power clamper 104: High-voltage line 106: Low-voltage line 108: Capacitor 109: Resistors 110: First Node 111: Resistor-capacitor structure 112: Transistor 114: First source / drain pole 116: Second source / drain pole 118: Gate terminal 120: Diode 122: Cathode 124: Anode 126: Corresponding circuit 128: Inverter Circuit 130: Input node 132: Output node 134: p-type transistor 200a, 200b, 300a, 300b, 400a, 400b, 500a, 500b: Top view 202: Interconnection Structure 203: Contacts 204: Base 206: Active Layer 208: Metal layer 210: Third source / drain pole 212: Gate terminal 214: Fourth source / drain pole 216: Source / drain terminal 218: First doped region 220: Second doped region 222: Doped Well 224: Conductive segment 226: Insulation Section 602: Interlayer dielectric layer 604: Through-hole level 606: Conductor Level 608: Channel Layer 610: Barrier Layer 612: First metal layer 614: Second metal layer 615: First transmission path 616: p-type gallium nitride layer 901: Circuit Components 902: Etching Stop Layer 1000, 1100, 1200, 600, 700, 800a, 800b, 900: Sectional Views 1002: First Opening 1004: First masking layer 1006: Dry Etching Process 1102: Metal at the bottom of the capacitor 1104: Capacitor dielectric 1106: Metal at the top of the capacitor 1108: Protective layer 1300: Flowchart 1302, 1304, 1306, 1308, 1310, 1312: Operations

Claims

1. An integrated element for electrostatic discharge, comprising: A resistor-capacitor structure is connected in series between a high-voltage line and a low-voltage line, and the resistor-capacitor structure has a first node electrically coupled to a resistor and a capacitor; The transistor includes a first source / drain terminal coupled to the high-voltage line, a second source / drain terminal coupled to the low-voltage line, and a gate terminal; And a diode, coupled between the gate terminal and the high-voltage line or the low-voltage line.

2. The electrostatic discharge integrated element as claimed in claim 1, wherein the gate terminal is electrically coupled to the first node between the resistor and the capacitor.

3. An electrostatic discharge integrated element as claimed in claim 2, wherein the resistor is coupled between the high-voltage line and the first node, and wherein the diode has a cathode coupled to the high-voltage line and an anode coupled to the gate terminal.

4. An electrostatic discharge integrated element as claimed in claim 2, wherein the resistor is coupled between the low-voltage line and the first node, and wherein the diode has a cathode coupled to the gate terminal and an anode coupled to the low-voltage line.

5. The electrostatic discharge integrated element as claimed in claim 1, further comprising a first inverter circuit coupled to the first node.

6. An integrated electrostatic discharge element as claimed in claim 5, wherein the first inverter circuit has an output node coupled to the gate terminal, wherein the resistor is coupled between the high-voltage line and the first node, and wherein the diode has a cathode coupled to the gate terminal and an anode coupled to the low-voltage line.

7. The electrostatic discharge integrated element as claimed in claim 5, further comprising a second inverter circuit coupled to the output node of the first inverter circuit and the gate terminal.

8. An electrostatic discharge integrated element as claimed in claim 7, wherein the resistor is coupled between the high-voltage line and the first node, and wherein the diode has a cathode coupled to the high-voltage line and an anode coupled to the gate terminal.

9. An integrated element for electrostatic discharge, comprising: The first transistor is located on a substrate and includes a gate terminal, a first source / drain terminal, and a second source / drain terminal. An interconnect structure is coupled to the gate terminal, the first source / drain terminal, and the second source / drain terminal; A high-voltage line extends through the interconnect structure and is coupled to the first source / drain terminal; A low-voltage line extending through the interconnect structure and coupled to the second source / drain terminal; a diode coupled via the interconnect structure to the gate terminal and one of the high-voltage line or the low-voltage line; a resistor coupled to a first node of the interconnect structure and one of the high-voltage line or the low-voltage line; and a capacitor coupled to the first node and the other of the high-voltage line or the low-voltage line, wherein the first node is coupled to the gate terminal or coupled to a first inverter circuit.

10. A method for forming an integrated element for electrostatic discharge, comprising: A first transistor is formed on a substrate, wherein the first transistor includes a gate terminal, a first source / drain terminal, and a second source / drain terminal; A diode is formed on the substrate, wherein the diode includes an anode and a cathode; a resistor is formed on the substrate; a first portion of an interconnect structure is formed on the substrate, including contacts coupled to the resistor, the diode, and the first transistor; a capacitor is formed on the substrate before or after the formation of the first portion of the interconnect structure; and a second portion of the interconnect structure is formed, wherein the interconnect structure includes a high-voltage line and a low-voltage line, wherein the interconnect structure is configured to couple a first source / drain terminal to the high-voltage line, couple a second source / drain terminal to the low-voltage line, couple the capacitor to the resistor at a first node, couple the first node to the gate terminal or the input node of a first inverter circuit, couple the cathode of the diode to the gate terminal or the high-voltage line, and couple the anode of the diode to the low-voltage line or the gate terminal.

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