Methods of formation of a sige / si superlattice
Patent Information
- Application Number
- TW113146566
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-07-23
- Filing Date
- 2022-07-22
- Publication Date
- 2026-10-21
- Estimated Expiration
- 2042-07-21
AI Technical Summary
Current methods for forming silicon and silicon germanium lattice structures in 3D DRAM applications suffer from low growth rates, large transition layers, and variability in layer thickness and quality, making it difficult to achieve uniform and repeatable layer formation.
A method involving the sequential introduction of silicon-containing and germanium-containing gases into a deposition chamber, followed by a halide species, and then silicon-containing gas alone, with precise control of temperature and pressure, to form a superlattice structure with sharp chemical transitions and high growth rates.
The method achieves uniform layer thickness and composition across the wafer, sharp chemical transitions between layers, and high growth rates exceeding 150 nm/min, with improved repeatability and reduced transition widths less than 1.4 nm.
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Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure generally relate to methods for forming semiconductor devices. More specifically, the present application relates to an epitaxial deposition method for forming silicon and silicon germanium superlattice structures. Background Art
[0002] As the feature sizes of transistor devices continue to shrink to achieve greater circuit density and higher performance, improvements to transistor device structures are needed to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure includes a plurality of lattice-matched channels suspended in a stacked configuration and connected by source / drain regions.
[0003] Current methods for forming lattice structures in three-dimensional dynamic random access memory (3D DRAM) applications include forming alternating silicon and silicon germanium layers. However, previous methods of growing lattice structures have a low growth rate and a large transition layer between each stacked layer. It is also difficult to achieve repeatability in layer formation, resulting in variations in the thickness and quality of the layers in the structure.
[0004] Therefore, a method for rapidly forming a silicon and silicon germanium lattice structure with a small transition layer and improved quality is needed. Summary of the Invention
[0005] Aspects described herein relate to methods for forming semiconductor devices. In one embodiment, a method for forming a semiconductor device is described. The method includes: (1) introducing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon germanium layer on a substrate in the deposition chamber; (2) after forming the silicon germanium layer, stopping the flow of the silicon-containing gas and the germanium-containing gas into the deposition chamber; (3) flowing a halide species into the deposition chamber; and (4) introducing a silicon-containing gas into the deposition chamber to form a silicon layer on the substrate in the deposition chamber.
[0006] In another embodiment, a method for forming a semiconductor device includes forming a unit cell by: introducing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon germanium layer on a substrate in the deposition chamber; after forming the silicon germanium layer, stopping the flow of the silicon-containing gas and the germanium-containing gas into the deposition chamber; flowing a halide species into the deposition chamber; introducing a silicon-containing gas into the deposition chamber to form a silicon layer on the substrate in the deposition chamber from the silicon-containing gas, and repeating the formation of the unit cell to form a stack of unit cells.
[0007] In another aspect, the semiconductor includes a superlattice device structure, which includes a first unit cell that includes a first silicon-germanium layer and a first silicon layer disposed on the first silicon-germanium layer. The superlattice device structure further includes a second unit cell that includes a second silicon-germanium layer and a second silicon layer disposed on the second silicon-germanium layer. The transition width between each of the silicon-germanium layers and the germanium layer is less than about 1.4 nm. Brief Description of the Drawings
[0008] To understand the manner in which the above-described features of the present disclosure are implemented, a more specific description of the present case briefly outlined above can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate exemplary embodiments and should not be considered as limiting the scope of the present disclosure. Other equivalent embodiments are recognized.
[0009] FIG. 1 is a schematic diagram of a type of deposition chamber according to an embodiment of the present disclosure.
[0010] FIGS. 2A and 2B are cross-sectional schematic diagrams of a superlattice structure according to an embodiment of the present disclosure.
[0011] FIGS. 3A and 3B illustrate a method of forming the superlattice structure of FIGS. 2A and 2B according to an embodiment.
[0012] FIGS. 4A and 4B illustrate a process gas flow diagram during a part of the method of FIGS. 3A and 3B according to an embodiment.
[0013] FIGS. 5A and 5B illustrate electron microscope measurement results of the layers of the superlattice structure.
[0014] FIGS. 6A and 6B are diagrams illustrating the transition width measurement results of the superlattice structure of FIGS. 5A and 5B.
[0015] FIG. 7 illustrates a partial device structure of a memory device according to an embodiment of the present disclosure.
[0016] For ease of understanding, wherever possible, the same reference numerals have been used to denote the same elements common to the figures. It is contemplated that the elements and features of one embodiment may be beneficially included in other embodiments without further recitation. Embodiments
[0017] This disclosure relates to a method of forming a superlattice structure, such as a silicon germanium (SiGe) / silicon (Si) superlattice structure used during the formation of 3D DRAM devices. Advantageously, there is a uniform layer (uniform in thickness and composition) across the diameter of the wafer, a uniform thickness and composition between the unit cells of the layer stack, and a sharp chemical transition between each layer in the superlattice structure. The method of forming a superlattice structure described herein improves the uniformity within each layer, improves the uniformity between layers, and the chemical transition between each layer is sharper.
[0018] The methods and chemistries described herein further enable high growth rates of SiGe and Si layers in a superlattice structure with sharp interfaces during the deposition process. Isothermal and isobaric process conditions are used during the deposition process. The deposition process includes the use of halide species or halogenated precursors. The use of halogenated precursors has been shown to improve the sharpness of the chemical transition between layers and increase the growth rate of the layers. Between the formation of each layer, the halide species flows co-currently or sequentially with a silicon- and / or germanium-containing reactive gas. Ballasting of the total flow rate on the deposited layer minimizes flow interference between layers, thereby improving the overall device layer formation result.
[0019] The methods described herein have shown growth rates in excess of 150 nm / min during the formation of SiGe and Si layers. High growth rates are achieved with a transition layer sharpness of less than about 1.4 nm. The repeatability between layers has also been shown to be improved when using a specific pyrometer temperature control scheme. The pyrometer temperature control scheme includes using a pyrometer disposed on the substrate to reduce thermal drift during the formation of layers on the substrate.
[0020] FIG. 1 is a schematic diagram of a deposition chamber 100 according to one embodiment of the present disclosure. A deposition chamber 100 is used to grow an epitaxial film on a substrate, such as substrate 102. The deposition chamber 100 forms a cross-flow of precursors on the top surface 150 of the substrate 102.
[0021] The deposition chamber 100 includes an upper main body 156, a lower main body 148 located below the upper main body 156, and a flow module 112 located between the upper main body 156 and the lower main body 148. The upper main body 156, the flow module 112, and the lower main body 148 form a chamber main body. The chamber main body includes a substrate support 106, an upper dome 108, a lower dome 110, a plurality of upper lamps 141, and a plurality of lower lamps 143 disposed therein. As shown in the figure, the controller 120 is in communication with the deposition chamber 100 and is used to control processes, such as those processes described herein. The substrate support 106 is disposed between the upper dome 108 and the lower dome 110. The plurality of upper lamps 141 are located between the upper dome 108 and the lid 154. The lid 154 includes a plurality of sensors 153 disposed therein, which are used to measure the temperature in the deposition chamber 100. At least one of the plurality of sensors 153 can be a thermometer for measuring the temperature of the substrate 102. The plurality of lower lamps 143 are located between the lower dome 110 and the bottom plate 152. The plurality of lower lamps 143 form a lower lamp assembly 145.
[0022] A processing volume 136 is formed between the upper dome 108 and the lower dome 110. The processing volume 136 includes a substrate support 106 disposed therein. The substrate support 106 includes a top surface on which the substrate 102 is disposed. The substrate support 106 is connected to a shaft 118. The shaft is connected to a motion assembly 121. The motion assembly 121 includes one or more actuators and / or adjustment devices that move and / or adjust the shaft 118 and / or the substrate support 106 in the processing volume 136. The motion assembly 121 includes a rotary actuator 122 that rotates the shaft 118 and / or the substrate support 106 about the longitudinal axis A of the deposition chamber 100. The motion assembly 121 further includes a vertical actuator 124 that raises or lowers the substrate support 106 in the z direction. The motion assembly includes a tilt adjustment device 126 for adjusting the planar orientation of the substrate support 106 and a lateral adjustment device 128 for adjusting the position of the shaft 118 and the substrate support 106 from one side to the other side in the processing volume 136.
[0023] The substrate support 106 can include lift pin holes 107 disposed therein. The lift pin holes 107 are sized to accommodate lift pins 132 to lift the substrate 102 from the substrate support 106 before or after performing a deposition process. When the substrate support 106 descends from the processing position to the transfer position, the lift pins 132 can be placed on a lift pin baffle 134.
[0024] The flow module 112 includes a plurality of process gas inlets 114, a plurality of purge gas inlets 164, and one or more exhaust outlets 116. The plurality of process gas inlets 114 and the plurality of purge gas inlets 164 are arranged on one side of the flow module 112 opposite to the one or more exhaust outlets 116. One or more flow deflectors 146 are arranged below the plurality of process gas inlets 114 and the one or more exhaust outlets 116. The flow deflector 146 is arranged above the purge gas inlet 164. A gasket 163 is arranged on the inner surface of the flow module 112 and protects the flow module 112 from the reaction gas used during the deposition process. The process gas inlet 114 and the purge gas inlet 164 are arranged such that the gas flows parallel to the top surface 150 of the substrate 102 arranged in the processing volume 136. The process gas inlet 114 is fluidly connected to a process gas source 151. The purge gas inlet 164 is fluidly connected to a purge gas source 162. The one or more exhaust outlets 116 are fluidly connected to an exhaust pump 157. Either the process gas source 151 or the purge gas source 162 can be configured to supply one or more precursors or process gases into the processing volume 136.
[0025] In the embodiments described herein, a valve 166 is fluidly arranged between the process gas source 151 and the process gas inlet 114. The valve 166 is configured to divert or split the gas flowing from the process gas source 151 into one of the first gas conduit 168 or the second gas conduit 170. The first gas conduit 168 is fluidly connected to the valve 166 and the process gas inlet 114. The second gas conduit 170 is fluidly connected to the valve 166 and the exhaust pump 157 such that the gas is diverted around the process volume 136 and exhausted without entering the process volume 136. The valve 166 described herein can be a flow diverter or a flow distributor. The valve 166 can be used to split the gas flow such that a controlled amount enters the process volume 136 while the remaining process gas flows around the process volume 136. In some embodiments, there are multiple valves 166 and multiple additional conduits similar to the first gas conduit 168 and the second gas conduit 170. The additional valves and conduits are used to enable different gas combinations to be utilized in the process volume 136 such that a single gas combination flows into and out of each valve 166, but multiple gas combinations can enter the processing volume 136 via the process gas inlet 114.
[0026] The substrate 102 can be a material such as crystalline silicon (e.g., Si<100> and / or Si<110>), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 102 can have various sizes (e.g., 200 mm, 300 mm, 450 mm, or other diameters) and can be a rectangular or square panel. Unless otherwise indicated, the examples described herein can be performed on substrates having a 200 mm diameter, 300 mm diameter, or 450 mm diameter.
[0027] FIGS. 2A and 2B are cross-sectional schematic views of superlattice structures 200a, 200b located on the top surface 150 of the substrate 102 of FIG. 1. The superlattice structures 200a, 200b include a plurality of layers and a plurality of unit cells described herein. The superlattice structures 200a, 200b are formed to enable the formation of devices such as 3D DRAM devices in the future.
[0028] FIG. 2A is a first superlattice structure 200a. The first superlattice structure 200a is formed using two layers of unit cells 206a, 206b. Each unit cell 206a, 206b includes a first layer 202a to 202e and a second layer 204a to 204e. The first layer 202a to 202e is a silicon germanium layer such that the first layer 202a to 202e includes silicon and germanium. The first layer 202a to 202e includes about 50% to about 90% silicon and about 10% to about 30% germanium, e.g., about 70% to about 90% silicon and about 12% to about 30% germanium. The second layer 204a to 204e is a silicon-containing layer such that the second layer 204a to 204e includes silicon but substantially no germanium, e.g., less than 1% germanium, e.g., less than 0.5% germanium, e.g., less than 0.1% germanium. The silicon in the second layer 204a to 204b is more than 95%, e.g., more than 98%, e.g., more than 99%, e.g., more than 99.5%.
[0029] The first layers 202a to 202e and the second layers 204a to 204e are arranged in an alternating manner such that between each pair of the first layers 202a to 202e is a second layer 204a to 204e. The first unit cell 206a includes the first layer 202a disposed on the top surface 150 of the substrate 102. The second layer 204a is disposed directly on top of the first layer 202a and forms the first unit cell 206a. The second unit cell 206b includes the first layer 202b disposed on top of the second layer 204a. A further second layer 204b is disposed directly on top of the first layer 202b and forms the second unit cell 206b. Additional unit cells are formed using the alternating first layers 202c, 202d, 202e and second layers 204c, 202d, 204e.
[0030] In the embodiments described herein, the thickness of the second layers 204a to 204e is greater than the thickness of the first layers 202a to 202e. In alternative embodiments, the thickness of the first layers 202a to 202e is greater than the thickness of the second layers 204a to 204e.
[0031] In the embodiments described herein, there are more than 30 unit cells 206a, 206b, such as more than 50 unit cells, such as more than 75 unit cells 206a, 206b, such as more than 100 unit cells 206a, 206b.
[0032] FIG. 2B is the second superlattice structure 200b. The second superlattice structure 200b is formed using four unit cells 216a, 216b. Each unit cell 216a, 216b includes a first layer 208a, 208b, 208c, a second layer 210a, 210b, 210c, a third layer 212a, 212b, 212c, and a fourth layer 214a, 214b, 214c. Each of the first layer 208a, 208b, 208c and the third layer 212a, 212b, 212c is a silicon-germanium layer, such that the first layer 208a, 208b, 208c and the third layer 212a, 212b, 212c contain silicon and germanium. The first layer 208a, 208b, 208c and the third layer 212a, 212b, 212c contain from about 50% to about 90% silicon and from about 10% to about 30% germanium, such as from about 70% to about 90% silicon and from about 12% to about 30% germanium. The second layer 210a, 210b, 210c and the fourth layer 214a, 214b, 214c are silicon-containing layers, such that the second layer 210a, 210b, 210c and the fourth layer 214a, 214b, 214c contain silicon but substantially no germanium, such as less than 1% germanium, such as less than 0.5% germanium, such as less than 0.1% germanium. The second layer 210a, 210b, 210c and the fourth layer 214a, 214b, 214c contain more than 95% silicon, such as more than 98% silicon, such as more than 99% silicon, such as more than 99.5% silicon.
[0033] The first layer 208a, 208b, 208c, the second layer 210a, 210b, 210c, the third layer 212a, 212b, 212c, and the fourth layer 214a, 214b, 214c are stacked such that the second layer 210a, 210b, 210c is on top of the first layer 208a, 208a, 208c, the third layer 212a, 212b, 212c is on top of the second layer 210a, 210b, 210c, and the fourth layer 214a, 214b, 214c is on top of the third layer 212a, 212b, 212c. As shown in FIG. 2B, the first layer 208a is disposed on the top surface 150 of the substrate 102. The second layer 210a is disposed on the first layer 208a. The third layer 212a is disposed on the second layer 210a. The fourth layer 214a is disposed on the third layer 212a. The first layer 208a, the second layer 210a, the third layer 212a, and the fourth layer 214a form the first unit cell 216a. A second set of the first layer 208b, the second layer 210b, the third layer 212b, and the fourth layer 214b is disposed on top of the first unit cell 216a and forms the second unit cell 216b. A collection of additional layers is disposed on the substrate 102 to form additional unit cells.
[0034] In the embodiments described herein, there are more than 30 unit cells 216a, 216b, such as more than 50 unit cells, such as more than 75 unit cells 216a, 216b, such as more than 100 unit cells 216a, 216b. As shown in FIG. 2B, the thicknesses of each of the first layer 208a, 208b, 208c, the second layer 210a, 210b, 210c, the third layer 212a, 212b, 212c, and the fourth layer 214a, 214b, 214c are different. The first layer 208a, 208b, 208c and the third layer 212a, 212b, 212c shown herein have similar thicknesses, while the thickness of the second layer 210a, 210b, 210c is smaller than the thickness of the fourth layer 214a, 214b, 214c. The thickness and number of layers in each unit cell 216a, 216b described herein are exemplary. Other combinations of layer thicknesses and layer combinations are also contemplated.
[0035] FIGS. 3A and 3B illustrate methods 300, 350 for forming superlattice structures 300, 350 similar to the superlattice structures 200a, 200b of FIGS. 2A and 2B. FIG. 3A illustrates a first method 300. The first method 300 includes an operation 302 of performing a pre-cleaning process on a substrate (such as substrate 102) in a first chamber. The pre-cleaning can remove any native oxide formed on the top surface 150 of the substrate 102. Subsequently, the substrate 102 is moved from the first chamber to a second chamber. After the pre-cleaning operation 302, during operation 304, the substrate 102 is baked in the second chamber. The second chamber can be similar to the deposition chamber 100 of FIG. 1 and can be an epitaxial deposition chamber. In some embodiments, when baking during operation 304 is performed at a high temperature (such as higher than about 500 ° C, such as higher than about 750 ° C, such as higher than about 850 ° C), operation 302 can be performed as appropriate. After baking the substrate 102, the top surface 150 of the substrate can be processed in the second chamber during operation 306. The processing can include growing silicon on the substrate 102 at a high temperature. The high-temperature growth of silicon is performed at a temperature higher than about 500 ° C (such as higher than about 750 ° C, such as higher than about 850 ° C). During the high-temperature growth of silicon, a silicon precursor is introduced into the second chamber.
[0036] After processing the substrate 102, the second chamber is cooled to the deposition temperature during operation 308. During operation 308, the second substrate reaches the deposition pressure simultaneously or sequentially. The deposition temperature described herein is lower than about 850 °C, such as from about 500 °C to about 850 °C, such as from about 550 °C to about 850 °C, such as from about 550 °C to about 800 °C. The deposition pressure is from about 1 torr to about 50 torr, such as from about 3 torr to about 30 torr, such as from about 5 torr to about 25 torr. In some embodiments, prior to operation 308, one or both of the temperature or pressure are already at the deposition temperature or deposition pressure. During operation 308, the temperature and pressure are stabilized such that the temperature and pressure are within a predetermined range, such as a range less than about 75 °C, such as less than about 50 °C, such as less than about 25 °C, such as less than about 10 °C. The pressure is stabilized within a range less than or about 10 torr, such as less than about 5 torr, such as less than about 3 torr, such as less than about 1 torr.
[0037] After or simultaneously with adjusting the temperature and pressure in the second chamber, the first flow of the first gas, the second flow of the second gas, and the third flow of the halide species are stabilized during operation 310 in a conduit from a process gas source (such as process gas source 151). Stabilizing the flow of the gas includes flowing each of the first gas, the second gas, and the halide species at a flow rate equal to the maximum flow rate used in method 300. Alternatively, the flow rate can be less than the maximum flow rate used in method 300. Stabilizing the flow of the first gas, the second gas, and the halide species prior to starting the deposition operation allows for rapid adjustment of the flow rate of each of the gases between the formation of each layer, thereby reducing the transition width between each layer. The stabilized gas flow can be turned around the processing volume of the second chamber such that the stabilized gas flow turns towards the exhaust port at a valve or a flow diverter.
[0038] As described herein, the first gas is a silicon-containing gas, the second gas is a germanium-containing gas, and the halide species is a gas containing a halogen precursor or a halogen gas. The silicon-containing gas includes any one or a mixture of silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), or trichlorosilane (SiCl3H). The germanium-containing gas includes any one or a mixture of germane (GeH4) or digermane (Ge2H6). The halide species includes any one or a mixture of HxSiY(4-x), HxGeY(4=x), or HY, where x is an integer between 0 and 3, and y is one of chlorine (Cl), bromine (Br), or iodine (I). Thus, the halide species can include any one of H3SiCl, H2SiCl2, HSiCl3, H3GeCl, H2GeCl2, HGeCl3, or HCl. Variants containing bromine or iodine are theoretically also used.
[0039] After stabilizing the gas flow, during operation 312, a first gas and a second gas are introduced into the process volume of the second chamber via a plurality of inlets (such as process gas inlet 114). Introducing the first gas and the second gas into the process volume enables the formation of silicon-germanium layers, such as silicon-germanium layers 202a to 202e, 208a to 208c, and 212a to 12c. The first gas and the second gas are caused to flow at a first flow rate as shown in FIG. 4A. Under process conditions and precursors similar to those described herein, the growth rate of the silicon-germanium layers 202a to 202e, 208a to 208c, and 212a to 212c is greater than about 100 nm / min, such as greater than about 150 nm / min, such as greater than about 200 nm / min.
[0040] After operation 312, the flow of the first gas and the second gas into the second chamber is stopped, and during operation 314, a halide species is caused to flow into the second chamber. For stopping the flow of the first gas and the second gas into the second chamber, only the flow into the process volume is stopped. Thus, similar to the gas flow stabilization period in operation 310, the first gas and the second gas are redirected to the vent or exhaust port. The flow of the halide species into the second chamber occurs after or simultaneously with stopping the flow of the first gas and the second gas into the second chamber. During operation 314, layer formation stops or slows down. The flow of the halide species between the depositions of the two layers reduces the width of the interface boundary between each layer. We have found that the halogen in the halide species inhibits the diffusion and accumulation of germanium near the surface of the silicon-germanium layer, and thus reduces the diffusion of germanium in the silicon layer deposited on the silicon-germanium layer.
[0041] After operation 314, the first gas is caused to flow into the second chamber again, and during operation 316, the flow of the halide species is stopped. Stopping the flow of the halide species includes stopping the flow of the halide species into the process volume having the substrate, but the halide species still flows at a stable rate to the vent or exhaust port in a manner similar to the gas flow stabilization period of operation 310. The flow of the first gas into the second chamber is used to grow silicon layers, such as second layers 204a to 204e, second layers 210a to 210c, and fourth layers 214a to 214c. The flow rate of the first gas into the second chamber may be greater than or equal to the flow rate of the first gas into the second chamber during operation 312. As shown in FIG. 4A, the flow rate of the first gas is greater during operation 316 than during operation 312. The second gas is not caused to flow during operation 316 to enable the formation of a germanium-free layer.
[0042] After forming the silicon layer during operation 316, the flow of the first gas into the second chamber is stopped during operation 310. Stopping the flow of the first gas includes stopping the flow of the first gas into the process volume having the substrate, but the first gas still flows at a steady flow rate. Instead of flowing the first gas into the process volume, the first gas is redirected to a vent or exhaust port in a manner similar to that described with respect to operation 310.
[0043] After the flow of the first gas is stopped, a purge gas is introduced into the second chamber during operation 320. Introducing the purge gas into the second chamber causes the formation of layers on the superlattice structures 200a, 200b to stop. The purge gas can be an inert gas, such that the purge gas includes one or a combination of nitrogen (N2), helium (He), neon (Ne), argon (Ar), or krypton. The purge gas can also flow during one of the other process operations, such as during process operations 310, 312, 314, 316, and 318.
[0044] After purging the process volume of the second chamber, operations 312 to 320 can be repeated the desired number of times, such as greater than 25 times, such as greater than 50 times, such as greater than 75 times, such as greater than 100 times. Each of operations 312, 314, 316, 316, 318, and 320 is repeated to form the stack of unit cells 206a, 206b to the desired number of unit cells 206a, 206b.
[0045] After forming the layers of the superlattice structures 200a, 200b, the substrate is cooled and unloaded from the second chamber during operation 322. The substrate can be cooled by stopping applying heat to the substrate. The substrate is cooled to a temperature below about 850 °C, such as below about 700 °C, such as below about 600 °C, such as below about 500 °C.
[0046] The method 350 of FIG. 3B is similar to the method 300 of FIG. 3A, but operations 324 to 328 replace operations 312 to 318. During operation 324, the first gas, the second gas, and a halide species are introduced into the second chamber simultaneously to form a silicon germanium layer. Introducing the halide species during the formation of the silicon germanium layer (such as silicon germanium layers 202a to 202e, 208a to 208c, and 212a to 212c) has been shown to reduce the transition width between each subsequent layer by suppressing germanium diffusion or aggregation in the superlattice structures 200a, 200b. The halide species has not been shown to slow down film growth as occurs in the case of introducing an etchant. Theoretically, the halogen molecules in the silicon- or germanium-containing molecules described herein reduce or eliminate the etchback effect of the halogen.
[0047] In operation 324, the flow of the second gas into the second chamber is stopped during operation 326. Stopping the flow of the second gas into the second chamber enables the formation of silicon layers, such as the second layers 204a to 204e, the second layers 210a to 210c, and the fourth layers 214a to 214c. Stopping the flow of the second gas includes stopping the flow of the second gas into the process volume having the substrate, but the second gas still flows at a stable flow rate. Instead of flowing the first gas into the process volume, the second gas is redirected to the vent or exhaust port in a similar manner as described for operation 310. During the transition from flowing the first gas and the second gas into the second chamber to flowing only the first gas into the chamber, the flow rate of the halide species can be increased, which helps to flush the process volume and suppress germanium diffusion or accumulation at the boundary between the first layer and the second layer. After stopping the flow of the second gas during operation 326 or while stopping the flow of the second gas during operation 316, the flow rate of the first gas is increased, thereby increasing the deposition rate of the silicon layer.
[0048] After forming the silicon layer, the flow of the first gas and the halide species into the second chamber is stopped during operation 328. Stopping the flow of the first gas and the halide species includes stopping the flow of the first gas and the halide species into the process volume having the substrate, but the first gas and the halide species still flow at a stable flow rate. Instead of flowing the first gas into the process volume, the first gas and the halide species are redirected to the vent or exhaust port in a similar manner as described for operation 310. After stopping the flow of the first gas and the halide species, a purge gas is introduced into the second chamber during operation 320. Introducing the purge gas into the second chamber stops the formation of the layers on the superlattice structures 200a, 200b. After flushing the process volume of the second chamber, operations 324 to 320 can be repeated the required number of times, such as more than 25 times, such as more than 50 times, such as more than 75 times, such as more than 100 times.
[0049] During each of operations 310, 312, 314, 316, 318, and 320 of method 300, the temperature and pressure in the process volume are maintained at the stable temperature and pressure determined during operation 308 and are relatively constant. Although slight variations in temperature and pressure can be measured, the temperature change between any two of operations 310, 312, 314, 316, 318, and 320 is less than about 100 °C. In some embodiments, the temperature change between any two of operations 310, 312, 314, 316, 318, and 320 is less than about 50 °C. In some embodiments, the temperature change between any two of operations 310, 312, 314, 316, 318, and 320 is less than about 25 °C. Similarly, during operations 310, 324, 326, 328, and 320 of method 350, the temperature and pressure are maintained relatively constant. Thus, the temperature change between any two of operations 310, 324, 326, 328, and 320 is less than about 100 °C. In some embodiments, the temperature change between any two of operations 310, 324, 326, 328, and 320 is less than about 50 °C. In some embodiments, the temperature change between any two of operations 310, 324, 326, 328, and 320 is less than about 25 °C.
[0050] Figures 4A and 4B illustrate process gas flow diagrams during a portion of the methods of Figures 3A and 3B. As shown in Figures 4A and 4B, a set of first graphics G1 illustrate the flow rate of a first gas, a set of second graphics G2 illustrate the flow rate of a second gas, and a set of third graphics G3 illustrate the flow rate of a halide species in the process volume of the second chamber. The exact flow rates described herein are exemplary. Consider other gas flow combinations.
[0051] In one embodiment, the flow rate of the halide species is constant during each of operations 312 to 316 of the first method 300 and during each of operations 324 to 328 of the second method 350. The flow rate of the first gas is also similar during operations 312 and 316 of the first method 300 and during operations 324 to 328 of the second method 350. As shown in Figures 4A and 4B, after flushing the process volume of the second chamber during flushing operation 320, the film formation operation is repeated.
[0052] FIG. 5A and FIG. 5B illustrate the electron microscope measurement results of the layers of the superlattice structure. A silicon-germanium layer with approximately 85% silicon and approximately 15% germanium forms the cross-section illustrated in FIG. 5A. A silicon-germanium layer with approximately 75% silicon and approximately 25% germanium forms the cross-section illustrated in FIG. 5B. During the formation of the superlattice structure of FIG. 5A and FIG. 5B, a halide species is introduced between the formation of each layer, thereby helping to reduce the transition width between the layers.
[0053] FIG. 5A illustrates a single silicon-germanium layer 506 disposed between two silicon layers 502, 510. The first silicon layer 502 and the silicon-germanium layer 506 include a first transition region 504 disposed therebetween. The silicon-germanium layer 506 and the second silicon layer 502 include a second transition region 508 disposed therebetween. FIG. 6A illustrates the widths of the transition regions 504, 508 above different lateral positions. As shown in FIG. 6A, on the measured lateral portion of the superlattice structure, the transition widths of both the first transition region 504 and the second transition region 508 are approximately 1.14 nm on average. In FIG. 6A, the average first transition width line 602 represents the average transition width on the first transition region 504. The average second transition width line 604 represents the average transition width on the second transition region 508.
[0054] FIG. 5B illustrates a single silicon-germanium layer 516 disposed between two silicon layers 512, 520. The first silicon layer 512 and the silicon-germanium layer 516 include a first transition region 514 disposed therebetween. The silicon-germanium layer 516 and the second silicon layer 520 include a second transition region 518 disposed therebetween. FIG. 6B illustrates the widths of the transition regions 514, 518 above different lateral positions. As shown in FIG. 6B, the transition width of the first transition region 514 is approximately 0.90 nm, and the transition width of the second transition region 518 is approximately 1.31 nm. In FIG. 6B, the average first transition width line 606 represents the average transition width on the first transition region 514. The average second transition width line 608 represents the average transition width on the second transition region 518.
[0055] FIG. 7 illustrates a partial device structure 700 of a memory device. The partial device structure 700 is formed from a first superlattice structure 200a. Similar device structures are formed from different superlattice structures (e.g., a second superlattice structure 200b). The partial device structure 700 includes a plurality of trenches 708 formed through layers 202a to 202e and 204a to 204e of the first superlattice structure 200a. The trenches include sidewalls 710 that can be etched or processed during subsequent process operations. The partial device structure 700 further includes a plurality of etch holes 702, which can be similar to the trenches 708. However, the etch holes 702 have been filled with one or more of a polymer material 704 and an oxide material 706. The polymer material 704 can be a polysilicon material. The oxide material 706 can be silicon oxide or silicon nitride. In some embodiments, alternatively, the oxide material 607 can be a silicon germanium material.
[0056] The partial device material 700 is illustrated herein as an exemplary structure that can be formed from the first superlattice structure 200a. It is contemplated that a variety of device structures can be formed from superlattice structures that can be produced using the methods described herein.
[0057] As described herein, the chemical and process conditions described herein can achieve well-defined interface transitions with high growth rates. The growth rate of the silicon germanium layer can be greater than 200 nm / min. The growth rate of the silicon layer can be greater than 150 nm / min. The layers formed herein have exhibited few, if any, defects in the layers and are capable of being used in a variety of different stack configurations.
[0058] The processes and operations described herein may include first removing native oxide by a pre-clean operation (HF dip or the like), followed by a suitable bake in an epitaxial deposition chamber. Additionally, a high-temperature bake in the epitaxial deposition chamber may be used without a separate pre-clean operation. Second, additional surface treatment may be performed in the epitaxial deposition chamber, such as high-temperature growth of silicon. Third, the epitaxial deposition chamber is cooled to a deposition temperature of less than or equal to 850 °C. Fourth, the pressure in the epitaxial deposition chamber is adjusted to a deposition pressure of about 1 torr to about 50 torr. Fifth, the temperature and pressure of the epitaxial deposition chamber are stabilized. Sixth, the process gas is exhausted to stabilize the process gas flow. Seventh, a suitable process gas is introduced into the epitaxial deposition chamber to initiate the growth of the initial layer. The initial layer is a silicon-germanium layer with a germanium content of about 12% to about 30%. Additional halide species may be incorporated to improve the compositional transition between layers. Eighth, the precursor flow is adjusted to stop the flow of the silicon-germanium reaction gas or evacuate the flow of the silicon-germanium reaction gas around the epitaxial deposition chamber. If the previous operation does not include halide species, the halide species are flowed. If the previous operation includes halide species, increasing the flow rate of the halide species during this operation is an option. It should be noted that this operation is also used to flush unwanted species (Ge) from the chamber. Ninth, a silicon layer growth precursor is introduced. Depending on the halide species used to improve the layer transition, the halide species may be kept directed to the chamber, closed, or directed to the vent. Tenth, the flow of the silicon precursor is stopped or the silicon precursor is evacuated around the chamber. Eleventh, the epitaxial deposition chamber is flushed. Flushing the epitaxial deposition chamber may include introducing a flushing gas such as helium (He), neon (Ne), or argon (Ar). Operations seven through eleven may be repeated the desired number of times to form a superlattice structure. Additional SiGe and Si layers of different thicknesses may be added to vary the unit cell, thereby producing different unit cells. After the formation of the superlattice structure is complete, the substrate is cooled and unloaded from the epitaxial deposition chamber.
[0059] While the foregoing refers to embodiments of the present disclosure, other and additional embodiments of the present disclosure may be designed without departing from the basic scope, and the scope of the present disclosure is determined by the claims that follow.
[0060] 100: Deposition chamber 102: Substrate 106: Substrate support 107: Lift pin hole 108: Upper dome 110: Lower dome 112: Flow module 114: Process gas inlet 116: Exhaust outlet 118: Shaft 120: Controller 121: Motion component 122: Rotary actuator 124: Vertical actuator 126: Tilt adjustment device 128: Lateral adjustment device 132: Lifting pin 134: Lifting pin baffle 136: Processing volume 141: Upper lamp 143: Lower lamp 145: Lower lamp assembly 146: Deflector 148: Lower main body 150: Top surface 151: Process gas source 152: Bottom plate 153: Sensor 154: Cover 156: Upper main body 157: Exhaust pump 162: Flushing gas source 163: Gasket 164: Flushing gas inlet 166: Valve 168: First gas conduit 170: Second gas conduit 200a: Superlattice structure 200b: Superlattice structure 202a: First layer 202b: First layer 202c: First layer 202d: First layer 202e: First layer 204a: Second layer 204b: Second layer 204c: Second layer 204d: Second layer 204e: Second layer 206a: First unit cell 206b: Second unit cell 208a: First layer 208b: First layer 208c: First layer 210a: Second layer 210b: Second layer 210c: Second layer 212a: Third layer 212b: Third layer 212c: Third layer 214a: Fourth layer 214b: Fourth layer 214c: Fourth layer 216a: Unit cell 216b: Unit cell 300: Method 302: Operation 304: Operation 306: Operation 308: Operation 310: Operation 312: Operation 314: Operation 316: Operation 318: Operation 320: Operation 322: Operation 324: Operation 326: Operation 328: Operation 350: Method 502: Second silicon layer 504: First transition region 506: Silicon-germanium layer 508: Second transition region 510: Silicon layer 512: First silicon layer 514: First transition region 516: Silicon-germanium layer 518: Second transition region 520: Silicon layer 602: Average first transition width line 604: Average second transition width line 606: Average first transition width line 608: Average second transition width line 700: Partial device structure 702: Etch hole 704: Polymer material 706: Oxide material 708: Groove 710: Sidewall A: Vertical axis G1: First figure G2: Second figure G3: Third figure
[0061] Domestic deposit information (Please note in the order of deposit institution, date, and number) None Foreign deposit information (Please note in the order of deposit country, institution, date, and number) None
Claims
1. A controller configured to control a process comprising the steps of: (1) flowing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon-germanium layer; (2) stopping the flow of the silicon-containing gas and the germanium-containing gas into the deposition chamber after the formation of the silicon-germanium layer; (3) flowing a halide species into the deposition chamber, wherein the halide species is a precursor; and (4) flowing a silicon-containing gas into the deposition chamber to form a silicon layer.
2. The controller as described in Request 1, wherein the process further comprises the following steps: repeating steps (1) to (4) more than 20 times.
3. The controller as claimed in claim 1, wherein the halogenated species comprises one or a combination of HxSiY(4-x), HxGeY(4-x) or HY, wherein x is equal to an integer between 0 and 3, and Y is equal to one of chlorine (Cl), bromine (Br) or iodine (I).
4. The controller as described in claim 1, wherein step (3) is performed between step (2) and step (4).
5. The controller as described in claim 1, wherein step (3) is performed during steps (1) and (4).
6. The controller as claimed in claim 1, wherein the silicon-germanium layer and the silicon layer are grown at a growth rate greater than about 150 nm / min, and a transition width between each of the silicon-germanium layer and the silicon layer is less than about 1.4 nm.
7. The controller as claimed in claim 1, wherein the silicon-germanium layer comprises about 12% to about 30% germanium.
8. A controller configured to control a process comprising the steps of: forming a unit cell comprising the steps of: flowing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon-germanium layer; stopping the flow of the germanium-containing gas into the deposition chamber after the formation of the silicon-germanium layer; flowing a halide species into the deposition chamber, wherein the halide species is a precursor; and forming a silicon layer from the silicon-containing gas.
9. The controller as described in claim 8, wherein the process further comprises the step of repeating the unit cell formation to form a stack of more than 25 unit cells.
10. The controller as claimed in claim 8, wherein the halide species flows in during each of the formation of the silicon-germanium layer, the formation of the silicon layer, and between the formation of the silicon-germanium layer and the formation of the silicon layer.
11. The controller as claimed in claim 8, wherein the silicon layer is disposed directly on the silicon-germanium layer.
12. The controller as claimed in claim 8, wherein the halide species flows into the deposition chamber during each of the formation of the silicon-germanium layer, the formation of the silicon layer, and between the formation of the silicon-germanium layer and the formation of the silicon layer.
13. The controller as claimed in claim 8, wherein the halide species flows into the deposition chamber between the formation of the silicon-germanium layer and the formation of the silicon layer.
14. A method of forming a semiconductor device, comprising the steps of: (1) flowing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon-germanium layer on a substrate in the deposition chamber, the silicon-containing gas flowing at a first flow rate and the germanium-containing gas flowing at a second flow rate; (2) after forming the silicon-germanium layer, stopping the flow of the germanium-containing gas into the deposition chamber; (3) flowing a halide species into the deposition chamber; and (4) forming a silicon layer on the substrate in the deposition chamber, wherein the second flow rate of the silicon-containing gas in step (4) is greater than the first flow rate.
15. The method as claimed in claim 14, wherein step (2) further comprises the step of stopping a flow of silicon-containing gas into the deposition chamber after the silicon-germanium layer is formed, and step (4) comprises the step of allowing a silicon-containing gas to flow into the deposition chamber to form the silicon layer.
16. The method as described in claim 14, wherein the silicon-containing gas in step (1) continues to flow during steps (3) and (4), and the first flow rate increases to the second flow rate.
17. The method as described in claim 16, wherein the increase in the first flow rate occurs simultaneously with or after the cessation in step (2).
18. The method as claimed in claim 14, wherein the halogenated species in step (3) flows during steps (1) and (2), and a third flow rate of the halogenated species is increased to a fourth flow rate before step (4).
19. The method as described in claim 18, wherein the halogenated species is reduced from the fourth flow rate back to the third flow rate for use in the formation of the silicon layer in step (4).
20. A controller configured to control a process comprising the steps of: (1) flowing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon-germanium layer; (2) after the formation of the silicon-germanium layer, stopping the flow of the silicon-containing gas and the germanium-containing gas into the deposition chamber; (3) flowing a halide species into the deposition chamber, the halide species comprising one or a combination thereof of HxSiY(4-x), HxGeY(4-x) or HY, wherein x is equal to an integer between 0 and 3, and Y is equal to one of chlorine (Cl), bromine (Br) or iodine (I); and (4) flowing a silicon-containing gas into the deposition chamber to form a silicon layer.
21. A controller configured to control a process comprising the steps of: (1) flowing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon-germanium layer; (2) stopping the flow of the silicon-containing gas and the germanium-containing gas into the deposition chamber after the formation of the silicon-germanium layer; (3) flowing a halide species into the deposition chamber; and (4) flowing a silicon-containing gas into the deposition chamber to form a silicon layer, wherein step (3) is performed during steps (1) and (4).
22. A controller configured to control a process comprising the steps of: (1) flowing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon-germanium layer comprising about 12% to about 30% germanium; (2) stopping the flow of the silicon-containing gas and the germanium-containing gas into the deposition chamber after the formation of the silicon-germanium layer; (3) flowing a halide species into the deposition chamber; and (4) flowing a silicon-containing gas into the deposition chamber to form a silicon layer.
23. A controller configured to control a process comprising the steps of: forming a unit cell comprising the steps of: flowing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon-germanium layer; stopping the flow of the germanium-containing gas into the deposition chamber after the formation of the silicon-germanium layer; flowing a halide species into the deposition chamber; and forming a silicon layer from the silicon-containing gas; wherein the halide species flows in during each of the formation of the silicon-germanium layer, the formation of the silicon layer, and between the formation of the silicon-germanium layer and the formation of the silicon layer.
24. A controller configured to control a process comprising the steps of: forming a unit cell comprising the steps of: flowing a silicon-containing gas and a germanium-containing gas into a deposition chamber to form a silicon-germanium layer; stopping the flow of the germanium-containing gas into the deposition chamber after the formation of the silicon-germanium layer; flowing a halide species into the deposition chamber; and forming a silicon layer from the silicon-containing gas; wherein the halide species is flowing into the deposition chamber during each of the formation of the silicon-germanium layer, the formation of the silicon layer, and between the formation of the silicon-germanium layer and the formation of the silicon layer.
Citation Information
Patent Citations
Manufacturing of an Si / SiGe super lattice structure by epitaxial growth
EP0858101A2
