Deskew circuit and method for operating one or more deskew stages

Abstract

A circuit includes one or more anti-skew stages. Each of the one or more anti-skew stages is used to adjust a transition edge of a signal and includes: a single inverter; a header for coupling a first power supply voltage to the single inverter; a pin for coupling a second power supply voltage to the single inverter; a capacitor coupled to an output of the single inverter; and a switching circuit coupled between the output of the single inverter and the capacitor.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Various types of 3D / 2.5D integrated circuit (IC) interfaces exist. For example, Universal Chiplet Interconnect Express (UCIe) is an interface standard that supports data rates up to 32 Gb / s. Such high-speed interfaces may include anti-skew circuitry to ensure signal synchronization and alignment within the interface. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify one embodiment of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of an embodiment of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] In addition, spatial relative terms, such as "below," "below," "lower part," "above," "upper part," "top," "bottom," and the like, may be used herein for ease of description to describe the relationship between one or more elements or features as illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] Generally, per-channel anti-skew circuitry is a component of IC interfaces, such as Universal Chiplet Interconnect Express (UCIe) interfaces, to ensure data channel anti-skewness, for example, meeting tolerance requirements for different speeds at a maximum anti-skew step resolution of 16 mUI. Design specifications, including correction range and resolution, can vary depending on the operating data rate. To achieve a wider correction range while maintaining fine resolution, additional tuning stages can be added. For example, anti-skew stage units can be cascaded to extend the correction range for lower speed applications. To achieve a k× tuning range, k× stages can be cascaded. However, this approach is accompanied by significant cost in terms of power and area, which is unacceptable for high-performance and energy-saving UCIe interface designs. For the above example of cascading k× stages, the cost is at least k times higher in terms of power and area. Furthermore, such designs that do not implement the techniques disclosed herein may not have sufficient rise / fall times, which can cause inter-symbol interference (ISI).

[0008] The technology disclosed herein provides a circuit including one or more anti-skew stages. Each of the one or more anti-skew stages can be used to adjust the transition edge of a signal based on a first power supply voltage coupled to a headend and a second power supply voltage coupled to a footer. In some embodiments, each of the one or more anti-skew stages may include an inverter having an input and an output. The input can be used to receive a signal, and the output can be used to provide an updated version of the signal with adjusted transition edges based on the first power supply voltage coupled to the headend and the second power supply voltage coupled to the footer. In some embodiments, the headend may selectively couple the first power supply voltage to the inverter, and the footer may selectively couple the second power supply voltage to the inverter. In some embodiments, a capacitor may be coupled to the output of the inverter, and a switching circuit may be coupled between the output of the inverter and the capacitor. In some embodiments, the technology disclosed herein may include additional structures for speed control drive to extend the tuning range. For example, a driver unit such as a speed control adjustable driver may be added. The process voltage and temperature (PVT) calibration structure or circuit can be additionally coupled. Additional switching units, such as transmission gate switches, can be added.

[0009] The techniques disclosed herein provide adaptive anti-skew circuitry for various speed data links (e.g., various data rates: 4 / 8 / 12 / 16 / 24 / 32 Gb / s) in IC interfaces (e.g., UCIe interfaces). The techniques allow anti-skew circuitry to support different data rate operation requirements and achieve improved tuning efficiency (e.g., at least twice as much) and finer resolution, while achieving power and area reduction (e.g., improved power, performance, and area (PPA)). Furthermore, for lower-speed operation applications, the techniques disclosed herein allow for slower rise / fall times without causing ISI problems. Additionally, problems caused by PVT variations can be prevented by incorporating PVT calibration structures or circuits. The techniques disclosed herein provide a novel, simple, and cost-effective solution for designing adaptive anti-skew circuitry in receivers and / or transmitters. In some embodiments, the techniques disclosed herein may be used in other applications, including but not limited to various die-to-die interfaces such as 3D IC applications, bandwidth on wafer (BoW), advanced interconnect bridge (AIB), high bandwidth memory (HBM), etc.

[0010] Figure 1A is a schematic diagram of an example circuit 100 according to some embodiments. In some embodiments, circuit 100 may be a circuit component or stage. For example, circuit 100 may be or include one or more anti-skew stages. Circuit 100 may include circuit components, including but not limited to inverters, headers, pins, capacitors, switching circuits, etc. The circuit 100 shown in Figure 1A is a non-limiting example of circuit 100. In some embodiments, circuit 100 may include more, fewer, or different components than those shown in or described with respect to Figure 1A.

[0011] In some embodiments, circuit 100 includes: a single inverter; a header for coupling a first power supply voltage to the single inverter; a pin for coupling a second power supply voltage to the single inverter; a capacitor coupled to the output of the single inverter; and a switching circuit coupled between the output of the single inverter and the capacitor. In some embodiments, circuit 100 may be included in the data channel of at least one of a transmitter or a receiver. Circuit 100 may include an inverter having an input and an output, and the inverter may be configured such that the input receives a signal and the output provides an updated version of a signal with adjusted transition edges. Circuit 100 may include: a header for selectively coupling a first power supply voltage to the inverter; a pin for selectively coupling a second power supply voltage to the inverter; a capacitor coupled to the output of the inverter; and a switching circuit coupled between the output of the inverter and the capacitor.

[0012] Circuit 100 can be used to adjust the transition edge of a signal. Figure 1B is a schematic diagram of an example waveform associated with circuit 100 of Figure 1A according to some embodiments. Figure 1C is a schematic diagram of an example waveform associated with circuit 100 of Figure 1A according to some embodiments. More specifically, Figure 1B illustrates a signal 150A that can be output by circuit 100 with adjusted transition edge for high-speed operation, and Figure 1C illustrates a signal 150B that can be output by circuit 100 with adjusted transition edge for low-speed operation. As illustrated in Figure 1B, circuit 100 can adjust the transition edge of signal 150A by a tuning range ∆T. As illustrated in Figure 1C, circuit 100 can adjust the transition edge of signal 150B by a tuning range 4×∆T.

[0013] Figure 2 is a schematic diagram of an example circuit 200 according to some embodiments. In some embodiments, circuit 200 may be substantially similar to or have the features of circuit 100. In some embodiments, circuit 200 includes an inverter 210, a header 220, a pin 230, and a variable capacitor 240. In some embodiments, variable capacitor 240 may include capacitor 250 and switching circuit 260. The examples shown in Figure 2 are non-limiting examples of circuit 200. In some embodiments, circuit 200 may include more, fewer, or different components than those shown in or described with respect to Figure 2.

[0014] In some embodiments, circuit 200 may be an anti-skew stage for adjusting the transition edge of a signal. Circuit 200 may include a single inverter, such as inverter 210. Inverter 210 may include an input IN for receiving a signal (e.g., a logic state, its voltage, etc.). Inverter 210 may include an output OUT for providing an updated version of the signal with adjusted transition edges. In some embodiments, as illustrated in Figure 2, inverter 210 may be coupled to a head terminal 220 and a pin terminal 230 such that the head terminal 220 and pin terminal 230 can provide a power supply voltage. In some embodiments, inverter 210 may output an updated version of the signal based on a power supply voltage from at least one of the head terminal 220 and pin terminal 230. In some embodiments, inverter 210 may include a semiconductor device, such as a metal-oxide-semiconductor (MOS) transistor. For example, inverter 210 may include n-type MOS (NMOS) and p-type MOS (PMOS) transistors.

[0015] Circuit 200 may include a header 220. Header 220 may be used to couple a first power supply voltage to inverter 210. In some embodiments, the first power supply voltage may be a positive voltage rail (VDD). In some embodiments, header 220 may include N PMOS transistors. In some embodiments, header 220 may selectively couple the first power supply voltage to inverter 210. For example, a first number of the coupled N NMOS transistors may be in a logic high state "H", while a second number of the coupled N PMOS transistors may be in a logic low state "L". In some instances, header 220 may selectively couple the first power supply voltage to inverter 210 at least in part based on a signal received from input IN. For example, a first number of the N PMOS transistors in header 220 may be turned on, the first number being determined based on the signal received from input IN.

[0016] Circuit 200 may include pin 230. Pin 230 may be used to couple a second power supply voltage to inverter 210. In some embodiments, the second power supply voltage may be a ground reference (GND) or a voltage level reference point in circuit 200. In some embodiments, pin 230 may include N NMOS transistors. In some embodiments, pin 230 may selectively couple the second power supply voltage to inverter 210. For example, a first number of the coupled N NMOS transistors may be in a logic high state "H", while a second number of the coupled N NMOS transistors may be in a logic low state "L". In some instances, pin 230 may selectively couple the second power supply voltage to inverter 210 at least in part based on a signal received from input IN. For example, a second number of the N N NMOS transistors at pin 230 may be turned on, the second number being determined based on the signal received from input IN.

[0017] In some embodiments, the head end 220 and the pin end 230 may be alternately turned on. For example, N PMOS transistors of the head end 220 and N NMOS transistors of the pin end 230 may be alternately turned on. The inverter 210 may be used to alternately couple to a first power supply voltage from the N PMOS transistors of the head end 220 and a second power supply voltage from the N NMOS transistors of the pin end 230. In some embodiments, the first number of PMOS transistors to be turned on in the head end 220 and the second number of NMOS transistors to be turned on in the pin end 230 may be the same. For example, the same number of PMOS transistors in the head end 220 and NMOS transistors in the pin end 230 may be in a logic high state "H" (and / or a logic low state "L"). In some embodiments, the first number and the second number may correspond to the adjustment range of the signal transition edge. For example, when the first number and the second number are larger (or smaller), the tuning range of the signal transition edge may be larger. In some embodiments, when a first number of PMOS transistors at the head end 220 and NMOS transistors at the pin end 230 are in a logic high state, circuit 200 can provide an updated version of the signal with a first adjusted transition edge (e.g., the first edge 190A in Figure 1B or the first edge 191A in Figure 1C). When a second number of PMOS transistors at the head end 220 and NMOS transistors at the pin end 230 are in a logic high state, circuit 200 can provide an updated version of the signal with a second adjusted transition edge (e.g., the second edge 190B in Figure 1B or the second edge 191B in Figure 1C). When a third number of PMOS transistors at the head end 220 and NMOS transistors at the pin end 230 are in a logic high state, circuit 200 can provide an updated version of the signal with a third adjusted transition edge (e.g., the third edge 190C in Figure 1C or the third edge 191C in Figure 1C). In some embodiments, the head end 220 and the foot end 230 can be programmed, are programmable, and / or reconfigurable to allow for a variety of adjustable transition edges. For example, by programming the head end 220 and the foot end 230, the anti-skew buffer drive strength can be adjusted according to speed requirements.

[0018] Circuit 200 may include a variable capacitor 240 coupled to the output OUT of inverter 210. In some embodiments, variable capacitor 240 may include a MOS capacitor, a passive capacitor, or a combination thereof. For example, variable capacitor 240 may include capacitor 250, which may be or include a MOS capacitor, a passive capacitor, or a combination thereof.

[0019] In some embodiments, the variable capacitor 240 may include a switching circuit 260. In some embodiments, the switching circuit 260 may be coupled between the output of the inverter 210 and the capacitor 250. In some embodiments, the switching circuit 260 may include a pass gate or be used as a pass gate. For example, when the head end 220 includes N PMOS transistors and / or the foot end 230 includes N NMOS transistors, the variable capacitor 240 may include 2M variable capacitors 240, and the switching circuit 260 may include 2M pass gates. In some embodiments, the switching circuit 260 (and / or pass gates) may include MOS transistors. For example, the switching circuit 260 may include both PMOS and NMOS transistors. This can provide improved capacitor charging / discharging efficiency, thereby allowing sufficient rise / fall times. In some embodiments, the number of pass gates to be activated corresponds to the adjustment resolution of the signal transition edge. For example, the circuit 200 may be configured to adjust the signal transition edge with an adjustment resolution corresponding to the number of pass gates. In some embodiments, when the transmission gate is activated, the gate is turned on and allows a signal (e.g., the output of inverter 210) to pass through. When the transmission gate is deactivated, the gate blocks the signal. In some embodiments, the switching circuit 260 can be used to adjust the delay and / or skew of the output signal from inverter 210. In some embodiments, the switching circuit 260 (and / or the transmission gate) can be used to adjust the timing of the signal by selectively introducing delays. For example, the timing of the signal passing through the switching circuit 260 can be adjusted by selectively enabling or disabling the gate. In some embodiments, each of the transmission gates in the switching circuit 260 can be used to introduce different amounts of delay, thereby finely tuning the timing of the signal with high precision (e.g., finer resolution).

[0020] In some embodiments, circuit 200 may be coupled to or include a capacitor connected to or included in buffer circuit 270. In some embodiments, buffer circuit 270 may provide impedance matching, signal amplification, etc., without changing the logic level of the output of inverter 210 (e.g., an updated version of the signal). For example, buffer circuit 270 may filter out noise, enhance signal stability, etc.

[0021] Figure 3 is a schematic diagram of an example circuit 300 according to some embodiments. Circuit 300 may include first circuits 300-1, ..., k-th circuits 300-K, where k may be any integer. In some embodiments, each of the first circuits 300-1, ..., k-th circuits 300-K may be substantially similar to or have the characteristics of circuits 100, 200, etc. In some embodiments, each of the first circuits 300-1, ..., k-th circuits 300-K may be used to adjust the transition edges of a signal. The examples of circuits 300 shown in Figure 3 are non-limiting examples. In some embodiments, circuit 300 may include more, fewer, or different components than those shown in or described with respect to Figure 3.

[0022] By incorporating multiple stage units, such as first circuit 300-1, ..., k-th circuit 300-K, the design challenge of meeting the requirement for improved speed anti-skew tuning range can be relaxed. In some embodiments, the same speed adjustment can be applied to each of the first circuit 300-1, ..., k-th circuit 300-K to achieve a wider correction range during lower speed operation without causing ISI problems. For example, to avoid ISI problems at 32 Gb / s, multiple stage units (e.g., first circuit 300-1, ..., k-th circuit 300-K) can be incorporated to obtain sufficient rise / fall times while meeting the minimum correction range requirement (e.g., K×2 M steps) for a 32 Gb / s design.

[0023] In some embodiments, as illustrated in Figure 3, the first circuits 300-1, ..., the kth circuit 300-K may be included in a unit circuit, a unit stage (e.g., an anti-skew stage), etc. In some embodiments, the first circuits 300-1, ..., the kth circuit 300-K may be connected in series, in parallel, or in a combination of series and parallel and / or coupled to each other. In some embodiments, each of the first circuits 300-1, ..., the kth circuit 300-K may be used to adjust the transition edge of the signal in the corresponding circuit, stage, etc. In some embodiments, each of the first circuits 300-1, ..., the kth circuit 300-K may be used to provide different adjustments to the transition edge. For example, a first number of MOS transistors may be activated in the first circuit 300-1, and a second number of MOS transistors may be activated in the kth circuit 300-K. Based on the coupled circuits (e.g., the first circuits 300-1, ..., the kth circuit 300-K), the output signal of the circuit can be modulated in various ways.

[0024] Figure 4 is a schematic diagram of an example circuit 400 according to some embodiments. More specifically, circuit 400 may be a receiver circuit. In some embodiments, circuit 400 is a UCIe receiver. Circuit 400 may include various components, including but not limited to data channel 420 (e.g., I_RXDATA[63:0]), bump structure (e.g., uBump), amplifier, circuit 410, matched delay wiring 415, D flip-flop (DFF), and deserializer 430, etc. In some embodiments, circuit 410 may be substantially similar to or have the characteristics of circuits 100, 200, 300, etc. That is, the anti-skew circuitry disclosed herein (e.g., circuits 100, 200, 300, etc.) may be included in the receiver. As illustrated in Figure 4, in some embodiments, one or more anti-skew stages (e.g., included in or related to circuit 410) may be included in circuit 400 and operatively coupled between data channel 420 and deserializer 430. In some embodiments, circuit 410 may be used to adjust the transition edge of a signal in circuit 400. For example, circuit 410 may receive a signal as input from data channel 420 and provide an updated version of the signal with adjusted transition edges to deserializer 430. In some embodiments, circuit 410 may provide an updated version of the signal to a matching delay line 415, which circuit 410 may insert into the data path to match the clock path delay. The illustration in Figure 4 is a non-limiting example of circuit 400. In some embodiments, circuit 400 may include more, fewer, or different components than those illustrated in or described with respect to Figure 4.

[0025] Figure 5 is a schematic diagram of an example circuit 500 according to some embodiments. More specifically, circuit 500 may be a transmitter circuit. In some embodiments, circuit 500 is a UCIe transmitter. Circuit 500 may include various components, including but not limited to a sequencer 530, a driver, a bump structure (e.g., uBump), a data channel (e.g., I_TXDATA[63:0]), circuit 510, clock tree 520, etc. In some embodiments, clock tree 520 may include clock tree synthesis (CTS), a phase interpolator (PI) and a digital clock manager (DCC), a delay locked loop (DLL), a phase locked loop (PLL), etc. In some embodiments, circuit 510 may be substantially similar to or have the features of circuits 100, 200, 300, etc. That is, the anti-skew circuitry disclosed herein (e.g., circuit 100, circuit 200, circuit 300, etc.) may be included in the transmitter. As illustrated in Figure 5, in some embodiments, one or more anti-skew stages (e.g., included in or related to circuit 510) may be included in circuit 500 and operatively coupled between sequencer 530 and clock tree 520. In some embodiments, circuit 510 may be used to adjust the transition edges of signals in circuit 500. For example, circuit 510 may receive a signal as input from clock tree 520 and provide sequencer 530 with an updated version of the signal having adjusted transition edges. The illustration in Figure 5 is a non-limiting example of circuit 500. In some embodiments, circuit 500 may include more, fewer, or different components than those illustrated in or described with respect to Figure 5.

[0026] In some embodiments, the anti-skew circuitry disclosed herein (e.g., circuit 100, circuit 200, circuit 300, etc.) may include corresponding data channels among a plurality of data channels operatively inserted between the transmitter and the receiver. For example, the circuitry may receive a signal from the transmitter as input and provide the receiver with an updated version of the signal having adjusted transition edges. By thus inserting the circuitry and aligning timing characteristics, compatibility between the transmitter and the receiver can be improved. For example, the circuitry inserted between the transmitter and the receiver may even enable effective communication between the transmitter and the receiver by means of different timing requirements or capabilities.

[0027] Figure 6 is a schematic diagram of an example circuit 600 according to some embodiments. Circuit 600 includes an inverter 610, a header 620, a pin 630, and a variable capacitor 640. In some embodiments, circuit 600 may be substantially similar to or have features of circuit 200, etc. For example, inverter 610, header 620, pin 630, and variable capacitor 640 may be substantially similar to or have features of inverter 210, header 220, pin 230, and variable capacitor 240, respectively. In some embodiments, circuit 600 may additionally include a first calibration circuit 625 and a second calibration circuit 635. For example, the first calibration circuit 625 may be included in or coupled to header 620. The second calibration circuit 635 may be included in or coupled to pin 630. The illustration in Figure 6 is a non-limiting example of circuit 600. In some embodiments, circuit 600 may include more, fewer, or different components than those shown in or described with respect to Figure 6.

[0028] In some embodiments, the headend 620 may be coupled to or include the following: a first current source 626 (e.g., I REFP); N first switches 627, each of which is used to selectively couple a first power supply voltage (e.g., VDD) to the headend 620; and N second switches 628, each of which is used to selectively couple the first current source 626 to the headend 620. In some embodiments, when the headend 620 includes N PMOS transistors (e.g., <0>, …, <N-1>), each of the N first switches 627 (e.g., ENB_P<0>, …, ENB_P<N-1>) may selectively couple the first power supply voltage to a corresponding PMOS transistor, and each of the N second switches 628 (e.g., EN_P<0>, …, EN_P<N-1>) may selectively couple the first current source 626 to a corresponding PMOS transistor.

[0029] In some embodiments, pin 630 may be coupled to or include the following: a second current source 636 (e.g., I REFN); N first switches 637, each of which is used to selectively couple a second power supply voltage (e.g., VSS) to pin 630; and N second switches 638, each of which is used to selectively couple the second current source 636 to pin 630. In some embodiments, when pin 630 includes N NMOS transistors (e.g., <0>, …, <N-1>), each of the N first switches 637 (e.g., ENB_P<0>, …, ENB_P<N-1>) may selectively couple the second power supply voltage to a corresponding NMOS transistor, and each of the N second switches 638 (e.g., EN_P<0>, …, EN_P<N-1>) may selectively couple the second current source 636 to a corresponding NMOS transistor.

[0030] In some embodiments, a first current source 626 may provide a current source I REFP, and a second current source 636 may provide a current source I REFN, such that a constant current bias (e.g., I REFN / I REFP) can be provided up to a current of 600. For example, I REFP and I REFN may be constant. This allows the driver strength to be unaffected by PVT variations.

[0031] Figure 7 is a flowchart of an example method 700 for operating a circuit according to some embodiments. Method 700 may be performed by one or more components of circuits 100, 200, 300, 400, 500, 600, etc. In some embodiments, method 700 is performed by other entities. In some embodiments, method 700 may include more, fewer, or different operations compared to those shown in Figure 7.

[0032] In short, method 700 can begin with operation 710, which receives a signal from the output of the inverter. Method 700 can continue with operation 720, which selectively couples a first power supply voltage to the inverter. Method 700 can continue with operation 730, which selectively couples a second power supply voltage to the inverter. Method 700 can continue with operation 740, which provides an updated version of the signal with adjusted transition edges from the output of the inverter.

[0033] Method 700 may be initiated by operation 710, which receives a signal at the output of the inverter. At operation 710, the inverter (e.g., inverter 210) may receive a signal via its input. In some embodiments, the inverter is included as part of one or more anti-skew stages in a receiver (e.g., circuit 400). In some embodiments, the inverter is included as part of one or more anti-skew stages in a transmitter (e.g., circuit 500).

[0034] Method 700 may continue with operation 720, selectively coupling a first power supply voltage to the inverter. At operation 720, a header (e.g., header 220) may couple the first power supply voltage to the inverter. Method 700 may simultaneously perform or continue with operation 730, selectively coupling a second power supply voltage to the inverter. At operation 730, a pin (e.g., pin 230) may couple the second power supply voltage to the inverter. In some embodiments, method 700 may include: turning on a first number of p-type metal-oxide-semiconductor (PMOS) transistors to selectively couple the first power supply voltage to the inverter, and turning on a second number of n-type metal-oxide-semiconductor (NMOS) transistors to selectively couple the second power supply voltage to the inverter. In some embodiments, the first number and the second number are the same. In some embodiments, method 700 may include alternately turning on PMOS transistors and NMOS transistors. In some embodiments, the first number of PMOS transistors to be turned on and the second number of NMOS transistors to be turned on are the same, and both numbers correspond to the adjustment range of the signal transition edges (e.g., edges 190A, 190B and 190C in Figure 1B, and edges 191A, 191B and 191C in Figure 1C).

[0035] Method 700 may continue with operation 740, which provides an updated version of the signal with adjusted transition edges (e.g., signal 150A, signal 150B, etc.) from the output of the inverter. At operation 740, in some embodiments, method 700 may include receiving a signal from a data channel of the receiver (e.g., data channel 420) and providing an updated version of the signal with adjusted transition edges to a deserializer (e.g., deserializer 430). At operation 740, in some embodiments, method 700 may include receiving a signal from the clock tree of the transmitter (e.g., clock tree 520) and providing an updated version of the signal with adjusted transition edges to a sequencer (e.g., sequencer 530).

[0036] In one embodiment of this disclosure, a circuit is disclosed. The circuit includes one or more anti-skew stages. Each of the one or more anti-skew stages is used to adjust a transition edge of a signal and includes: a single inverter; a header for coupling a first power supply voltage to the single inverter; a pin for coupling a second power supply voltage to the single inverter; a capacitor coupled to an output of the single inverter; and a switching circuit coupled between the output of the single inverter and the capacitor.

[0037] In another embodiment of this disclosure, a circuit is disclosed. The circuit includes one or more anti-skew stages included in a data channel of at least one of a transmitter or a receiver. Each of the one or more anti-skew stages includes an inverter having an input and an output. The input is used to receive a signal, and the output is used to provide an updated version of the signal having an adjusted transition edge. Each of the one or more anti-skew stages includes: a header for selectively coupling a first power supply voltage to the inverter; a pin for selectively coupling a second power supply voltage to the inverter; a capacitor coupled to the output of the inverter; and a switching circuit coupled between the output of the inverter and the capacitor.

[0038] In yet another embodiment of this disclosure, a method for operating one or more anti-skew stages is disclosed, the one or more anti-skew stages being included in a data channel of at least one of a transmitter or a receiver. The method includes: receiving a signal from one input of an inverter; selectively coupling a first power supply voltage to the inverter, at least in part based on the signal; selectively coupling a second power supply voltage to the inverter, at least in part based on the signal; and providing an updated version of the signal having an adjusted transition edge from an output of the inverter.

[0039] As used herein, the terms “about” and “approximately” generally indicate a given number of values ​​that may vary based on a particular technology node associated with the target semiconductor device. Based on a particular technology node, the subject “about” may indicate a given number of values ​​that may vary within, for example, 10% to 30% of the value (e.g., +10%, ±20% or ±30%).

[0040] The foregoing summarizes the features of several embodiments to enable those skilled in the art to better understand the appearance of an embodiment disclosed herein. Those skilled in the art should understand that an embodiment disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment disclosed herein, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of an embodiment disclosed herein. [Simplified Explanation of the Diagram]

[0004] The embodiments disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of description. Figure 1A is a schematic diagram of an example circuit according to some embodiments. Figure 1B is a schematic diagram of an example waveform associated with the circuit of Figure 1A according to some embodiments. Figure 1C is a schematic diagram of an example waveform associated with the circuit of Figure 1A according to some embodiments. Figure 2 is a schematic diagram of an example circuit according to some embodiments. Figure 3 is a schematic diagram of an example circuit according to some embodiments. Figure 4 is a schematic diagram of an example circuit according to some embodiments. Figure 5 is a schematic diagram of an example circuit according to some embodiments. Figure 6 is a schematic diagram of an example circuit according to some embodiments. Figure 7 is a flowchart of an example method for operating a circuit according to some embodiments.

Claims

1. An anti-skew circuit, comprising: one or more anti-skew stages; wherein each of the one or more anti-skew stages is configured to adjust a transition edge of a signal and includes: A single inverter; A terminal for coupling a first power supply voltage to the single inverter, wherein the terminal includes: a first transistor and a second transistor, coupled in parallel between the first power supply voltage and the single inverter, wherein a gate of the first transistor is coupled to a first signal, and a gate of the second transistor is coupled to a second signal different from the first signal; a pin for coupling a second power supply voltage to the single inverter; a capacitor coupled to an output of the single inverter; and a switching circuit coupled between the output of the single inverter and the capacitor.

2. The anti-skew circuit as claimed in claim 1, wherein the head terminal includes N p-type metal-oxide-semiconductor transistors and the pin terminal includes N n-type metal-oxide-semiconductor transistors.

3. The anti-skew circuit as claimed in claim 2, wherein the single inverter is used to alternately couple to the first power supply voltage from the N p-type metal-oxide-semiconductor transistors and the second power supply voltage from the N n-type metal-oxide-semiconductor transistors.

4. The anti-skew circuit as described in claim 3, wherein N corresponds to an adjustment range of the transition edge of the signal.

5. The anti-skew circuit as claimed in claim 1, wherein the one or more anti-skew stages are included in a transmitter and operatively coupled between a clock tree and a sequencer.

6. The anti-skew circuit as claimed in claim 1, wherein the one or more anti-skew stages are included in a receiver and operatively coupled between a data channel and a deserializer.

7. The anti-skew circuit as claimed in claim 1, wherein the one or more anti-skew stages are included in a corresponding data channel of a plurality of data channels operatively inserted between a transmitter and a receiver.

8. An anti-skew circuit, comprising: one or more anti-skew stages, included in a data channel of at least one of a transmitter or a receiver; wherein each of the one or more anti-skew stages includes: An inverter having an input and an output, wherein the input is for receiving a signal and the output is for providing an updated version of the signal having an adjusted transition edge; a header including a plurality of transistors, wherein a first number of the transistors are for conducting to selectively couple a first power supply voltage to the inverter, wherein the first number is determined based on the signal; a pin for selectively coupling a second power supply voltage to the inverter; a capacitor coupled to the output of the inverter; and a switching circuit coupled between the output of the inverter and the capacitor.

9. The anti-skew circuit as claimed in claim 8, wherein the switching circuit includes 2M transmission gates, and wherein the one or more anti-skew stages are configured to provide the updated version of the signal having the adjusted transition edge at an adjusted resolution corresponding to one number of the transmission gates.

10. A method of operation for one or more anti-skew stages, the one or more anti-skew stages being included in a data channel of at least one of a transmitter or a receiver, the method comprising the steps of: receiving a signal from one input of an inverter; turning on a first number of transistors to selectively couple a first power supply voltage to the inverter, the first number being determined based on the signal; selectively coupling a second power supply voltage to the inverter at least in part based on the signal; and providing an updated version of the signal having an adjusted transition edge from an output of the inverter.

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