Connectors, cable assemblies and interconnect systems

Abstract

This document describes several aspects of a smart identification cable assembly. One example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes: a plurality of signal wafer assemblies electrically connected to the cables in the cable bundle; and an identification wafer assembly. The identification wafer assembly includes an identification wafer module. The identification wafer module stores a unique identifier for the cable assembly, such as the slot address of the connector. In other aspects, the identification wafer module is configured to respond to a query by communicating an identification word response from the cable assembly. The identification word response may include a series of information, such as a unique identifier for a connector or slot address, information related to a cable bundle, and other information related to an interconnect system used in a computing environment.

Description

Marking wafer assemblies, connectors, cable assemblies, and interconnect systems The present invention relates to a cable assembly, and more particularly to a smart identification cable assembly. Computing, networking, telecommunications, and related systems and environments rely on interconnect systems to provide data and power connections between various computing devices, switches, routers, and other equipment. A range of different input / output (I / O) connectors, cable assemblies, and interconnect systems are designed for those types of data, power, and data and power interconnect applications. Example interconnect systems include board-to-board systems, wire-to-wire systems, and wire-to-board systems. Numerous designs exist for each type of connector, cable assembly, and interconnect system, depending on the power and data communication requirements of the environment in which the connector, assembly, and system are used. As an example, a wire-to-board system includes a free-end connector attached to a cable bundle of wires and a fixed-end connector attached to a printed circuit board (PCB). As another example, a wire-to-wire system includes a first free-end connector attached to one end of the cable bundle and a second free-end connector attached to the other end of the cable bundle. This document describes various aspects of smart identification cable assemblies. An example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes: a plurality of signal wafer assemblies that are electrically connected to the cables in the cable bundle; and an identification wafer assembly. The identification wafer assembly includes an identification wafer module. The identification wafer module stores a unique identification code for the cable assembly, such as a slot address of the connector. In other aspects, the identification wafer module is configured to communicate an identification word response of the cable assembly in response to a query. The identification word response can include a range of information, such as a unique identification code for a connector or a slot address, information related to a cable bundle, and other information related to an interconnect system used in a computing environment. An example interconnect system includes a first cable assembly and a second cable assembly. The first cable assembly includes a first cable bundle and a first connector at one end of the first cable bundle. The first connector includes: a first signal wafer assembly electrically connected to a cable in the first cable bundle; and a first identification wafer assembly. The first identification wafer assembly includes: a first identification wafer module storing a first unique identification code of the first cable assembly. The second cable assembly includes a second cable bundle and the second cable bundle at one end of a second connector. The second connector includes: a second signal wafer assembly electrically connected to a cable in the second cable bundle; and a second identification wafer assembly. The second identification wafer assembly includes: a second identification wafer module storing a second unique identification code of the second cable assembly. Another example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes a signal wafer assembly electrically connected to a cable in the cable bundle; and an identification wafer module. The identification wafer module stores a unique identification code for the cable assembly. In one example, the unique identification code includes a slot address identifier in a computing system. In other aspects of various embodiments, the identification wafer module is configured to communicate an identification code response of the cable assembly in response to a query on the identification interface of the identification wafer module. The identification code response includes information related to the connector, the cable bundle, or both the connector and the cable bundle. In another example, the identification code response includes information related to an address of the connector and at least one other connector in an arrangement of multiple connectors on a bulkhead, as well as other information. An exemplary connector includes: a housing; a signal wafer assembly retained in the housing; and an identification wafer assembly retained in the housing. The identification wafer assembly includes an identification wafer module, and the identification wafer module stores a unique identification code for the connector. In one example, a plurality of signal wafer assemblies are arranged in a row within the housing, and the identification wafer assembly is located at one end of the row of the plurality of signal wafer assemblies. In other aspects, the signal wafer assembly includes a signal connection interface, the identification wafer assembly includes an identification connection interface, and the signal connection interface is the same as the identification connection interface. An exemplary identification sheet assembly for a connector includes a connection interface and an identification sheet module. The connection interface can include a plurality of conductors and at least one shield. The identification sheet module can include an integrated circuit storing a unique identification code for the connector. In other aspects, the integrated circuit can include a data bus and power terminals respectively connected to a plurality of conductors in the connection interface. The unique identification code can include a slot address identifier, data related to the address of the connector and at least one other connector in an arrangement of a plurality of connectors on a partition, and other information. Another example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes a plurality of signal conductors electrically connected to the cables in the cable bundle; and an identification module. The identification module stores a unique identifier for the cable assembly. The unique identifier can include a slot address identifier, information related to an address of the connector and at least one other connector in an arrangement of multiple connectors on a bulkhead, and other information. Another example connector includes a housing, a plurality of signal conductors, and an identification module retained in the housing. The identification module stores a unique identifier for the connector. The unique identifier can include a slot address identifier, information related to an address of the connector and at least one other connector in an arrangement of multiple connectors on a bulkhead, and other information. As mentioned above, computing, networking, telecommunications, and related systems and environments rely on interconnect systems to provide data and power connections between various computing devices, switches, routers, and other equipment. A variety of different input / output (I / O) connectors, cable assemblies, and interconnect systems are designed for those types of data, power, and data and power interconnect applications. Interconnect systems can include board-to-board systems, wire-to-wire systems, wire-to-board systems, and related systems. Numerous designs exist for each type of connector, cable assembly, and interconnect system, depending on the requirements of the power and data communication environment in which the connector, assembly, and system are employed. High-data-rate connectors, cable assemblies, and interconnect systems often rely on differentially coupled signal pairs, in which two conductors are arranged as a pair to transmit a differential signal. The transmitted signal is represented by the electrical difference measured between the conductor pairs. Differential signaling helps prevent spurious signals and crosstalk and avoids unintended signaling modes between adjacent signal pairs. In connector interfaces, ground terminals can be used to create a return path for electrical grounding, provide shielding between differential pairs, and other purposes. Connectors used in high-data-rate applications are typically designed to meet a range of mechanical and electrical requirements. As an example, high-data-rate connectors, cable assemblies, and interconnect systems are often used in backplane applications that require very high conductor density and high data rates. To achieve the required mechanical and electrical requirements, connectors used in such applications often include one or more wafer assemblies. In some interconnect systems, an array of connectors can be arranged and held in a connector panel or bulkhead. A connector bulkhead can be referred to as a structure, such as a wall of a housing or an associated barrier, to which one or more connectors of an interconnect system are mounted or otherwise held. In some cases, connectors can extend through openings or perforations in the bulkhead. The connector bulkhead thus supports multiple connectors and holds the multiple connectors in place relative to each other and the surrounding system. Connector bulkheads can be particularly helpful for wire-to-wire interconnect systems of multiple cable assemblies that include free-end connectors at the ends of cable bundles. The bulkhead can support a group of free-end connectors, and the mating connector can be mechanically and electrically connected to the group of free-end connectors. This document describes various aspects of smart identification cable assemblies. An example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes: a plurality of signal wafer assemblies that are electrically connected to the cables in the cable bundle; and an identification wafer assembly. The identification wafer assembly includes an identification wafer module. The identification wafer module stores a unique identification code for the cable assembly, such as a slot address for the connector. In other aspects, the identification wafer module is configured to respond to a query and communicate an identification word response for the cable assembly. The identification word response can include a range of information, such as a unique identification code for a connector or a slot address, information related to a cable bundle, and other information related to an interconnect system used in a computing environment. FIG1 illustrates an example computing environment 10 (i.e., “environment 10”) with an interconnect system 100 according to various aspects of the present disclosure. Both environment 10 and interconnect system 100 are shown in FIG1 as a representative example. The interconnect system and concepts described herein can be extended to computing environments that include any number of computing systems, cable assemblies, connectors, cables, cable harnesses, and other devices. As shown in Figure 1, environment 10 includes two computing systems 20 and 40 and an interconnection system 100. Computing system 20 includes computing devices 30-39, etc., and computing system 40 includes computing devices 50-53, etc. Computing devices 30-39 can be multiple individual line cards of computing system 20. Each of computing devices 30-39 can be embodied as, but not limited to, one or more general-purpose, special-purpose, or general-purpose and special-purpose processors and memory, a data communication device or system, a network storage device or system, a network switch, router, or a switching and routing system, a computer or server of a telecommunications system, or a related computing system. Computing devices 50-53 can also be multiple line cards of computing system 40. Each of computing devices 50-53 can be embodied as, but not limited to, one or more general-purpose, special-purpose, or general-purpose and special-purpose processors and memory, a network storage device or system, a network switch, router, or a switching and routing system, a computer or server of a telecommunications system, or a related computing system. In one example, interconnect system 100 provides a data interconnection between two computing systems 20 and 40. In other cases, interconnect system 100 can provide a power supply or a data and power interconnection between two computing systems 20 and 40. Interconnect system 100 includes a plurality of cable bundles 110-119 and a plurality of free-end connectors 120-129 at the ends of each of the cable bundles 110-119. Interconnect system 100 also includes a plurality of cable bundles 130-133 and a plurality of free-end connectors 140-143 at the ends of each of the cable bundles 130-133. Examples of connectors 120-129 and 140-143 are described below with reference to FIG. 2, and examples of wafer assemblies within connectors 120-129 and 140-143 are described below with reference to FIG. 3A, FIG. 3B, FIG. 4, and FIG. 5A through FIG. 5C. Cable bundles 110-119, 130-133 include a plurality of cables extending between connectors 120-129 and connectors 140-143, or more. In one example, the cables can be implemented as conductive twinaxial or twinax cables, although other types of cables (e.g., shielded or unshielded twisted pair, coaxial cable, fiber optic cable, etc.) can be utilized in interconnect system 100. When implemented as twinax cables, each of the plurality of cables in cable bundles 110-119, 130-133 can include a pair of inner conductors, a dielectric insulator surrounding the two conductors, one or more shielding members or layers surrounding the dielectric insulator, one or more shielding conductors, and an outer sheath. Twinax cables can be used in high-speed differential data signaling applications and can be utilized in interconnect system 100 in a variety of data interconnect applications. Each of the cable bundles 110-119, 130-133 includes a number of cables. The number of cables in each cable bundle 110-119, 130-133 of the interconnect system 100 can depend on the type, style, number of the plurality of wafer components, and the associated characteristics of the free-end connectors at the ends of each cable bundle. In one example described herein, each of the cable bundles 110-119 includes sixty-four twin-axial cables. In other examples, each cable bundle in a first group of the cable bundles 110-119 includes a first number of cables, while each cable bundle in a different second group of the cable bundles 110-119 includes a different second number of cables. However, embodiments are not limited to cable bundles having any particular number of cables, and in other cases, each of the cable bundles 110-119 can include more or less than sixty-four twin-axial cables. Other examples include, but are not limited to, cable bundles having two (2), four (4), eight (8), sixteen (16), thirty-two (32), one hundred and twenty-eight (128), or other numbers of cables. Each of the cable bundles 130 - 133 can also include more or less than sixty-four twinaxial cables. In the illustrated example, each of the connectors 120-129 is secured to a bulkhead 22. As an example, bulkhead 22 can be embodied as a wall of a housing, cabinet, box, or related structure of the computing system 20. In one embodiment, the connectors 120-129 can extend through perforations or openings extending through the bulkhead 22, but the connectors 120-129 can be secured to the bulkhead 22 in other arrangements or patterns using any suitable connectors, fasteners, or related means. As described in further detail below, the bulkhead 22 can facilitate alignment between the connectors 120-129 of the interconnect system 100 and the mating connectors of the computing devices 30-39. The connectors 120-129 can be arranged in a linear or matrix array using the bulkhead 22. Each of the connectors 140-143 is secured to a bulkhead 42. As an example, bulkhead 42 can be embodied as a wall of a housing, cabinet, box, or related structure of the computing system 40. In one embodiment, the connectors 140-143 can extend through perforations or openings extending through the bulkhead 42, but the connectors 140-143 can also be secured to the bulkhead 42 in other arrangements or patterns using any suitable connectors, fasteners, or related means. As described in further detail below, the bulkhead 42 can facilitate alignment between the connectors 140-143 of the interconnect system 100 and the mating connectors of the computing devices 50-53. The connectors 140-143 can be arranged in a linear or matrix array using the bulkhead 42. As shown in FIG1 , computing devices 30-39 of computing system 20 each include connectors 60-69. In the example shown in FIG1 , connectors 60-69 can be fixed-end connectors mounted on the printed circuit boards (PCBs) of computing devices 30-39. Thus, connector 60 facilitates electrical connection between computing device 30 and connector 120 of interconnect system 100. Similarly, connectors 61-69 facilitate electrical connection between computing devices 31-39 and connectors 121-129 of interconnect system 100. Also as shown in FIG1 , computing devices 50-53 of computing system 40 each include connectors 70-73. Connectors 70-73 can be fixed-end connectors mounted on the PCBs of computing devices 50-53. Connectors 70-73 facilitate electrical connection between computing devices 50-53 and connectors 140-143 of interconnect system 100. Fixed-end connectors 60-69, 70-73 can also incorporate various aspects of the smart identification concepts described herein. For example, any of the fixed-end connectors 60 - 69 , 70 - 73 may further include an ID wafer assembly 220 or a component thereof described below with reference to FIG. 5A to FIG. 5C . In interconnect system 100, cables in cable bundles 110-119, 130-133 can be routed between connectors 120-129 and connectors 140-143 in any suitable manner depending on the interconnect needs in environment 10. In other words, cable bundles 110-119, 130-133 can facilitate data communication between line cards of computing system 20 and computing system 40 in various manners. As an example, cable bundle 110 can include cables extending between computing device 30 and one or more of computing devices 31-39 in computing system 20. Additionally or alternatively, cable bundle 110 can include cables extending between computing device 30 and one or more of computing devices 50-53 in computing system 40. In general, each of cable bundles 110-119 can include cables extending between one or more of computing devices 30-39, 50-53, or between other computing devices not shown. Likewise, cable bundle 130 can include cables extending between computing device 50 and one or more of computing devices 51-53 in computing system 40. Additionally or alternatively, cable bundle 130 can include cables extending between computing device 50 and one or more of computing devices 30-39 in computing system 20. Each of cable bundles 130-133 can include cables extending between computing devices 30-39, 50-53, or other possible computing devices. According to aspects of various embodiments, the interconnect system 100 includes one or more identifiers or "ID" components. For example, one or more of the connectors 120-129, 140-143 includes a component, assembly, or device configured to provide a unique identifier or ID (i.e., an "ID response"). The ID response can be provided at any time, such as when power is supplied to the ID component, in response to a query from one of the computing devices 30-39 and 50-53, or in response to other conditions. The ID response can be provided in the form of voltage potentials or logic levels on terminals of the connectors 120-129, 140-143, serial or parallel data on the terminals, or other suitable formats. In one example, an ID response provided by one of the connectors 120-129, 140-143 can be at least partially unique compared to any or all responses provided by the other connectors 120-129, 140-143. The ID response from connectors 120-129, 140-143 can include a range of information. The ID response can include a unique identifier or code, such as a unique identifier for connector 120-129, 140-143. The ID response can include the physical or logical slot address of connector 120-129, 140-143. The ID response can include information related to the type, style, or other characteristics of connector 120-129, 140-143. The ID response can include information related to the relative or absolute address of connector 120-129 on bulkhead 22. Similarly, the ID response can include information related to the relative or absolute address of connector 140-143 on bulkhead 42. The ID response can include information related to the cable bundles 110-119, 130-133, the number and type of cables in the cable bundles 110-119, 130-133 (e.g., number of components, conductor or fiber type, gauge, length, etc.), the number of cable bundles in the interconnect system 100, and other information related to the cable bundles 110-119, 130-133 and the interconnect system 100. The ID response can also include information related to the specific cable connection between the connectors 120-129 and the connectors 140-143. These and other types of ID responses are described below. As discussed in further detail below, based on the ID response, the computing devices 30-39 and 50-53 can tailor or adjust certain operating parameters, such as clock or offset timing. Conventional interconnect systems do not provide any mechanism for computing devices to identify or determine the structural, electrical, and related characteristics of the interconnect system between them. For example, if interconnect system 100 does not include the ID response concepts described herein, computing device 30 will not be able to identify that it is connected to connector 120 rather than any other connector among connectors 121-129, 140-143 in environment 10. Computing device 30 will not be able to identify that it is connected to computing device 31, computing devices 31-33, or any other specific combination of computing devices in environment 10. As another example, if interconnect system 100 does not include the ID response concepts described herein, computing device 30 will not be able to determine the address of connector 120 relative to other connectors 121-129 on bulkhead 22 or determine the physical or logical address of other computing devices 31-39 in computing system 20 (or be connected to other computing devices 31-39 in computing system 20). The computing device 30 also does not determine any characteristics about the cable bundle 110 or the interconnect system 100, and the computing device 30 does not clip or adjust any operating parameters. These and other aspects of various embodiments are described below. FIG2 shows a perspective view of connector 120 at the free end of a cable bundle 110 in the interconnect system 100 shown in FIG1 . Connector 120 is shown as a representative example and is not drawn to any particular scale or size. The shape, size, proportions, and other characteristics of connector 120 can vary relative to that shown. In addition, while connector 120 and other connectors discussed herein are described for use in high-speed backplanes and related interconnect applications, the concepts are not limited to use with such interconnect applications or systems. The concepts can be extended to use with other types of connectors and other types of interconnect systems and applications. Connector 120 includes a housing 200. Housing 200 has a docking interface 202 and a cable interface 204. Another docking connector, such as connector 60 of computing device 30 shown in FIG1 , can dock and electrically connect to connector 120 at docking interface 202. In other examples, the free end of another interconnect system cable can dock and electrically connect to connector 120 at docking interface 202. In the illustrated example, connector 120 is a hermaphroditic or genderless type connector. In other words, a copy of connector 120 can be rotated and docked with connector 120 (i.e., itself) at docking interface 202. The concept is not limited to use with hermaphroditic connectors and can rely on other types or styles of connectors in interconnect system 100. Housing 200 can be formed from a plastic or polymer such as liquid crystal polymer (LCP), polyethylene (PE), polytetrafluoroethylene (PTFE), a fluoropolymer, or other plastic or insulating material. Housing 200 can be formed using any suitable additive or subtractive manufacturing technique, including molding, injection molding, printing, and other techniques. In some cases, the outer surface of housing 200 can be plated with one or more conductive plating metals, and housing 200 can be embodied as a plated plastic component. The surface can, in some cases, be etched and metallized or plated in a bath, barrel plated, plated by physical vapor deposition (PVD), plated by electroless plating, electroplating, sputtering, ion plating, or other plating techniques, or a combination thereof. The surface of housing 200 can be metallized or plated with copper, nickel, tin, silver, another plating metal, or a combination of these. The cable bundle 110 extends into the cable interface 204 of the connector 120. As described in further detail below, the tail ends of the multiple cables in the cable bundle 110 are mechanically and electrically terminated to a plurality of wafer assemblies located in a side-by-side arrangement within the housing 200. The plurality of wafer assemblies include signal conductors or terminals and ground shields, among other components, and the multiple conductors in the cable bundle 110 are electrically connected to the signal conductors of the plurality of wafer assemblies. Any wafer assembly electrically connected to the cables in the cable bundle 110 can be referred to herein as a signal wafer assembly. Among other signal wafer assemblies, an identification or ID wafer assembly is also located within the housing 200. The housing 200 is located over and holds the plurality of wafer assemblies in the connector 120. As described later, the connector 120 includes sixteen signal wafer assemblies and an additional ID wafer assembly, for a total of seventeen wafer assemblies. However, in other cases, the connector 120 can include other numbers of signal and multiple ID wafer assemblies, including fewer or greater numbers of wafer assemblies. Each of the multiple signal wafer assemblies, which will be described in further detail later with reference to FIG. 4 , includes multiple pairs of signal conductors and a channel-shaped shield for each pair of signal conductors. In the example shown, each of the multiple signal wafer assemblies includes four pairs of signal conductors and four channel-shaped shields. Each pair of signal conductors extends within a channel of a respective channel-shaped shield, and the channel-shaped shield provides a common ground and shield for the pair of signal conductors. In the example shown, the ID wafer assembly, which will be described in further detail later with reference to FIG. 5A to FIG. 5D , also includes four pairs of signal conductors and four channel-shaped shields. Figure 3A shows a perspective view of the plurality of wafer assemblies of the connector 120 shown in Figure 2 and Figure 3B shows a side view of the plurality of wafer assemblies of the connector 120 shown in Figure 2. The housing 200 of the connector 120 is omitted from the figures in Figures 3A and 3B so that the plurality of wafer assemblies are visible. The plurality of wafer assemblies shown in Figures 3A and 3B are shown as a representative example and are not drawn to any particular scale or size. The shape, size, scale, and other characteristics of the plurality of wafer assemblies can vary relative to those shown. Each of the connectors 120-129, 140-143 can include an arrangement of plurality of wafer assemblies similar to that shown in Figures 3A and 3B, including both plurality of signal wafer assemblies and an ID wafer assembly. As shown, connector 120 includes a number of wafer assemblies, including a plurality of wafer assemblies 210A, 210B, 210C, 210D, 210P, and so on (collectively, "plural wafer assemblies 210"). The plurality of wafer assemblies 210 are arranged side by side in connector 120. Each of the plurality of wafer assemblies 210 is a signal wafer assembly, as a plurality of cables from cable harness 110 are terminated to the plurality of wafer assemblies 210. For example, cables 110A-110D are terminated to wafer assembly 210A, while other cables from cable harness 110 are terminated to wafer assemblies 210B, 210C, 210D, 210P, and so on. In the illustrated example, connector 120 includes sixteen wafer assemblies 210. However, in other cases, connector 120 can include other numbers of wafer assemblies, including fewer or more wafer assemblies. Connector 120 also includes an ID wafer assembly 220, which is an example of an ID component in interconnect system 100. In one example, each of connectors 120-129, 140-143 in interconnect system 100 can include an ID wafer assembly similar to ID wafer assembly 220. However, in other cases, a subset of connectors 120-129, 140-143 in interconnect system 100 may include an ID wafer assembly. Note that no cables from cable bundle 110 terminate at ID wafer assembly 220, and for that reason, ID wafer assembly 220 can be referred to as a "dead-end" wafer assembly. In the example shown in Figures 3A and 3B, ID wafer assembly 220 is located at one end (e.g., at the right end) of the plurality of signal wafer assemblies 210 in connector 120. In other cases, ID wafer assembly 220 can be located at the other end (e.g., at the left end) of the plurality of signal wafer assemblies 210. However, the ID wafer assembly 220 is not limited to being located at one end of the side-by-side arrangement of the signal wafers. In other cases, the ID wafer assembly 220 can also be located at any position among the plurality of wafer assemblies 210 (e.g., in the middle of the plurality of wafer assemblies 210 or between the plurality of wafer assemblies 210). Each of the plurality of wafer assemblies 210 includes a signal connection interface. For example, the plurality of wafer assemblies 210A, 210B, 210C, 210D, and 210P include signal connection interfaces 212A, 212B, 212C, 212D, and 212P, respectively. The signal connection interface 212A of the wafer assembly 210A is described in further detail below with reference to FIG. 4 and includes conductive contacts for signal conductors and a grounding shield. In the illustrated example, the signal connection interface in each of the other wafer assemblies 210B, 210C, 210D, and 210P is identical to the signal connection interface 212A of the wafer assembly 210A. The ID wafer assembly 220 includes an identification or ID connection interface 222. The ID connection interface 222 of the ID wafer assembly 220 is described in further detail below with reference to Figures 5A to 5C and includes conductive contacts for signal conductors and a ground shield. As described in further detail below, the ID connection interface 222 of the ID wafer assembly 220 can be the same as the signal connection interface of the wafer assembly 210. In other cases, the ID connection interface 222 of the ID wafer assembly 220 can be different from the signal connection interface of the wafer assembly 210. The connection interfaces of multiple wafer assemblies 210 and ID wafer assemblies 220 can be electrically connected to the connector 60 (see Figure 1) of the computing device 30 to electrically connect to the computing device 30. The ID wafer assembly 220 includes wiring and / or circuitry for storing a unique identification code and other data associated with the connector 120, the cable harness 110, the interconnect system 100, or some combination thereof. More specifically, FIG3B illustrates an ID circuit module 280 of the ID wafer assembly 220. Referring to FIG3A , the ID wafer assembly 220 includes a wafer insert 270, with the ID circuit module 280 positioned within the wafer insert 270. The wafer insert 270 is omitted from FIG3B so that the ID circuit module 280 is visible. In response to a query from computing device 30, ID circuit module 280 can store and provide a unique identification code or ID. The ID response can be provided in the form of voltage potentials or logic levels on connection interface 222 of ID wafer assembly 220, serial or parallel data on connection interface 222, or in other suitable format. An ID response from ID circuit module 280 can be at least partially unique compared to any or all ID responses provided by the ID wafer assemblies of other connectors 121-129, 140-143. Additional aspects of ID circuit module 280 are described in more detail below with reference to Figures 5B and 5C. As shown in Figures 3A and 3B, in interconnect system 100, the plurality of wafer assemblies of connector 120 are representative of the plurality of wafer assemblies in other connectors 121-129, 140-143. More specifically, connectors 121-129, 140-143 also each include a plurality of signal wafer assemblies and an ID wafer assembly. In some cases, each of connectors 121-129, 140-143 includes an ID wafer assembly. In other cases, a subset of connectors 120-129, 140-143 in interconnect system 100 includes an ID wafer assembly. Consistent with the concepts described herein, the ID wafer assembly of each (or any) of connectors 120-129, 140-143 can be queried or interrogated by computing device 30-30, 50-53, respectively, to receive an ID response from connector 120-129, 140-143. The ID response from connector 120-129, 140-143 can include a range of information. The ID response can include a unique identifier or code, such as a unique identifier for connector 120-129, 140-143. The ID response can include information related to the type, model, or other characteristics of connector 120-129, 140-143. The ID response can include information related to the relative or absolute address of connector 120-129 on bulkhead 22. Similarly, the ID response can include information related to the relative or absolute address of connector 140-143 on bulkhead 42. The ID response can include information related to the cable bundles 110-119, 130-133, the number and type of cables in the cable bundles 110-119, 130-133 (e.g., number of components, conductor or fiber type, gauge, length, etc.), the number of cable bundles in the interconnect system 100, and other information related to the cable bundles 110-119, 130-133 and the interconnect system 100. Based on the ID response, the computing devices 30-39 and the computing devices 50-53 can clip or adjust certain operating parameters, such as clock or offset timing. FIG4 illustrates a perspective view of wafer assembly 210A within connector 120 shown in FIG1 . Wafer assembly 210A is shown as a representative example and is not drawn to any particular scale or size. The shape, size, proportions, and other characteristics of wafer assembly 210A may vary relative to that shown. Each of the plurality of wafer assemblies 210 within connector 120 may be similar to wafer assembly 210A and include the same components and features as wafer assembly 210A. The wafer assembly 210A includes channel-shaped shielding members 231-234, a wafer insert 240, and signal conductors 251-258. The signal conductors 251-258 are conductive terminals for communicating data signals between the wafer assembly 210A and the connector 120. The channel-shaped shielding members 231-234 are common or grounded shielding members between the wafer assembly 210A and the connector 120. At one end, the channel-shaped shielding members 231-234 and the signal conductors 251-258 form a signal connection interface 212A of the wafer assembly 210A. In the example shown, the channel-shaped shield members 231-234 are formed as U-shaped shield members, but the channel-shaped shield members 231-234 can be formed in other shapes. Each of the channel-shaped shield members 231-234 includes a pair of side walls that extend generally orthogonally to a back wall to form a U-shaped shield member. Pairs of signal conductors 251-258 extend within the channels of the channel-shaped shield members 231-234. In particular, the signal conductors 251 and 252 extend within a channel of the channel-shaped shield member 231, the signal conductors 253 and 254 extend within a channel of the channel-shaped shield member 232, the signal conductors 255 and 256 extend within a channel of the channel-shaped shield member 233, and the signal conductors 257 and 258 extend within a channel of the channel-shaped shield member 234. The signal conductors 251-258 can be formed from a flat sheet of metal, such as a lead frame (e.g., by stamping, shearing, or otherwise forming). In some cases, the metal sheet or lead frame can be plated with one or more plating metals. The signal conductors 251-258 can be shaped by bending, pressing, or stamping. The channel-shaped shield members 231-234 are independently formed from a flat sheet of metal (e.g., by stamping, shearing, or otherwise forming). The channel-shaped shield members 231-234 can be shaped by bending, pressing, or stamping. The wafer insert 240 can be formed from a plastic or polymer such as LCP, PE, PTFE, fluoropolymer, or other plastic or insulating material. The wafer insert 240 can be molded around the signal conductors 251-258 and the channel-shaped shields 231-234. The wafer insert 240 holds the signal conductors 251-258 and the channel-shaped shields 231-234 in place and positions them relative to each other and the other components of the wafer assembly 210A. As also shown in FIG4 , cables 110A-110D are terminated to wafer assembly 210A. More specifically, cable 110A includes conductors 151 and 152, which are electrically coupled to signal conductors 251 and 252 within wafer assembly 210A. Furthermore, cable 110B includes conductors 153 and 154, which are electrically coupled to signal conductors 253 and 254 within wafer assembly 210A. Cable 110C includes conductors 155 and 156, which are electrically coupled to signal conductors 255 and 256, and cable 110D includes conductors 157 and 158, which are electrically coupled to signal conductors 257 and 258. Thus, conductors 151-158 of cables 110A-110D are electrically coupled to signal conductors 251-258. The data signals carried by conductors 151-158 are transmitted to signal conductors 251-258 through wafer assembly 210A. The other wafer assemblies 210 in connector 120 are similarly designed to conduct data signals from other cables in cable bundle 110 to the signal conductors. The shield conductors in cables 110A-110D are also electrically connected to the channel-shaped shield members 231-234 in wafer assembly 210A. FIG5A shows a perspective view of an ID wafer assembly 220 in the connector 120 of the interconnect system 100 shown in FIG1 . The ID wafer assembly 220 is shown as a representative example and is not drawn to any particular scale or size. The shape, size, proportions, and other characteristics of the ID wafer assembly 220 may vary from that shown. The ID wafer assembly 220 includes channel-shaped shielding members 261-264, a wafer insert 270, and conductors 281-288. The conductors 281-288 and the channel-shaped shielding members 231-234 form the ID link interface 222 of the ID wafer assembly 220. The ID wafer assembly 220 also includes an ID circuit module 280 retained within the wafer insert 270. As described below with reference to Figures 5B and 5C, the ID circuit module 280 is configured to generate an ID response in response to a query presented to the ID link interface 222 of the ID circuit module 280 by the computing device 30. Comparing FIG5A with FIG4 , the ID connection interface 222 of the ID wafer assembly 220 is identical to the signal connection interface 212A of the wafer assembly 210A (e.g., having the same number, location, and arrangement of conductors / terminals, the same lead style, etc.). Furthermore, in the illustrated example (see also FIG3A and FIG3B ), the ID connection interface 222 of the ID wafer assembly 220 is also identical to the signal connection interfaces of all other wafer assemblies 210 in the connector 120. Thus, in the illustrated example, the connection between the docking connector 60 (see FIG1 ) of the computing device 30 and the connector 120 does not require modification or adjustment. However, in other cases, the ID connection interface 222 of the ID wafer assembly 220 can differ from the signal connection interfaces of multiple wafer assemblies 210 in the connector 120. The channel-shaped shielding members 261-264 of the ID wafer assembly 220 shown in FIG5A are formed as U-shaped shielding members, but the channel-shaped shielding members 261-264 can be formed in other shapes. Each of the channel-shaped shielding members 261-264 includes a pair of side walls that extend generally orthogonally to a back wall to form a U-shaped shielding member. Pairs of signal conductors 281-288 extend within the channels of the channel-shaped shielding members 261-264. The conductors 281-288 can be formed from a flat sheet of metal such as a lead frame (e.g., by stamping, shearing, or other means). In some cases, the sheet of metal or lead frame can be plated with one or more plating metals. The shape of the signal conductors 281-288 can be formed by bending, pressing, or stamping. The channel-shaped mask members 261 - 264 can be independently formed from a flat metal sheet material (eg, by stamping, shearing, or other means). The shape of the channel-shaped mask members 261 - 264 can be formed by bending, pressing, or stamping. The wafer insert 270 can be formed from a plastic or polymer such as LCP, PE, PTFE, a fluoropolymer, or other plastic or insulating material. The wafer insert 270 can be molded around the conductors 281-288 and the channel-shaped shielding members 261-264. The wafer insert 270 holds the conductors 281-288 and the channel-shaped shielding members 261-264 in place and positions the conductors 281-288 and the channel-shaped shielding members 261-264 relative to each other and the other components of the ID wafer assembly 220. The wafer insert 270 is also molded around the ID circuit module 280. Thus, the wafer insert 270 holds the conductors 281-288, the channel-shaped shielding members 261-264, and the ID circuit module 280 in place and positions the conductors 281-288, the channel-shaped shielding members 261-264, and the ID circuit module 280 relative to each other. FIG5B illustrates a first side view of the ID circuit module 280 within the ID wafer assembly 220 shown in FIG5A , and FIG5C illustrates a second side view of the ID circuit module 280. The ID circuit module 280 is shown in FIG5A and FIG5B as an example, and in practice, the ID circuit module 280 can vary relative to that shown. In the illustrated example, the ID circuit module 280 includes a PCB 300 and circuit components or assemblies on the PCB 300. As shown in FIG5C , the ID circuit module 280 includes a circuit 330 and a resistor 340 on the PCB 300, as well as possible other active integrated circuits and passive components. The PCB 300 includes a ground plane 310 and conductive traces 320-324. In various embodiments, the PCB 300 can include additional ground planes, conductive traces, conductive pads, and related features. The channel-shaped shields 261 - 264 and the conductors 281 - 288 of the ID wafer assembly 220 are electrically coupled to the conductive pads of the PCB 300 for electrical connection to the ground plane 310 and the conductive traces 320 - 324 of the PCB 300 . In various embodiments, circuit 330 can be implemented as a variety of discrete and integrated circuit devices. As an example, circuit 330 can be implemented as an electrically erasable programmable read-only memory (EEPROM) with a serial bus interface. Thus, in the illustrated example, ID circuit module 280 includes a memory circuit or device. Circuit 330 can also be implemented as other types of integrated circuits, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), and other integrated circuits. In various embodiments, circuit 330 can include any suitable interface, such as a serial, parallel, or correlated bus interface. In other cases, circuit 330 can also be implemented as one or more discrete devices, other integrated devices, or a combination thereof. In the example shown, circuit 330 includes an internal integrated circuit or I²C serial bus interface, including clock or SCL and data or SDA pins. Circuit 330 also includes a write-protect or WP pin, as well as pins for power or VDC, ground or GND, and possibly other interfaces. The VDC pin of circuit 330 is electrically connected to conductor 288 of ID wafer assembly 220 via trace 321 on PCB 300. The SCL pin and SDA pin of circuit 330 are electrically connected to conductor 287 and conductor 285 of ID wafer assembly 220 via trace 322 and trace 323, respectively. The WP pin of circuit 330 is connected to conductor 284 via trace 324, and the GND pin of circuit 330 is connected to ground plane 310 of PCB 300. Ground plane 310 of PCB 300 is also connected to conductor 283 via resistor 340 and trace 320. An example of the connection between circuit 330 and conductors 281-288 is provided in FIG5C . In other examples, circuit 330 can be electrically connected to conductors 281-288 in other ways, depending on the type and format of circuit 330. In some cases, all conductors 281-288 can be connected to circuit 330, for example, if more pins are required for a different type of data bus. Circuit 330 can receive power and communicate data via ID link interface 222. For example, when connector 120 is docked with connector 60 of computing device 30, computing device 30 can provide power to ID wafer assembly 220 of circuit 330 and receive data from ID wafer assembly 220 of circuit 330. More specifically, computing device 30 can provide power to circuit 330 via conductor 288, and computing device 30 can query data stored in circuit 330 using conductors 287 and 285 connected to the SCL and SDA pins of circuit 330. Any data received by computing device 30 from circuit 330 can be referred to herein as an ID response from ID wafer assembly 220. The circuit 330 of the ID wafer assembly 220 can store data related to the connector 120, the cable harness 110, the interconnect system 100, and other information. The data can be defined or programmed into the circuit 330 when the circuit module 280 is manufactured, when the connector 120 is installed in the environment 10, or at any other suitable time. As a number of examples, the circuitry 330 can store a unique identifier for the connector 120, a physical or logical slot address or identifier for the connector 120, information regarding the type, style, or other characteristics of the connector 120, information regarding the relative or absolute address of the connector 120 on the bulkhead 22, information regarding the relative or absolute addresses of the other connectors 121-129 on the bulkhead 22, information regarding the relative or absolute addresses of the connectors 140-143 on the bulkhead 42, information regarding the cable bundle 110 or the other cable bundles 111-119, 130-133, information regarding the number and type (e.g., number of components, conductor or fiber type, standard size, length, etc.) of the cables 130-133 in the cable bundles 110-119, information regarding the number of cable bundles or cable assemblies in the interconnection system 100, information regarding cable interconnections between individual cables in the interconnection system 100, and other information. When the connector 120 is docked with the connector 60 of the computing device 30 as shown in FIG. 1 , the circuit 330 can communicate any or all of the above information to the computing device 30 via the ID link interface 222 . For example, based on an ID response from ID wafer assembly 220 in connector 120, computing device 30 can determine its slot address in computing system 20. The slot address can be defined as a physical or logical address relative to other computing devices 31-39 in computing system 20. Based on the slot address, computing device 30 can also clip or adjust certain operating parameters, such as clock or offset timing. Computing device 30 can also identify that it is connected to connector 120 and not to any other connector 121-129, 140-143 in environment 10. For example, computing device 30 can also identify that it is connected to computing device 31 at another slot address or to another computing device or devices in environment 10. Computing device 30 can also determine the address of connector 120 relative to other connectors 121-129 on bulkhead 22 or determine the physical or logical address of (or connection to) other computing devices 31-39 in computing system 20. The computing device 30 also does not determine any characteristics about the cable bundle 110 or the interconnect system 100, and the computing device 30 does not clip or adjust any operating parameters. These and other aspects of various embodiments are described below. In a similar manner, based on the ID responses from the ID wafer assemblies in connectors 121-129, computing devices 31-39 can determine the slot address in computing system 20. For example, computing device 30 can determine a first slot address identifier from connector 120, and computing device 31 can determine a different second slot address identifier from connector 121. Additionally, based on the ID responses from the ID wafer assemblies in connectors 140-143, computing devices 50-53 can determine the slot address in computing system 40. The multiple ID wafer assemblies in connectors 120-129, 140-143 can each include unique information, such as unique information associated with connectors 120-129, 140-143, cable bundles 110-119, 130-133, and interconnect system 100. Terms such as top, bottom, side, front, back, right, and left are not intended to provide an absolute frame of reference. Rather, these terms are relative and are intended to identify certain features in relationship to one another, as the orientation of the structures described herein can vary. The terms comprising, including, having, and the like are synonymous and are used in an open-ended manner and do not exclude additional elements, features, actions, operations, and the like. Furthermore, the term or is used in its inclusive sense rather than its exclusive sense; thus, for example, when used in conjunction with a list of elements, the term or refers to one, some, or all of the elements in the list. Unless otherwise specified, combination language, such as at least one of X, Y, and Z, or any of X, X, or Z, is generally used to identify one, a combination of any two, or all three (or more if identifying a larger group), such as X and only X, Y and only Y, Z and only Z, X and Y, a combination of X and Z and Y and Z, and all of X, Y, and Z. Unless otherwise specified, such combination language is generally not intended to and does not identify or require the inclusion of at least one of X, at least one of Y, and at least one of Z. Unless otherwise defined herein, the terms "about" and "substantially," as associated with a particular range, percentage, or related measure of deviation, describe at least some manufacturing tolerances between a theoretical design and a manufactured product or component, such as the geometric dimensioning and tolerancing standards described in the American Society of Mechanical Engineers (ASME®) Y14.5 and related International Standards Organization (ISO®) standards. As one of ordinary skill in the art recognizes, such manufacturing tolerances are contemplated despite the absence of explicit reference to about, substantially, or related terms, or even the use of theoretical terms such as geometric perpendicular, orthogonal, apex, colinear, coplanar, etc. The above-described embodiments of the present disclosure are merely examples of implementation to provide a clear understanding of the principles of the present disclosure. Many variations and modifications may be made to the above-described embodiments without departing substantially from the spirit and principles of the present disclosure. In addition, components and features described in one embodiment may be included in another embodiment. All such modifications and variations are intended to be included within the scope of the present disclosure. 100: Interconnection system 110-119: Cable harness 110A-110D: Cables 151-158: Conductors 120-129: Free-end connector (connector) 200: Housing 202: Docking interface 204: Cable interface 130-133: Cable harness 140-143: Free-end connector (connector) 10: Computing environment (environment) 20: Computing system 22: Partition 30-39: Computing device 40: Computing system 42: Partition 50-53: Computing device 60-69: Connector (fixed-end connector) 70-73: Connector (fixed-end connector) 210, 210A-210P: Wafer assembly 212A-212P: Signal connection interface 220: Identification wafer assembly (ID wafer assembly) 222: Identification connection interface (ID connection interface) 231-234, 261-264: Channel-shaped shielding members 240, 270: Sheet inserts 251-258: Signal conductors 280: ID circuit module (ID sheet module, ID module) 281-288: Conductors (signal conductors) 300: PCB 310: Ground plane 320-324: Conductive traces (traces) 330: Circuit 340: Resistor Other features and benefits of the present invention will become apparent in the embodiments with reference to the accompanying drawings, in which: FIG1 illustrates an example computing environment with an interconnect system according to various aspects of the present disclosure. FIG2 illustrates a perspective view of an example connector at a free end of a cable assembly in the interconnect system shown in FIG1 according to various aspects of the present disclosure. FIG3A illustrates a perspective view of an example wafer assembly of the connector shown in FIG2 according to various aspects of the present disclosure, with the housing removed. FIG3B illustrates a side view of the connector shown in FIG2 according to various aspects of the present disclosure, with the housing removed. FIG4 illustrates a perspective view of a wafer assembly in a connector of the interconnect system shown in FIG1 according to various aspects of the present disclosure. FIG5A illustrates a perspective view of an identification wafer assembly in a connector of the interconnect system shown in FIG1 according to various aspects of the present disclosure. FIG5B illustrates a first side view of a circuit module in the identification wafer assembly shown in FIG5A according to various aspects of the present disclosure. FIG5C illustrates a second side view of the circuit module shown in FIG5B according to various aspects of the present disclosure. 110: Cable harness 110A~110D: Cable 210A~210P: Thin-film components 212A~212P: Signal connection interface 220: ID sheet assembly (ID sheet assembly) 222: Identification link interface (ID link interface) 270: Thin-film plug-in

Claims

1. A cable assembly, comprising: A cable bundle; A connector at one end of the cable bundle, the connector comprising: a plurality of signal wafer assemblies electrically connected to cables in the cable bundle; and an identification wafer assembly including an identification wafer module storing a unique identifier for the cable assembly, wherein each of the signal wafer assemblies includes a signal connection interface; the identification wafer assembly includes an identification connection interface; and the signal connection interface is identical to the identification connection interface.

2. The cable assembly according to claim 1, wherein, The connector further includes a housing; the plurality of signal sheet body assemblies are arranged in a row within the housing; and the identification sheet body assembly is located at one end of the row of the plurality of signal sheet body assemblies.

3. The cable assembly according to claim 1, wherein, The identification connection interface includes a data bus and a power terminal.

4. The cable assembly according to claim 1, wherein, The identification connection interface includes a series of data buses and power terminals.

5. The cable assembly according to claim 1, wherein, Each signal connection interface of the plurality of signal sheet body assemblies is electrically connected to a conductor of a plurality of cables in the cable bundle; and the identification sheet body assembly is not electrically connected to any conductor of any cable in the cable bundle.

6. The cable assembly according to claim 1, wherein, The unique identifier includes a slot address identifier.

7. The cable assembly according to claim 1, wherein, The identification sheet module is configured to respond to a query in response to an identification connection interface of the identification sheet assembly, communicating the unique identifier of the cable assembly.

8. The cable assembly according to claim 1, wherein, The identification sheet module is configured to respond to a query in response to an identification connection interface of the identification sheet assembly, and communicate an identification word response from the cable assembly.

9. The cable assembly according to claim 8, wherein, The identification response includes a unique identification code on the connector at one end of the cable bundle.

10. The cable assembly according to claim 8, wherein, The identification response includes information related to the connector, the cable harness, or both the connector and the cable harness.

11. The cable assembly according to claim 8, wherein, The identification response includes information related to the addresses of the connector and at least one other connector in a plurality of connectors arranged in a partition.

12. An interconnection system, comprising: A first cable assembly includes: a first cable bundle; a first connector at one end of the first cable bundle, the first connector including: a first signal sheet assembly electrically connected to a cable in the first cable bundle; and a first identification sheet assembly including a first identification sheet module storing a first unique identifier of the first cable assembly; and a second cable assembly includes: a second cable bundle; a second connector at one end of the second cable bundle, the second connector including: a second signal sheet assembly electrically connected to a cable in the second cable bundle; and a second identification sheet assembly including a second identification sheet module storing a second unique identifier of the second cable assembly, wherein the first signal sheet assembly includes a signal connection interface; the first identification sheet assembly includes an identification connection interface; and the signal connection interface is the same as the identification connection interface.

13. The interconnection system according to claim 12, wherein, The identification connection interface includes a series of data buses and power terminals.

14. The interconnection system according to claim 12, wherein, The first unique identifier includes a first slot address identifier; and the second unique identifier includes a second slot address identifier.

15. A cable assembly comprising: A cable bundle; A connector at one end of the cable bundle, the connector comprising: a signal wafer assembly electrically connected to a cable in the cable bundle; and an identification wafer module storing a unique identifier of the cable assembly, wherein the signal wafer assembly includes a signal connection interface; the identification wafer assembly includes an identification connection interface; and the signal connection interface is identical to the identification connection interface.

16. The cable assembly according to claim 15, wherein, The unique identifier includes the slot address identifier.

17. The cable assembly according to claim 15, wherein, The identification sheet module is configured to respond to queries on the identification connection interface of the identification sheet module by communicating the identification word of the cable assembly.

18. The cable assembly according to claim 17, wherein, The identification response includes information related to the connector, the cable harness, or both the connector and the cable harness.

19. A connector comprising: A shell; A signal sheet assembly is held within the housing; And an identification sheet assembly held in the housing, the identification sheet assembly including an identification sheet module storing a unique identification code of the connector, wherein the signal sheet assembly includes a signal connection interface; the identification sheet assembly includes an identification connection interface; and the signal connection interface is the same as the identification connection interface.

20. The connector according to claim 19, wherein, The signal sheet assembly includes a plurality of signal sheet assemblies arranged in a row within the housing; and the identification sheet assembly is located at one end of the row of the plurality of signal sheet assemblies.

21. The connector according to claim 19, wherein, The identification connection interface includes a data bus and a power terminal.

22. The connector according to claim 19, wherein, The unique identifier includes a slot address identifier.

23. The connector according to claim 19, wherein, The unique identifier includes information related to the address of the connector and at least one other connector in the arrangement of multiple connectors in a partition.

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