Packaging substrate and manufacturing method thereof

Abstract

This invention relates to an encapsulation substrate and a method for manufacturing an encapsulation substrate. The encapsulation substrate according to the invention includes: a glass substrate having a first surface and a second surface opposite to each other; a cavity portion formed in the glass substrate; and a cavity element disposed in the cavity portion. The cavity portion includes: a cavity space for insertion of at least a portion of the cavity element; and a sidewall surrounding the cavity space. A gap is disposed between one side of the cavity element and the sidewall, the gap being formed by filling with one or more filler materials, and the length of the gap being 50 μm or less. Accordingly, the volume used to fill the gap between the sidewall of the cavity portion and the cavity element can be reduced, and the usable area of ​​the glass substrate can be increased while reducing filler material loss. Furthermore, reducing surface disturbance can facilitate the formation of additional deposited layers.

Description

[Technical Field]

[0001] The embodiments involve packaging substrates, semiconductor packaging, methods for manufacturing packaging substrates, methods for manufacturing semiconductor packaging, etc. [Previous Technology]

[0002] In the manufacturing of electronic products, the process of realizing circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling wafers into a state that can be used in a physical product is called the back-end process (BE), which includes the packaging process.

[0003] Recently, the four core technologies of the semiconductor industry, which enable the rapid development of electronic products, are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms, such as linewidths of sub-micrometer nanometers, tens of millions of cells, high-speed operation, and large-scale heat dissipation. However, there is no correspondingly perfect packaging technology to support this. Therefore, the electrical performance of semiconductors is determined more by packaging technology and its electrical connections than by the performance of semiconductor technology itself.

[0004] The material used as the substrate for packaging includes ceramic or resin. In the case of ceramic substrates such as silicon substrates, the high resistance or high dielectric constant makes it difficult to mount high-performance, high-frequency semiconductor devices. In the case of resin substrates, high-performance, high-frequency semiconductor devices can be mounted relatively easily. However, there are limitations in shortening the wiring pitch.

[0005] Recently, silicon or glass has been used as the packaging substrate for high-end applications. By forming through-holes on the silicon or glass substrate and applying conductive materials to these through-holes, the wiring length between components and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

[0006] Furthermore, the semiconductor package can generate heat during operation and also includes a heat dissipation unit for releasing such heat.

[0007] Examples of prior art include Korean Patent Publication No. 10-2021-0022980 and Korean Patent Publication No. 10-2022-0050121. [Summary of the Invention]

[0008] The technical problem to be solved

[0009] The purpose of the embodiments is to provide a method for manufacturing a packaging substrate and a packaging substrate using the same, wherein in a packaging substrate using a glass substrate, the gap between the sidewall of the cavity portion and the cavity element is configured to have a small volume.

[0010] Furthermore, the purpose of the embodiments is to provide a method for manufacturing an encapsulation substrate and an encapsulation substrate using the same, wherein the gap is formed in a tapered shape by forming the sidewall of the cavity portion at an angle, thereby reducing surface fluctuation by reducing the loss of filler material used to fill the gap, which is beneficial to the formation of the deposited layer.

[0011] Technical solution for solving the problem

[0012] In order to achieve the above objective, according to one embodiment of the encapsulation substrate, it includes: a glass substrate having a first surface and a second surface opposite to each other; a cavity portion formed in the glass substrate; and a cavity element disposed in the cavity portion.

[0013] The cavity portion includes: a cavity space for insertion of at least a portion of the cavity element; and a sidewall surrounding the cavity space, with a gap disposed between one side of the cavity element and the sidewall.

[0014] The gap may be formed by filling with one or more filling materials.

[0015] The length of the gap can be less than 50 μm.

[0016] The sidewall may be formed at an angle, and the angle between the sidewall and the second surface is 65 degrees or more.

[0017] When the side is inclined, the length of the gap can be the maximum value of the distance between the sidewall and one side of the cavity element, and the length of the gap is less than 50 μm.

[0018] The cavity portion can be a full cavity type, wherein the cavity space penetrates the glass substrate; or, the cavity portion can be a semi-cavity type, wherein the cavity space is in the form of a recess in the first or second surface of the glass substrate.

[0019] The cavity portion may have an open surface located at the opening of the cavity space and a bottom surface of the recessed portion of the cavity space or a bottom surface facing the open surface, wherein the area of ​​the open surface is larger than the area of ​​the bottom surface.

[0020] The glass substrate may include a first cavity and a second cavity.

[0021] A first cavity element may be disposed in the first cavity portion, and a second cavity element may be disposed in the second cavity portion.

[0022] When viewed in cross-section, the sum of the gaps on both sides of the first cavity element and the gaps on both sides of the second cavity element can be less than 200 μm.

[0023] A first cavity element and a second cavity element may be configured in the cavity portion.

[0024] When viewed in cross-section, the sum of the gaps on both sides of the first cavity element and the gaps on both sides of the second cavity element can be less than 150 μm.

[0025] In addition, in order to achieve the above objective, a method for manufacturing an encapsulation substrate according to one embodiment includes the steps of: preparing a glass substrate having a cavity portion and a cavity element; and the steps of disposing of and filling the cavity portion with the cavity element.

[0026] The glass substrate has a first surface and a second surface that are opposite to each other.

[0027] The cavity portion may include: a cavity space for inserting at least a portion of the cavity element; and a sidewall surrounding the cavity space, with a gap disposed between one side of the cavity element and the sidewall, wherein in the filling step, the gap is filled with a filling material to form a filling portion.

[0028] The cavity portion can be a full cavity type, wherein the cavity space penetrates the glass substrate, and the step of configuring the cavity element is performed with the support layer attached below the second surface, and the support layer is removed after the filling step.

[0029] The sidewall can be formed at an angle, which reduces the amount of filling material required by more than 30% compared to the case where the sidewall is perpendicular to the second surface.

[0030] Technical Effect

[0031] According to the manufacturing method of the encapsulation substrate and the encapsulation substrate of the embodiment, the volume of the gap between the sidewall used to fill the cavity and the cavity element can be reduced, thereby increasing the usable area of ​​the glass substrate, reducing the loss of filling material, and reducing surface fluctuation, which is beneficial to the formation of an additional build-up layer.

[0032] Furthermore, by forming the sidewalls of the cavity portion at an angle, the volume of the gap between the sidewalls used to fill the cavity portion and the cavity element can be reduced, thereby increasing the usable area of ​​the glass substrate, reducing the loss of filling material, and reducing surface fluctuation, which is beneficial for generating an additional build-up layer.

Implementation Method

[0034] The following detailed description is provided to aid in a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, after understanding the disclosure of this application, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will be apparent. For example, the sequence of actions described herein is merely illustrative and is not limited to the actions described herein. The sequence of actions may be altered based on an understanding of the disclosure of this application, except for actions that must be performed in a specific order. Furthermore, after understanding the disclosure of this application, descriptions of known features may be omitted to increase clarity and conciseness. However, the omission of these features and descriptions is not intended to imply that they are common knowledge.

[0035] The features described in this specification may be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate a portion of the many possible ways of implementing the methods, apparatus, and / or systems described herein, which will be apparent upon understanding the disclosure of this application.

[0036] Although terms such as “first,” “second,” and “third” may be used in this specification to describe a variety of components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section.

[0037] In all specifications, when an element such as a layer, region, or substrate is described as “on another element,” “connected to another element,” or “bonded to another element,” it can be directly “on another element,” “connected to another element,” or “bonded to another element,” or there may be one or more other elements between them. Conversely, when an element is described as “directly on another element,” “directly connected to another element,” or “directly bonded to another element,” there cannot be other elements intervening between them. Similarly, expressions such as “between…” and “immediately between…” and “adjacent to” and “closely adjacent” can also be interpreted as described above.

[0038] The terminology used in this specification is for the purpose of describing particular examples only and is not intended to limit this disclosure. As used in this specification, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. As used in this specification, the term "and / or" includes any one of the associated listed items and any combination of any two or more items. As used in this specification, the terms "comprising," "including," and "having" specify the presence of the stated features, digits, actions, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, digits, actions, elements, components, and / or combinations thereof. The use of the term "may" in this specification with respect to examples or embodiments (e.g., with respect to what an example or embodiment may include or implement) means that there exists at least one example or embodiment that includes or implements such a feature, rather than all examples being limited thereto.

[0039] In this application, “B is located on A” means that B is in direct contact with A or is configured on A in such a way as to intervene in another layer or structure therebetween, and therefore should not be construed as being limited to B being in direct contact with A.

[0040] Unless otherwise defined, all terms used in this specification shall have the same meaning as understood in one of the general technical fields to which this invention pertains. Terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the prior art and this invention, and shall not be interpreted in an idealized or overly formal sense unless expressly defined in this specification.

[0041] In one or more examples, the description of “A and / or B” means “A, B, or A and B”.

[0042] In one or more examples, terms such as “first”, “second”, “A” or “B” are used to distinguish the same terms.

[0043] In one or more examples, unless otherwise stated, the singular expression is to be interpreted as including the meaning of the singular or plural as interpreted in the context.

[0044] Packaging substrate

[0045] FIG1 is a conceptual diagram illustrating an example of a glass substrate for an encapsulation substrate according to an embodiment; FIG2a is a conceptual diagram illustrating a cross-section A-A' of the glass substrate according to an embodiment; and FIG2b is a conceptual diagram illustrating a cross-section A-A' of a glass substrate according to another embodiment. Hereinafter, the glass substrate included in the encapsulation substrate will be described in detail with reference to FIGS. 1 to 2b.

[0046] According to one or more examples, the glass substrate 100 includes element regions 110 and substrate regions 120 that are distinct from each other. Element regions 110 are regions configured with cavities, and substrate regions 120 are regions without cavities. Element regions 110 and substrate regions 120 may be configured adjacent to each other. The glass substrate 100 may include one element region 110 or more element regions 110. The element region may also be referred to as a cavity structure.

[0047] The glass substrate 100 has a first surface and a second surface that are opposite to each other and are generally parallel to each other, so that the glass substrate 100 has a constant thickness as a whole.

[0048] Conventionally, silicon substrates and organic substrates have been used as packaging substrates for semiconductor devices. In the case of silicon substrates, when used in high-speed circuits, parasitic elements may be generated due to the characteristics of the semiconductor, resulting in relatively large power losses. Furthermore, in the case of organic substrates, a large area is required to form more complex patterns, which is not in line with the trend of manufacturing ultra-miniaturized electronic devices. In order to form complex patterns within a predetermined size, pattern miniaturization is substantially required, but there are substantial limitations to pattern miniaturization due to the properties of materials such as polymers suitable for organic substrates.

[0049] In this embodiment, as a method to solve such a problem, a glass substrate 100 is used as a support for the packaging substrate. Furthermore, along with the glass substrate 100, a through-hole formed through the glass substrate 100 is used to provide a packaging substrate with shorter electrical flow length, greater miniaturization, faster response, and fewer loss characteristics.

[0050] The glass substrate 100 is preferably a glass substrate suitable for semiconductors, such as borosilicate glass substrate, alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0051] The through-hole penetrates the glass substrate 100. The through-hole can be formed by removing a predetermined area of ​​the glass substrate 100, specifically by etching the plate-shaped glass using physical and / or chemical methods.

[0052] Specifically, when forming the core through-hole, chemical etching or laser etching can be performed after forming defects (flaws) on the surface of the glass substrate by means of laser or the like, but the present invention is not limited thereto.

[0053] Based on the unit area (1cm × 1cm) of the glass substrate 100, the number of through-holes can be 100 to 3000, 100 to 2500, or 225 to 1024. Under these pitch conditions, the formation of conductive layers and the performance of the encapsulation substrate can be improved.

[0054] The cavity portion 110 may include a cavity structure.

[0055] The cavity structure refers to a structure in which a portion of the glass substrate 100 includes a recess, wherein the recess is configured to allow an element to be disposed within the glass substrate 100. The space formed by the recess is referred to as the cavity space.

[0056] The cavity portion 110 may include: a cavity space for inserting at least a portion of the cavity element; a sidewall surrounding the cavity space; and a contact surface, which may selectively serve as the bottom surface.

[0057] Referring to Figures 2a and 2b, a cavity portion 110 can be formed on a glass substrate 100 having a first surface and a second surface that are opposite to each other.

[0058] For example, referring to FIG2a, the cavity portion 110 may have a space for component placement by extending through the first surface and the second surface of the glass substrate 100. The cavity space of the cavity portion 110 shown in FIG2a may be a full cavity type extending through the glass substrate 100.

[0059] For example, referring to FIG2b, the cavity portion 110 can be formed as a recessed surface with only one of the first or second surfaces being open. The cavity portion 110 can be formed as a recessed surface with only one of the first or second surfaces being open, thereby providing space for component placement. The cavity space of the cavity portion 110 shown in FIG2b can be a semi-cavity type, wherein the first or second surface of the glass substrate 100 is recessed.

[0060] When the component is placed in the cavity, the contact surface of the cavity portion 110 can directly contact the component or contact it through another layer. The contact surface is arranged facing the opening.

[0061] The sidewall of the cavity portion 110 is a wall that surrounds the contact surface. That is, it can be a wall that surrounds the cavity space of the cavity portion 110. When the contact surface has a quadrilateral shape, the sidewall may include four surfaces.

[0062] The sidewall connects the first surface of the base region 120 and the contact surface.

[0063] When viewed from the opening, the cavity 110 can be substantially circular, triangular, quadrilateral, hexagonal, octagonal, cross-shaped, etc., and its shape is not limited.

[0064] Furthermore, as described above, a cavity portion can be formed in the glass substrate, and a cavity element can be disposed in the cavity portion. In this case, in order to prevent short circuits or the like from occurring in the cavity element, a gap can be disposed in the cavity portion between the cavity element and the sidewall. A filling portion can be disposed in the gap.

[0065] The cavity element may include active elements such as transistors or passive elements such as multilayer ceramic capacitors (MLCCs).

[0066] When an active element such as a transistor is used as the cavity element, the transistor converts the electrical signal between the motherboard and the semiconductor element at an appropriate level. It is implemented in the form of a transistor or the like at the intersection of the package substrate, thereby providing a more efficient and faster semiconductor device.

[0067] Furthermore, power transmission elements such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. As passive components, power transmission elements can be used in semiconductor devices in at least 200 or more forms, which can be plate-shaped or the like, and the number of power transmission elements used can be varied.

[0068] When transmitting power, the performance of the component is also affected by the characteristics of the conductive layer surrounding the component. In one embodiment, a non-circular through-hole can be used at the location of the conductive layer where low resistance is required in power transmission components such as this one.

[0069] Furthermore, the cavity element can be configured to insert the elements individually, or it can be embedded between insulating layers (cavity element insulating layers), such that a group of elements comprising multiple elements is formed with the electrodes exposed and then inserted into the cavity element. In the latter case, the efficiency of the packaging substrate manufacturing process can be achieved more smoothly, and it is more advantageous to ensure that the insulating layer is located in the space between complex elements in a sufficient and highly reliable manner.

[0070] Here, depending on the shape and size of the gap, there may be a significant loss of filler material used to configure the filler portion. In the embodiment, by substantially reducing the volume of the filler portion, surface fluctuation of the filler material can be reduced, and the formation of an additional build-up layer can be facilitated.

[0071] That is, embodiments are proposed in this specification that reduce the volume of the gap within the cavity or reduce surface fluctuation. Accordingly, the usable area of ​​the glass substrate can be increased, and the loss of filler material can be reduced, which is beneficial for the formation of additional build-up layers.

[0072] FIG3 is a diagram illustrating the structure of a packaging substrate according to one embodiment, FIG4a is a conceptual diagram illustrating a cross-section of the packaging substrate according to an embodiment, and FIG4b is a conceptual diagram illustrating a cross-section of a glass substrate according to another embodiment. Furthermore, FIG5a is a conceptual diagram illustrating a cross-section of the packaging substrate according to another embodiment, and FIG5b is a conceptual diagram illustrating a cross-section of a glass substrate according to another embodiment.

[0073] Referring to FIG3, the encapsulation substrate 200 may include a glass substrate 100 having a first surface and a second surface, and a cavity portion may be formed in the glass substrate 100 having the first surface and the second surface. A cavity element 210 may be disposed in the cavity portion, and a filling portion 220 may be disposed in the gap between the cavity element 210 and the sidewall of the cavity portion.

[0074] Furthermore, the encapsulation substrate 200 may optionally include a film layer 22 located beneath the glass substrate 100. The film layer 22 can be bonded during manufacturing and removed after use during component placement and filling of the cavity. The film layer can be, as an example, an adhesive film such as a PI tape.

[0075] In this embodiment, after arranging the cavity elements 210 in the cavity portion, a filling portion 220 can be generated. For example, a method such as depressurized lamination of the membrane-shaped filling portion 220 can be used. When depressurized lamination is performed in this way, the filling portion 220 is sufficiently embedded into the empty space inside the cavity portion, thereby forming a void-free filling portion 220. The filling portion 220 can be filled using a filling material.

[0076] The filling materials can be used together, one or more.

[0077] The filling material can be used in two or more ways to differentiate spaces.

[0078] The filling material can be filled in two or more stages. Depending on the filling time, a boundary line can be configured on the filling material. The boundary line can be presented as a clear boundary line depending on the difference between the materials, or it can be presented as a gradual transition by the first and second materials being partially mixed near the boundary line.

[0079] The filling material can be an insulating material.

[0080] The filler material can be used together with insulating materials and metallic materials.

[0081] The insulating material can be a mixture of polymer resin, polymer resin and filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), inorganic deposition layer, etc.

[0082] For example, acrylic resins, epoxy resins, modified resins thereof, etc., can be used as the polymer resin, and materials suitable for use in electronic devices for molding or the like can be employed. For example, liquid crystal polymers (LCPs) can be used.

[0083] Exemplarily, the mixed material may be a mixture of acrylic resin and filler, a mixture of acrylic resin and epoxy resin and filler, a mixture of epoxy resin and filler, etc. Inorganic particles may be used as fillers, and silicon dioxide particles may be used exemplary. Commercially available products may include Ajinomoto Build-up Film (ABF), Epoxy Molding Compound (EMC), Modified Polyimide (MPI), etc., but the present invention is not limited thereto.

[0084] The metal material can function as a conductive layer, a heat dissipation layer, etc.

[0085] Copper or an alloy of copper with titanium, chromium, nickel, etc., can be used as the metal material. Alternatively, aluminum or an alloy containing the same can be used as the metal material.

[0086] When the filling material is filled in two or more parts, the filling part may be provided with a boundary line in the form of a shallow depression or an inclined surface.

[0087] Referring to FIG4a, the cavity space formed in the cavity portion of the glass substrate 100 can be a full cavity type that extends through the glass substrate 100. The cavity portion may include a gap 280 disposed between the cavity element 210 and the sidewall of the cavity portion, and a filling portion 220 may be disposed in the gap 280. For example, the width of the gap 280 may be less than 50 μm, less than 45 μm, less than 40 μm, less than 35 μm, less than 30 μm, or less than 25 μm. The width of the gap 280 may be more than 15 μm or more, or more than 20 μm. When the width of the gap 280 is different at the upper and lower measurement positions of each gap, the width at the widest position is considered to be the width of the gap. As other characteristics, the encapsulation substrate 200 may include a film layer 22 or the like located below the second surface of the glass substrate 100, which can apply all the above-described characteristics to the embodiment.

[0088] Referring to FIG4b, the cavity space formed in the cavity portion of the glass substrate 100 can be a semi-cavity type with the first or second surface of the glass substrate 100 recessed. The cavity portion may include: a cavity space for at least a portion of the cavity element 210 to be inserted; sidewalls and contact surfaces surrounding the cavity space. Furthermore, the cavity portion may include a gap 280 disposed between the cavity element 210 and the sidewall of the cavity portion, and a filling portion 220 may be disposed in the gap 280. For example, the width of the gap 280 may be less than 50 μm, less than 45 μm, less than 40 μm, less than 35 μm, less than 30 μm, or less than 25 μm. The width of the gap 280 may be more than 15 μm or more, or more than 20 μm. When the width of the gap 280 is different when measured at the top and bottom of each gap, the width at the widest position is considered to be the width of the gap. As other characteristics, the encapsulation substrate 200 may include a film layer 22 or the like located below the second surface of the glass substrate 100, which can apply all the characteristics described above to the embodiments.

[0089] This specification proposes an embodiment in which a tapered structure is used to form the gap, thereby reducing the volume of the gap within the cavity. For example, the cavity may include a gap disposed between the cavity element and the sidewall, and the sidewall may be tilted at a specific angle with respect to a first or second surface of the glass substrate. Accordingly, the usable area of ​​the glass substrate can be increased, the loss of filler material can be reduced, and the surface fluctuation of the filler material can be reduced, thereby producing an effect that facilitates the formation of an additional build-up layer.

[0090] Referring to FIG5a, the cavity space formed in the cavity portion of the glass substrate 100 can be a full cavity type that extends through the glass substrate 100. The cavity portion may include a gap 280 disposed between the cavity element 210 and the sidewall of the cavity portion, and a filling portion 220 may be disposed in the gap 280. The sidewall may be tilted at a specific angle 225 with respect to the second surface of the glass substrate. For example, the angle 225 between the sidewall and the second surface may be 65 degrees or more, 70 degrees or more, 75 degrees or more, 80 degrees or more, 82 degrees or more, or 83 degrees or more. The angle 225 may be 86 degrees or less, or 85 degrees or less.

[0091] The cavity portion may have the following characteristics: it has an open surface located at the opening of the cavity space and a bottom surface of the recessed portion of the cavity space or a bottom surface facing the open surface, and the area of ​​the open surface is greater than the area of ​​the bottom surface.

[0092] The width of the gap 280, which is another characteristic, may include a film layer 22 located below the second surface of the glass substrate 100, etc., and all the above-described characteristics can be applied to the embodiments.

[0093] Referring to FIG5b, the cavity space formed in the cavity portion of the glass substrate 100 can be a semi-cavity type with the first or second surface of the glass substrate 100 recessed. The cavity portion may include: a cavity space for at least a portion of the cavity element 210 to be inserted; sidewalls and contact surfaces surrounding the cavity space. The cavity portion may include a gap 280 disposed between the cavity element 210 and the sidewall of the cavity portion, and a filling portion 220 may be disposed in the gap 280. The sidewall may be tilted at a specific angle with reference to the second surface of the glass substrate. For example, the angle 225 between the sidewall and the second surface may be 65 degrees or more, 70 degrees or more, 75 degrees or more, 80 degrees or more, 82 degrees or more, or 83 degrees or more. The angle 225 may be 86 degrees or less, or 85 degrees or less. Other characteristics such as the width of the gap 280 may also be applicable to the embodiments.

[0094] Multiple cavity elements can be disposed on the glass substrate. This specification presents an embodiment in which gaps are formed in the cavity portion where multiple cavity elements are disposed.

[0095] FIG6a is a conceptual diagram illustrating a cross-section of an encapsulation substrate according to another embodiment, and FIG6b is a conceptual diagram illustrating a cross-section of a glass substrate according to another embodiment.

[0096] Referring to FIG6a, the cavity space formed in the cavity portion of the glass substrate 100 can be a full cavity type that extends through the glass substrate 100. A plurality of cavity elements 210 can be disposed in the cavity portion.

[0097] For example, the glass substrate 100 may include a first cavity portion and a second cavity portion. A first cavity element may be disposed in the first cavity portion, and a second cavity element may be disposed in the second cavity portion. The first cavity portion may include a gap 280 disposed between the first cavity element and the sidewall of the first cavity portion, and the second cavity portion may include a gap 280 disposed between the second cavity element and the sidewall of the second cavity portion. Furthermore, a gap 280 may be disposed between the first cavity portion and the second cavity portion. Referring to FIG6a, when viewed in cross-section, gaps may be disposed on both sides of the first cavity element and both sides of the second cavity element. For example, when viewed in cross-section, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element may be less than 200 μm. The sum of the gaps can be less than 200 μm, less than 190 μm, less than 180 μm, less than 170 μm, less than 160 μm, less than 150 μm, less than 140 μm, less than 130 μm, less than 120 μm, less than 110 μm, less than 100 μm, or less than 98 μm. The sum of the gaps can be more than 60 μm, more than 70 μm, or more than 80 μm. A filling portion 220 can be provided in the gap 280.

[0098] The angle 225 between the sidewall and the second surface, which is another characteristic, may include a film layer 22 located below the second surface of the glass substrate 100, etc., which can apply all the above-described characteristics to the embodiments.

[0099] Alternatively, for example, although not shown in FIG. 6a, a first cavity element and a second cavity element may be arranged together in a cavity portion. When viewed in cross-section, the cavity portion may include a gap between the first cavity element and the second cavity element, and two gaps respectively disposed between the cavity element and the sidewall. In this case, the sum of the gaps may be less than 150 μm, less than 140 μm, less than 130 μm, less than 120 μm, less than 100 μm, less than 90 μm, or less than 80 μm. The sum of the gaps may be more than 50 μm, more than 60 μm, or more than 70 μm. A filling portion 220 may be disposed in the gap 280.

[0100] The angle 225 between the sidewall and the second surface, which is another characteristic, may include a film layer 22 located below the second surface of the glass substrate 100, etc., which can apply all the above-described characteristics to the embodiments.

[0101] Referring to FIG6b, the cavity space formed in the cavity portion of the glass substrate 100 can be a semi-cavity type with the first or second surface of the glass substrate 100 recessed. The cavity portion may include: a cavity space for at least a portion of the cavity element 210 to be inserted; sidewalls and contact surfaces that surround the cavity space.

[0102] For example, the glass substrate 100 may include a cavity portion, in which a first cavity element and a second cavity element may be disposed. The cavity portion may include a gap 280 disposed between the first cavity element and the sidewall of the cavity portion, and a gap 280 disposed between the second cavity element and the sidewall of the cavity portion. Furthermore, a gap 280 may be disposed between the first cavity element and the second cavity element. Referring to FIG6b, when viewed in cross-section, gaps may be disposed on both sides of the first cavity element and both sides of the second cavity element. For example, when viewed in cross-section, the sum of the gaps disposed on both sides of the first cavity element and the gaps disposed on both sides of the second cavity element may be 150 μm or less. That is, the sum of the gaps may be 150 μm or less, 140 μm or less, 130 μm or less, 120 μm or less, 100 μm or less, 90 μm or less, or 80 μm or less. The sum of the gaps may be 50 μm or more, 60 μm or more, or 70 μm or more. A filling portion 220 may be provided in the gap 280.

[0103] Although not shown in FIG. 6b, the glass substrate 100 may include a first cavity portion and a second cavity portion. A first cavity element may be disposed in the first cavity portion, and a second cavity element may be disposed in the second cavity portion. The first cavity portion may include a gap 280 disposed between the first cavity element and the two side walls of the first cavity portion, and the second cavity portion may include a gap 280 disposed between the second cavity element and the two side walls of the second cavity portion. A gap 280 may be disposed between the first cavity portion and the second cavity portion. The sum of the gaps may be less than 200 μm, less than 190 μm, less than 180 μm, less than 170 μm, less than 160 μm, less than 150 μm, less than 140 μm, less than 130 μm, less than 120 μm, less than 110 μm, less than 100 μm, or less than 98 μm. The sum of the gaps may be more than 60 μm, more than 70 μm, or more than 80 μm. A filling portion 220 may be provided in the gap 280.

[0104] The angle 225 between the sidewall and the second surface, which is another characteristic, may include a film layer 22 located below the second surface of the glass substrate 100, etc., which can apply all the above-described characteristics to the embodiments.

[0105] Furthermore, according to one embodiment, the encapsulation substrate 200 includes: a glass substrate 100, an upper layer 300 located on one side of the glass substrate 100, and a cavity portion 110 for arranging cavity elements.

[0106] The encapsulation substrate 200 may further include: a lower layer 400 located below the other side of the glass substrate 100.

[0107] Figures 7a and 7b are examples of the cross-sectional structure of the packaging substrate generated according to the embodiment. In the figures, the upper and lower layers are shown simplified to omit the display of the conductive layers, the structure of the insulating layers, etc. inside them.

[0108] Referring to FIG7a, the encapsulation substrate 200 may include a cavity element and a glass substrate having a cavity portion including a gap. An upper layer 300 may be disposed on one side of the glass substrate 100, and a lower layer 400 may be disposed below the other side of the glass substrate 100. Furthermore, referring to FIG7b, the encapsulation substrate 200 may include a cavity element, a glass substrate having a cavity portion including a gap, and a film layer. An upper layer 300 may be disposed on one side of the glass substrate 100, and a lower layer 400 may be disposed below the other side of the glass substrate 100.

[0109] The upper layer 300 includes an upper partition layer and an upper surface connection layer located above the upper partition layer. The uppermost surface of the upper layer 300 can be protected by a cover layer having an opening that allows the contact electrode of the semiconductor element portion to directly abut.

[0110] The upper distribution layer includes: an upper insulating layer located above the first surface; and an upper distribution pattern having a pre-defined pattern, which is built into the upper insulating layer and serves as a conductive layer electrically connected to the core distribution layer as at least a part thereof.

[0111] The upper insulating layer can be made of any material as long as it is used as an insulating layer for semiconductor devices or packaging substrates, such as epoxy resin containing fillers, but the present invention is not limited thereto.

[0112] The insulating layer can be formed by forming a coating and then hardening it, or by laminating an insulating film that is in an unhardened or semi-hardened state onto the glass substrate 100 and then hardening it. In this case, if a depressurized lamination method is used, the insulator can be embedded into the space inside the through-hole, thereby enabling a highly efficient process.

[0113] Semiconductor Devices

[0114] In order to achieve the above objective, a semiconductor device according to an embodiment includes: a semiconductor element portion, wherein one or more semiconductor elements are located in the semiconductor element portion; a package substrate electrically connected to the semiconductor elements; and a motherboard electrically connected to the package substrate, transmitting external electrical signals to the semiconductor elements and being connected to each other.

[0115] The semiconductor element section refers to an element mounted on a semiconductor device, which is mounted on the package substrate using contact electrodes or the like. Specifically, the semiconductor element section can be, for example, computing elements such as CPUs and GPUs, memory elements such as memory chips, etc., but any semiconductor element mounted on a semiconductor device can be used without limitation.

[0116] The motherboard can be a printed circuit board, a printed wiring board, or other motherboard.

[0117] According to one embodiment, even when multiple layers of insulating material are stacked, it may be difficult to substantially distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Furthermore, the core insulating layer and the upper insulating layer may use the same insulating material, in which case their boundaries may not be substantially distinguishable. Alternatively, according to different embodiments, the boundaries of the insulating layers can be generated by setting different pressures and temperatures for hardening the multiple insulating layers.

[0118] The aforementioned upper distribution pattern refers to a conductive layer located within the upper insulating layer in a predetermined shape, which may be formed, for example, by a stacking method. Specifically, an insulating layer may be formed, and after removing unnecessary portions of the insulating layer, a conductive layer may be formed by copper plating or the like. After selectively removing unnecessary portions of the conductive layer, an insulating layer may be formed again on the conductive layer. After removing unnecessary portions again, a conductive layer may be formed by plating or the like. By repeating this process, an upper distribution pattern in which the desired pattern is formed with a conductive layer in the vertical or horizontal direction may be created.

[0119] Since the upper distribution pattern is located between the glass substrate 100 and the semiconductor element portion, the upper distribution pattern is formed such that at least a portion of it includes fine patterns, thereby enabling smooth transmission of electrical signals with the semiconductor element portion and adequately accommodating the desired complex pattern. Here, fine patterns refer to patterns whose width and spacing can be less than 4 μm, less than 3.5 μm, less than 3 μm, less than 2.5 μm, or 1 to 2.3 μm, respectively (the description of fine patterns is the same below).

[0120] The upper surface connection layer includes: an upper surface connection pattern, at least a portion of which is electrically connected to the upper distribution pattern and located in the upper insulating layer; and an upper surface contact electrode that electrically connects the semiconductor element portion and the upper surface connection pattern. The upper surface connection pattern may be located on one side of the upper insulating layer, or it may be configured such that at least a portion of it is exposed and embedded in the upper insulating layer. For example, when the upper surface connection pattern is located on one side of the upper insulating layer, the upper insulating layer can be formed by means of plating or the like. When a portion of the upper surface connection pattern is exposed and embedded in the upper insulating layer, a portion of the insulating layer or conductive layer can be removed by means of surface polishing, surface etching, or the like after forming a copper plating layer.

[0121] Similar to the upper parting pattern described above, the upper surface connection pattern may include fine patterns in at least a portion thereof. Such an upper surface connection pattern including fine patterns allows for electrical connections of a greater number of components even in a narrower area, thereby enabling smoother electrical signal connections between components or with external devices, and achieving more integrated packaging.

[0122] The upper surface contact electrode can be directly connected to the semiconductor element using terminals or the like, or it can be connected using an element connection part such as a solder ball as a medium.

[0123] The encapsulation substrate 200 is also connected to a motherboard. The motherboard can be directly connected to the core distribution pattern on at least a portion of the second surface of the glass substrate 100 using its terminals, or it can be electrically connected using a board connection portion such as solder balls as a medium. Furthermore, the core distribution pattern connected to the motherboard can also be connected to the motherboard using a lower layer 400 located at the lower part of the glass substrate 100 as a medium.

[0124] According to one example, in the package substrate 200 located between the semiconductor element section and the motherboard, no additional substrate may be used in addition to the glass substrate.

[0125] Method for manufacturing a substrate for packaging

[0126] To achieve the aforementioned objective, this specification provides a method for manufacturing a packaging substrate according to an embodiment. For example, the method for manufacturing a packaging substrate according to an embodiment of this specification includes the steps of: preparing a glass substrate having a cavity portion and a cavity element; and the steps of disposing of and filling the cavity portion with the cavity element.

[0127] A glass plate having a first and a second surface facing each other and having a cavity formed thereon is used as the glass substrate. A glass substrate having a through hole formed together with the cavity can also be used. Since the specific description of the shape, characteristics, etc. of the cavity is repeated above, detailed description will be omitted here.

[0128] The cavity portion of the glass substrate can be formed by a defect formation process and an etching process. Defects can be formed at the location where the cavity portion and / or through hole are to be formed on the glass plate using a laser or the like, and then immersed in an etching solution, thereby obtaining a glass substrate with a cavity portion and / or through hole by utilizing the difference in etching rate.

[0129] Next, cavity elements may be disposed in the cavity portion. The cavity elements may include active elements such as transistors or passive elements such as multilayer ceramic capacitors (MLCCs).

[0130] If the cavity element is disposed in the cavity portion, a gap will be formed between the cavity element and the side wall of the cavity portion as described above. Since the specific explanation of this is repeated above, a detailed explanation will be omitted here.

[0131] When the cavity portion is a full cavity, a support layer, such as a film layer, can be disposed below the second surface of the glass substrate between the cavity elements. This film layer can be an adhesive film. In this case, it is more advantageous to align the cavity elements in the cavity portion, which is a full cavity.

[0132] The filling material used to fill the gap can be any of the filling materials described above. For example, materials that can be hardened using methods such as ultraviolet curing or thermosetting can be used as the filling material. Therefore, when forming the filling portion, a method can be used to place the filling material in the gap using methods such as depressurized lamination, and then harden the filling material using methods such as ultraviolet curing or thermosetting.

[0133] The filling portion can be formed by one or more filling processes.

[0134] For example, a first filler material (first filler material) is used to form a first filler portion before hardening by a first depressurized lamination or the like, and then hardened or semi-hardened. Subsequently, a second filler material (second filler material) can be used again to form a second filler portion before hardening by a second depressurized lamination or the like, and then hardened or semi-hardened again. In this case, when viewed in cross-section, a boundary line can be provided between the first filler portion and the second filler portion. Alternatively, when the formation of the filler portion is divided into a first and a second process, its boundary can be observed on the filler portion. Alternatively, forming the filler portion in two or more stages can reduce the stress generated in the glass substrate, which can help suppress warpage. Alternatively, by filling in two or more stages, it is possible to substantially suppress the formation of dimples, the formation of inclined surfaces on the surface of the filler portion, etc.

[0135] In addition, an upper layer may be disposed on one side of the packaging substrate, and a lower layer may be disposed on the other side of the packaging substrate. The formation of the upper layer and / or the lower layer may be performed in any manner that forms redistribution lines.

[0136] For example, the upper layer manufacturing steps may be as follows.

[0137] The upper layer manufacturing step involves forming an upper insulating layer and an upper subdivision layer including an upper subdivision pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming the insulating layer or by laminating an insulating film; the simpler method of laminating an insulating film is preferred. The lamination of the insulating film can be formed by laminating and curing the insulating film, in which case the insulating resin can be fully embedded in the unconductive layer inside the core through-hole by using a depressurized lamination method. The upper insulating layer also directly abuts the glass substrate in at least a portion therein, so an insulating layer with sufficient adhesion is preferred. Specifically, the glass substrate and the upper insulating layer preferably have an adhesion test value of 4B or higher corresponding to ASTM D3359.

[0138] The upper parting pattern can be formed by repeatedly performing the following process: after forming the insulating layer and forming the conductive layer with a pre-set pattern, unnecessary parts are etched to form an etched layer of the conductive layer. In the case where conductive layers are formed adjacent to each other with an insulating layer in between, the conductive layer can be formed by forming blind vias on the insulating layer and then performing a plating process. When forming blind vias, dry etching methods such as laser etching and plasma etching, or wet etching methods using a mask layer and an etching solution can be used.

[0139] Subsequently, although not shown in the figure, an upper surface connecting layer and a covering layer can be formed.

[0140] The upper surface connection pattern and the upper surface contact electrode can also be formed using a process similar to that used to form the upper partial layer. Specifically, it can be formed by etching an insulating layer in an insulating layer and then forming a conductive layer therein, followed by etching an conductive layer. However, it is also possible to selectively form the conductive layer instead of using etching. The cover layer can be formed such that an opening is formed at a position corresponding to the upper surface contact electrode to expose the upper surface contact electrode, allowing it to be directly connected to a component connection portion or a component terminal.

[0141] If an upper layer is formed, a lower surface connecting layer and a capping layer can be formed to perform the process of forming the lower layer. The lower sub-layer and / or the lower surface connecting layer can be formed in a manner similar to that described above in the upper surface connecting layer and capping layer forming steps, and the capping layer can be selectively formed.

[0142] According to the above-described embodiment of the packaging substrate manufacturing method and the packaging substrate using the same, by reducing the volume of the gap between the sidewall of the cavity portion and the cavity element, the usable area of ​​the glass substrate can be increased, the loss of filling material can be reduced, and the surface fluctuation of the filling material can be reduced, thereby producing an effect that is conducive to the formation of an additional build-up layer.

[0143] The present specification has been described above with reference to the embodiments illustrated in the accompanying drawings. However, these are merely examples, and those skilled in the art should understand that various changes and modifications can be made to the embodiments. In other words, the scope of this specification is not limited to the above-described embodiments, but rather includes various changes or modifications made by those skilled in the art using the basic concepts of the embodiments defined in the appended claims. Therefore, the true scope of protection of this specification should be determined based on the technical concept of the appended claims. [Simplified Explanation of the Diagram]

[0033] FIG1 is a conceptual diagram illustrating an example of a glass substrate for an encapsulation substrate according to an embodiment. FIG2a and FIG2b are conceptual diagrams illustrating a cross-section along A-A' of the glass substrate according to an embodiment. FIG3 is a diagram illustrating, exemplarily, the structure of an encapsulation substrate according to one embodiment. FIG4a and FIG4b are conceptual diagrams illustrating a cross-section of a glass substrate according to another embodiment. FIG5a and FIG5b are conceptual diagrams illustrating a cross-section of a glass substrate according to another embodiment. FIG6a and FIG6b are conceptual diagrams illustrating a cross-section of a glass substrate according to another embodiment. FIG7a and FIG7b are diagrams illustrating, exemplarily, the cross-sectional structure of an encapsulation substrate generated according to an embodiment.

Claims

1. A packaging substrate, comprising: A glass substrate having a first and a second surface that are opposite to each other; A cavity portion is formed in the glass substrate and is semi-cavity type; And a cavity element disposed in the cavity portion, wherein the cavity portion includes: a cavity space for inserting at least a portion of the cavity element, and is a semi-cavity type in which the first or second surface of the glass substrate is recessed; A sidewall surrounds the cavity space; a gap is disposed between one side of the cavity element and the sidewall; an open surface is located at the opening of the cavity space; and a bottom surface is located at the recess of the cavity space and faces the open surface, wherein the gap is formed by filling with one or more filling materials, and wherein the length of the gap is 50 μm or less.

2. The packaging substrate as claimed in claim 1, wherein the sidewall is formed obliquely, the angle between the sidewall and the second surface is greater than 65 degrees, and the length of the gap is the largest of the distances between the sidewall and one side of the cavity element.

3. The packaging substrate as claimed in claim 1, wherein the area of ​​the open surface is greater than the area of ​​the bottom surface of the recess.

4. The encapsulation substrate as claimed in claim 1, wherein the glass substrate includes a first cavity portion and a second cavity portion, a first cavity element is disposed in the first cavity portion, a second cavity element is disposed in the second cavity portion, and when viewed in cross-section, the sum of the gaps on both sides of the first cavity element and the gaps on both sides of the second cavity element is less than 200 μm.

5. The packaging substrate as claimed in claim 1, wherein a first cavity element and a second cavity element are disposed in the cavity portion, and when viewed in cross-section, the sum of the gaps on both sides of the first cavity element and the gaps on both sides of the second cavity element is less than 150 μm.

6. A method for manufacturing a packaging substrate, comprising: The steps of preparing a glass substrate and a cavity element having a semi-cavity cavity portion, and the steps of placing the cavity element in the cavity portion and filling it; The glass substrate has a first surface and a second surface opposite to each other, wherein the cavity portion includes: a cavity space for insertion of at least a portion of the cavity element, and is a semi-cavity type with the first surface or the second surface of the glass substrate recessed; a sidewall surrounding the cavity space; a gap disposed between one side of the cavity element and the sidewall; an open surface located at the opening of the cavity space; and a bottom surface located at the recess of the cavity space and facing the open surface, wherein in the filling step, the gap is filled with a filling material to form a filling portion, wherein the length of the gap is less than 50 μm.

7. A method of manufacturing an encapsulation substrate as claimed in claim 6, wherein the sidewalls are formed at an angle, and the required amount of filler material is reduced by more than 30% compared to the case where the sidewalls are perpendicular to the second surface.

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