Semiconductor device

Abstract

A semiconductor device capable of functioning as a memory device is disclosed. The memory device includes a plurality of memory cells, each memory cell containing a first transistor and a second transistor. The first transistor is disposed above a substrate containing a semiconductor material and has a channel forming region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor is electrically connected to one of the source and drain electrodes of the second transistor. The extremely low turn-off current of the second transistor allows data stored in the memory cell to be retained for a significantly long time even without a power supply.

Description

Technical Field

[0001] The present invention discloses a semiconductor device using semiconductor elements and a method for manufacturing the semiconductor device. Prior Technology Memory devices using semiconductor components can be broadly classified into two categories: electrically dependent devices that lose stored data when the power is cut off, and non-electrically dependent devices that retain stored data even when no power is supplied. A typical example of an electrical memory device is Dynamic Random Access Memory (DRAM). DRAM stores data by selecting transistors included in the memory elements and storing charge in capacitors. When data is read from DRAM, the charge in the capacitors is lost based on the principles described above. Furthermore, the transistors included in the memory elements have leakage current, and charge flows into or out of the capacitors even when no transistor is selected, resulting in short data retention time. For this reason, another write operation (update operation) at predetermined intervals is necessary, and it is difficult to sufficiently reduce power consumption. Moreover, since stored data is lost when power is off, additional memory devices using magnetic or optical materials are required to retain data for extended periods. Another example of an electrical memory device is Static Random Access Memory (SRAM). SRAM uses circuitry such as flip-flops to retain stored data, thus eliminating the need for update operations. This means that SRAM is superior to DRAM. However, the cost per unit of storage capacity increases because of the use of flip-flops. Furthermore, as in DRAM, the data stored in SRAM is lost when the power is turned off. A typical example of a non-electrically dependent memory device is flash memory. Flash memory includes a floating gate between the gate electrode and the channel formation region in the transistor and stores data by retaining charge in the floating gate. Therefore, flash memory has the advantage of extremely long data retention time (almost permanent) and does not require the update operations necessary in electrically dependent memory devices (see Patent Document 1). However, the gate insulation layer within the memory element is degraded by the tunneling current flowing during writing, causing the memory element to cease functioning after multiple write operations. To avoid this problem, methods such as equalizing the number of write operations on the memory element can be employed. However, this requires additional complex supplementary circuitry. Furthermore, such methods do not address the fundamental issue of lifespan. In other words, flash memory is unsuitable for applications where data is frequently rewritten. In addition, high voltage is necessary for injecting charge into the floating gate or removing charge. Furthermore, injecting or removing charge takes a considerable amount of time and cannot be easily performed at high speeds for writing and erasing. [refer to] Patent Document 1: Japanese Patent Application Publication No. S57-105889 Summary of the Invention In view of the above problems, the object of one embodiment of the present invention disclosed herein is to provide a semiconductor device with a novel structure in which stored data can be retained even when no power is supplied and there is no limit to the number of writes. One embodiment of the present invention is a semiconductor device having a layered structure comprising a transistor formed using an oxide semiconductor and a transistor formed using a non-oxide semiconductor material. For example, the following structure may be employed. One embodiment of the present invention is a semiconductor device, including a first line (source line), a second line (bit line), a third line (first signal line), a fourth line (second signal line), a first transistor having a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is disposed above a substrate comprising a semiconductor material. The second transistor includes an oxide semiconductor layer. The first gate electrode is electrically connected to one of the second source electrode and the second drain electrode. The first line (source line) is electrically connected to the first source electrode. The second line (bit line) is electrically connected to the first drain electrode. The third line (first signal line) is electrically coupled to the other of the second source electrode and the second drain electrode. The fourth line (second signal line) is electrically connected to the second gate electrode. In the above structure, the first transistor includes a channel forming region disposed above a substrate comprising a semiconductor material, an impurity region disposed to clamp the channel forming region, a first gate insulating layer above the channel forming region, a first gate electrode above the first gate insulating layer, and a first source electrode and a first drain electrode electrically connected to the impurity region. In the above structure, the second transistor includes a second gate electrode disposed above a substrate comprising a semiconductor material, a second gate insulating layer disposed above the second gate electrode, an oxide semiconductor layer disposed above the second gate insulating layer, and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer. In the above structure, the substrate including the semiconductor material is preferably a single-crystal semiconductor substrate or an SOI substrate. In particular, the semiconductor material is preferably silicon. In the above structure, the oxide semiconductor layer preferably comprises an In-Ga-Zn-O based oxide semiconductor material. In particular, the oxide semiconductor layer preferably comprises In2Ga2ZnO7 crystal. Furthermore, the hydrogen concentration of the oxide semiconductor layer is preferably 5 × 10¹⁹ atoms / cm³ or less. The turn-off current of the second transistor is preferably 1 × 10⁻¹³ A or less, more preferably 1 × 10⁻²⁰ A or less. In the above structure, the second transistor can be disposed in the region overlapping with the first transistor. Note that in this specification, terms such as "above" or "below" do not necessarily mean that one component is placed "directly above" or "directly below" another component. For example, the phrase "first gate electrode above the gate insulation layer" does not exclude the possibility that one component is positioned between the gate insulation layer and the gate electrode. Furthermore, terms such as "above" or "below" are used for ease of description only and may include cases where the positional relationship of the components is reversed, unless otherwise specified. Furthermore, in this specification, the use of terms such as "electrode" or "wire" is not limited to the function of the component. For example, "electrode" is sometimes used as part of "wire," and vice versa. In addition, the use of "electrode" or "wire" may include cases in which multiple "electrodes" or "wires" are formed in a cumulated manner. When, for example, transistors of opposite polarity are used, or when the direction of current flow changes during circuit operation, the functions of "source" and "drain" may sometimes be interchanged. Therefore, the terms "source" and "drain" may be used interchangeably in this instruction manual and similar documents. Note that in this specification, the term "electrical connection" includes the case where components are connected via objects having any electrical function. There are no specific restrictions on the objects having any electrical function, as long as they can transmit and receive electrical signals between components connected via such objects. Examples of objects with any electrical function include switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions, as well as electrodes and wires. Generally, the term "SOI substrate" refers to a substrate in which a silicon semiconductor layer is disposed on an insulating surface. In this specification, the term "SOI substrate" also includes substrates in which a semiconductor layer formed using a non-silicon material is disposed on an insulating surface. That is, the semiconductor layer included in "SOI substrate" is not limited to a silicon semiconductor layer. The substrate in "SOI substrate" is not limited to semiconductor substrates such as silicon wafers and can be a non-semiconductor substrate such as a glass substrate, quartz substrate, sapphire substrate, or metal substrate. In other words, "SOI substrate" also includes conductive substrates with insulating surfaces or insulating substrates having layers formed of semiconductor materials. Furthermore, in this specification, the term "semiconductor substrate" does not only refer to a substrate formed using only one semiconductor material, but can refer to all substrates including semiconductor materials. That is, in this specification, "SOI substrate" is also included in the category of "semiconductor substrate." One embodiment of the present invention provides a semiconductor device, including a transistor of a non-oxide semiconductor material disposed at a lower portion and an oxide semiconductor transistor disposed at an upper portion. Because transistors, including oxide semiconductor transistors, have extremely low turn-off currents, stored data can be retained for a very long time. In other words, power consumption can be significantly reduced because update operations become unnecessary or can be performed very infrequently. Furthermore, stored data can be retained for extended periods even when no power is available. Furthermore, no high voltage is required to write data, and component degradation is negligible. Additionally, high-speed operation can be easily achieved by switching between the transistor's on and off states to write data. Moreover, data can be rewritten by controlling the transistor's potential inputs, eliminating the need for data erasure, which is another advantage. Since transistors containing non-oxide semiconductor materials can operate at higher speeds than transistors containing oxide semiconductor materials, stored data can be read at high speeds using such transistors. Semiconductor devices with novel features can be realized by using both transistors made of materials including non-oxide semiconductors and transistors made of oxide semiconductors. Simple Explanation of the Diagram In the attached diagram: Figure 1 is a circuit diagram of a semiconductor device; Figures 2A and 2B are cross-sectional and plan views of a semiconductor device; Figures 3A to 3H are cross-sectional views illustrating the steps involved in manufacturing a semiconductor device; Figures 4A to 4G are cross-sectional views illustrating the steps involved in manufacturing a semiconductor device; Figures 5A to 5D are cross-sectional views illustrating the steps involved in manufacturing a semiconductor device; Figure 6 is a cross-sectional view of a semiconductor device; Figures 7A and 7B are cross-sectional views of a semiconductor device; Figures 8A and 8B are cross-sectional views of a semiconductor device; Figures 9A and 9B are cross-sectional views of a semiconductor device; Figures 10A to 10F each depict an electronic device; Figure 11 is a cross-sectional view of an anti-interlaced transistor including oxide semiconductors; Figures 12A and 12B are band diagrams (schematic diagrams) of cross section A-A' in Figure 11; Figure 13A illustrates the state in which a positive potential (+VG) is applied to the gate (GE1), and Figure 13B illustrates the state in which a negative potential (-VG) is applied to the gate (GE1); Figure 14 illustrates the relationship between the vacuum energy level, the working function (φM) of a metal, and the electron affinity (χ) of an oxide semiconductor; Figures 15A and 15B are circuit diagrams of semiconductor devices; Figure 16 is a circuit diagram of a semiconductor device; Figures 17A and 17B are circuit diagrams of semiconductor devices; Figures 18A to 18C are circuit diagrams of semiconductor devices; Figure 19 is a circuit diagram of a semiconductor device; Figure 20 is a timing diagram illustrating the potential relationship; Figure 21 is a circuit diagram of a semiconductor device; Figures 22A and 22B are cross-sectional and plan views of a semiconductor device; Figures 23A to 23D are cross-sectional views illustrating a semiconductor device; Figures 24A to 24C are cross-sectional views illustrating a semiconductor device; Figure 25 shows the characteristics of transistors, including oxide semiconductors; Figure 26 is a circuit diagram for evaluating the characteristics of transistors including oxide semiconductors; Figure 27 is a timing diagram for evaluating the characteristics of transistors including oxide semiconductors; Figure 28 shows the characteristics of transistors, including oxide semiconductors; Figure 29 shows the characteristics of transistors, including oxide semiconductors; Figure 30 is a diagram showing the characteristics of transistors, including oxide semiconductors; and Figure 31 shows the evaluation results of the memory window width. Implementation Examples of embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the invention is not limited to the following description, and those skilled in the art will readily understand that various modifications can be made to the patterns and details disclosed herein without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as limited to the embodiments included herein. It should be noted that in some cases, for ease of understanding, the positions, sizes, extents, or similar aspects of the various structures shown in the figures are not precisely represented. Therefore, embodiments of the present invention are not necessarily limited to such positions, sizes, extents, or similar aspects disclosed in the figures. In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components, and these terms do not imply a limitation on the number of components. (Example 1) In this embodiment, the structure and method of manufacturing a semiconductor device according to one embodiment of the present invention disclosed herein will be described with reference to Figures 1, 2A and 2B, 3A to 3H, 4A to 4G, 5A to 5D, 6, 7A and 7B, 8A and 8B, and 9A and 9B. <Circuit Configuration of Semiconductor Devices> Figure 1 illustrates an example of a circuit configuration for a semiconductor device. The semiconductor device includes a transistor 160 formed using a non-oxide semiconductor material (such as silicon) and a transistor 162 formed using an oxide semiconductor material. Note that the semiconductor device shown in Figure 1 is referred to as a memory cell in some of the following descriptions. Here, the gate electrode of transistor 160 is electrically connected to one of the source and drain electrodes of transistor 162. A first line (also called the source line SL) is electrically connected to the source electrode of transistor 160. A second line (also called the bit line BL) is electrically connected to the drain electrode of transistor 160. A third line (also called the first signal line) is electrically connected to the other of the source and drain electrodes of transistor 162. A fourth line (also called the second signal line) is electrically connected to the gate electrode of transistor 162. Since the transistor 160, which includes a non-oxide semiconductor layer, can operate at a higher speed than transistors including oxide semiconductor layers, stored data can be read at high speed using the transistor 160. Furthermore, the transistor 162, which includes an oxide semiconductor layer, has an extremely low turn-off current. For these reasons, the potential of the gate electrode of the transistor 160 can be maintained for a very long time by turning off the transistor 162. Moreover, the absence of short-channel effects in the transistor 162, which includes an oxide semiconductor layer, is another advantage. Taking advantage of the ability to maintain the gate electrode potential, data writing, holding, and reading can be performed in the following ways. First, the writing and holding of the instruction data will be performed. First, the potential of the fourth line is set to the potential that turns on transistor 162, and transistor 162 is turned on. Therefore, the potential of the third line is supplied to the gate electrode of transistor 160 (writing). Then, the potential of the fourth line is set to the potential that turns off transistor 162, and transistor 162 is turned off, thereby maintaining the potential of the gate electrode of transistor 160 (holding). Because the turn-off current of transistor 162 is extremely low, the potential of the gate electrode of transistor 160 can be maintained for an extremely long time. For example, when the potential of the gate electrode of transistor 160 is the potential that turns on transistor 160, the turn-on state of transistor 160 can be maintained for a long time. Furthermore, when the potential of the gate electrode of transistor 160 is the potential that turns off transistor 160, the turn-off state of transistor 160 can be maintained for a long time. Next, we will explain the reading of the data. When a predetermined potential (low potential) is supplied to the first line while the transistor 160 is maintained in an on or off state as described above, the potential of the second line changes depending on whether the transistor 160 is on or off. For example, when the transistor 160 is on, the potential of the second line becomes lower under the influence of the potential of the first line. Conversely, when the transistor 160 is off, the potential of the second line does not change. In this way, the potential of the second line is compared with the predetermined potential while the data is being maintained, thereby allowing the data to be read. Third, the data rewriting process will be explained. Data rewriting is performed in a similar manner to data writing and retention. That is, the potential of the fourth line is set to the potential that turns on transistor 162, and transistor 162 is turned on. Therefore, the potential of the third line (the potential of the new data) is supplied to the gate electrode of transistor 160. Then, the potential of the fourth line is set to the potential that turns off transistor 162, and transistor 162 is turned off, thereby storing the new data. In the semiconductor device disclosed herein, data can be directly rewritten by another data write operation as described above. For that reason, the necessary erase operation, such as that required by flash memory, is eliminated, thus preventing the reduction in operating speed caused by erase operations. In other words, high-speed operation of the semiconductor device can be achieved. Because the write-dependent shut-off current of the transistor 162, which includes an oxide semiconductor layer, is extremely small, the potential of the gate electrode of the transistor 160 can be maintained for a long time. Therefore, for example, the update operations required by conventional DRAM can be eliminated, or the frequency of update operations can be significantly reduced (e.g., approximately once a month or once a year). Thus, the semiconductor device according to the disclosed invention substantially possesses the characteristics of a non-electrically dependent memory device. Furthermore, unlike conventional DRAM, the semiconductor device of the disclosed invention does not lose data when it is read; therefore, there is no need to rewrite data in each read operation. As mentioned above, the data write frequency can be significantly reduced compared to DRAM, which allows for a substantial reduction in power consumption. Furthermore, for the semiconductor device disclosed in this invention, data can be directly rewritten by writing new data to the semiconductor device. Therefore, the necessary erase operation required by flash memory or similar devices is eliminated, and the reduction in operating speed (due to the erase operation) can be suppressed. In other words, high-speed operation of the semiconductor device can be achieved. Additionally, the high voltage required for writing and erasing data by conventional floating-gate transistors is eliminated; thus, the power consumption of the semiconductor device can be further reduced. The semiconductor device according to the disclosed invention may include at least one write transistor and one read transistor; thus, the area of ​​each memory cell is small enough compared to SRAM or the like, which requires six transistors per memory cell. In other words, such semiconductor devices can be configured at high density. In conventional floating-gate transistors, charge travels through the gate insulating layer (tunnel insulating film) during write operations, thus making deterioration of the gate insulating layer (tunnel insulating film) unavoidable. Conversely, in the memory cell according to one embodiment of the present invention, data is written by switching operations of the write transistor, thus the deterioration of the gate insulating film (traditionally considered a problem) can be ignored. This means that, in principle, there is no limit to the number of write cycles and write endurance is extremely high. For example, even after writing data 1 × 10⁹ or more times (one hundred million or more times), the current-voltage characteristics do not deteriorate. Note that the field-effect mobility of the transistor 162, which includes the semiconductor device, in the on-state is 3 cm² / Vs to 250 cm² / Vs (inclusive); preferably 5 cm² / Vs to 200 cm² / Vs (inclusive); and even more preferably 10 cm² / Vs to 150 cm² / Vs (inclusive). Furthermore, the subcritical swing (S-value) of the transistor, including the oxide semiconductor layer, is set to 0.1 V / dec or less. By using this type of transistor, the time required for data writing can be sufficiently short. The channel length L of the transistor 162, which includes the semiconductor device, is preferably between 10 nm and 400 nm (inclusive). With this channel size, various benefits can be obtained, such as high-speed operation, low power consumption, and high transistor integration. It is noted that transistors including crystalline silicon are preferably used for readout transistors 160. In particular, to increase the speed of readout operations, n-channel transistors including single-crystal silicon are preferred. Such single-crystal silicon transistors can be formed using, for example, bulk silicon (so-called silicon wafers). Note that an n-channel transistor is used in the above description; needless to say, a p-channel transistor can be used instead of an n-channel transistor. <Planar and Cross-sectional Structures of Semiconductor Devices> Figures 2A and 2B illustrate an example of the structure of a semiconductor device. Figure 2A shows a cross-sectional view of the semiconductor device, and Figure 2B shows a plan view of the semiconductor device. Here, Figure 2A corresponds to the cross-section along lines A1-A2 and B1-B2 in Figure 2B. The semiconductor device shown in Figures 2A and 2B includes a transistor 160 in the lower part, comprising a non-oxide semiconductor material, and a transistor 162 in the upper part, comprising an oxide semiconductor layer. Note that transistors 160 and 162 are n-channel transistors; alternatively, p-channel transistors can be used. In particular, it is readily possible to use a p-channel transistor as transistor 160. The transistor 160 includes a channel forming region 116 disposed in a substrate 100 comprising semiconductor material, an impurity region 114 and a high-concentration impurity region 120 disposed to clamp the channel forming region 116 (these regions are simply collectively referred to as impurity regions), a gate insulating layer 108 disposed above the channel forming region 116, a gate electrode 110 disposed above the gate insulating layer 108, and a source electrode or drain electrode (hereinafter referred to as source / drain electrode) 130a and source / drain electrode 130b electrically connected to the impurity region 114. A sidewall insulating layer 118 is disposed on one side surface of the gate electrode 110. A high-concentration impurity region 120 is placed in a region of the substrate 100 that does not overlap with the sidewall insulating layer 118, as shown in the cross-sectional view. A metal compound region 124 is disposed above the high-concentration impurity region 120. An element isolation insulating layer 106 is disposed above the substrate 100 to surround the transistor 160. Interlayer insulating layers 126 and 128 are disposed to cover the transistor 160. Each of the source / drain electrodes 130a and 130b is electrically connected to the metal compound region 124 via openings formed in the interlayer insulating layers 126 and 128. That is, each of the source / drain electrodes 130a and 130b is electrically connected to the high-concentration impurity region 120 and the impurity region 114 via the metal compound region 124. Electrode 130c, formed in a manner similar to source / drain electrodes 130a and 130b, is electrically connected to gate electrode 110. Transistor 162 includes a gate electrode 136d disposed above an interlayer insulating layer 128, a gate insulating layer 138 disposed above the gate electrode 136d, an oxide semiconductor layer 140 disposed above the gate insulating layer 138, and source / drain electrodes 142a and 142b disposed above the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140. Here, a gate electrode 136d is provided to be embedded in the insulating layer 132 formed above the interlayer insulating layer 128. For example, the gate electrode 136d forms electrodes 136a, 136b, and 136c that are in contact with the source / drain electrode 130a, source / drain electrode 130b, and electrode 130c, respectively. A protective insulating layer 144 is disposed above the transistor 162 to contact a portion of the oxide semiconductor layer 140. An interlayer insulating layer 146 is disposed above the protective insulating layer 144. Openings leading to the source / drain electrodes 142a and 142b are formed in the protective insulating layer 144 and the interlayer insulating layer 146. Electrodes 150d and 150e are formed, respectively, to contact the source / drain electrodes 142a and 142b through individual openings. Electrodes 150d and 150e, for example, form electrodes 150a, 150b, and 150c, respectively, to contact electrodes 136a, 136b, and 136c through openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. Here, the oxide semiconductor layer 140 is preferably a highly purified oxide semiconductor layer from which impurities such as hydrogen have been sufficiently removed. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5 × 10¹⁹ atoms / cm³ or less; preferably 5 × 10¹⁸ atoms / cm³ or less; more preferably 5 × 10¹⁷ atoms / cm³ or less. Compared to a typical silicon wafer (a silicon wafer with trace amounts of phosphorus or boron impurities) having a carrier concentration of approximately 1 × 10¹⁴ / cm³, this extremely low hydrogen concentration results in a sufficiently low carrier concentration (e.g., less than 1 × 10¹² / cm³ or 1.45 × 10¹⁰ / cm³). This type of oxide semiconductor can be used to obtain a transistor 162 with significantly superior turn-off current characteristics, which is highly purified and becomes essentially (type I) or substantially (type I) by sufficiently reducing the hydrogen concentration. For example, the turn-off current of transistor 162 (here, per unit channel width (1 μm)) at room temperature (25 °C) is 10 zA / μm (1 zA (1 × 10⁻²¹ A) is equivalent to 1 × 10⁻²¹ A) or less; preferably 1 zA / μm or less. The turn-off current of transistor 162 at 85 °C is 100 zA / μm (1 × 10⁻¹⁹ A / μm) or less; preferably 10 zA / μm (1 × 10⁻²⁰ A / μm) or less. By using an oxide semiconductor layer 140 that becomes essentially or substantially essentially hydrogen by sufficiently reducing the hydrogen concentration to reduce the turn-off current of transistor 162, a semiconductor device with a novel structure can be realized. Note that the hydrogen concentration in the oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS). An insulating layer 152 is disposed above the interlayer insulating layer 146. Electrodes 154a, 154b, 154c, and 154d are disposed and embedded in the insulating layer 152. Electrode 154a is in contact with electrode 150a. Electrode 154b is in contact with electrode 150b. Electrode 154c is in contact with electrodes 150c and 150d. Electrode 154d is in contact with electrode 150e. That is, in the semiconductor device shown in Figures 2A and 2B, the gate electrode 110 of transistor 162 and the source / drain electrode 142a of transistor 162 are electrically connected via electrodes 130c, 136c, 150c, 154c and 150d. Methods for Manufacturing Semiconductor Devices Next, an example of a method for manufacturing a semiconductor device will be described. First, the method for manufacturing the transistor 160 in the lower part will be described below with reference to Figures 3A to 3H, and then the method for manufacturing the transistor 162 in the upper part will be described with reference to Figures 4A to 4G and 5A to 5D. <Methods for Manufacturing Transistors> First, a substrate 100 comprising semiconductor material is prepared (see Figure 3A). The substrate 100 comprising semiconductor material can be a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanide, or the like, an SOI substrate, or the like. Here, an example of using a single-crystal silicon substrate as the substrate 100 comprising semiconductor material will be described. A protective layer 102 (see Figure 3A) is formed above the substrate 100 to act as a mask for forming an insulating layer that isolates components. The protective layer 102 may be, for example, an insulating layer formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. Note that before or after this step, impurity elements providing n-type conductivity or p-type conductivity may be added to the substrate 100 to control the threshold voltage of the transistor. When the semiconductor material included in the substrate 100 is silicon, phosphorus, arsenic, or the like may be used as impurities providing n-type conductivity. Boron, aluminum, gallium, or the like may be used as impurities providing p-type conductivity. Next, the portion of the substrate 100 not covered by the protective layer 102 (i.e., the exposed area) is removed by etching, using the protective layer 102 as a mask. Thus, an isolated semiconductor region 104 is formed (see Figure 3B). Dry etching is preferred, but wet etching can also be performed. The etchant can be appropriately selected based on the material of the layer being etched. Next, an insulating layer is formed to cover the semiconductor region 104, and the insulating layer in one of the regions overlapping with the semiconductor region 104 is selectively removed, thereby forming a device isolation insulating layer 106 (see Figure 3B). Silicon oxide, silicon nitride, silicon oxynitride, or similar materials are used to form the insulating layer. As a method of removing the insulating layer, any etching process and polishing process such as CMP can be employed. Note that the protective layer 102 is removed after the formation of the semiconductor region 104 or after the formation of the device isolation insulating layer 106. Next, an insulating layer is formed over the semiconductor region 104, and a layer including a conductive material is formed over the insulating layer. Since the insulating layer subsequently serves as the gate insulating layer, it preferably has a monolayer or layered structure formed by CVD, sputtering, or similar methods using thin films containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like. Alternatively, the insulating layer can be formed such that one surface of the semiconductor region 104 is oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment. High-density gas plasma treatment can be performed, for example, using a mixture of rare gases such as He, Ar, Kr, or Xe with gases such as oxygen, oxynitride, ammonia, nitrogen, or hydrogen. There is no particular limitation on the thickness of the insulating layer; it can have a thickness of, for example, from 1 nm to 100 nm (inclusive). Metallic materials such as aluminum, copper, titanium, tantalum, or tungsten can be used to form the layer containing the conductive material. Semiconductor materials such as polycrystalline silicon containing the conductive material can also be used to form the layer containing the conductive material. There are no particular limitations on the method for forming the layer containing the conductive material, and various thin film formation methods such as evaporation, CVD, sputtering, or spin coating can be employed. Note that this embodiment shows one example of a case where the layer containing the conductive material is formed using a metallic material. Subsequently, the insulating layer and the layer including the conductive material are selectively etched to form the gate insulating layer 108 and the gate electrode 110 (see Figure 3C). Next, an insulating layer 112 covering the gate electrode 110 is formed (see Figure 3C). Then, an impurity region 114 having a shallow contact depth with the substrate 100 is formed by adding phosphorus (P), arsenic (As), or the like to the semiconductor region 104 (see Figure 3C). Note that phosphorus or arsenic is added here to form an n-channel transistor; impurities such as boron (B) or aluminum (Al) can be added in the case of forming a p-channel transistor. By forming the impurity region 114, a channel forming region 116 is formed in the semiconductor region 104 below the gate insulating layer 108 (see Figure 3C). Here, the concentration of the added impurities can be appropriately set; it is preferable to increase the concentration when the size of the semiconductor device is greatly reduced. Here, the step of forming the impurity region 114 after the formation of the insulating layer 112 is adopted; alternatively, the insulating layer 112 can be formed after the formation of the impurity region 114. Next, a sidewall insulating layer 118 is formed (see Figure 3D). An insulating layer is formed to cover the insulating layer 112 and then highly isotropically etched, thereby enabling the sidewall insulating layer 118 to be formed in a self-aligned manner. At this time, the insulating layer 112 is preferably etched in a portion to expose the top surface of the gate electrode 110 and the top surface of the impurity region 114. Next, an insulating layer is formed to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, and so on. Then, phosphorus (P), arsenic (As), or similar substances are added to the region where the insulating layer contacts the impurity region 114 to form a high-concentration impurity region 120 (see Figure 3E). Afterward, the insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110, the sidewall insulating layer 118, the high-concentration impurity region 120, and so on (see Figure 3E). The metal layer 122 can be formed using various thin-film formation methods such as vacuum evaporation, sputtering, or spin coating. Preferably, a metal material that reacts with the semiconductor material included in the semiconductor region 104 to form a low-resistance metal compound is used to form the metal layer 122. Examples of such metal materials are titanium, tantalum, tungsten, nickel, cobalt, and platinum. Next, a heat treatment is performed to allow the metal layer 122 to react with the semiconductor material. This forms a metal compound region 124 in contact with the high-concentration impurity region 120 (see Figure 3F). Note that when polysilicon or similar materials are used to form the gate electrode 110, a metal compound region is also formed in a region of the gate electrode 110 in contact with the metal layer 122. As a heat treatment, irradiation with a flash lamp can be used, for example. While another heat treatment can be used, it is preferable to use a method that allows for a very short heat treatment time to improve the controllability of the chemical reaction in the formation of the metal compound. Note that the metal compound region is formed by the reaction of the metal and semiconductor materials, and it has sufficiently high conductivity. The formation of the metal compound region can appropriately reduce resistance and improve device characteristics. Note that the metal layer 122 is removed after the metal compound region 124 is formed. Next, interlayer insulating layers 126 and 128 are formed to cover the component formed in the above steps (see Figure 3G). Interlayer insulating layers 126 and 128 can be formed using inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Alternatively, organic insulating materials such as polyimide or acrylic resin can be used to form interlayer insulating layers 126 and 128. Note that a two-layer structure of interlayer insulating layers 126 and 128 is used here; however, the structure of the interlayer insulating layers is not limited to this structure. After forming interlayer insulating layer 128, the surface of interlayer insulating layer 128 is preferably planarized by CMP, etching, or the like. Next, openings reaching the metal compound region 124 are formed in the interlayer insulating layers 126 and 128, and source / drain electrodes 130a and 130b are formed in the openings (see Figure 3H). The source / drain electrodes 130a and 130b can be formed in one manner, for example, by forming a conductive layer in the region including the openings by a PVC method, CVD method, or the like, and then removing portions of the conductive layer by etching, CMP, or the like. It is noted that in cases where source / drain electrodes 130a and 130b are formed by removing portions of the conductive layer, a preferred procedure is to planarize the surface. For example, when a thin titanium film or a thin titanium nitride film is formed in a region including an opening, followed by the formation of a tungsten film to embed into the opening, excess tungsten, titanium, titanium nitride, or the like can be removed, and the surface planarization can be improved by subsequent CMP. Planarizing the surfaces including source / drain electrodes 130a and 130b in a manner that allows for the advantageous formation of electrodes, wires, insulating layers, semiconductor layers, and the like in subsequent steps. Note that only the source / drain electrodes 130a and 130b in contact with the metal compound region 124 are shown here; however, electrodes such as the gate electrode 110 (electrode 130c in Figure 2A) can also be formed in this step. There are no particular limitations on the materials used for the source / drain electrodes 130a and 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium can be used. Through the above steps, a transistor 160 using a substrate 100 including semiconductor materials is formed. Note that electrodes, wires, insulating layers, or the like can be further formed after the above steps. When the wires have a multilayer structure including an interlayer insulating layer and a conductive layer, a highly integrated semiconductor device can be provided. <Methods for Manufacturing Transistors> Next, the fabrication of transistor 162 above interlayer insulating layer 128 will be described with reference to Figures 4A to 4G and 5A to 5D. Note that Figures 4A to 4G and 5A to 5D illustrate the steps of fabricating electrodes, transistor 162, and the like above interlayer insulating layer 128; therefore, transistor 160 and the like placed below transistor 162 are omitted. First, an insulating layer 132 is formed over the interlayer insulating layer 128, the source / drain electrodes 130a and 130b, and the electrode 130c (see Figure 4A). The insulating layer 132 can be formed by PVD, CVD, or similar methods. The insulating layer 132 can be formed using inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Next, openings leading to the source / drain electrodes 130a and 130b and electrode 130c are formed in the insulating layer 132. At the same time, an opening is also formed in the region where the gate electrode 136d will subsequently be formed. Then, a conductive layer 134 is formed to embed into the openings (see Figure 4B). The openings are formed by etching methods such as using a mask. The mask is formed by exposure methods such as using a photomask. Wet etching or dry etching can be used as etching; dry etching is preferred for microfabrication. The conductive layer 134 can be formed by thin film formation methods such as PVD or CVD methods. The conductive layer 134 can be formed using conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or any alloys or compounds of these materials (such as nitrides). In detail, a method can be employed, for example, in which a thin titanium film is formed in the region including the opening by PVD and a thin titanium nitride film is formed by CVD, and then a tungsten film is formed to embed into the opening. Here, the titanium film formed by PVD has the function of reducing the oxide film formed on the surface of the lower electrode (here, source / drain electrodes 130a and 130b, electrode 130c, and the like), thereby reducing the contact resistance with the lower electrode. The titanium nitride film formed after the titanium film formation has a barrier function to prevent the diffusion of conductive materials. After forming the titanium, titanium nitride, or similar barrier films, a copper film can be formed by a plating method. After the conductive layer 134 is formed, portions of the conductive layer 134 are removed by etching, CMP, or the like to expose the insulating layer 132 and form electrodes 136a, 136b, and 136c and a gate electrode 136d (see Figure 4C). Note that when forming electrodes 136a, 136b, and 136c and the gate electrode 136d by removing portions of the conductive layer 134, it is preferable to perform a process to planarize the surface. Planarizing the surfaces of the insulating layer 132, electrodes 136a, 136b, and 136c, and gate electrode 136d in a manner that allows for the advantageous formation of electrodes, wires, insulating layers, semiconductor layers, and the like in subsequent steps. Next, a gate insulating layer 138 is formed to cover the insulating layer 132, electrodes 136a, 136b, and 136c, and gate electrode 136d (see Figure 4D). The gate insulating layer 138 can be formed by CVD, sputtering, or similar methods. Silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, or similar materials are preferred for forming the gate insulating layer 138. Note that the gate insulating layer 138 can have a monolayer or layered structure. For example, a gate insulating layer 138 made of silicon oxynitride can be formed by plasma CVD using silane (SiH4), oxygen, and nitrogen as source gases. There is no particular limitation on the thickness of the gate insulating layer 138; the gate insulating layer 138 can have a thickness of, for example, from 10 nm to 50 nm (inclusive). In the case of a layered structure, for example, the gate insulating layer 138 is preferably a stack of a first gate insulating layer having a thickness of 50 nm to 200 nm (inclusive) and a second gate insulating layer having a thickness of 5 nm to 300 nm (inclusive) above the first gate insulating layer. It is noted that oxide semiconductors that have become essentially or substantially pure through the removal of impurities (highly purified oxide semiconductors) are quite susceptible to the effects of interface energy levels and interface charges; therefore, when such oxide semiconductors are used as oxide semiconductor layers, the interface with the gate insulating layer is important. In other words, the gate insulating layer 138 that contacts the highly purified oxide semiconductor layer must be of high quality. For example, the gate insulating layer 138 is preferably formed using a high-density plasma CVD method with microwaves (2.45 GHz) because the gate insulating layer 138 can be dense and has high withstand voltage and high quality. When the highly purified oxide semiconductor layer and the high-quality gate insulating layer are in contact, the interface energy level can be reduced and the interface characteristics are advantageous. Needless to say, even when using a highly purified oxide semiconductor layer, another method such as sputtering or plasma CVD can be employed, as long as a high-quality insulating layer can be formed as the gate insulating layer. Furthermore, the quality and characteristics of the interface between the insulating layer and the oxide semiconductor layer can be improved by heat treatment performed after the insulating layer is formed. In any case, the gate insulating layer 138 is formed with advantageous film quality as the gate insulating layer 138 and can reduce the interfacial energy level density with the oxide semiconductor layer to form a favorable interface. If impurities are included in an oxide semiconductor, stresses such as high electric fields or high temperatures can break the bonds between the impurities and the main components of the oxide semiconductor, creating dangling bonds that cause a shift in the threshold voltage (Vth). By minimizing impurities (especially hydrogen and water) in the oxide semiconductor and making the interface characteristics between the oxide semiconductor and the gate insulating layer advantageous, as described above, a transistor that is stable under stresses such as high electric fields and high temperatures can be obtained. Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and processed by a method such as etching using a mask to form an island-shaped oxide semiconductor layer 140 (see Figure 4E). As the oxide semiconductor layer, In-Ga-Zn-O based oxide semiconductor layers, In-Sn-Zn-O based oxide semiconductor layers, In-Al-Zn-O based oxide semiconductor layers, Sn-Ga-Zn-O based oxide semiconductor layers, Al-Ga-Zn-O based oxide semiconductor layers, Sn-Al-Zn-O based oxide semiconductor layers, In-Zn-O based oxide semiconductor layers, Sn-Zn-O based oxide semiconductor layers, Al-Zn-O based oxide semiconductor layers, In-O based oxide semiconductor layers, Sn-O based oxide semiconductor layers, or Zn-O based oxide semiconductor layers are preferred. These oxide semiconductors are particularly preferred to exist in an amorphous state. In this embodiment, as the oxide semiconductor layer, an amorphous oxide semiconductor layer is formed by a sputtering method using a target material for depositing In-Ga-Zn-O based oxide semiconductors. Note that since the crystallization of the amorphous oxide semiconductor layer can be suppressed by adding silicon to the amorphous oxide semiconductor layer, a target containing, for example, 2 wt% to 10 wt% (inclusive) SiO2 can be used to form the oxide semiconductor layer. As a target material for forming an oxide semiconductor layer by sputtering, an oxide semiconductor deposition target containing zinc oxide as its main component can be used, for example. Alternatively, a target material for depositing oxide semiconductors containing, for example, In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO in a molar ratio of 1:1:1 [molar ratio]) can be used. Furthermore, a target material for depositing oxide semiconductors containing, for example, In, Ga, and Zn (In₂O₃:Ga₂O₃:ZnO in a molar ratio of 1:1:2 [molar ratio] or In₂O₃:Ga₂O₃:ZnO in a molar ratio of 1:1:4 [molar ratio]) can be used. The fill rate of the target material for depositing oxide semiconductors is 90% to 100% (inclusive), preferably greater than or equal to 95% (e.g., 99.9%). A dense oxide semiconductor layer is formed using a target material for depositing oxide semiconductors with a high fill rate. The surrounding environment for forming the oxide semiconductor layer is preferably a rare gas (typically argon) environment, an oxygen environment, or a mixed environment containing a rare gas (typically argon) and oxygen. Specifically, it is preferable to use a high-purity gas, for example, from which impurities such as hydrogen, water, and compounds having hydroxyl groups or hydrides are removed at a concentration of several ppm (preferably several ppb). In forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained under reduced pressure, and the substrate temperature is set to 100°C to 600°C (inclusive), preferably 200°C to 400°C (inclusive). The oxide semiconductor layer is formed while the substrate is heated, thereby reducing the impurity concentration of the oxide semiconductor layer. Furthermore, damage to the oxide semiconductor layer caused by sputtering is reduced. Next, sputtering gas, from which hydrogen and water have been removed, is introduced into the processing chamber where residual moisture has been removed, and the oxide semiconductor layer is formed using a metal oxide as a target. A trapping vacuum pump is preferably used to remove residual moisture from the processing chamber. For example, a cryogenic pump, an ion pump, or a titanium sublimation pump can be used. The evacuation unit can be a turbopump equipped with a cold trap. In the deposition chamber evacuated by the cryogenic pump, compounds containing hydrogen atoms, such as water (H2O), are removed, in addition to compounds containing carbon and hydrogen atoms, thereby reducing the impurity concentration of the oxide semiconductor layer formed in the deposition chamber. The oxide semiconductor layer can be formed under the following conditions: a distance of 100 nm between the substrate and the target; a pressure of 0.6 Pa; a direct current (DC) power supply of 0.5 kW; and an ambient oxygen environment (oxygen flow rate of 100%). It is noted that a pulsed DC power supply is preferred because it reduces powder material (also known as particles or dust) formed during thin film deposition and allows for a smaller thickness distribution. The thickness of the oxide semiconductor layer is from 2 nm to 200 nm (inclusive), preferably from 5 nm to 30 nm (inclusive). It is noted that the appropriate thickness varies depending on the oxide semiconductor material, and the thickness should be appropriately set according to the material used. Note that before forming the oxide semiconductor layer by sputtering, dust on the surface of the gate insulating layer 138 is removed by reverse sputtering, in which argon gas is introduced and plasma is generated. Here, compared to normal sputtering of the ion-bombarded sputtering target, reverse sputtering is a method of modifying the surface by bombarding the surface to be treated with ions. One example of a method of bombarding the surface to be treated with ions is a method in which a high-frequency voltage is supplied to the surface in an argon-environment to generate plasma near the substrate. Note that instead of an argon-environment, a nitrogen-environment, a helium-environment, an oxygen-environment, or the like can be used. Etching methods for oxide semiconductor layers can be either dry etching or wet etching. Needless to say, dry etching and wet etching can be combined. Etching conditions (such as etching gas or etching solution, etching time, and temperature) are appropriately set according to the material to etch the oxide semiconductor into the desired shape. An example of an etching gas used for dry etching is a gas containing chlorine (chlorine-based gases such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), or carbon tetrachloride (CCl4)). Alternatively, fluorine-based gases (fluorine-based gases such as carbon tetrafluoride (CF4), sulfur fluoride (SF4), nitrogen fluoride (NF3), or trifluoromethane (CHF3)), hydrogen bromide (HBr), oxygen (O2), or rare gases such as (He) or (Ar) can be added to any of these gases, or the like. As a dry etching method, parallel plate RIE (reactive ion etching) or ICP (inductively coupled plasma) etching can be used. In order to etch the oxide semiconductor layer to the desired shape, the etching conditions (such as the electrical force supplied to the coiled electrode, the electrical force supplied to the electrode on the substrate side, and the electrode temperature on the substrate side) are appropriately set. As an etchant for wet etching, a mixture of phosphoric acid, acetic acid, and nitric acid can be used. Alternatively, an etchant such as ITO07N (manufactured by KANTO CHEMICAL CO., INC.) can be used. Next, a first heat treatment is preferably performed on the oxide semiconductor layer. This first heat treatment may dehydrate or dehydrogenate the oxide semiconductor layer. The temperature of the first heat treatment is greater than or equal to 300°C and less than or equal to 750°C, preferably greater than or equal to 400°C and less than the strain point of the substrate. For example, the substrate is placed in an electric furnace using a resistance heating element or similar, and the oxide semiconductor layer 140 is heated at 450°C in a nitrogen-filled environment for one hour. The oxide semiconductor layer 140 is not exposed to air during the heat treatment, thus preventing the ingress of water and hydrogen. Heat treatment equipment is not limited to electric furnaces and can be any device that heats an object from a medium such as a heating gas by means of thermal radiation or heat conduction. For example, rapid thermal annealing (RTA) equipment such as gas rapid thermal annealing (GRTA) equipment or lamp rapid thermal annealing (LRTA) equipment can be used. LRTA equipment is a device that heats the object to be treated by radiation (electromagnetic waves) from light emitted by lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. GRTA equipment is a device that uses high-temperature gas to perform heat treatment. The gas used is an inert gas, such as nitrogen, or a rare gas, such as argon, that does not react with the object during heat treatment. For example, as a first heat treatment, the GRTA process can be performed as follows: The substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C for several minutes, and then removed from the inert gas. The GRTA process allows for short-duration high-temperature heat treatment. Furthermore, the GRTA process can still be used even when the temperature exceeds the strain point of the substrate because it is a short-duration heat treatment. It is noted that the first heat treatment is preferably performed in an environment containing nitrogen or a rare gas (such as helium, neon, or argon) as the main component and free from water, hydrogen, or similar substances. For example, the purity of the nitrogen or rare gas such as helium, neon, or argon introduced into the heat treatment chamber is preferably greater than or equal to 6N (99.9999%), more preferably greater than or equal to 7N (99.99999%) (that is, the impurity concentration is less than or equal to 1 ppm, preferably less than or equal to 0.1 ppm). Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may sometimes crystallize into microcrystalline or polycrystalline forms. For example, the oxide semiconductor layer may sometimes become a microcrystalline oxide semiconductor layer with a crystallinity of 90% or more, or 80% or more. Alternatively, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may become an amorphous oxide semiconductor layer without any crystalline components. In addition, oxide semiconductor layers sometimes become layers in which microcrystals (with a particle size of 1 nm to 20 nm (inclusive), typically 2 nm to 4 nm (inclusive)) are mixed in with amorphous oxide semiconductors (such as the surface of oxide semiconductor layers). The electrical properties of an oxide semiconductor layer can be altered by aligning microcrystals in the amorphous regions of the oxide semiconductor layer. For example, when an oxide semiconductor layer is formed using a target material for depositing In-Ga-Zn-O-based oxide semiconductors, the electrical properties of the oxide semiconductor can be altered by forming microcrystal portions (where the electrically anisotropic In2Ga2ZnO7 grains are aligned). In detail, for example, when the grains are configured such that the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer, the conductivity in the direction parallel to the oxide semiconductor layer and the insulation properties in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Furthermore, these microcrystalline portions have the function of suppressing impurities such as water or hydrogen from entering the oxide semiconductor layer. It is noted that an oxide semiconductor layer including microcrystalline portions can be formed by heating the oxide semiconductor layer using a GRTA process. Furthermore, an oxide semiconductor layer can be formed in a better manner by using a sputtering target in which the Zn content is less than the In or Ga content. A first heat treatment of the oxide semiconductor layer 140 can be performed on the oxide semiconductor layer before it has been processed into an island-shaped oxide semiconductor layer 140. In that case, after the first heat treatment, the substrate is removed from the heating device and a photolithography step is performed. Note that the first heat treatment may be referred to as a dehydration treatment, dehydrogenation treatment, or something similar, due to its effect on the dehydration or dehydrogenation of the oxide semiconductor layer 140. Such a dehydration or dehydrogenation treatment may be performed, for example, after forming the oxide semiconductor layer, after stacking the source and drain electrodes on the oxide semiconductor layer 140, or after forming a protective insulating layer on the source and drain electrodes. Such a dehydration or dehydrogenation treatment may be performed once or several times. Next, source / drain electrodes 142a and 142b (see Figure 4F) are formed to contact the oxide semiconductor layer 140. The source / drain electrodes 142a and 142b can be formed in one manner to form a conductive layer covering the oxide semiconductor layer 140 and then selectively etched. The conductive layer can be formed by PVD methods such as sputtering or CVD methods such as plasma CVD. The material for the conductive layer can be an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten, any alloy of these elements, or the like. Additionally, one or more materials selected from manganese, magnesium, zirconium, beryllium, or thorium can be used. Aluminum combined with one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, or scandium can be used. The conductive layer can be a single-layer structure or a layered structure comprising two or more layers. For example, the conductive layer can have a single-layer structure of silicon-containing aluminum film, a two-layer structure in which a titanium film is stacked on top of an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. Here, ultraviolet light, KrF laser light, or ArF laser light is preferably used for exposure to form a mask for etching. The channel length (L) of the transistor is determined by the distance between the lower edges of the source / drain electrodes 142a and 142b. Note that for exposures with a channel length (L) less than 25 nm, extreme ultraviolet (EUV) radiation (with wavelengths ranging from a few nanometers to hundreds of nanometers) is used to form the mask. EUV exposure offers high resolution and a large depth of focus. For these reasons, the channel length (L) of the subsequently formed transistor can range from 10 nm to 1000 nm, and the circuit can operate at higher speeds. Furthermore, the shutdown current is extremely low, preventing increased power consumption. The material and etching conditions of the conductive layer and the oxide semiconductor layer 140 are appropriately adjusted so that the oxide semiconductor layer 140 is not removed during the etching of the conductive layer. Note that in some cases, depending on the material and etching conditions, the oxide semiconductor layer 140 is partially etched during the etching step, and it therefore has trench portions (recesses). An oxide conductive layer can be formed between the oxide semiconductor layer 140 and the source / drain electrode 142a, and between the oxide semiconductor layer 140 and the source / drain electrode 142b. The oxide conductive layer and the metal layer used to form the source / drain electrodes 142a and 142b can be formed sequentially. The oxide conductive layer can serve as the source and drain regions. The provision of this type of oxide conductive layer can reduce the resistance of the source and drain regions, enabling the transistor to operate at high speeds. To reduce the number of masks used and the number of steps, an etching step can be performed using a resist mask formed with a multi-tone mask, which is an exposure mask through which light transmitted has multiple intensities. The resist mask formed using a multi-tone mask has multiple thicknesses (with a stepped shape) and can be further modified by graying; therefore, the resist mask can be used in multiple etching steps to process different shapes. That is, resist masks corresponding to at least two different patterns can be formed by using a multi-tone mask. This reduces the number of exposure masks and also reduces the number of corresponding photolithography steps, thereby simplifying the process. Note that after the above steps, it is preferable to use a gas such as N2O, N2, or Ar to perform the plasma treatment. This plasma treatment removes water or similar substances attached to the exposed surface of the oxide semiconductor layer. A mixture of oxygen and argon can be used to perform the plasma treatment. Next, a protective insulating layer 144 is formed in contact with the portion of the oxide semiconductor layer 140 that is not exposed to air (see Figure 4G). The protective insulating layer 144 can be formed by a method that prevents impurities such as water and hydrogen from mixing into the protective insulating layer 144, suitably, for example, by sputtering. The protective insulating layer 144 has a thickness of at least 1 nm. Silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like can be used to form the protective insulating layer 144. The protective insulating layer 144 can have a single-layer structure or a multilayer structure. The substrate temperature during the formation of the protective insulating layer 144 is preferably higher than or equal to room temperature and lower than or equal to 300°C. The surrounding environment for forming the protective insulating layer 144 is preferably a rare gas (typically argon) environment, an oxygen environment, or a mixed environment containing a rare gas (typically argon) and oxygen. If hydrogen is included in the protective insulating layer 144, it may enter the oxide semiconductor layer or extract oxygen from it, thereby potentially reducing the resistance of the oxide semiconductor layer on the back channel side and possibly forming parasitic channels. Therefore, it is important not to use hydrogen in forming the protective insulating layer 144 so that the oxide semiconductor layer 140 contains as little hydrogen as possible. Furthermore, it is preferable to form a protective insulating layer 144 while removing water remaining in the processing chamber, so that hydrogen, hydroxyl groups, or water are not contained in the oxide semiconductor layer 140 and the protective insulating layer 144. A trapping vacuum pump is preferably used to remove residual moisture in the processing chamber. For example, a cryogenic pump, ion pump, or titanium sublimation pump is preferred. The evacuation unit can be a turbopump with a cold trap. In the deposition chamber evacuated by the cryogenic pump, hydrogen atoms and hydrogen-containing compounds such as water (H2O) are removed; thus, the impurity concentration of the protective insulating layer 144 formed in the deposition chamber can be reduced. As the sputtering gas used to form the protective insulating layer 144, it is preferable to use a high-purity gas that has removed impurities such as hydrogen, water, compounds with hydroxyl groups, or hydrides, so that the impurity concentration is reduced to a few ppm (preferably a few ppb). Next, the second heat treatment is preferably performed in an inert gas environment or an oxygen gas environment (at 200°C to 400°C, inclusive), for example, at 250°C to 350°C, inclusive). For example, the second heat treatment is performed for one hour at 250°C in a nitrogen environment. The second heat treatment can reduce variations in the electrical properties of the transistor. In addition, heat treatment can be performed in air at 100°C to 200°C for one to 30 hours. This heat treatment can be performed at a fixed heating temperature; alternatively, the heating temperature can be repeated several times with the following variations: increasing the heating temperature from room temperature to 100°C to 200°C and then decreasing it to room temperature. This heat treatment can be performed under reduced pressure before forming the protective insulating layer. Reduced pressure can shorten the heat treatment time. This heat treatment under reduced pressure can be performed instead of a second heat treatment, or it can be performed before or after a second heat treatment. Next, an interlayer insulating layer 146 (see Figure 5A) is formed on top of the protective insulating layer 144. The interlayer insulating layer 146 can be formed by PVD, CVD, or similar methods. Inorganic insulating materials, including silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide, can be used to form the interlayer insulating layer 146. After forming the interlayer insulating layer 146, the surface of the interlayer insulating layer 146 is preferably planarized by CMP, etching, or similar methods. Next, openings leading to electrodes 136a, 136b, and 136c and source / drain electrodes 142a and 142b are formed in the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. Then, a conductive layer 148 is formed to embed into the openings (see Figure 5B). The openings can be formed by etching methods such as masking. The mask can be formed by exposure methods such as using a photomask. Wet etching or dry etching can be used as etching; dry etching is preferred for microfabrication. The conductive layer 148 can be formed by thin film formation methods such as PVD or CVD methods. The conductive layer 148 can be formed, for example, using conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or any alloys or compounds of these materials (such as nitrides). Specifically, a method can be employed, for example, in which a thin titanium film is formed in the region including the opening by PVD and a thin titanium nitride film is formed by CVD, and then a tungsten film is formed to embed within the opening. Here, the titanium film formed by PVD has the function of reducing the oxide film formed on the surface of the lower electrode (here, electrodes 136a, 136b, and 136c and source / drain electrodes 142a and 142b) to reduce the contact resistance with the lower electrode. The titanium nitride film formed after the titanium film formation has a barrier function to prevent the diffusion of conductive materials. After forming the titanium, titanium nitride, or similar barrier film, a copper film can be formed by plating. After the conductive layer 148 is formed, portions of the conductive layer 148 are removed by etching, CMP, or the like to expose the interlayer insulating layer 146 and form electrodes 150a, 150b, 150c, 150d, and 150e (see Figure 5C). Note that when forming electrodes 150a, 150b, 150c, 150d, and 150e by removing portions of the conductive layer 148, it is preferable to perform a process to planarize the surfaces. Planarizing the surfaces of the interlayer insulating layer 146 and electrodes 150a, 150b, 150c, 150d, and 150e in a manner that allows for the advantageous formation of electrodes, wires, insulating layers, and the like in subsequent steps. Next, an insulating layer 152 is formed, and openings leading to electrodes 150a, 150b, 150c, 150d, and 150e are formed in the insulating layer 152. After forming a conductive layer to embed into the openings, portions of the conductive layer are removed by etching, CMP, or the like. Thus, the insulating layer 152 is exposed and electrodes 154a, 154b, 154c, and 154d are formed (see Figure 5D). This step is similar to the steps for forming electrodes 150a and the like; therefore, a detailed description will not be repeated. In the case where the transistor 162 is formed by the above method, the hydrogen concentration of the oxide semiconductor layer 140 is 5 × 10¹⁹ atoms / cm³ or less, and the turn-off current of the transistor 162 is 100 oz A / μm or less. A transistor 162 with excellent characteristics can be obtained by using a highly purified oxide semiconductor layer 140 with sufficiently reduced hydrogen concentration as described above. Furthermore, a semiconductor device with excellent characteristics can be manufactured, comprising a transistor 160 formed using a non-oxide semiconductor material in the lower part and a transistor 162 formed using an oxide semiconductor material in the upper part. It is noteworthy that silicon carbide (such as 4H-SiC) is proposed as a semiconductor material, comparable to oxide semiconductors. Both oxide semiconductors and 4H-SiC share several common characteristics, one of which is carrier density. The intrinsic carrier density in oxide semiconductors is estimated at approximately 10⁻⁷ / cm³ at room temperature. This intrinsic carrier density is extremely small, similar to that in 4H-SiC, at 6.7 × 10⁻¹¹ / cm³. When comparing the intrinsic carrier density of oxide semiconductors with that of silicon (approximately 1.4 × 10¹⁰ / cm³), it becomes clear that the intrinsic carrier density of oxide semiconductors is significantly lower. Furthermore, the band gap of oxide semiconductors is 3.0 eV to 3.5 eV, while that of 4H-SiC is 3.26 eV. Therefore, oxide semiconductors and silicon carbide are similar, as both are wide-bandgap semiconductors. On the other hand, a key difference between oxide semiconductors and silicon carbide lies in their process temperature. Silicon carbide typically requires heat treatment at 1500°C to 2000°C, making it difficult to stack silicon carbide with semiconductor devices using non-silicon carbide semiconductor materials. This is because the semiconductor substrate, semiconductor devices, or similar components would be damaged at such high temperatures. Meanwhile, oxide semiconductors can be formed through heat treatment at 300°C to 500°C (glass transition temperature or lower, up to approximately 700°C); therefore, non-oxide semiconductor materials can be used to form integrated circuits and subsequently semiconductor devices including oxide semiconductors. Furthermore, oxide semiconductors are more advantageous compared to silicon carbide because they can use low-heat-resistant substrates such as glass substrates. In addition, oxide semiconductors do not require high-temperature heat treatment, thus significantly reducing energy costs compared to silicon carbide, which is another advantage. While much research has been conducted on the properties of oxide semiconductors, this has not included the idea of ​​significantly reducing localized levels within the band gap. According to one embodiment of the disclosed invention, a highly purified oxide semiconductor is formed by removing water or hydrogen, which could be a cause of localized level formation. This is based on the idea of ​​significantly reducing localized levels within the band gap. Such highly purified oxide semiconductors allow for the manufacture of significantly superior industrial products. Furthermore, highly purified (type i) oxide semiconductors can also be formed by reducing the localization energy levels caused by oxygen vacancies through dangling bonds generated by supplying oxygen to oxygen vacancies. For example, an oxide film containing excessive oxygen can be formed in contact with the channel formation region, and then oxygen can be supplied from the oxide film to the channel formation region to reduce the localization energy levels caused by oxygen vacancies. Defects in oxide semiconductors are believed to be caused by shallow energy levels below the conduction band (due to excess hydrogen), deep energy levels (due to lack of oxygen), or similar factors. Complete removal of hydrogen and a sufficient supply of oxygen are performed to eliminate these defects. (Including the conduction mechanism of oxide semiconductor transistors) Next, the conduction mechanism of transistors, including oxide semiconductors, will be explained with reference to Figures 11, 12A and 12B, 13A and 13B, and 14. Note that for simplicity, the following explanation is based on ideal assumptions. Figure 11 is a cross-sectional view of an inverted-staggered transistor including oxide semiconductor. The oxide semiconductor layer (OS) is disposed above the gate electrode layer (GE1), with a gate insulating layer (GI) in between, and the source electrode (S) and drain electrode (D) are disposed above the oxide semiconductor layer. Figures 12A and 12B are schematic diagrams of the band structure along A-A' in Figure 11. Figure 12A illustrates the case where no voltage is applied to the gate electrode layer (VG=0), and no voltage or the same voltage is applied to the source and drain electrodes (VD=VS=0 or VD=VS). Figure 12B illustrates the case where a positive voltage (VD>0) is applied to the drain electrode and no voltage is applied to the gate electrode layer (VG=0) (shown as dashed lines), and the case where a positive voltage (VD>0) is applied to the drain electrode and a positive voltage +VG (VG>0) is applied to the gate electrode layer (shown as solid lines). In the case where no voltage is applied to the gate electrode layer, due to the high potential barrier, no carrier (electron) is injected from the source electrode to the oxide semiconductor side, so no current flows, which means the off state. On the other hand, when a positive voltage is applied to the gate electrode layer, the potential barrier decreases and therefore current flows, which means the on state. Figures 13A and 13B are schematic diagrams of the band structure along B-B' in Figure 11. Figure 13A illustrates the case where a positive voltage (VG>0) is applied to the gate electrode layer (GE1), that is, the on-state where carriers (electrons) flow between the source and drain electrodes. Figure 13B illustrates the case where a negative voltage -VG (VG<0) is applied to the gate (GE1), that is, the off-state (where minority carriers do not flow). Figure 14 illustrates the relationship between the vacuum energy level, the working function (φM) of a metal, and the electron affinity (χ) of an oxide semiconductor. Metal degradation occurs, and the Fermi level exists in the conduction band. Meanwhile, conventional oxide semiconductors are n-type, and the Fermi level (Ef) is some distance from the intrinsic Fermi level (Ei) at the center of the band gap and is close to the conduction band. It is known that hydrogen moieties in oxide semiconductors become donors and are one of the causes of n-type oxide semiconductors. Furthermore, oxygen vacancies are known to be one of the causes of n-type oxide semiconductors. In contrast, the oxide semiconductor according to one embodiment of the disclosed invention is a type-i or near-type oxide semiconductor that is made inherently (i-type) by highly purifying and removing hydrogen that would result in an n-type oxide semiconductor, thereby minimizing the inclusion of elements (impurity elements) that are the main components of an oxide semiconductor and eliminating oxygen vacancies. That is, a feature of one embodiment of the invention is that the oxide semiconductor is made into or near-highly purified type-i (inherent) semiconductors not by adding impurity elements but by eliminating impurities (such as hydrogen, water, and oxygen vacancies) as much as possible. Therefore, the Fermi level (Ef) is comparable to the inherent Fermi level (Ei). The band gap (Eg) and electron affinity (χ) of oxide semiconductors are reportedly 3.15 eV and 4.3 eV, respectively. The working function of titanium (Ti) contained in the source or drain electrode is essentially equal to the electron affinity (χ) of the oxide semiconductor. In this case, no Schottky barrier against electrons is formed at the interface between the metal and the oxide semiconductor. In the case where the working function (φM) of the metal is equal to the electron affinity (χ) of the oxide semiconductor, the band diagram shown in Figure 12A (schematic diagram) can be obtained when the metal and the oxide semiconductor are in contact. In Figure 12B, the black dots (˙) represent electrons. When a positive potential is supplied to the drain electrode, electrons cross the barrier (h) and are injected into the oxide semiconductor, flowing to the drain electrode. The height of the barrier (h) depends on the gate voltage (VG). When a positive drain voltage is supplied to the drain electrode, the height of the barrier (h) is lower than the height of the barrier in Figure 12A where no voltage is applied, i.e., half the band gap (Eg). At that time, as shown in Figure 13A, electrons travel near the interface between the gate insulating layer and the highly purified oxide semiconductor (the oxide semiconductor being the stable bottom in terms of energy). As shown in Figure 13B, in the case where a negative potential is supplied to the gate electrode (GE1), the current value is as close to 0 as possible since there are virtually no holes for minority carriers. For example, the shut-off current at room temperature (25°C) is 10 zA / μm (1×10⁻²⁰ / μm) or less, or 1 zA / μm (1×10⁻²¹A / μm) or less. Therefore, a transistor with a subcritical swing (S value) of 0.1 V / dec can be obtained. In this way, oxide semiconductors are highly purified to include as few impurities as possible of the main components of non-oxide semiconductors, thereby making the operation of the transistors advantageous. <Modification Example> Figures 6, 7A and 7B, 8A and 8B, and 9A and 9B illustrate modified examples of the structure of the semiconductor device. Below, we will describe semiconductor devices in each of these examples where the transistor 162 has a different structure than described above. That is, the structure of the transistor 160 is the same as described above. Figure 6 illustrates an example of a semiconductor device including a transistor, wherein the gate electrode 136d is placed below the oxide semiconductor layer 140 and the source / drain electrodes 142a and 142b are in contact with the bottom surface of the oxide semiconductor layer 140. Note that the planar structure can be appropriately modified to correspond to the cross-section; only the cross-section is shown here. A major difference between the structure in Figure 6 and the structure in Figure 2A lies in the location where the oxide semiconductor layer 140 connects to the source / drain electrodes 142a and 142b. Specifically, in the structure of Figure 2A, the top surface of the oxide semiconductor layer 140 contacts the source / drain electrodes 142a and 142b, while in the structure of Figure 6, the bottom surface of the oxide semiconductor layer 140 contacts the source / drain electrodes 142a and 142b. Furthermore, this difference in contact location results in different configurations of other electrodes, insulating layers, and the like. The details of each component are the same as in Figures 2A and 2B. In detail, the semiconductor device in Figure 6 includes a gate electrode 136d disposed above the interlayer insulating layer 128, a gate insulating layer 138 disposed above the gate electrode 136d, source / drain electrodes 142a and 142b disposed above the gate insulating layer 138, and an oxide semiconductor layer 140 in contact with the top surfaces of the source / drain electrodes 142a and 142b. Here, a gate electrode 136d is provided to be embedded in an insulating layer 132 formed above an interlayer insulating layer 128. For example, the gate electrode 136d forms electrodes 136a, 136b, and 136c that are in contact with source / drain electrodes 130a, 130b, and 130c, respectively. A protective insulating layer 144 is disposed above the transistor 162 to partially contact the oxide semiconductor layer 140. An interlayer insulating layer 146 is disposed above the protective insulating layer 144. Openings leading to source / drain electrodes 142a and 142b are formed in the protective insulating layer 144 and the interlayer insulating layer 146. Electrodes 150d and 150e are formed, respectively, to contact the source / drain electrodes 142a and 142b through individual openings. Electrodes 150d and 150e, for example, form electrodes 150a, 150b, and 150c, respectively, to contact electrodes 136a, 136b, and 136c through openings in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. An insulating layer 152 is disposed above the interlayer insulating layer 146. Electrodes 154a, 154b, 154c, and 154d are disposed and embedded within the insulating layer 152. Electrode 154a is in contact with electrode 150a. Electrode 154b is in contact with electrode 150b. Electrode 154c is in contact with electrodes 150c and 150d. Electrode 154d is in contact with electrode 150e. Figures 7A and 7B illustrate an example of a semiconductor device structure, wherein a gate electrode 136d is disposed above an oxide semiconductor layer 140. Figure 7A illustrates an example of a structure in which source / drain electrodes 142a and 142b are in contact with the bottom surface of the oxide semiconductor layer 140. Figure 7B illustrates an example of a structure in which source / drain electrodes 142a and 142b are in contact with the top surface of the oxide semiconductor layer 140. A major difference between the structures in Figures 7A and 7B and those in Figures 2A and 6 is that the gate electrode 136d is disposed above the oxide semiconductor layer 140. Furthermore, a major difference between the structures in Figure 7A and Figure 7B is that the source / drain electrodes 142a and 142b are in contact with the bottom or top surface of the oxide semiconductor layer 140. These differences also result in different configurations of other electrodes, insulating layers, and the like. The details of each component are the same as those in Figures 2A and 2B and the like. In detail, the semiconductor device shown in Figure 7A includes source / drain electrodes 142a and 142b disposed above the interlayer insulating layer 128, an oxide semiconductor layer 140 in contact with the top surfaces of the source / drain electrodes 142a and 142b, a gate insulating layer 138 disposed above the oxide semiconductor layer 140, and a gate electrode 136d in a region above the gate insulating layer 138 that overlaps with the oxide semiconductor layer 140. The semiconductor device shown in Figure 7B includes source / drain electrodes 142a and 142b disposed above an interlayer insulating layer 128, source / drain electrodes 142a and 142b disposed in contact with the top surface of an oxide semiconductor layer 140, a gate insulating layer 138 disposed above the oxide semiconductor layer 140 and the source / drain electrodes 142a and 142b, and a gate electrode 136d in a region above the gate insulating layer 138 that overlaps with the oxide semiconductor layer 140. Note that in the structures shown in Figures 7A and 7B, in some cases a component (such as electrode 150a or electrode 154a) can be omitted from the structures shown in Figures 2A and 2B. In such cases, secondary effects such as process simplification can be achieved. Needless to say, unnecessary components can be omitted in Figures 2A and 2B and the like. Figures 8A and 8B each illustrate an example where the component is relatively large and the gate electrode 136d is disposed beneath the oxide semiconductor layer 140. In this case, the need for surface and overlay planarization is relatively mild, thus eliminating the need to form wires, electrodes, etc., to be embedded in the insulating layer. For example, the gate electrode 136d and the like can be formed by patterning after the conductive layer is formed. Note that although not shown here, the transistor 160 can be formed in a similar manner. A major difference between the structure in Figure 8A and the structure in Figure 8B is that the source / drain electrodes 142a and 142b are in contact with the bottom or top surface of the oxide semiconductor layer 140. Furthermore, these differences result in different configurations of other electrodes, insulating layers, and the like. The details of each component are the same as those in Figures 2A and 2B, and the like. In detail, the semiconductor device in Figure 8A includes a gate electrode 136d disposed above an interlayer insulating layer 128, a gate insulating layer 138 disposed above the gate electrode 136d, source / drain electrodes 142a and 142b disposed above the gate insulating layer 138, and an oxide semiconductor layer 140 in contact with the top surfaces of the source / drain electrodes 142a and 142b. The semiconductor device in Figure 8B includes a gate electrode 136d disposed above an interlayer insulating layer 128, a gate insulating layer 138 disposed above the gate electrode 136d, an oxide semiconductor layer 140 disposed above the gate insulating layer 138 in a region overlapping with the gate electrode 136d, and source / drain electrodes 142a and 142b disposed in contact with the top surface of the oxide semiconductor layer 140. Note that in the structures shown in Figures 8A and 8B, in some cases a component can be omitted from the structures shown in Figures 2A and 2B, or similar. Similarly, in such cases, secondary effects such as process simplification can be achieved. Figures 9A and 9B each illustrate an example where the component is relatively large and the gate electrode 136d is disposed above the oxide semiconductor layer 140. Similarly, in this case, the need for surface and overlay planarization is relatively mild, thus eliminating the need to form wires, electrodes, etc., to be embedded in the insulating layer. For example, the gate electrode 136d and the like can be formed by patterning after the conductive layer is formed. Note that although not shown here, the transistor 160 can be formed in a similar manner. A major difference between the structure in Figure 9A and the structure in Figure 9B is that the source / drain electrodes 142a and 142b are in contact with the bottom or top surface of the oxide semiconductor layer 140. Furthermore, these differences result in different configurations of other electrodes, insulating layers, and the like. The details of each component are the same as those in Figures 2A and 2B, and the like. In detail, the semiconductor device in Figure 9A includes source / drain electrodes 142a and 142b disposed above the interlayer insulating layer 128, an oxide semiconductor layer 140 in contact with the top surfaces of the source / drain electrodes 142a and 142b, a gate insulating layer 138 disposed above the source / drain electrodes 142a and 142b and the oxide semiconductor layer 140, and a gate electrode 136d disposed above the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140. The semiconductor device in Figure 9B includes an oxide semiconductor layer 140 disposed above an interlayer insulating layer 128, source / drain electrodes 142a and 142b disposed in contact with the top surface of the oxide semiconductor layer 140, a gate insulating layer 138 disposed above the source / drain electrodes 142a and 142b, and a gate electrode 136d disposed above the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140. Note that in the same structures shown in Figures 9A and 9B, in some cases a component can be omitted from the structures shown in Figures 2A and 2B, or similar. In such cases, secondary effects such as process simplification can be achieved. As described above, a semiconductor device with a novel structure can be implemented according to one embodiment of the invention disclosed herein. In this embodiment, an example is illustrated where each semiconductor device is formed by stacking transistors 160 and 162; however, the structure of the semiconductor device is not limited to this structure. Furthermore, this embodiment shows an example where the channel length direction of each transistor 160 is perpendicular to that of transistor 162; however, the positional relationship between transistors 160 and 162 is not limited to this example. Additionally, transistors 160 and 162 can be arranged to overlap each other. In this embodiment, a semiconductor device with a minimum storage cell (bit) is described for simplicity; however, the structure of the semiconductor device is not limited to this. More advanced semiconductor devices can be formed by appropriately connecting multiple semiconductor devices. For example, NAND or NOR type semiconductor devices can be formed by using multiple of the above-described semiconductor devices. The wiring configuration is not limited to that in Figure 1 and can be appropriately modified. The semiconductor device according to this embodiment can store data for an extremely long time because the transistor 162 has a low shutdown current. That is, no update operation required in DRAM and the like is needed, thus suppressing power consumption. Furthermore, the semiconductor device according to this embodiment can be used as a substantially non-electrically dependent semiconductor device. Since data writing and other operations are performed using the switching operation of transistor 162, high voltage is not required and component degradation is negligible. Furthermore, writing and erasing data based on the transistor's on / off state easily enables high-speed operation. Additionally, it is advantageous to eliminate the need for data erasure operations, as data can be directly rewritten by controlling the potential input to the transistor, which is necessary in block flash memory and similar applications. Since transistors containing non-oxide semiconductor materials can operate at a faster speed than transistors containing oxide semiconductor materials, stored data can be read at high speed using such transistors. The structures and methods described in this embodiment may be appropriately combined with any structures and methods described in other embodiments. (Example 2) In this embodiment, the structure and method of manufacturing a semiconductor device according to another embodiment of the disclosed invention will be described with reference to Figures 15A and 15B. Figure 15A illustrates an example of a circuit configuration for a semiconductor device. The difference between Figure 15A and Figure 1 is the inclusion of capacitor 164. Specifically, in Figure 15A, one of the source and drain electrodes of transistor 162, one of the electrodes of capacitor 164, and the gate electrode of transistor 160 are electrically connected. A first line (also called the source line BL) is electrically connected to the source electrode of transistor 160, and a second line (also called the bit line BL) is electrically connected to the drain electrode of transistor 160. A third line (also called the first signal line S1) is electrically connected to the other of the source and drain electrodes of transistor 162, and a fourth line (also called the second signal line S2) is electrically connected to the gate electrode of transistor 162. A fifth line (also called the word line WL) is electrically connected to the other electrode of transistor 164. Note that in each of Figures 15A and 15B, "OS" is written next to a transistor to indicate that it includes an oxide semiconductor transistor. Here, the aforementioned transistor, including an oxide semiconductor, is used as transistor 162. Transistors including oxide semiconductors have a significantly low turn-off current characteristic. Therefore, when transistor 162 is off, the potential of the gate electrode of transistor 160 can be maintained for a very long time. The arrangement of capacitor 164 facilitates the retention of charge supplied to the gate electrode of transistor 160 and the retrieval of stored data. It should be noted that there are no particular restrictions on transistor 160. In order to increase the speed of data reading, it is preferable to use transistors with high switching rates, such as transistors formed of single-crystal silicon. The semiconductor device in Figure 15A utilizes the property of maintaining the potential of the gate electrode of transistor 160 to write, store, and read data as follows. The instruction manual describes the writing and storage of data. First, the potential of the fourth line is set to the potential of the transistor 162 to turn it on. Accordingly, the gate electrode of the transistor 160 and the capacitor 164 of the third line are supplied. That is, a predetermined charge is provided to the gate electrode of the transistor 160 (writing). Here, one of two different potentials (hereafter referred to as charge QL for supplying the low potential and charge QH for supplying the high potential) is provided to the gate electrode of the transistor 160. Note that three or more different potentials can be supplied to improve the storage capacitor. Then, the potential of the fourth line is set to the potential of the transistor 162 to turn it off. Therefore, the charge supplied to the gate electrode of the transistor 160 is maintained (storage). Because the turn-off current of transistor 162 is significantly small, the charge on the gate electrode of transistor 160 can be maintained for a long time. Next, the data reading operation will be explained. By simultaneously supplying a predetermined potential (constant potential) to the first line and an appropriate potential (read potential) to the fifth line, the potential of the second line varies depending on the amount of charge held in the gate electrode of the transistor 160. This is because, generally, when the transistor 160 is an n-channel transistor, the apparent threshold voltage Vth_H in the case where QH is supplied to the gate electrode of the transistor 160 is lower than the apparent threshold voltage Vth_L in the case where QL is supplied to the gate electrode of the transistor 160. Here, the apparent threshold voltage refers to the potential of the fifth line, which is required to turn on the transistor 160. Therefore, by setting the potential of the fifth line to a potential V0 between Vth_H and Vth_L, the charge supplied to the gate electrode of the transistor 160 can be determined. For example, in the case where QH is supplied during writing, when the potential of the fifth line is set to V0 (>Vth_H), the transistor 160 is turned on. In the case where QL is provided during writing, the transistor 160 remains in the off state even when the potential of the fifth line is set to V0 (>Vth_L). Therefore, the stored data can be read by the potential of the second line. Note that in the case where memory cells are arranged in an array for use, only the data of the desired memory cell needs to be read. Therefore, in the case where data of a predetermined memory cell is read and data of other memory cells are not read, a potential (which allows transistor 160 to be turned off regardless of the gate electrode state) can be applied, that is, a potential below Vth_H up to the fifth line of the memory cell whose data is not read. Alternatively, a potential (which allows transistor 160 to be turned on regardless of the gate electrode state) can be applied, that is, a potential above Vth_L up to the fifth line. Next, the data rewriting process will be explained. Data rewriting is performed similarly to data writing or storage. That is, the potential of the fourth line is set to a potential that allows transistor 162 to be turned on, thereby turning on transistor 162. Accordingly, the potential of the third line (the potential for the new data) is supplied to the gate electrode of transistor 160 and capacitor 164. Then, the potential of the fourth line is set to a potential that allows transistor 162 to be turned off, thereby turning off transistor 162. In this way, a potential for the new data is provided to the gate electrode of transistor 160. Therefore, in the semiconductor device according to the disclosed invention, data can be directly rewritten by rewriting new data. Thus, the high voltage required in flash memory or similar devices to draw charge from the floating gate is eliminated, thereby suppressing the reduction in operating speed due to the erase operation. In other words, high-speed operation of the semiconductor device can be achieved. Note that the source and drain electrodes of transistor 162 are electrically connected to the gate electrode of transistor 160, thereby achieving a similar effect to the floating gate of a floating gate transistor used in non-electrically dependent memory devices. Therefore, the portion of transistor 162 whose source and drain electrodes are electrically connected to the gate electrode of transistor 160 is referred to in some cases as the floating gate portion FG. When transistor 162 is off, the floating gate portion FG can be considered embedded in an insulator and thus retains charge within it. The turn-off current of transistor 162, including oxide semiconductor, is less than or equal to one ten-thousandth of the turn-off current of transistor including silicon semiconductor; therefore, the charge loss accumulated in the floating gate portion FG due to leakage current of transistor 162 is negligible. That is, by means of transistor 162 including oxide semiconductor, a non-electrically dependent memory device capable of storing data without power supply can be realized. For example, when the turn-off current of transistor 162 is 10 zA (1 zA (zeptoampere) is 1 × 10⁻²¹ A) or less at room temperature (25°C) and the capacitance of capacitor 164 is close to 10 fF, data can be stored for 10⁴ seconds or longer. Needless to say, the storage time depends on the characteristics of the transistor and the capacitance value. Furthermore, in that case, there is no issue of gate insulation film (tunnel insulation film) degradation, which is present in conventional floating-gate transistors. That is, the degradation of the gate insulation film due to injected electrons to the floating gate is negligible, which has traditionally been considered a problem. This means that, in principle, there is no limit to the number of write cycles. Moreover, the high voltages required for writing or erasing, as in conventional floating-gate transistors, are not needed. The transistor-like components in the semiconductor device shown in Figure 15A can be considered as consisting of resistors and capacitors as shown in Figure 15B. That is, in Figure 15B, transistor 160 and capacitor 164 are each considered to include a resistor and a capacitor, respectively. R1 and C1 indicate the resistance and capacitance values ​​of capacitor 164, respectively. The resistance value R1 corresponds to the resistance value of the insulating layer included in capacitor 164. R2 and C2 indicate the resistance and capacitance values ​​of transistor 160, respectively. The resistance value R2 corresponds to the resistance value of the gate insulating layer when transistor 160 is turned on. The capacitance value C2 corresponds to the so-called gate capacitance (the capacitance formed between the gate electrode and the source electrode or drain electrode, or the capacitance formed between the gate electrode and the channel formation region). The electron retention period (also known as the data storage period) is mainly determined by the turn-off current of transistor 162 under the condition that the gate leakage current of transistor 162 is small enough and R1≧ROS and R2≧ROS are satisfied. When transistor 162 is turned off, the resistance value (also known as the effective resistance) between the source electrode and the drain electrode is ROS. On the other hand, when these conditions are not met, even if the current of transistor 162 is small enough, it is still difficult to maintain the hold-up period sufficiently. This is because the leakage current of the turn-off current of non-transistor 162 (such as the leakage current generated between the source electrode and the gate electrode) is large. Therefore, the semiconductor device disclosed in this embodiment can be said to advantageously satisfy the above-mentioned relationships. It is advantageous to satisfy C1 ≥ C2. If C1 is large, then when the potential of the floating gate section FG is controlled by the fifth line (such as during reading), the change in the potential of the fifth line can be suppressed. When the above relationships are satisfied, a better semiconductor device can be achieved. Note that R1 and R2 are controlled by the gate insulating layer of transistor 160 and the insulating layer of capacitor 164. The same relationship applies to C1 and C2. Therefore, the material, thickness, and so on of the gate insulating layer can be appropriately set to satisfy the above relationships. In the semiconductor device described in this embodiment, the floating gate portion FG has similar functionality to the floating gate of a flash memory or similar floating gate transistor, but the floating gate portion FG in this embodiment has a feature that is fundamentally different from the floating gate of a flash memory or similar transistor. In the case of flash memory, since the voltage supplied to the control gate is high, it is necessary to maintain an appropriate distance between cells to prevent the potential from affecting the floating gate of adjacent cells. This is one of the obstacles to high integration in semiconductor devices. This factor is attributed to the basic principle of flash memory, in which tunneling current flows when a high electric field is supplied. Furthermore, due to the aforementioned principle of flash memory, the deterioration of the insulating film continues, resulting in a limitation on the number of rewrites (approximately 10⁴ to 10⁵ times). The semiconductor device according to the disclosed invention operates by switching transistors, including oxide semiconductors, without using the aforementioned principle of injecting charge via tunneling current. That is, unlike flash memory, it does not require a high electric field for charge injection. Therefore, there is no need to consider the effect of a high electric field from the control gate on neighboring cells, which promotes high integration. Furthermore, since no tunneling current is used to inject charge, there is no cause for memory cell degradation. In other words, the semiconductor device according to the disclosed invention has higher durability and reliability than flash memory. In addition, compared to flash memory, it is advantageous that it does not require a high electric field and large auxiliary circuits (such as boost circuits). In cases where the dielectric constant εr1 of the insulating layer included in C1 differs from the dielectric constant εr2 of the insulating layer included in C2, it is easy to satisfy C1 ≥ C2 while simultaneously satisfying 2.S2 ≥ S1 (S2 ≥ S1 is advantageous), where S1 is the area of ​​C1 and S2 is the area of ​​C2. Specifically, for example, C1 can be constructed by using a thin film formed of a high-k material such as hafnium oxide, or a stack of a thin film formed of a high-k material such as hafnium oxide and a thin film formed of an oxide semiconductor, such that εr1 can be set to 10 or more, preferably 15 or more, and silicon oxide can be used as C2, such that εr2 can be set to 3 to 4. This combination of structures allows for high integration of the semiconductor device according to the disclosed invention. Note that the above description uses an n-channel transistor. However, it goes without saying that a p-channel transistor can be used instead of an n-channel transistor. As described above, a semiconductor device according to one embodiment of the disclosed invention has a non-electrically dependent memory cell, including a write transistor (in which the leakage current (shutdown current) between the source and drain is small in the off state), a read transistor formed of a semiconductor material different from the write transistor, and a capacitor. The write transistor has a turn-off current of 100 Hz (1 × 10⁻¹⁹ A) or less; preferably 10 Hz (1 × 10⁻²⁰ A) or less at room temperature (e.g., 25 °C); and more preferably 1 Hz (1 × 10⁻²¹ A) or less at room temperature (e.g., 25 °C). In the case of conventional silicon semiconductors, it is difficult to achieve such a low turn-off current. However, in transistors obtained by processing oxide semiconductors under appropriate conditions, a low turn-off current can be achieved. Therefore, it is preferable to use a transistor comprising an oxide semiconductor as the write transistor. Furthermore, transistors including oxide semiconductors have small subcritical swing (S-value), resulting in a high switching rate even with relatively low mobility. Therefore, by using this transistor as a write transistor, the rise of the write pulse provided to the floating gate FG can be very sharp. In addition, the shutdown current is small, thus reducing the amount of charge held in the floating gate FG. In other words, by using transistors including oxide semiconductors, data rewriting can be performed at high speed. For read transistors, it is preferable to use transistors that operate at high speeds to increase the read rate. For example, it is preferable to use transistors with a switching rate of 1 nanosecond or lower as read transistors. Data is written to the memory cell by activating the write transistor to supply potential to the floating gate FG (where one of the source and drain electrodes of the write transistor, one of the capacitor electrodes, and the gate electrode of the read transistor are electrically connected), and then deactivating the write transistor to maintain a predetermined amount of charge in the floating gate FG. Here, the turn-off current of the write transistor is very small; therefore, the charge supplied to the floating gate FG can be maintained for a long time. When the turn-off current is, for example, substantially zero, there is no need for the update operations required by conventional DRAM, or the update operation frequency is significantly low (e.g., about once a month or once a year). This significantly reduces the power consumption of the semiconductor device. Furthermore, data can be directly rewritten by writing new data to the memory cell. Therefore, the erasure operation required by flash memory or similar devices is eliminated, and the reduction in operating speed due to the erasure operation is suppressed. In other words, high-speed operation of the semiconductor device can be achieved. Also, the high voltage required for writing and erasing data in conventional floating-gate transistors is eliminated; thus, the power consumption of the semiconductor device can be further reduced. The highest voltage supplied to the memory cell according to this embodiment (the difference between the highest and lowest potentials simultaneously supplied to the individual terminals of the memory cell) can be 5V or lower or 3V or lower in each memory cell in the case of writing two-stage (one-bit) data. The memory cells disposed in the semiconductor device according to the disclosed invention may include at least the write transistor and the read transistor; thus, for example, the area of ​​each memory cell can be small enough compared to SRAM which requires six transistors per memory cell. In other words, memory cells can be configured in a high density in the semiconductor device. In conventional floating-gate transistors, charge travels through the gate insulating film (tunnel insulating film) during write operations, thus making it impossible to avoid deterioration of the gate insulating film (tunnel insulating film). Conversely, in a memory cell according to an embodiment of the present invention, data is written by switching operations of the write transistor; therefore, there is no deterioration of the gate insulating film. This means that, in principle, there is no limit to the number of write cycles and rewrite durability is very high. For example, in a memory cell according to an embodiment of the present invention, even after writing data 1 × 10⁹ or more times (one hundred million or more times), the current-voltage characteristics do not deteriorate. Furthermore, in the case of writing transistors, including oxide semiconductors, as memory cells, the current-voltage characteristics do not deteriorate even at high temperatures, such as 150°C, because oxide semiconductors generally have a wide bandgap (e.g., 3.0 to 3.5 eV in the case of In-Ga-Zn-O based oxide semiconductors) and very few thermally excited carriers. By using these transistors with superior properties as write transistors for memory cells, semiconductor devices with novel features can be provided. The methods and structures described in this embodiment can be appropriately combined with any of the methods and structures described in other embodiments. (Example 3) In this embodiment, an application example of a semiconductor device according to another embodiment of the disclosed invention is illustrated with reference to Figures 16, 17A and 17B, 18A to 18C, 19, 20 and 21. Figure 16 illustrates a schematic diagram of a semiconductor device according to this embodiment. Figure 16 is an example of a circuit diagram of a semiconductor device including one of the complex semiconductor devices (hereinafter referred to as memory cell 1200) shown in Figure 1 or Figure 15A. The semiconductor device in Figure 16 includes a memory cell array (where a plurality of memory cells 1200 are arranged in a matrix), a first driver circuit 1211, a second driver circuit 1212, a third driver circuit 1213, a fourth driver circuit 1214, a plurality of lines L1 electrically connected to the first driver circuit 1211, a plurality of lines L2 electrically connected to the second driver circuit 1212, a plurality of lines L3 electrically connected to the third driver circuit 1213, and a plurality of lines L4 electrically connected to the fourth driver circuit 1214. As shown in Figure 16, lines L1, L2, L3, and L4 are electrically connected to each of the memory cells 1200. Therefore, the operation of each of the memory cells 1200 can be controlled using the first driver circuit 1211, the second driver circuit 1212, the third driver circuit 1213, and the fourth driver circuit 1214. The memory cells 1200 are arranged in a matrix, and lines L1, L2, L3, and L4 are positioned in the low or row direction of the grid pattern, thereby enabling write and read operations of the semiconductor device to be performed in each column or row of the memory cells 1200. Note that in Figure 16, one line from each of the first driver circuits 1211 to the fourth driver circuit 1214 is electrically connected to the memory cell 1200; however, the disclosed invention is not limited thereto. A plurality of lines from any or some of the driver circuits may be electrically connected to the memory cell 1200. Alternatively, a configuration may be adopted in which one or some lines from any or some of the driver circuits are not electrically connected to any or some of the memory cells 1200. In the semiconductor device shown in Figure 16, a first driver circuit 1211, a second driver circuit 1212, a third driver circuit 1213, and a fourth driver circuit 1214 are respectively provided; however, the disclosed invention is not limited thereto. Driver circuits having any or some of these functions can be used alternatively. It is noted that single-crystal semiconductor materials are advantageously used to form the driver circuits to maintain sufficient operating speed. For example, bulk silicon (so-called silicon wafers) is preferred. Next, we will describe more specific configuration examples. Figures 17A and 17B are examples of circuit diagrams for semiconductor devices, each including the complex semiconductor devices shown in Figure 15A (hereinafter also referred to as memory cells 400). Figure 17A is a circuit diagram of a so-called NAND semiconductor device in which memory cells 400 are connected in series, and Figure 17B is a circuit diagram of a so-called NOR semiconductor device in which memory cells 400 are connected in parallel. The semiconductor device in Figure 17A includes a source line SL, a bit line BL, a first signal line S1, a plurality of second signal lines S2, a plurality of digital lines WL, and a plurality of memory cells 400. In Figure 17A, one source line SL and one bit line BL are disposed in the semiconductor device; however, one embodiment of the disclosed invention is not limited thereto. A plurality of source lines SL and a plurality of bit lines BL may be disposed. In each of the memory cells 400, the gate electrode of transistor 160, one of the source and drain electrodes of transistor 162, and one of the electrodes of capacitor 164 are electrically connected to each other. A first signal line S1 is electrically connected to the other of the source and drain electrodes of transistor 162, and a second signal line S2 is electrically connected to the gate electrode of transistor 162. A word line WL is electrically connected to the other electrode of capacitor 164. Furthermore, the source electrode of the transistor 160 included in memory cell 400 is electrically connected to the drain electrode of the transistor 160 included in adjacent memory cell 400. The drain electrode of the transistor 160 included in memory cell 400 is electrically connected to the source electrode of the transistor 160 in the adjacent memory cell 400. Note that the series-connected drain electrode (located at one end) of the transistor 160 included in the memory cell 400 of the plurality of memory cells is electrically connected to bit line BL. The series-connected source electrode (located at the other end) of the transistor 160 included in the memory cell 400 of the plurality of memory cells is electrically connected to source line SL. In the semiconductor device shown in Figure 17A, write and read operations are performed in each column. The write operation is performed as follows: The potential of the turn-on transistor 162 is supplied to the second signal line S2 of the column to be written to, thereby turning on the transistor 162 in that column. Correspondingly, the potential of the first signal line S1 is supplied to the gate electrode of the transistor 160 in the designated column to provide a predetermined charge to the gate electrode. Therefore, data can be written to the memory cell of the designated column. Furthermore, the read operation is performed as follows. First, regardless of the charge supplied to the gate electrode of transistor 160, a potential for turning on transistor 160 is supplied to the word line WL of the column not to be read, thereby turning on transistor 160 of the column not to be read. Next, a potential (read potential) that determines whether transistor 160 is on or off, depending on the charge of its gate electrode, is supplied to the word line WL of the column to be read. Afterward, a constant potential is supplied to the source line SL to operate the read circuit (not shown) connected to the bit line BL. Here, multiple transistors 160 between the source line SL and the bit line BL are turned on, except for the transistor 160 of the column to be read; therefore, the conductance between the source line SL and the bit line BL is determined by the state (on or off) of the transistor 160 of the column to be read. The conductance of the transistor 160 to be read depends on the charge in its gate electrode. Therefore, the potential of bit line BL changes accordingly. By reading the potential of bit line BL using a read circuit, data can be read from the memory cells of a specified column. The semiconductor device in Figure 17B includes a complex number of source lines SL, a complex number of bit lines BL, a complex number of first signal lines S1, a complex number of second signal lines S2, a complex number line WL, and a complex number of memory cells 400. The gate electrode of transistor 160, one of the source and drain electrodes of transistor 162, and one of the electrodes of capacitor 164 are electrically connected to each other. The source line SL and the source electrode of transistor 160 are electrically connected to each other. The bit line BL and the drain electrode of transistor 160 are electrically connected to each other. The first signal line S1 and the other of the source and drain electrodes of transistor 162 are electrically connected to each other, and the second signal line S2 and the gate electrode of transistor 162 are electrically connected to each other. The word line WL and the other electrode of capacitor 164 are electrically connected to each other. In the semiconductor device shown in Figure 17B, write and read operations are performed in each column. The write operation is performed in a similar manner to the semiconductor device shown in Figure 17A. The read operation is performed as follows: First, regardless of the charge supplied to the gate electrode of transistor 160, the potential of the turn-on transistor 160 is supplied to the word line WL of the column not to be read, thus turning off the transistors 160 of the column not to be read. Next, a potential (read potential) that determines whether transistor 160 is on or off, depending on the charge of its gate electrode, is supplied to the word line WL of the column to be read. Then, a constant potential is supplied to the source line SL to operate the read circuit (not shown) connected to the bit line BL. Here, the conductance between the source line SL and the bit line BL is determined by the state (on or off) of the transistor 160 in the column to be read. That is, the potential of the bit line BL depends on the charge in the gate electrode of the transistor 160 to be read. Data can be read from memory cells in a specified column by reading the potential of bit line BL using a read circuit. Although the amount of data that can be stored in each of the memory cells 400 is one bit in the above description, the structure of the memory device in this embodiment is not limited to this. The amount of data stored in each of the memory cells 400 can be increased by providing three or more potentials to the gate electrode of the transistor 160. For example, in the case where the number of potentials supplied to the gate electrode of the transistor 160 is four, two bits of data can be stored in each of the memory cells 400. Next, examples of readout circuits that can be used in the semiconductor devices or similar devices shown in Figures 17A and 17B will be described with reference to Figures 18A to 18C. Figure 18A illustrates a schematic diagram of a readout circuit. The readout circuit includes a transistor and a sense amplifier circuit. During data reading, terminal A is connected to a bit line BL (one of the memory cells from which the data will be read is connected). Additionally, a bias potential Vbias is supplied to the gate electrode of a transistor to control the potential of terminal A. The resistance of memory cell 400 varies depending on the stored data. Specifically, when the transistor 160 of the selected memory cell 400 is turned on, the memory cell 400 has low resistance, and when the transistor 160 of the selected memory cell 400 is turned off, the memory cell 400 has high resistance. When the memory cell has high resistance, the potential at terminal A is higher than the reference potential Vref, and the sense amplifier circuit outputs a potential corresponding to the potential at terminal A. On the other hand, when the memory cell has low resistance, the potential at terminal A is lower than the reference potential Vref, and the sense amplifier circuit outputs a potential corresponding to the potential at terminal A. Therefore, by using the read circuit, data can be read from the memory cell. Note that the read circuit of this embodiment is only one of many examples. Another circuit can be used. The read circuit may further include a precharge circuit. Instead of the reference potential Vref, the reference bit line BL can be connected to the sense amplifier circuit. FIG. 18B shows a differential sense amplifier as an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout and amplifies the potential difference between Vin(+) and Vin(-). If the potential of Vin(+) is greater than the potential of Vin(-), the Vout output signal is high, and if the potential of Vin(+) is lower than the potential of Vin(-), the Vout output signal is low. In the case where the differential sense amplifier is used in the read circuit, one of Vin(+) and Vin(-) is connected to terminal A, and the reference potential Vref is supplied to the other of Vin(+) and Vin(-). FIG. 18C shows a latch sense amplifier as an example of a sense amplifier circuit. The latch sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the control signals Sp and Sn are set to signal high and signal low, respectively, and the power supply potential (Vdd) is interrupted. Then, the individual potentials V1in and V2in for comparison are supplied to V1 and V2, respectively. After that, the control signals Sp and Sn are set to signal low and signal high, respectively, and the power supply potential (Vdd) is supplied. If the potentials for comparing V1in and V2in satisfy V1in > V2in, the output from V1 is signal high and the output from V2 is signal low, and if V1in < V2in is satisfied, the output from V1 is signal low and the output from V2 is signal high. By utilizing this relationship, the difference between V1in and V2in can be amplified. In the case where the latch sense amplifier is used in the read circuit, one of V1 and V2 is connected to terminal A and the output terminal is through a switch, and the reference potential Vref is supplied to the other of V1 and V2. FIG. 19 is an example of a circuit diagram of a semiconductor device including the plurality of semiconductor devices in FIG. 15A. The semiconductor device in FIG. 19 has a memory capacity of m×n bits. The semiconductor device in Figure 19 includes a memory cell array, wherein m-word lines WL, m-second signal lines S2, n-bit lines BL, n-source lines SL, n-first signal lines S1, and complex memory cells 1100 are arranged in an m (column) × n (row) matrix (m and n are natural numbers), and peripheral circuits for a first driver circuit 1111, a second driver circuit 1112, a third driver circuit 1113, and a fourth driver circuit 1114. Here, the configuration described in any of the above embodiments (such as the configuration in Figure 15A) is applied to the memory cells 1100. That is, each of the memory cells 1100 includes a first transistor 160, a second transistor 162, and a capacitor 164. The gate electrode of the first transistor 160, one of the source and drain electrodes of the second transistor 162, and one of the electrodes of the capacitor 164 are interconnected. The source line SL is interconnected with the source electrode of the first transistor 160. The bit line BL is interconnected with the drain electrode of the first transistor 160. The first signal line S1 and the other of the source and drain electrodes of the second transistor 162 are interconnected. The second signal line S2 is interconnected with the gate electrode of the second transistor 162. The word line WL is interconnected with the other electrode of the capacitor 164. Furthermore, memory cell 1100 is connected in parallel between source line SL and bit line BL. For example, memory cell 1100 in column i and row j (i, j) (where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) is connected to source line SL(j), bit line BL(j), first signal line S1(j), word line WL(i), and second signal line S2(i). The source line SL and bit line BL are connected to the first driver circuit 1111. The first signal line S1 is connected to the second driver circuit 1112. The second signal line S2 is connected to the third driver circuit 1113. The word line WL is connected to the fourth driver circuit 1114. Note that the first driver circuit 1111, the second driver circuit 1112, the third driver circuit 1113, and the fourth driver circuit 1114 are respectively configured here; however, the disclosed invention is not limited thereto. A decoder having any or some of these functions may be used alternatively. Next, the write and read operations of the semiconductor device in Figure 19 will be explained with reference to the timing diagram in Figure 20. Although the invention disclosed is for the purpose of simply illustrating the operation of the two-column and two-row semiconductor device, it is not limited to this. Figure 20 is a diagram illustrating the operation of the semiconductor device in Figure 19. In Figure 20, S1(1) and S1(2) are the potentials of the first signal line S1; S2(1) and S2(2) are the potentials of the second signal line S2; BL(1) and BL(2) are the potentials of the bit line BL; WL(1) and WL(2) are the potentials of the word line WL; and SL(1) and SL(2) are the potentials of the source line SL. First, write data to memory cells (1,1) and (1,2) in the first column, and read data from memory cells (1,1) and (1,2) in the first column. Note that in the following description, it is assumed that the data to be written to memory cell (1,1) is "1" and the data to be written to memory cell (1,2) is "0". First, the instructions are written. During the writing period of the first column, a potential VH is supplied to the second signal line S2(1) of the first column to turn on the second transistor 162 of the first column. In addition, a potential of 0V is supplied to the second signal line S2(2) of the second column to turn off the second transistor 162 of the second column. Next, the potentials V2 and 0V are supplied to the first signal line S1(1) of the first row and the first signal line S1(2) of the second row, respectively. As a result, potentials V2 and 0V are supplied to the floating gates FG of memory cells (1,1) and (1,2), respectively. Here, potential V2 is higher than the threshold voltage of the first transistor 160. Next, the potential of the second signal line S2(1) of the first column is set to 0V to turn off the second transistor 162 of the first column. Thus, the write operation is completed. Note that word lines WL(1) and WL(2) are at a potential of 0V. Furthermore, before changing the potential of the first signal line S1(1) of the first column, the potential of the second signal line S2(1) of the first column is set to 0V. The threshold voltage of the memory element to which data has been written is Vw0 in the case of data "0" and Vw1 in the case of data "1". Assume that in the memory element, one terminal connected to word line WL is a control gate electrode, the source electrode of the first transistor 160 is a source electrode, and the drain electrode of the second transistor 162 is a drain electrode. Here, the threshold voltage of the memory cell refers to the voltage at that terminal connected to word line WL, which changes the resistance between the source and drain electrodes of the first transistor 160. Note that Vw0>0>Vw1 is satisfied. First, the reading process will be explained. During the reading period of the first column, potentials 0V and V1 are supplied to word line WL(1) of the first column and word line WL(2) of the second column, respectively. Potential VL is lower than the threshold voltage Vw1. When WL(1) is at a potential of 0V, in the first column, the first transistor 160 of memory cell (1,2) (where data "0" is stored) is off, and the first transistor 160 of memory cell (1,1) (where data "1" is stored) is on. When WL(2) is at a potential of VL, in the second column, the first transistor 160 of memory cells (2,1) and (2,2) (where data "0" or data "1" is stored) is off. Next, a potential of 0V is supplied to the source line SL(1) of the first row and the source line SL(2) of the second row. As a result, the first transistor 160 in memory cell (1,1) between bit line BL(1) and source line SL(1) is turned on, thus having low resistance, and the first transistor 160 in memory cell (1,2) between bit line BL(2) and source line SL(2) is turned off, thus having high resistance. The read circuit connected to bit line BL(1) and bit line BL(2) can read data based on the difference between the bit lines. Furthermore, a potential of 0V and a potential of VL are supplied to the second signal line S2(1) and the second signal line S2(2) respectively to turn off all the second transistors 162. The potential of the floating gate section FG of the first column is 0V or V2; therefore, the potential of the second signal line S2(1) is set to 0V, thereby turning off all the second transistors 162 of the first column. On the other hand, the potential of the floating gate section FG of the second column is lower than the potential when data is written directly after the potential VL is supplied to the word line WL(2). Therefore, in order to prevent the second transistors 162 from being turned on, the potential of the second signal line S2(2) is set to low, similar to the potential of the word line WL(2). Thus, all the second transistors 162 can be turned off. Next, the output potential will be explained when the circuit in Figure 21 is used as the read circuit. Since the resistance between bit line BL(1) and source line SL(1) is low, a low potential is supplied to the time inverter and the output D(1) is signal high. Since the resistance between bit line BL(2) and source line SL(2) is high, a high potential is supplied to the time inverter and the output D(2) is signal low. For the operating voltage, assume that the following conditions are met, for example, VDD=2V, V2=1.5V, VH=2V, and VL=-2V. As described in this embodiment, the memory capacity of the semiconductor device can be increased by providing a plurality of memory cells. Note that the number and arrangement of memory cells, the number and arrangement of lines, and the number and arrangement of driver circuits can be appropriately designed; therefore, they are not limited to the above-described structure. The methods and structures described in this embodiment can be appropriately combined with any of the methods and structures described in other embodiments. (Example 4) In this embodiment, the structure and method of manufacturing a semiconductor device according to another embodiment of the disclosed invention are described with reference to Figures 22A and 22B, 23A to 23D, and 24A to 24C, which differ from those in Embodiments 1 and 2. Note that the transistors 260, 262, and 264 described in this embodiment can be used as transistors 160, 162, and 164 in the circuit diagrams of the above embodiments, respectively. <Cross-sectional and planar structures of semiconductor devices> Figures 22A and 22B illustrate an example of the structure of a semiconductor device. Figure 22A shows a cross-sectional view of the semiconductor device, and Figure 22B shows a plan view of the semiconductor device. Here, Figure 22A corresponds to the cross-section along lines C1-C2 and D1-D2 in Figure 22B. In the plan view of Figure 22B, certain components, such as source / drain electrodes 254 and line 256, are omitted to avoid complexity. The semiconductor device shown in Figures 22A and 22B includes a transistor 260 in the lower part, which is made of a non-semiconductor material, and a transistor 262 in the upper part, which includes an oxide semiconductor layer. Transistors formed using non-oxide semiconductor materials can easily operate at high speeds. On the other hand, transistors including oxide semiconductors can retain charge for a long time due to their characteristics. Although all transistors herein are n-channel transistors, p-channel transistors can be used. Since the technical nature of the disclosed invention is to use oxide semiconductors in transistor 262 to store data, there is no need to limit the specific structure of the semiconductor device to the structure described herein. In the semiconductor device shown in Figures 22A and 22B, transistor 262 and capacitor 264 are disposed to overlap with transistor 260. High integration is possible by employing the planar layout shown in Figure 22B. For example, given a minimum processing size of F, the area occupied by a memory cell can be 15F² to 25F². The semiconductor device in Figures 22A and 22B differs from the semiconductor device described in the previous embodiment in that the transistor 260 does not have a sidewall insulating layer. That is, the semiconductor device in Figures 22A and 22B does not include a sidewall insulating layer. Because no sidewall insulating layer is formed, impurity regions 114 are not formed (see Figures 2A and 2B). Therefore, in the case where no sidewall insulating layer is provided, high integration is easier compared to the case where a sidewall insulating layer is provided. Furthermore, the manufacturing process can be simplified compared to the case where a sidewall insulating layer is provided. Another difference between the semiconductor device in Figures 22A and 22B and the semiconductor device described in the previous embodiment is the presence of an interlayer insulating layer in the transistor 260. Specifically, the semiconductor device in Figures 22A and 22B includes a hydrogen-containing interlayer insulating layer 225 that contacts the metal compound region 224 of the transistor 260. By providing the hydrogen-containing interlayer insulating layer 225 in contact with the metal compound region 224, hydrogen can be supplied to the transistor 260 to improve its characteristics. For example, a hydrogen-containing silicon nitride layer formed by a plasma CVD method can be provided as the interlayer insulating layer 225. Furthermore, by using an insulating layer with a low hydrogen concentration as the interlayer insulating layer 226, hydrogen that could adversely affect the transistor 262 can be prevented from entering the transistor 262. For example, a silicon nitride layer formed by a sputtering method under hydrogen-deficient conditions can be provided as the interlayer insulating layer 226. When this structure is adopted, the characteristics of the transistors 260 and 262 can be sufficiently improved. Note that in Figures 22A and 22B, the substrate 200, the element isolation insulating layer 206, the gate insulating layer 208, the gate electrode 210, the channel forming region 216, the high-concentration impurity region 220, and the metal compound region 224 correspond to the substrate 100, the element isolation insulating layer 106, the gate insulating layer 108, the gate electrode 110, the channel forming region 116, the high-concentration impurity region 120, and the metal compound region 124 in Embodiment 1, respectively. Another difference between the semiconductor device in Figures 22A and 22B and the semiconductor device described in the previous embodiment is that insulating layers 243a and 243b are respectively provided between the oxide semiconductor layer 244 and the source electrode 242a, and between the oxide semiconductor layer 244 and the drain electrode 242b in the transistor 262. By providing insulating layers 243a and 243b in this way, the so-called gate capacitance formed by the gate electrode 248a and the source electrode 242a (or the gate electrode 248a and the drain electrode 242b) can be reduced, thereby increasing the operating speed of the transistor 262. Note that in Embodiment 1, the source electrode 242a is formed directly on the gate electrode 210, thereby electrically connecting the lower transistor 260 and the upper transistor 262. This structure increases integration compared to cases where additional electrodes and wires are provided. Furthermore, it simplifies the manufacturing process. Although a structure including all the differences is described in this embodiment, a structure including any of these differences may be used. Methods for Manufacturing Semiconductor Devices Next, an example of a method for manufacturing the above-described semiconductor device will be described. Thereafter, the steps following the formation of the lower transistor 260 and the method for manufacturing the upper transistor 262 will be described with reference to Figures 23A to 23D and 24A to 24C. The lower transistor 260 can be formed by a method similar to that described in Example 1. More details can be obtained by referring to Example 1. Note that a capacitor 264 is provided in this embodiment. Additionally, three interlayer insulating layers 225, 226, and 228 are formed to cover the transistor 260 in this embodiment. Note that the source / drain electrodes 130a and 130b in Example 1 are not formed through the process of the transistor 260 in this embodiment, and for convenience, the structure in which the source / drain electrodes 130a and 130b are not formed is still referred to as transistor 260. First, the transistor 260 in the lower part is formed by the method described in Example 1, and then a portion of the top surface of the gate electrode 210 of the transistor 260 is removed. For the removal step, a polishing process such as chemical mechanical polishing (CMP) can be used. Therefore, the interlayer insulating layers 225, 226, and 228 above the top surface of the gate electrode 210 are removed. Note that the surface subjected to this polishing process is sufficiently planarized, thereby advantageously allowing the formation of electrodes, wires, insulating layers, semiconductor layers, or the like in subsequent steps. Next, a conductive layer is formed above the gate electrode 210, and interlayer insulating layers 225, 226, and 228 and the conductive layer are selectively etched to form source and drain electrodes 242a and 242b (see Figure 23A). Here, a source electrode 242a is formed that is in direct contact with the gate electrode 210. The conductive layers for forming the source and drain electrodes 242a and 242b can be formed using materials similar to those described in Example 1 for the source / drain electrodes 142a and 142b. Furthermore, the conductive layers can be etched using methods similar to those described in Example 1. See Example 1 for more details. Next, an insulating layer is formed to cover the source and drain electrodes 242a and 242b and is selectively etched to form insulating layers 243a and 243b above the source and drain electrodes 242a and 242b, respectively (see Figure 23B). By providing insulating layers 243a and 243b, the parasitic capacitance formed between the gate electrode 248a and the source and drain electrodes 242a and 242b formed subsequently can be reduced. Subsequently, an oxide semiconductor layer 244 is formed to cover the source and drain electrodes 242a and 242b, and a gate insulating layer 246 is formed above the oxide semiconductor layer 244 (see Figure 23C). The oxide semiconductor layer 244 can be formed using the materials and methods of the oxide semiconductor layer 140 described in Example 1. Furthermore, the oxide semiconductor layer 244 is advantageously subjected to heat treatment (a first heat treatment). See Example 1 for more details. The gate insulating layer 246 can be formed using the material and method of the gate insulating layer 138 described in Example 1. Furthermore, it is advantageous to subject the formed gate insulating layer 246 to heat treatment (second heat treatment) in an inert gas environment or an oxygen environment. See Example 1 for further details. Next, above the gate insulating layer 246, a gate electrode 248a is formed in a region that overlaps with one of the transistors 262 (which serves as a channel forming region), and an electrode 248b is formed in a region that overlaps with the source electrode 242a (see Figure 23D). Gate electrodes 248a and 248b can be formed in one manner to form a conductive layer over the gate insulating layer 246 and then selectively etched. The conductive layer that will become gate electrodes 248a and 248b can be formed by PVD methods (typically sputtering) or CVD methods (such as plasma CVD). Details are similar to those of source electrode 242a or the like; therefore, refer to its description. Next, interlayer insulating layers 250 and 252 are formed over the gate insulating layer 246, the gate electrode 248a, and the electrode 248b (see Figure 24A). The interlayer insulating layers 250 and 252 can be formed using the materials and methods described in Example 1 for the protective insulating layer 144 and the interlayer insulating layer 146. Further details can be found in the examples. Note that the interlayer insulating layer 252 is advantageously formed to have a planarized surface. This is because, even in cases where the size of the semiconductor device is reduced, electrodes, wires, or the like can be advantageously formed over the interlayer insulating layer 252. Methods such as chemical mechanical polishing (CMP) can be used to planarize the interlayer insulating layer 252. Subsequently, interlayer insulating layers 225, 226, and 228, oxide semiconductor layer 244, gate insulating layer 246, and interlayer insulating layers 250 and 252 are selectively etched to form an opening reaching the metal compound region 224 of transistor 260 (see Figure 24B). For etching, dry etching or wet etching can be used; for microfabrication, dry etching is advantageous. A source / drain electrode 254 is formed to be embedded in the opening. Next, a line 256 is formed to connect to the source / drain electrode 254 (see Figure 24C). The source / drain electrode 254 can be formed in a manner such as by PVD, CVD, or similar methods to form a conductive layer in the region including the opening, and then by etching, CMP, or similar methods to remove portions of the conductive layer. Specifically, a method can be employed in which a thin titanium film is formed in the region including the opening by PVD, a thin titanium nitride film is formed by CVD, and then a tungsten film is formed to embed in the opening. Here, the titanium film formed by PVD has the function of reducing oxide films (such as native nitride films) formed on the surface on which the titanium film is formed, thereby reducing contact resistance with the lower electrode (here, such as the metal compound region 224). The titanium nitride film formed after the titanium film formation has the function of preventing the diffusion of conductive materials. A copper film can be formed by plating after the formation of the titanium, titanium nitride, or similar barrier films. Line 256 can be formed in one manner to create a conductive layer in contact with the source / drain electrode 254 and then selectively etched. The conductive layer can be formed using PVD methods (typically sputtering) or CVD methods (such as plasma CVD). Details are similar to those for source electrode 242a or the like. Therefore, a semiconductor device including transistor 260, transistor 262, and capacitor 264 is completed. In the semiconductor device described in this embodiment, for example, transistor 262 and capacitor 264 overlap with transistor 260, transistor 260 does not include a sidewall insulating layer, and source electrode 242a is directly formed on gate electrode 210; therefore, high integration is possible. Furthermore, the manufacturing process is simplified. Furthermore, in the semiconductor device described in this embodiment, hydrogen-containing insulating layers and insulating layers with reduced hydrogen concentration are used as interlayer insulating layers 225 and 226, respectively; thus improving the characteristics of transistors 260 and 262. Due to insulating layers 243a and 243b, the so-called gate capacitance is reduced, and therefore the operating speed of transistor 262 is increased. The features described in this embodiment make it possible to provide a semiconductor device with significantly superior properties. The methods and structures described in this embodiment may be appropriately combined with any methods and structures described in other embodiments. (Example 5) This embodiment illustrates an example of an electronic device in which a semiconductor device derived from any of the above embodiments is mounted, with reference to Figures 10A to 10F. The semiconductor device derived from any of the above embodiments can store data even when no power is supplied. Furthermore, it does not cause degradation due to writing and erasing. Additionally, the write and erase operations are high-speed. For these reasons, the above-described semiconductor device can be used to provide electronic devices with novel structures. Note that the semiconductor device according to any of the above embodiments is mounted on an integrated circuit board and the like, and is installed within each electronic device. Figure 10A shows a notebook computer including a semiconductor device according to any of the foregoing embodiments, and is formed with a housing 301, a housing 302, a display 303, a keyboard 304, and the like. Figure 10B shows a personal digital assistant (PDA) including a semiconductor device according to any of the foregoing embodiments, and includes a housing 311, a display 313, an external interface 315, an operation button 314, and the like. Additionally, a stylus 312 is provided as an operating accessory. As an example of electronic paper, Figure 10C is a drawing of an e-book reader 320, which includes a semiconductor device according to any of the foregoing embodiments. The e-book reader 320 includes two housings, housings 321 and 323. Housings 321 and 323 are joined by a hinge 337 to open and close the e-book reader 320 along the hinge 337. With this structure, the e-book reader 320 can be operated like a paper book. Display unit 325 is incorporated into housing 321, and display unit 327 is incorporated into housing 323. Display units 325 and 327 can display one image or different images. In the case where display units 325 and 327 display different images, for example, text can be displayed on the right display unit (display unit 325 in figure 10C), and graphics can be displayed on the left display unit (display unit 327 in figure 10C). Figure 10C illustrates an example in which the housing 321 is provided with an operating section and the like. For example, the housing 321 includes a power supply 331, operation keys 333, a speaker 335, and the like. Pages can be turned using the operation keys 333. Note that a keyboard, indicator device, or the like can also be provided on the surface of the housing on which the display section is located. In addition, external connection terminals (such as headphone terminals, USB terminals, terminals for connecting to various cables such as AC adapters and USB cables, or the like), recording media insertion parts, and the like can be provided on the back surface or side surface of the housing. Furthermore, the e-book reader 320 may have the function of an electronic dictionary. Furthermore, the e-book reader 320 can wirelessly send and receive data. Through wireless communication, users can purchase and download desired books or similar materials from e-book servers. It is noted that e-paper can be applied to any device in any field, as long as it can display data. For example, in addition to e-book readers, e-paper can be used for posters, advertisements such as those in train vehicles, displays on various credit cards, and so on. Figure 10D shows a mobile phone including a semiconductor device according to any of the foregoing embodiments. The mobile phone includes two housings, housing 340 and housing 341. Housing 341 includes a display panel 342, a speaker 343, a microphone 344, an indicator 346, a camera lens 347, an external connection terminal 348, and the like. Additionally, housing 341 includes a solar cell unit 349 for charging the mobile phone, an external memory slot 350, and the like. Furthermore, an antenna is incorporated into housing 341. Display panel 342 functions as a touchpad and, as shown by the dashed lines in Figure 10D, displays multiple operation keys 345 as images. Note that the mobile phone is equipped with a boost circuit for increasing the output voltage of the solar cell unit 349 to the voltage required by each circuit. Furthermore, in addition to the above structure, the mobile phone may further incorporate contactless IC chips, small memory devices, or the like. The display orientation of the display panel 342 can be appropriately changed according to the usage mode. Furthermore, since the camera lens 347 is mounted on the same surface as the display panel 342, the mobile phone can be used as a video phone. The speaker 343 and microphone 344 can be used not only for voice calls but also for video calls, recording, sound playback, and the like. Additionally, the housings 340 and 341, as shown in Figure 10D, can slide so that one covers the other; therefore, the size of the mobile phone can be reduced, making it more portable. The external connection terminal 348 can be connected to various cables such as AC adapters or USB cables, thereby charging the mobile phone or performing data communication, etc. Furthermore, by inserting recording media into the external memory slot 350, the mobile phone can handle the storage and transfer of large amounts of data. Moreover, in addition to the above functions, it may be equipped with infrared communication functions, television reception functions, etc. Figure 10E shows a digital camera including a semiconductor device according to any of the foregoing embodiments. The digital camera includes a main body 361, a display unit A 367, an eyepiece 363, an operation switch 364, a display unit B 365, a battery 366, and the like. Figure 10F shows a television set including a semiconductor device according to any of the foregoing embodiments. The television set 370 has a display unit 373 housed in a housing 371. Images can be displayed on the display unit 373. Note that the housing 371 can be supported by a bracket 375. The television 370 can be operated via the operation switch on the housing 371 or via a separate remote control 380. Channels and volume can be controlled using the operation keys 379 on the remote control 380, thus controlling the images displayed on the display unit 373. Furthermore, the remote control 380 may have a display unit 377, in which information output from the remote control 380 is displayed. It is noted that the television set 370 is preferably equipped with a receiver, modem, and the like. By using the receiver, general television broadcasts can be received. In addition, when the display device is connected to a communication network via a modem, either wired or wirelessly, one-way (from transmitter to receiver) or two-way (between transmitter and receiver or between receivers) data communication can be performed. The structures, methods, and the like described in this embodiment may be appropriately combined with any structures, methods, and the like described in other embodiments. (Example 1) This example illustrates the results obtained by measuring the shut-off current of a transistor comprising a highly purified oxide semiconductor. First, considering the very small turn-off current of highly purified oxide semiconductor transistors, a transistor with a sufficiently wide channel width W of 1 μm was prepared, and the turn-off current was measured. Figure 25 shows the results obtained by measuring a transistor with a channel width W of 1 μm. In Figure 25, the horizontal axis shows the gate voltage VG and the vertical axis shows the drain current ID. When the drain voltage VD is +1V or +10V and the gate voltage VG is in the range of -5V to -20V, the turn-off current of the transistor was found to be less than or equal to 1 × 10⁻¹³ A, which is the detection limit. Furthermore, the turn-off current of the transistor (per unit channel width (1 μm)) was found to be less than or equal to 1 A / μm (1 × 10⁻¹⁸ / μm). The following will explain the results obtained by more accurately measuring the turn-off current of transistors including highly purified oxide semiconductors. As mentioned above, the turn-off current of transistors including highly purified oxide semiconductors was found to be less than or equal to 1 × 10⁻¹³ A, which is the measurement limit of the measuring equipment. Here, the results obtained by using components for characteristic evaluation to measure a more accurate turn-off current (value less than or equal to the detection limit of the measuring equipment in the above measurement) will be explained. First, refer to Figure 26 to explain the components used for this characteristic evaluation. In the component used for characteristic evaluation shown in Figure 26, three measurement systems 800 are connected in parallel. The measurement system 800 includes a capacitor 802, a transistor 804, a transistor 805, a transistor 806, and a transistor 808. Transistors including highly purified oxide semiconductors are used for transistors 804, 805, and 806. In the measurement system 800, one of the source and drain terminals of transistor 804, one terminal of capacitor 802, and one of the source and drain terminals of transistor 805 are connected to a power supply (for supplying V2). The other source and drain terminal of transistor 804, one of the source and drain terminals of transistor 808, the other terminal of capacitor 802, and the gate terminal of capacitor 805 are interconnected. The other source and drain terminal of transistor 808, one of the source and drain terminals of transistor 806, and the gate terminal of transistor 806 are connected to a power supply (for supplying V1). The other source and drain terminal of transistor 805 and the other source and drain terminal of transistor 806 are interconnected. Additionally, an output terminal is provided. A potential Vext_b2, used to control the on and off states of transistor 804, is supplied to the gate terminal of transistor 804. A potential Vext_b1, used to control the on and off states of transistor 808, is supplied to the gate terminal of transistor 808. A potential Vout is output from this output terminal. Next, we will explain the method for measuring current using components for characteristic evaluation. First, the initial period for supplying a potential difference to measure the turn-off current will be briefly described. During this initial period, a potential Vext_b1 for turning on transistor 808 is input to the gate terminal of transistor 808, and a potential V1 is supplied to node A, which is the node connected to the other of the source and drain terminals of transistor 804 (i.e., the node connected to one of the source and drain terminals of transistor 808, the other terminal of capacitor 802, and the gate terminal of capacitor 805). Here, potential V1 is, for example, a high potential. Transistor 804 is off. Next, a potential Vext_b1 for turning on transistor 808 is input to the gate terminal of transistor 808 to turn off transistor 808. After transistor 808 is turned off, potential V1 is set low. Transistor 804 remains off. Potential V2 is the same as potential V1. Thus, the initial period is completed. In the state where the initial period is completed, a potential difference is generated between node A and one of the source and drain terminals of transistor 804, and also, a potential difference is generated between node A and the other of the source and drain terminals of transistor 808. Therefore, charge flows slightly through transistors 804 and 808. In other words, a shutdown current is generated. Next, the measurement period of the shut-off current will be briefly described. During the measurement period, the potential of one of the source and drain terminals of transistor 804 (i.e., V2) and the other of the source and drain terminals of transistor 808 (i.e., V1) are set to low and fixed. On the other hand, the potential of node A is not fixed during the measurement period (node ​​A is in a floating state). Accordingly, as time passes, charge flows through transistor 804 and the charge is maintained at node A. Furthermore, when the charge maintained at node A changes, the potential of node A changes. That is, the output potential Vout of the output terminal also changes. Figure 27 shows the details of the relationship between potentials during the initial period of the applied potential difference and during subsequent measurement periods (time series diagram). In the initial phase, the potential Vext_b2 is set to the potential of the turn-on transistor 804 (high potential). Therefore, the potential of node A reaches V2, that is, the low potential (VSS). Then, the potential Vext_b2 is set to the potential of the turn-off transistor 804 (low potential), thereby turning off transistor 804. Next, the potential Vext_b1 is set to the potential of the turn-on transistor 808 (high potential). Therefore, the potential of node A reaches V1, that is, the high potential (VDD). Then, the potential Vext_b1 is set to the potential of the turn-on transistor 808. In this way, node A is brought to the floating state and the initial phase is completed. During the subsequent measurement period, potentials V1 and V2 are individually set to the potential at which charge flows back and forth to node A. Here, potentials V1 and V2 are at low potentials (VSS). Note that the output circuit must be operated when measuring the output potential Vout; therefore, in some cases, V1 is temporarily set to a high potential (VDD) to ensure that the period during which V1 is at a high potential (VDD) is short enough not to affect the measurement. When a potential difference is applied as described above to initiate the measurement period, the amount of charge held at node A changes over time, and consequently, the potential of node A changes. This means that the potential of the gate terminal of transistor 805 changes, and therefore the output potential Vout of the output terminal also changes over time. The method for calculating the shutdown current based on the obtained output potential Vout will be explained below. Before calculating the shutdown current, the relationship between the potential VA of node A and the output potential Vout is obtained in advance. Therefore, the potential VA of node A can be obtained based on the output potential Vout. From the above relationship, the potential VA of node A can be expressed as a function of the output potential Vout by the following equation. [Equation 1] VA = F(Vout) The charge QA at node A is expressed by the following equation using the potential VA of node A, the capacitance CA connected to node A, and a constant (const). Here, the capacitance CA connected to node A is the sum of the capacitance of capacitor 802 and the other capacitances. [Equation 2] QA = CAVA + const Since the current IA of node A is obtained by differentiating the charge flowing to node A with respect to time, the current IA of node A is expressed by the following equation. Therefore, the current IA of node A can be obtained based on the capacitor CA connected to node A and the output potential Vout of the output terminal. Using the above method, the leakage current (shutdown current) flowing between the source and drain of a switched-off transistor can be calculated. In this example, transistors 804, 805, 806, and 808 are fabricated using highly purified oxide semiconductors with a channel length of 10 μm and a channel width W of 50 μm. In each of the parallel-configured measurement systems 800, capacitors 802a, 802b, and 802c have capacitance values ​​of 100 fF, 1 pF, and 3 pF, respectively. Note that the measurement according to this example is performed under the assumption that VDD=5V and VSS=0V. During the measurement period, the potential V1 is basically set to VSS and only set to VDD in 100-millisecond cycles every 10 to 300 seconds, and Vout is measured. In addition, the Δt used when the current I flowing through the element is approximately 30,000 seconds. Figure 28 shows the relationship between the output potential Vout and the elapsed time Time during current measurement. According to Figure 28, the potential evolves over time. Figure 29 shows the shutdown current at room temperature (25°C) calculated based on the aforementioned current measurements. Note that Figure 29 shows the relationship between the source-drain voltage V and the shutdown current I. According to Figure 29, the shutdown current is approximately 40 zA / μm, where the source-drain voltage is 4V. When the source-drain voltage is 3.1V, the shutdown current is less than or equal to 10 zA / μm. Note that 1 zA is equivalent to 10⁻²¹ A. Furthermore, Figure 30 shows the shutdown current calculated based on the aforementioned current measurements at room temperature (85°C). Figure 30 also shows the relationship between the source-drain voltage V and the shutdown current I at 85°C. According to Figure 30, when the source-drain voltage is 3.1V, the shutdown current is approximately 100 μA / μm. This example confirms that the shut-off current is sufficiently small in transistors including highly purified oxide semiconductors. [Example 2] The number of times data can be rewritten by a semiconductor device according to one embodiment of the disclosed invention is tested. In this example, the test results will be explained with reference to Figure 31. The semiconductor device used for testing is a semiconductor device having the circuit configuration shown in Figure 15A. Here, an oxide semiconductor is used as the transistor corresponding to transistor 162, and a capacitor with a capacitance value of 0.33pF is used as the capacitor corresponding to capacitor 164. The verification is performed by comparing the initial memory window width with the memory window width after a predetermined number of data storage and writing operations. Data is stored and written by applying 0V or 5V to the line corresponding to the third line in Figure 15A and applying 0V or 5V to the line corresponding to the fourth line in Figure 15A. When the potential of the line corresponding to the fourth line is 0V, the transistor (write transistor) corresponding to transistor 162 is off; therefore, the potential supplied to node FG is maintained. When the potential of the line corresponding to the fourth line is 5V, the transistor (write transistor) corresponding to transistor 162 is on; therefore, the potential of the line corresponding to the third line is supplied to node FG. The memory window width is one of the indicators of a memory device's characteristics. Here, the memory window width represents the displacement ΔVcg in the curves (Vcg-Id curves) between different memory states. These curves show the relationship between the potential Vcg corresponding to the fifth line and the drain current Id corresponding to the transistor 160 (read transistor). Different memory states refer to the state where 0V is applied to node FG (hereinafter referred to as the low state) and the state where 5V is applied to node FG (hereinafter referred to as the high state). That is, the memory window width can be checked by sweeping the potential Vcg in the low and high states. Figure 31 shows the test results of the memory window width after 1×10⁹ write operations. Note that in Figure 31, the horizontal axis shows Vcg(V) and the vertical axis shows Id(A). According to Figure 31, the memory window width remained unchanged after 1×10⁹ write operations, which means that the semiconductor device did not deteriorate in the period following at least 1×10⁹ write operations. As described above, in the semiconductor device according to one embodiment of the disclosed invention, the characteristics remain unchanged even after data has been stored and written 1×10⁹ times, and the resistance to rewriting is very high. That is, it can be said that a remarkably reliable semiconductor device can be achieved according to one embodiment of the disclosed invention. This application is based on Japanese Patent Application No. 2009-249330 filed with the Japan Patent Office on October 29, 2009, and Japanese Patent Application No. 2010-012619 filed with the Japan Patent Office on January 22, 2010, the entire contents of which are incorporated herein by reference. 100:Substrate 102: Protective layer 104: Semiconductor Region 106: Component isolation insulation layer 108: Gate insulation layer 110: Gate electrode 112: Insulation layer 114: Impurity Region 116: Channel Formation Area 118: Sidewall insulation layer 120: High concentration of impurities area 122: Metal layer 124: Metal compound region 124: Metal compound region 126: Interlayer insulation layer 128: Interlayer insulation layer 130a: Source / Drain Electrode 130b: Source / Drain Electrode 130c: Electrode 132: Insulation layer 134: Conductive layer 136a: Electrode 136b: Electrode 136c: Electrode 136d: Gate electrode 138: Gate insulation layer 140: Oxide semiconductor layer 142a: Source / Drain Electrode 142b: Source / Drain Electrode 144: Protective insulation layer 146: Interlayer insulation layer 148: Conductive layer 150a: Electrode 150b: Electrode 150c: Electrode 150d: Electrode 150e: Electrode 152: Insulation layer 154a: Electrode 154b: Electrode 154c: Electrode 154d: Electrode 160: Transistor 162: Transistor 164: Capacitor 200:Substrate 206: Component isolation insulation layer 208: Gate insulation layer 210: Gate electrode 216: Channel Formation Area 220: High concentration of impurities region 224: Metal compound region 225: Interlayer insulation layer 226: Interlayer insulation layer 228: Interlayer insulation layer 242a: Source electrode 242b: Drain electrode 243a: Insulation layer 243b: Insulation layer 244: Oxide semiconductor layer 246: Gate insulation layer 248a: Gate electrode 248b: Electrode 250: Interlayer insulation layer 252: Interlayer insulation layer 254: Drain electrode 256: Line 260: Transistor 262: Transistor 264: Capacitor 301: Main Body 302: Housing 303: Display Section 304: Keyboard 311: Main Body 312: Stylus 313: Display Section 314: Operation Button 315: External Interface 320: E-book reader 321: Shell 323: Shell 325: Display Unit 327: Display Section 331: Power switch 333: Operation Key 335: Speaker 337: Hinges 340: Housing 341: Shell 342: Display panel 343: Speaker 344: Microphone 345: Operation Keys 346: Indicating device 347: Camera Lens 348: External connection terminal 349: Solar cell unit 350: External memory slot 361: Main Body 363: Eyepiece 364: Operation Switch 365: Display Unit B 366: Battery 367: Display Unit A 370: Television 371: Shell 373: Display Section 375: Bracket 377: Display Section 379: Operation Keys 380: Remote Control 400: Memory Cell 800: Measurement System 802: Capacitor 802a: Capacitor 802b: Capacitor 802c: Capacitor 804: Transistor 805: Transistor 806: Transistor 808: Transistor 1100: Memory Cell 1111: First driver circuit 1112: Second driver circuit 1113: Third driver circuit 1114: Fourth Driver Circuit 1200: Memory Cell 1211: First driver circuit 1212: Second driver circuit 1213: Third driver circuit 1214: Fourth Driver Circuit

Claims

1. A semiconductor device comprising a plurality of circuits having a first transistor having an oxide semiconductor in a first channel forming region and a second transistor having silicon in a second channel forming region, wherein one of the source or drain of the first transistor is electrically connected to the gate of the second transistor, comprising: a semiconductor film having the second channel forming region; a first conductive film having a region above the semiconductor film and functioning as a gate of the second transistor; a first insulating film having a region above the semiconductor film and comprising silicon nitride; and a second conductive film having a region above the first insulating film and functioning as a gate of the first transistor. An oxide semiconductor film having a region located above the second conductive film, and having the first channel forming region; The third conductive film has a region located above the oxide semiconductor film and functions as either the source or drain of the first transistor; the fourth conductive film has a region located above the oxide semiconductor film and functions as either the source or drain of the first transistor.

2. A semiconductor device comprising a plurality of circuits having a first transistor having an oxide semiconductor in a first channel forming region and a second transistor having silicon in a second channel forming region, wherein one of the source or drain of the first transistor is electrically connected to the gate of the second transistor, comprising: a semiconductor film having the second channel forming region; a first conductive film having a region above the semiconductor film and functioning as the gate of the second transistor; a first insulating film having a region above the semiconductor film and comprising silicon nitride; a second conductive film having a region above the first insulating film and functioning as the gate of the first transistor; an oxide semiconductor film having a region above the second conductive film and having the first channel forming region; a third conductive film having a region adjacent to the top surface of the oxide semiconductor film and functioning as one of the source or drain of the first transistor; and a fourth conductive film having a region adjacent to the top surface of the oxide semiconductor film and functioning as the other of the source or drain of the first transistor.

3. The semiconductor device as claimed in claim 1 or 2, wherein, Data is input to the gate of the second transistor via the fourth conductive film.

4. The semiconductor device as claimed in claim 1 or 2, wherein, The potential held by the gate of the second transistor corresponds to a complex number of bits of data.

5. The semiconductor device as claimed in claim 1 or 2, wherein, This oxide semiconductor is of the In-O type.

6. A semiconductor device comprising a plurality of circuits having a first transistor having an oxide semiconductor in a first channel forming region and a second transistor having silicon in a second channel forming region, wherein one of the source or drain of the first transistor is electrically connected to the gate of the second transistor, comprising: a semiconductor film having the second channel forming region.

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