Systems and methods for stable intermediate node operation in series stacked phase dc-dc converters

Abstract

The present invention provides a power converter circuit. In one embodiment, the power converter circuit includes a first buck converter connected in series to a second buck converter at an intermediate node, and a control circuit coupled to each of the first buck converter and the second buck converter. In another embodiment, the control circuit is configured to continuously operate the first buck converter, sense a voltage at the intermediate node, compare the sensed voltage with the first threshold voltage, and disable the second buck converter in response to the sensed voltage being below the first threshold voltage. In yet another embodiment, the control circuit is configured to continuously operate the first buck converter, compare the sensed voltage with the second threshold voltage, and operate the second buck converter in response to the sensed voltage being above the second threshold voltage.

Description

Technical Field

[0001] The described embodiments generally relate to power converters, and more particularly, the present embodiments relate to systems and methods for stable mid-node operation in series stacked phase DC-DC converter circuits. Prior Art

[0002] Consumers today have access to a wide variety of electronic devices. Many of these devices have integrated circuits that are powered by regulated low voltage DC power supplies. These low voltage supplies are often generated by dedicated power converter circuits that use a higher voltage input from a battery or other power source. In some applications, the dedicated power converter circuit can be one of the largest power dissipating components of the electronic device and sometimes consume more space than the integrated circuit it powers. As electronic devices become more complex and more compact, more efficient power converter circuits are needed. Summary of the invention

[0003] In some embodiments, a power converter circuit is disclosed. The power converter circuit includes: a first buck converter having a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal at a first switch node; a second buck converter having a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is coupled to the first buck converter in series at an intermediate node such that the third drain terminal is coupled to the second a source terminal; an input terminal coupled to the first drain terminal; an output terminal coupled to the first switch node and the second switch node; and a control circuit coupled to each of the first buck converter and the second buck converter and configured to continuously operate the first buck converter, wherein the control circuit is further configured to: sense a voltage at the intermediate node; compare the sensed voltage with a first threshold voltage, and in response to the sensed voltage being at a voltage below the first threshold voltage, the control circuit disables the second buck converter; and compare the sensed voltage with a second threshold voltage, and in response to the sensed voltage being at a voltage above the second threshold voltage, the control circuit operates the second buck converter.

[0004] In some embodiments, the first buck converter and the second buck converter are configured to generate an output voltage at the output terminal that is lower than an input voltage at the input terminal.

[0005] In some embodiments, the first buck converter and the second buck converter are configured to control power transfer from an input terminal to an output terminal.

[0006] In some embodiments, the control circuit includes a window comparator including a first comparator and a second comparator.

[0007] In some embodiments, the first comparator is configured to receive a voltage at the intermediate node and to receive a first threshold voltage.

[0008] In some embodiments, the second comparator is configured to receive the voltage at the intermediate node and to receive the second threshold voltage.

[0009] In some embodiments, the output terminal is coupled to the first switch node via a first inductor.

[0010] In some embodiments, the output terminal is coupled to the second switch node via a second inductor.

[0011] In some embodiments, the first inductor is coupled to the first switch node via a first capacitor.

[0012] In some embodiments, the second capacitor is coupled to the intermediate node at a first terminal thereof and to ground at a second terminal thereof.

[0013] In some embodiments, a method of operating a power converter circuit is disclosed. The method includes: providing a first buck converter, the first buck converter including a first switch having a first gate terminal, a first drain terminal, and a first source terminal, and a second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal at a first switch node; providing a second buck converter, the second buck converter including a third switch having a third gate terminal, a third drain terminal, and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at the second switch node, wherein the second buck converter is serially coupled to the first buck converter at an intermediate node such that the third drain terminal is coupled to the first buck converter. a second source terminal; providing an input terminal coupled to the first drain terminal; providing an output terminal coupled to the first switch node and the second switch node; and providing a control circuit coupled to each of the first buck converter and the second buck converter; the first buck converter is continuously operated by the control circuit; the voltage at the intermediate node is sensed by the control circuit; the sensed voltage is compared with a first threshold voltage by the control circuit; the second buck converter is disabled by the control circuit in response to the sensed voltage being at a voltage lower than the first threshold voltage; the sensed voltage is compared with a second threshold voltage by the control circuit; and the second buck converter is operated by the control circuit in response to the sensed voltage being at a voltage higher than the second threshold voltage.

[0014] In some embodiments, the method further includes generating, by the first buck converter and the second buck converter, an output voltage at the output terminal that is lower than an input voltage at the input terminal.

[0015] In some embodiments, the method further includes controlling, by the first buck converter and the second buck converter, power transfer from the input terminal to the output terminal.

[0016] In some embodiments, a circuit is disclosed. The circuit includes: a first buck converter having a first switch node; a second buck converter having a second switch node and coupled in series to the first buck converter at an intermediate node; an input terminal coupled to the first buck converter; an output terminal coupled to the first switch node and the second switch node; and a control circuit coupled to each of the first buck converter and the second buck converter and configured to continuously operate the first buck converter, wherein the control circuit is further configured to: sense a voltage at the intermediate node; compare the sensed voltage to a first threshold voltage, and in response to the sensed voltage being at a voltage below the first threshold voltage, the control circuit disables the second buck converter; and compare the sensed voltage to a second threshold voltage, and in response to the sensed voltage being at a voltage above the second threshold voltage, the control circuit operates the second buck converter. Simple diagram description

[0017] FIG. 1 illustrates a series stacked phase DC-DC power converter circuit with a stable intermediate node according to an embodiment of the present disclosure; and

[0018] FIG. 2 illustrates a switching sequence and timing diagram of the DC-DC power converter circuit of FIG. 1 . Implementation

[0019] Cross-reference to related applications This application claims priority to the following commonly assigned U.S. provisional patent applications: No. 63 / 265,611, filed on December 17, 2021, "SYSTEMS AND METHODS FOR STABLE INTERMEDIATE NODE OPERATION IN SERIES STACKED PHASE DC-DC CONVERTERS," and No. 63 / 265,823, filed on December 21, 2021, "PHASE MULTIPLEXED SERIES STACKED DC-DC CONVERTER," which are incorporated herein by reference in their entirety for all purposes. This application is also related to the following concurrently filed and commonly assigned U.S. patent application No. _______________ (Agent Docket No.: 096868-1357957-002310US) filed by _______________, entitled “PHASE MULTIPLEXED SERIES STACKED DC-DC CONVERTER”, which is also incorporated herein by reference in its entirety for all purposes.

[0020] The circuits and related techniques disclosed herein are generally related to power converters. More specifically, the circuits, devices, and related techniques disclosed herein are related to systems and methods for stable intermediate node operation in a series stacked phase DC-DC converter. In some embodiments, the series stacked phase DC-DC converter may include a top phase buck converter and a bottom phase buck converter, wherein the bottom phase may be switched on and off to keep the intermediate node of the series stacked phase DC-DC converter within a preset range. By keeping the intermediate node of the series stacked phase DC-DC converter within a preset range, embodiments of the present disclosure may be able to eliminate positive feedback loops that may exist in the series stacked phase DC-DC converter. In this way, interruptions in the operation of the series stacked phase DC-DC converter may be prevented, and continuous stable operation of the series stacked phase DC-DC converter may be achieved.

[0021] In various embodiments, systems and methods for stable intermediate node operation in a series stacked phase DC-DC converter can eliminate the use of relatively high voltage components in the series stacked phase DC-DC converter. More specifically, embodiments of the present disclosure can eliminate positive feedback loops and keep the intermediate node of the series stacked phase DC-DC converter stable without using additional capacitors or power path switches. In addition, embodiments of the present disclosure can prevent interruptions in the operation of the series stacked phase DC-DC power converter without affecting the efficiency of the power converter. In some embodiments, the series stacked phase DC-DC converter with a stable intermediate node can have an improved electromagnetic interference (EMI) spectrum. Various inventive embodiments are described herein, including methods, processes, systems, devices, etc.

[0022] Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part of the present invention. The following description provides only embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. In fact, the following description of the embodiments will provide an instructive description for implementing one or more embodiments for those skilled in the art. It should be understood that various changes can be made to the functions and configurations of the components without departing from the spirit and scope of the present disclosure. In the following description, for the purpose of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments can be practiced without these specific details. The drawings and descriptions are not intended to be limiting. The word "example" or "exemplary" is used herein to mean "serving as an example, instance or illustration." Any embodiment or design described herein as "exemplary" or "example" is not necessarily to be interpreted as being better or advantageous relative to other embodiments or designs.

[0023] FIG. 1 illustrates a series stacked phase DC-DC power converter circuit 100 with a stable intermediate node according to an embodiment of the present disclosure. As shown in FIG. 1 , the power converter circuit 100 may include a top buck converter stage 109 (top phase) and a bottom buck converter stage 111 (bottom phase). In the illustrated embodiment, the top phase 109 and the bottom phase 111 buck converter stages may be configured in a series configuration, where the top phase 109 is connected to the bottom phase 111 at an intermediate node 107 having a voltage VM. The intermediate node 107 may be coupled to a capacitor 115. The power converter circuit 100 may have an input terminal 110 configured to receive an input voltage (V in).

[0024] The top phase 109 buck converter stage may include a first switch 102 having a gate terminal 150, a drain terminal 157, and a source terminal 152, and a second switch 104 having a gate terminal 154, a drain terminal 155, and a source terminal 156. The first switch 102 and the second switch 104 may be coupled in series at a first switch node 175 having a voltage Vsw1. The bottom phase 111 buck converter stage may include a third switch 106 having a gate terminal 160, a drain terminal 161, and a source terminal 162, and a fourth switch 108 having a gate terminal 167, a drain terminal 168, and a source terminal 169. The third switch 106 and the fourth switch 108 may be coupled in series at a second switch node 117 having a voltage Vsw2. The first switch node 175 may be coupled to a flying capacitor 112 coupled to an inductor 114. The second switch node 117 may be coupled to an inductor 116. Inductors 114 and 116 may be coupled together at an output terminal 118 having an output voltage Vout. Output terminal 118 may be coupled to capacitor 131 and load 135. Capacitor 131 and load 135 may be coupled to ground 120. In some embodiments, power converter circuit 100 is configured to deliver an output voltage Vout at output terminal 118 that is lower than an input voltage Vin at input terminal 110.

[0025] The power converter circuit 100 may include a logic and control circuit 158 ​​coupled to the top phase 109 and the bottom phase 111. The logic and control circuit 158 ​​may be configured to generate control signals that control the operation of the top phase 109 and the bottom phase 111 buck converter stages so as to control the power delivery from the input terminal 110 to the output terminal 118. In some embodiments, the bottom phase 111 may be alternately turned on and off by the logic and control circuit 158 ​​while the top phase 109 continues to execute. In one embodiment, the logic and control circuit 158 ​​may include a window comparator 128 and a set-reset (S / R) latch 141. The window comparator 128 may sense the voltage VM at the intermediate node 107 and compare it to a preset threshold value and maintain the voltage VM within a preset window, for example, within 100 mV below and 10 mV above the ideal value of VM. As will be appreciated by one of ordinary skill in the art having the benefit of this disclosure, the value of the preset window may be set to any suitable value. In some embodiments, the ideal value of VM would be Vin / 2.

[0026] The window comparator 128 may include a first comparator 151 and a second comparator 153. The outputs of the first comparator 151 and the second comparator 153 may trigger the S / R latch 141, which in turn may alternately enable / disable the operation of the bottom phase 111. The first input 121 of the first comparator 151 may be connected to the intermediate node 107. The second input 124 of the first comparator 151 may be connected to a first reference voltage, which may be set to a preset threshold value, such as a value equal to the ideal value of the voltage VM plus 10 mV. The first input 127 of the second comparator 153 may be connected to the intermediate node 107. The second input 126 of the second comparator 153 may be connected to a second reference voltage, which may be set to a preset threshold value, such as a value equal to the ideal value of VM minus 100 mV. In this way, the intermediate node 107 may be kept within a preset window, such as within 100 mV below and 10 mV above the ideal of VM. In various embodiments, the first comparator 151 may have a hysteresis threshold that is the same value as a preset threshold that is higher than the ideal value of VM. As will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, the first reference voltage and the second reference voltage may be set to any suitable values.

[0027] When the middle node 107 rises above a preset threshold, e.g., above more than 10 mV of Vin / 2, the bottom phase 111 may be turned on and begin switching until the middle node 107 (VM) drops below a preset threshold, e.g., below 100 mV of Vin / 2, at which time the bottom phase is turned off. In this way, the middle node 107 (VM) may not drop below a preset threshold. This prevents positive feedback from occurring and disrupting the operation of the power converter circuit. The top phase 109 may continue to switch continuously while the bottom phase 111 is alternately turned on and off. Although the above discusses one particular embodiment of a window comparator circuit, those skilled in the art having the benefit of this disclosure will appreciate that the middle node 107 (VM) may be monitored directly, or a filtered version of the middle node 107 (VM) may be monitored, or a digital filter may be applied to the output of the comparator, all of which are within the scope of identifying a degraded middle node voltage without falsely triggering the comparator due to noise.

[0028] The S / R latch 141 may generate a signal HiZ at the node 136. The signal HiZ may enable / disable the operation of the bottom phase 111. The power converter circuit 100 may include a first clock generator 142 that may generate a first clock φ 1146, and a second clock generator 144 that may generate a second clock φ 2148. The first clock 146 may be applied to a gate terminal 150 of the first switch 102, and an inversion of the first clock 146 may be applied to a gate terminal 154 of the second switch 104. The second clock 148 may be applied to a gate terminal 160 of the third switch 106 via an OR gate 138, and an inversion of the second clock 148 may be applied to a gate terminal 167 of the fourth switch 108 via an AND gate 140. Although one particular control circuit and algorithm are discussed above, those skilled in the art having the benefit of the present disclosure will appreciate that other control circuit architectures and control algorithms may be used for the series stacked phase DC-DC power converter circuit 100 and are within the scope of the present disclosure.

[0029] Referring now to FIGS. 1 and 2 simultaneously, an embodiment of a switching sequence and timing diagram of the circuit 100 is described. FIG. 2 illustrates waveforms of a signal (Φ1) on the gate of the first switch 102, a signal on the intermediate node 107 (VM), a signal HiZ at the node 136, and an output voltage (Vout) at the output terminal 118. During a first time period 216, where in FIG. 208 the bottom phase 111 is switching, the signal HiZ is low, so the bottom phase 111 is enabled and can switch, while the top phase 109 can switch simultaneously, as shown in FIG. 202, where the timing Φ1 at the gate of the first switch 102 is switching. During the first time period 216, the voltage at the intermediate node 107 (VM) is stable, and then rapidly decreases during time period 212 due to the onset of the positive feedback effect. During time period 212, VM continues to decrease until it reaches 100 mV below Vin / 2, as shown in FIG. 206. The window comparator 128 then triggers the S / R latch 141. This causes the "bottom phase switching" period to end and the second time period 218 to begin, in which the bottom phase 111 is disabled.

[0030] During the second time period 218, in which the bottom phase 111 is disabled, the signal HiZ is high, thus disabling the bottom phase 111, while the top phase 109 continues to switch. During the second time period 218, VM may begin to recover and increase in value. VM continues to increase during the second time period 218 until it reaches 10mV above Vin / 2. The window comparator 128 then triggers the S / R latch 141. This causes the second period to end and a new "bottom phase switching" period to begin. As will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, an acceptable value for the voltage fluctuation on the intermediate node 107 (VM) may be set based on the power converter specifications. Graph 210 shows the voltage (V OUT) at the output terminal 118. As can be seen in Graph 210, V OUT is regulated during the first time period 216. During the second time period 218, when the top phase is switching and the bottom phase is disabled, V OUT may not be able to regulate within the set point. However, this situation may be acceptable because the converter may be overloaded beyond its normally specified operating parameters.

[0031] As will be appreciated by one of ordinary skill in the art having the benefit of this disclosure, the disclosed on / off switching technique for the bottom phase is one technique for reducing the current drawn from the middle node, thereby preventing its degradation. Other techniques may be used, such as blanking the switching cycles (so that the bottom phase switches only, for example, every other cycle), or forcing the duty cycle of the bottom phase to draw less current from the middle node, resulting in a lower high-side on-time. Furthermore, one of ordinary skill in the art having the benefit of this disclosure will recognize that other techniques for monitoring the middle node and more than one set of comparator thresholds may be used, such as a "soft response" may be used to recover from minor degradations of the VM voltage, while a "hard response" may be used for more significant VM degradations.

[0032] As will be appreciated by those of ordinary skill in the art having the benefit of this disclosure, other feedback loops based on voltages and / or currents at other nodes within the series stacked phase DC-DC power converter circuit 100 may be used to monitor the intermediate node. It will be appreciated by those of ordinary skill in the art that there may be alternative methods of controlling the switches in the circuit 100 in a manner that achieves overall loop control, and such methods are within the scope of this disclosure. It will be further appreciated by those of ordinary skill in the art that alternative methods of controlling the switches in the circuit 100 may be used in order to optimize light load efficiency, or minimize area, and / or minimize electromagnetic interference (EMI), and such methods are within the scope of this disclosure.

[0033] Although the system and method for stable intermediate node operation in a series stacked phase DC-DC converter are described and illustrated herein with respect to one specific configuration of a series stacked phase DC-DC power converter circuit, embodiments of the present disclosure are suitable for use with other configurations of DC-DC power converters. For example, a multi-phase DC-DC power converter circuit can employ embodiments of the present disclosure to alternately switch phases for more efficient operation.

[0034] In some embodiments, the described switches may be formed in silicon or any other suitable semiconductor material. In various embodiments, the described switches may be transistors. In some embodiments, the described switches may be metal oxide semiconductor field effect transistors (MOSFETs). In various embodiments, the disclosed MOSFETs may all be formed within a single die well. In some embodiments, the disclosed series stacked phase DC-DC power converter circuits (including transistors and control circuitry) may be monolithically integrated onto a single die. In various embodiments, the top phase and bottom phase stages may be formed on separate individual dies. In some embodiments, the top phase, bottom phase, and logic and control circuitry and any combination thereof may be formed as a group on separate dies, for example, the top phase and bottom phase may be formed on a single die and the logic and control circuitry may be formed on separate dies, or the top phase and bottom phase may be formed on the same die as the logic and control circuitry. In various embodiments, the top phase, the bottom phase, and the logic and control circuits may all be integrated into one electronic package, such as, but not limited to, a quad flat no-lead (QFN) package, or a double flat no-lead (DFN) package, or a ball grid array (BGA) package. In some embodiments, the top phase and the bottom phase may be individually packaged into an electronic package. In various embodiments, the controller circuit and / or the control logic circuit may be integrated into a single die along with the disclosed series stacked phase DC-DC converter.

[0035] In the foregoing description, the embodiments of the present disclosure have been described with reference to many specific details that may be varied for different implementations. Therefore, the description and drawings should be considered illustrative rather than restrictive. The only and exclusive indicator of the scope of the present disclosure, and what the applicant intends to be the scope of the present disclosure, is the literal and equivalent scope of the technical solution set published by this application, in the specific form in which such technical solution is published, including any subsequent corrections. The specific details of a particular embodiment may be combined in any suitable manner without departing from the spirit and scope of the embodiments of the present disclosure.

[0036] Additionally, spatially relative terms such as "bottom" or "top" may be used to describe an element and / or feature in relationship to another element and / or feature(s), such as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as the "bottom" surface may be oriented "above" other elements or features. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0037] As used herein, the terms "and", "or", and "and / or" may include a variety of meanings, which are also expected to depend at least in part on the context in which such terms are used. In general, if used in connection with a list such as A, B, or C, "or" is intended to mean A, B, and C, which are used in an inclusive sense herein, and A, B, or C, which are used in an exclusive sense herein. In addition, as used herein, the term "one or more" may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe a certain combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. In addition, if used in connection with a list such as A, B, or C, the term "at least one of..." may be interpreted to mean any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0038] References throughout this specification to "one example," "an example," "some examples," or "illustrative implementations" mean that the particular features, structures, or characteristics described in conjunction with the features and / or examples may be included in at least one feature and / or example of the claimed subject matter. Thus, the appearance of the phrases "in one example," "an example," "in some examples," or "in some implementations," or other similar phrases, in various places throughout this specification are not necessarily referring to the same features, examples, and / or limitations. Furthermore, particular features, structures, or characteristics may be combined in one or more examples and / or features.

[0039] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, one skilled in the art will appreciate that the claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses generally known to one skilled in the art have not been described in detail in order to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter is not limited to the specific examples disclosed, but that such claimed subject matter may also include all aspects that fall within the scope of the appended claims and their equivalents.

[0040] 100: Series stacked phase DC-DC power converter circuit 102: First switch 104: Second switch 106: The third switch 107: Intermediate node 108: The fourth switch 109: Top Buck Converter Stage / Top Phase 110: Input terminal 111: Bottom Buck Converter Stage / Bottom Phase 112: Flying Capacitor 114: Inductor 115:Capacitor 116: Inductor 117: Second switch node 118: Output terminal 120: Earth 121: First input 124: Second input 126: Second input 127: First input 128: Window comparator 131:Capacitor 135: Load 136: Node 138: or gate 140: Gate 141: Set-Reset (S / R) Latch 142: First clock generator 144: Second clock generator 146: First Pulse 148: Second Pulse 150: Gate terminal 151: First comparator 152: Source terminal 153: Second comparator 154: Gate terminal 155:Drain terminal 156: Source terminal 157:Drain terminal 158:Logic and control circuits 160: Gate terminal 161: Drain terminal 162: Source terminal 167: Gate terminal 168:Drain terminal 169: Source terminal 175: first switch node 202: Figure 206: Figure 208: Figure 210: Figure 212: Time period 216: First time period 218: Second time period

Claims

1. A power converter circuit comprising: a first buck converter having a first switching node; a second buck converter having a second switching node and coupled to the first buck converter at an intermediate node; an input terminal coupled to the first buck converter; an output terminal coupled to the first switching node and the second switching node; and a control circuit coupled to the first buck converter and the second buck converter.

2. The power converter circuit of claim 1, wherein the control circuit is configured to enable the first buck converter to operate continuously, and wherein the control circuit is further configured to: sense a voltage at the intermediate node to obtain a sense voltage; compare the sense voltage with a first threshold voltage, and in response to the sense voltage being below the first threshold voltage, disenable the operation of the second buck converter; and compare the sense voltage with a second threshold voltage, and in response to the sense voltage being above the second threshold voltage, enable the operation of the second buck converter.

3. The power converter circuit of claim 1, wherein the first buck converter and the second buck converter are configured to control the power transfer from the input terminal to the output terminal.

4. The power converter circuit of claim 2, wherein the control circuit includes a window comparator, the window comparator including a first comparator and a second comparator.

5. The power converter circuit of claim 4, wherein the first comparator is configured to receive the voltage at the intermediate node and to receive the first threshold voltage.

6. The power converter circuit of claim 5, wherein the second comparator is configured to receive the voltage at the intermediate node and the second threshold voltage.

7. The power converter circuit of claim 5, wherein the output terminal is coupled to the first switching node via a first inductor.

8. The power converter circuit of claim 5, wherein the output terminal is coupled to the second switching node via a second inductor.

9. The power converter circuit of claim 7, wherein the first inductor is coupled to the first switching node via a first capacitor.

10. The power converter circuit of claim 9, wherein a second capacitor is coupled between the intermediate node and a ground.

11. The power converter circuit of claim 1, wherein the first buck converter and the second buck converter are configured to generate an output voltage at the output terminal that is lower than an input voltage at the input terminal.

12. A method of operating a circuit, the method comprising: A first buck converter is provided, the first buck converter having a first switching node; A second buck converter is provided, the second buck converter having a second switching node and coupled to the first buck converter at an intermediate node; an input terminal is provided, coupled to the first buck converter; an output terminal is provided, coupled to the first switching node and the second switching node; and a control circuit is provided, coupled to the first buck converter and the second buck converter.

13. The method of claim 12, further comprising: continuously operating the first buck converter by means of the control circuit; sensing a voltage at the intermediate node by means of the control circuit to obtain a sense voltage; comparing the sense voltage with a first threshold voltage by means of the control circuit; and stopping the operation of the second buck converter by means of the control circuit in response to the sense voltage being at a voltage lower than the first threshold voltage.

14. The method of claim 13, further comprising: comparing the sensed voltage with a second threshold voltage by means of the control circuit; and stopping the operation of the second buck converter by means of the control circuit in response to the sensed voltage being at a voltage lower than the second threshold voltage.

15. The method of claim 12, further comprising generating an output voltage at the output terminal that is lower than an input voltage at the input terminal by the first buck converter and the second buck converter.

16. The method of claim 12, further comprising controlling the power transfer from the input terminal to the output terminal by the first buck converter and the second buck converter.

17. A power converter circuit comprising: a first buck converter, the first buck converter including a first switch having a first gate terminal, a first drain terminal and a first source terminal, and a second switch having a second gate terminal, a second drain terminal and a second source terminal, the first source terminal being coupled to the second drain terminal at a first switch node; a second buck converter, the second buck converter including a third switch having a third gate terminal, a third drain terminal and a third source terminal, and a fourth switch having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is connected in series to the first buck converter at an intermediate node such that the third drain terminal is coupled to the second source terminal; and an input terminal coupled to the first drain terminal; The circuit is coupled to one of the output terminals of the first switching node and the second switching node; and to one of the control circuits of the first buck converter and the second buck converter.

18. The power converter circuit of claim 17, wherein the control circuit is configured to enable continuous operation of the first buck converter, wherein the control circuit is further configured to: sense a voltage at the intermediate node to obtain a sense voltage; compare the sense voltage with a first threshold voltage, and in response to the sense voltage being below the first threshold voltage, disenable operation of the second buck converter; and compare the sense voltage with a second threshold voltage, and in response to the sense voltage being above the second threshold voltage, enable operation of the second buck converter.

19. The power converter circuit of claim 17, wherein the first buck converter and the second buck converter are configured to generate an output voltage at the output terminal that is lower than an input voltage at the input terminal.

20. The power converter circuit of claim 17, wherein the first buck converter and the second buck converter are configured to control power transfer from the input terminal to the output terminal.

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