Semiconductor device and method of fabricating the same

Abstract

A semiconductor device includes a substrate having an active region and a well region, and a bit cell on the well region. The bit cell includes a first gate structure and a second gate structure extending across the active region in a first direction and spaced apart in a second direction; a first conductive structure at a first side of the first gate structure; a second conductive structure between a second side of the first gate structure and a first side of the second gate structure; and a third conductive structure at a second side of the second gate structure. The semiconductor device includes a fourth conductive structure perpendicularly overlapping the well region; a first conductor connected to the first and third conductive structures; a second conductor connected to the fourth conductive structure; and a third conductor connected to the first and second gate structures. The second and fourth conductive structures are electrically connected to the well region.

Description

Technical Field

[0001] none Prior Technology

[0002] Some semiconductor devices include read-only memory (ROM) structures to store information. One type of ROM is programmed or encoded during the manufacturing process of a semiconductor device to provide fixed information that does not change during device operation or when power is off. This type of ROM can be referred to as hardware-configured.

[0003] ROM device density and device performance depend at least in part on routing, such as the routing of bit line conductors, word line conductors, reference voltage conductors, and the like. Congestion in routing can lead to suboptimal conductor dimensions, resulting in increased resistance and limiting the increase in bit cell density. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] Figure 1A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 1B is a cross-sectional view corresponding to line A-A' in Figure 1A, and Figure 1C is a cross-sectional view corresponding to line B-B' in Figure 1A. Figure 2A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 2B is a cross-sectional view corresponding to line A-A' in Figure 2A, and Figure 2C is a cross-sectional view corresponding to line B-B' in Figure 2A. Figure 3A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 3B is a cross-sectional view corresponding to line A-A' in Figure 3A, and Figure 3C is a cross-sectional view corresponding to line B-B' in Figure 3A. Figure 4A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 4B is a cross-sectional view corresponding to line A-A' in Figure 4A, and Figure 4C is a cross-sectional view corresponding to line B-B' in Figure 4A. Figure 5A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 5B is a cross-sectional view corresponding to line A-A' in Figure 5A, and Figure 5C is a cross-sectional view corresponding to line B-B' in Figure 5A. Figure 6A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 6B is a cross-sectional view corresponding to line A-A' in Figure 6A, and Figure 6C is a cross-sectional view corresponding to line B-B' in Figure 6A. Figure 7A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 7B is a cross-sectional view corresponding to line A-A' in Figure 7A, and Figure 7C is a cross-sectional view corresponding to line B-B' in Figure 7A. Figure 8A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 8B is a cross-sectional view corresponding to line A-A' in Figure 8A, and Figure 8C is a cross-sectional view corresponding to line B-B' in Figure 8A. Figure 9A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 9B is a cross-sectional view corresponding to line A-A' in Figure 9A, and Figure 9C is a cross-sectional view corresponding to line B-B' in Figure 9A. Figure 10A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 10B is a cross-sectional view corresponding to line A-A' in Figure 10A, and Figure 10C is a cross-sectional view corresponding to line B-B' in Figure 10A. Figure 11A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 11B is a cross-sectional view corresponding to line A-A' in Figure 11A, and Figure 11C is a cross-sectional view corresponding to line B-B' in Figure 11A. Figure 12A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 12B is a cross-sectional view corresponding to line A-A' in Figure 12A, and Figure 12C is a cross-sectional view corresponding to line B-B' in Figure 12A. Figure 13A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 13B is a cross-sectional view corresponding to line A-A' in Figure 13A, and Figure 13C is a cross-sectional view corresponding to line B-B' in Figure 13A. Figure 14A is a schematic plan view of a semiconductor device according to at least one embodiment, Figure 14B is a cross-sectional view corresponding to line A-A' in Figure 14A, Figure 14C is a cross-sectional view corresponding to line B-B' in Figure 14A, and Figure 14D is a cross-sectional view corresponding to line C-C' in Figure 14A. Figure 15 is a flowchart of a method for manufacturing a semiconductor device according to at least one embodiment. Figure 16 is a block diagram of an IC device according to at least one embodiment. Figure 17 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 18 is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to at least one embodiment. Implementation

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components, values, steps, operations, materials, configurations, or the like are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, or the like are also contemplated. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0008] A ROM semiconductor device according to at least one embodiment is hardware-configured and includes conductive structures, such as well zones or back conductors, that provide one or more of bit lines, word lines, and / or reference signals and / or voltages. Using one or more of well zones or back conductors provides greater routing flexibility compared to routing using a single metal layer. Therefore, while another approach provides all of the bit lines, word lines, and / or reference signals and / or voltages in a single metal layer (e.g., the M0 layer), embodiments provide more routing options by routing the bit lines, word lines, and / or reference signals and / or voltages in one or more of a front metal layer such as the M0 layer, a well zone, and / or a back metal layer such as the BMO layer.

[0009] In some embodiments, ROM density, i.e., ROM data capacity per unit area, is increased by providing additional routing flexibility and reducing the number of conductors in a given metal layer. In some embodiments, cell height is reduced by reducing the number of conductors in a given metal layer. In some embodiments, ROM cells are overlaid on two conductors in the MO layer, and cell height (in the X-axis direction) is reduced by replacing the MO conductors with one or more of the well zone or back-side conductors. In some embodiments, cell height is about 100 nm or less.

[0010] In some embodiments, using pre-existing process operations, such as by modifying an existing mask, the ROM semiconductor device provides electrical pathways, for example, through well regions, to provide increased bit cell density without incurring significant additional process costs.

[0011] Figure 1A is a schematic plan view of a semiconductor device 100 according to at least one embodiment, Figure 1B is a cross-sectional view corresponding to line A-A' in Figure 1A, and Figure 1C is a cross-sectional view corresponding to line B-B' in Figure 1A.

[0012] Referring to Figure 1A, the semiconductor device 100 includes a substrate 110, which includes an active region 114 and a well region 118 below the active region 114.

[0013] In some embodiments, substrate 110 comprises elemental semiconductors, including silicon, germanium, or the like in crystalline, polycrystalline, or amorphous structures; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or the like; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some embodiments, substrate 100 has gradient SiGe characteristics, wherein the Si and Ge composition varies from one ratio at one location in the substrate to another ratio at another location. In some embodiments, a SiGe alloy is formed over a silicon layer. In some embodiments, substrate 110 is a strained SiGe substrate. In some embodiments, substrate 110 has a semiconductor-on-insulator structure, for example, a silicon-on-insulator (SOI) structure. In some embodiments, substrate 110 includes a doped epitaxial layer and / or a buried layer. In some embodiments, substrate 110 has a multilayer structure or includes a multilayer compound semiconductor structure.

[0014] In some embodiments, well region 118 is an N-type well region, that is, a region doped with one or more N-type dopants. In some embodiments, well region 118 is a P-type well region, that is, a region doped with one or more P-type dopants. In some embodiments, well region 118 is silicon, silicon-germanium, or the like.

[0015] In Figure 1A, a bit cell region 120 encoding a one-bit logic value (e.g., logic "1") overlaps perpendicularly with a well region 118. The bit cell region 120 includes a first gate structure 122a extending across the active region 114 in a first direction (parallel to the X-axis), and a second gate structure 122b extending across the active region 114 in the first direction and spaced apart from the first gate structure 122a in a second direction (parallel to the Y-axis). The first gate structure 122a and the second gate structure 122b are configured along the second direction with a first pitch P1. In some embodiments, the first pitch P1 is determined based on the center-to-center distance between adjacent gate structures in the second direction (i.e., those without intermediate gate structures). A first conductive structure 126a is located at a first side 122a-1 of a first gate structure 122a; a second conductive structure 126b is located between a second side 122a-2 of the first gate structure 122a and a first side 122b-1 of the second gate structure 122b; and a third conductive structure 126c is located at a second side 122b-2 of the second gate structure 122b. The first, second, and third conductive structures 126a-126c extend in a first direction. The first conductive structure 126a and the second conductive structure 126b are configured along a second direction with a second pitch P2. In some embodiments, the second pitch P2 is determined based on the center-to-center distance between adjacent conductive structures in the second direction (i.e., those without intermediate conductive structures). The second conductive structure 126b and the third conductive structure 126c are also configured along the second direction with a second pitch P2.

[0016] The first gate structure 122a and the second gate structure 122b are used to receive signals, such as word line signals, to control the conductivity of the corresponding channel regions of the active region 114. In Figures 1A to 1C, the bit cell region 120 is shown as including two gate structures, namely, the first gate structure 122a and the second gate structure 122b. In some embodiments, a single gate structure is provided. In still other embodiments, two or more gate structures are provided. Increasing the number of gate structures increases the drive current, although increasing the number of gate structures also increases the cell width.

[0017] In some embodiments, the first gate structure 122a and the second gate structure 122b comprise polycrystalline silicon or metal. In some embodiments, the first gate structure 122a and the second gate structure 122b comprise multiple layers, such as a gate dielectric layer spanning or covering the active region 114, a gate electrode comprising a work function metal layer formed above the gate dielectric layer, a bulk conductive layer formed above the work function metal layer, and the like. In some embodiments, the gate dielectric layer comprises one or more high-k layers (or one or more layers of high-k dielectric materials) of a high-k dielectric material, such as aluminum oxide, hafnium oxide, hafnium silicon oxide, lanthanum oxide, strontium titanate, titanium oxide, yttrium oxide, zirconium oxide, or the like. In some embodiments, the work function metal layer comprises one or more of aluminum, molybdenum, platinum, ruthenium, tantalum carbide, tantalum carbonitride, tantalum nitride, tantalum nitride silicon, titanium, titanium nitride, titanium nitride silicon, tungsten, or the like. In some embodiments, the work function metal layer comprises multiple material layers of the same or different types (e.g., all n-type work function metals or all p-type work function metals) to achieve the desired threshold voltage. In some embodiments, the bulk conductive layer comprises one or more of aluminum, cobalt, copper, ruthenium, tungsten, or the like. In some embodiments, the first gate structure 122a and the second gate structure 122b comprise other material layers, such as one or more of a barrier layer, an adhesive layer, a hard masking layer, a capping layer, or the like. In some embodiments, each layer in the first gate structure 122a and the second gate structure 122b is formed by atomic layer deposition, chemical or thermal oxidation, chemical vapor deposition, physical vapor deposition, plating, or the like.

[0018] The first conductive structure 126a, the second conductive structure 126b, and the third conductive structure 126c include a conductive material, such as one or more metals, such as copper, silver, aluminum, tungsten, titanium, nickel, tin, cobalt, or the like, or another conductive material, such as a doped semiconductor or epitaxial material doped at a level sufficient to provide low resistivity, such as one or more of arsenic, boron, gallium, phosphorus, silicon, silicon carbide, silicon germanium, or the like. The first conductive structure 126a, the second conductive structure 126b, and the third conductive structure 126c may be referred to as an MD pattern, an MD segment, an MD structure, or the like.

[0019] A fourth conductive structure 126d, perpendicularly overlapping with well region 118, is spaced apart from the third conductive structure 126c in a second direction. In some embodiments, the fourth conductive structure 126d is positioned at a location in the second direction from the third conductive structure 126c by a distance n x a second pitch P2, where n is an integer of 1 or greater. In some embodiments, the fourth conductive structure 126d is formed of the same material used to form the first conductive structure 126a, the second conductive structure 126b, and the third conductive structure 126c. In some embodiments, one or more of the first conductive structure 126a, the second conductive structure 126b, the third conductive structure 126c, and the fourth conductive structure 126d are formed of a material different from one or more of the other three conductive structures.

[0020] A first conductor 130 is electrically connected to a first conductive structure 126a and a third conductive structure 126c. The first conductor 130 extends in a second direction and overlaps perpendicularly with the active region 114. The first conductor 130 is electrically connected to the first conductive structure 126a via a first via 132a. The first conductor 130 is electrically connected to the third conductive structure 126c via a second via 132b. In Figures 1A to 1C, the first conductor 130 is configured as a bitline (BL) of the bit cell region 120. In some embodiments, the first conductor 130 is used to provide a reference voltage, such as VSS.

[0021] The second conductor 134 is electrically connected to the fourth conductive structure 126d via the third via 132c. The second conductor 134 extends in a second direction and overlaps perpendicularly with the active region 114. The second conductor 134 is used to provide a reference voltage, for example, a constant voltage. In Figures 1A to 1C, the second conductor is used to provide a voltage VSS. In some embodiments, the second conductor 134 is used to provide a reference voltage other than VSS. In some embodiments, the second conductor 134 is configured as a bit line.

[0022] The third conductor 138 extends in the second direction and is electrically connected to the first gate structure 122a and the second gate structure 122b. Referring to Figure 1C, the third conductor 138 is electrically connected to the first gate structure 122a via the first gate via 140a. The third conductor 138 is electrically connected to the second gate structure 122b via the second gate via 140b. In Figures 1A to 1C, the third conductor 138 is configured as a wordline (WL).

[0023] The first conductor 130, the second conductor 134, and the third conductor 138 comprise one or more conductive materials, such as one or more metals such as aluminum, copper, nickel, silver, tin, titanium, tungsten, or the like. In some embodiments, each of the first conductor 130, the second conductor 134, and the third conductor 138 is formed of the same material in the same layer (e.g., the same metal layer, such as MO). In some embodiments, one or more of the first conductor 130, the second conductor 134, and the third conductor 138 are formed of a material different from one or more of the other three conductors.

[0024] The first, second, and third vias 132-132c comprise one or more conductive materials, such as metals like aluminum, copper, tantalum, titanium, tungsten, or similar materials. In some embodiments, each of the first, second, and third vias 132-132c is formed of the same material in the same layer (e.g., VD). In some embodiments, one or more of the first, second, and third vias 132-132c are formed of a material different from one or more of the other two vias 132-132c.

[0025] The first gate via 140a and the second gate via 140b comprise one or more conductive materials, such as one or more metals, including aluminum, copper, tantalum, titanium, tungsten, or the like. In some embodiments, each of the first gate via 140a and the second gate via 140b is formed of the same material in the same layer (e.g., VG). In some embodiments, one of the first gate via 140a and the second gate via 140b is formed of a different material than the other of the first gate via 140a and the second gate via 140b.

[0026] In semiconductor device 100, the height H1 of a first conductor 130 determined in a first direction is substantially the same as the height H2 of a second conductor 134 determined in the first direction, and the first conductor 130 and the second conductor 134 are substantially centered along the same virtual line or track extending in the second direction. Heights H1 and H2 are greater than the height H3 of a third conductor 138 in the second direction. Increasing height H1 and / or height H2 helps to reduce the resistance on the first conductor 130 and / or the second conductor 134, while decreasing height H3 helps to maintain the gap between the first conductor 130 and the third conductor 138 in the first direction and helps to reduce the cell height. In at least one embodiment, such as the embodiments in Figures 1A to 1C where the first conductor 130 is configured as a bit line, increasing height H1 helps to reduce the resistance of the bit line.

[0027] Referring again to Figure 1A, the third conductor 138 is spaced apart from the well region 118 in the first direction, that is, the third conductor 138, the first gate via 140a, and the second gate via 140b do not overlap perpendicularly with the well region 118. In some embodiments, the third conductor 138 overlaps completely or partially perpendicularly with the well region 118, and / or the first gate via 140a and the second gate via 140b overlap completely or partially perpendicularly with the well region 118. In some embodiments, the third conductor 138 and / or the first gate via 140a and the second gate via 140b overlap completely or partially perpendicularly with the well region 118, while being spaced apart from the active region 114 in the first direction. In some embodiments, the third conductor 138 and / or the first gate via 140a and the second gate via 140b overlap completely or partially perpendicularly with the active region 114.

[0028] In Figure 1A, the first, second, third, and fourth conductive structures 126a-126d are in the MD layer, and the first conductor 130, the second conductor 134, and the third conductor 138 are in the M0 layer. M0 refers to the first metal layer in a sequence of metal layers, such as M0, M1, M2, M3, M4, M5, and the like, where M0 is the first metal layer above the MD layer, and the MD layer is a conductive layer (also called metal-to-diffusion layer), forming source / drain contacts directly on the active region 114 (sometimes called the oxide-defined or OD region), and is generally at the same level as the polycrystalline silicon layer or gate layer. In some embodiments, one or more of the metal layers, such as M0, M1, M2, M3, M4, M5, and the like, are formed of one or more of aluminum, copper, tantalum, titanium, tungsten, or the like. In some embodiments, one or more of the first conductor 130, the second conductor 134, and the third conductor 138 are in a layer other than the M0 layer, for example, in a layer such as M1, M2, or similar above the M0 layer. In still other embodiments, one or more of the first conductor 130, the second conductor 134, and the third conductor 138 are in a rear-side metal layer, such as in BMO as described below.

[0029] Referring to Figure 1B, the active region 114 includes a plurality of nanostructures, namely, a first nanostructure 114a, a second nanostructure 114b, and a third nanostructure 114c, which are at least partially surrounded by a dielectric material 112. In some embodiments, the nanostructures serve as channels for one or more transistors. In some embodiments, the transistors are gate-all-around field-effect transistors (GAA FETs). In some embodiments, other transistor structures are used. The first gate structure 122a and the second gate structure 122b surround the channel region of nanostructures 114a-114c.

[0030] In some embodiments, nanostructures 114a-114c comprise semiconductor materials, such as silicon or silicon compounds, such as silicon germanium, or the like. In some embodiments, nanostructures 114a-114c have dimensions in the range of several nanometers and have an elongated shape extending parallel to the Y-axis. In some embodiments, nanostructures 114a-114c are nanowires, nanosheets, nanotubes, or the like. In some embodiments, nanostructures 114a-114c have a cross-sectional profile (e.g., in the XZ plane) that is rectangular, circular, square, annular, elliptical, hexagonal, or the like. In some embodiments, nanostructures 114a-114c comprise one or more layers of semiconductor materials with n-type or p-type doping in a continuous volume. In some embodiments, individual nanosheet layers comprise a single layer or multiple layers of semiconductor material.

[0031] The first epitaxial structure 116a, the second epitaxial structure 116b, and the third epitaxial structure 116c each surround and are electrically connected to the nanostructures 114a-114c to provide a source / drain (s / d) region adjacent to the first gate structure 122a and the second gate structure 122b. The second epitaxial structure 116b is positioned relative to the second direction between the first epitaxial structure 116a and the third epitaxial structure 116c. The first, second, and third conductive structures 126a-126c are perpendicularly overlapped and electrically connected to their corresponding counterparts in the first, second, and third epitaxial structures 116a-116c.

[0032] In some embodiments, the first, second, and third epitaxial structures 116a-116c comprise semiconductor materials, such as epitaxially grown silicon-germanium or boron-doped silicon, or epitaxially grown semiconductors, such as silicon doped with a dopant, or one or more of carbon, phosphorus, or the like. In some embodiments, the dopant is supplied via an implantation process after epitaxial growth. In some embodiments, the epitaxial structure is grown from the surface of well region 118.

[0033] The second epitaxial structure 116b is electrically connected to the well region 118. The fourth epitaxial structure 116d surrounds the nanostructures 114a-114c and is electrically connected to both the nanostructures 114a-114c and the well region 118. In some embodiments, the fourth epitaxial structure 116d is formed of the same material used to form the first, second, and third epitaxial structures 116a-116c. In some embodiments, one or more of the first, second, third, and fourth epitaxial structures 116a-116d are formed of a material different from one or more of the other materials in the first, second, third, and fourth epitaxial structures 116a-116c.

[0034] Semiconductor device 100 includes an insulating structure 142 on a well region 118 and between the well region 118 and an overlying active region 114. In some embodiments, the insulating structure 142 includes a plurality of insulating layers or structures, such as a first insulating layer directly on the well region 118 and one or more additional insulating layers on the first insulating layer, each of the first and one or more additional insulating layers being formed of the same or different insulating materials. In some embodiments, the insulating structure 142 is an oxide layer or includes an oxide layer. In some embodiments, the insulating structure 142 is a flexible bottom isolation structure or includes a flexible bottom isolation structure. In some embodiments, the insulating structure 142 includes a dielectric material, such as one or more of silicon oxide, silicon nitride, SiOCN, or the like. In some embodiments, the dielectric material is formed by a process including atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like.

[0035] The second epitaxial structure 116b and the fourth epitaxial structure 116d extend in a third direction (parallel to the Z-axis) through an opening in the insulating structure 142 and are electrically connected to the well region 118. Using the well region 118 to connect the second epitaxial structure 116b and the fourth epitaxial structure 116d together allows for a reduction in the number of conductors in the metal layer (e.g., the M0 layer) by using the well region 118 as a conductor. This provides design and / or layout flexibility by enabling the use of wider, lower-resistance conductors for bit lines or the like and / or by reducing the overall cell height.

[0036] In some embodiments, the second epitaxial structure 116b and the fourth epitaxial structure 116d are formed by epitaxial growth from the exposed surface of the well region 118. In some embodiments, the surface of the well region 118 is exposed by patterning an insulating structure 142 to form openings therein.

[0037] In some embodiments, the openings in the insulation structure 142 are formed using existing lithography techniques during the manufacturing process, for example, by modifying an existing mask, rather than using additional lithography techniques. Modifying an existing mask instead of using additional lithography techniques helps to minimize costs.

[0038] In Figures 1A and 1B, the first region 146a is a region without an insulating structure 142 and where the second epitaxial structure 116b is electrically connected to the well region 118. The second region 146b is a region without an insulating structure 142 and where the fourth epitaxial structure 116d is electrically connected to the well region 118. Therefore, both the second epitaxial structure 116b and the fourth epitaxial structure 116d are short-circuited to the well region 118. The first region 146a and the second region 146b may be referred to as non-isolated regions. In some embodiments, the selective absence or presence of non-isolated regions in the bit cells is used to encode logic values ​​(e.g., "0" and "1" respectively) during device manufacturing, thereby providing an intuitive ROM with fixed data encoded in hardware.

[0039] In Figure 1A, the first region 146a is shown as having a dimension extending beyond the height of the active region 114 in a first direction and a dimension extending beyond the width of the second conductive structure 126b in a second direction. In some embodiments, as shown in Figure 1B, the first region 146a is smaller in one or both of the first and second directions. In some embodiments, the first region 146a has the same area as the coverage area of ​​the second epitaxial structure 116b, that is, the first region 146a and the second epitaxial structure 116b have the same height in the first direction and the same width in the second direction.

[0040] Similarly, in Figure 1A, the second region 146b is shown as having a dimension extending beyond the height of the active region 114 in the first direction and a dimension extending beyond the width of the fourth conductive structure 126d in the second direction. In some embodiments, as shown in Figure 1B, the second region 146b is smaller in one or both of the first and second directions. In some embodiments, the second region 146b has the same area as the coverage area of ​​the second epitaxial structure 116b, i.e., the second region 146b and the second epitaxial structure 116b have the same height in the first direction and the same width in the second direction. The dimensions of the first region 146a and the second region 146b may vary, as long as these dimensions are sufficient to provide an electrical connection between the second conductive structure 126b and the fourth conductive structure 126d and the underlying well region 118.

[0041] Well region 118 electrically connects the second epitaxial structure 116b and the fourth epitaxial structure 116d. A reference voltage, such as VSS, is supplied to the second conductor 134 via an electrical path through well region 118, and thus to the second conductive structure 126b. The first conductor 130 is configured as a bit line, and the third conductor 138 is configured as a word line.

[0042] As described above, the second epitaxial structure 116b is electrically connected to the well region 118, and thus electrically connected to the reference voltage VSS supplied to the second conductor 134. Therefore, the bit cell region 120 encodes a first logic value, for example, logic "1". In other words, the existence of the non-isolated region of the first region 146a (where the second epitaxial structure 116b is on the well region 118) means that the second epitaxial structure 116b is electrically connected to the well region 118, and the bit cell region 120 encodes a first logic value, for example, logic "1".

[0043] In some embodiments described below, the non-isolated region is missing, i.e., the insulating structure 142 exists below the second epitaxial structure 116b, such that the second epitaxial structure 116b is not electrically connected to the well region 118, and therefore the bit unit encodes a second logic value, for example, logic "0". In other words, the absence of the non-isolated region of the first region 146a (where the second epitaxial structure 116b is on the well region 118) means that the second epitaxial structure 116b is electrically disconnected from the well region 118, and the bit unit encodes a second logic value, for example, logic "0".

[0044] Therefore, the logic value encoded by bit cell region 120 is determined by the presence or absence of the insulating structure 142 between the second epitaxial structure 116b and the well region 118. In other words, the logic value encoded by bit cell region 120 is determined by the absence or presence of the non-isolated region (where the second epitaxial structure 116b is on the well region 118).

[0045] As described in further detail below, in some embodiments, a ROM having a plurality of bit units is encoded using an electrical connection to and from well 118, wherein logic values ​​of "1" and "0" are encoded by the absence of a non-isolated region (e.g., for "1") or the presence of a non-isolated region (e.g., for "0").

[0046] Figure 2A is a schematic plan view of a semiconductor device 200 according to at least one embodiment, Figure 2B is a cross-sectional view corresponding to line A-A' in Figure 2A, and Figure 2C is a cross-sectional view corresponding to line B-B' in Figure 2A.

[0047] The components of semiconductor device 200 that are similar to those of semiconductor device 100 have corresponding component symbols, but with the addition of 100. The main focus will be on describing the features of semiconductor device 200 that differ from those of semiconductor device 100.

[0048] Referring to Figure 2A, the semiconductor device 200 is an example of a 2T unit type device (2T = two transistors), wherein bit cell regions 220 encode first and second logic values ​​that are different from each other, for example

[01] . The first logic value, for example, logic "0", is encoded in the first bit cell 220a. The second logic value, for example, logic "1", is encoded in the second bit cell 220b corresponding to the bit cell region 120 in Figure 1A. In the semiconductor device 200, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to well region 218, respectively.

[0049] In semiconductor device 200, a first conductor 230 extends in a second direction and overlaps perpendicularly with the active region 214, and is configured as a bit line. Additionally, a second conductor 234 extends in the second direction along the same virtual line or track as the first conductor 230 and overlaps perpendicularly with the active region 214, and is used to provide VSS. The first conductor 230 is electrically connected to a first epitaxial structure 216a (via via 232a and conductive structure 226a), a third epitaxial structure 216c (via via 232b and conductive structure 226c), and a fifth epitaxial structure 216e (via via 232d and conductive structure 226e).

[0050] The first region 246a in Figure 2A is a region without an insulating structure 242 (see Figures 2B and 2C) or with an opening therein, therefore the second epitaxial structure 216b (see Figures 2B and 2C) is electrically connected to the well region 218. The second region 246b in Figure 2A is a region without an insulating structure 242 or with an opening therein, therefore the fourth epitaxial structure 216d (see Figures 2B and 2C) is electrically connected to the well region 218. Connecting the second epitaxial structure 216b and the fourth epitaxial structure 216d together using the well region 218 allows for a reduction in the number of conductors in the metal layer (e.g., the M0 layer), thereby providing layout flexibility, such as allowing the use of wider, lower-resistance conductors for bit lines or the like, and / or a reduction in overall cell height. The first region 246a and the second region 246b may be referred to as non-isolated regions.

[0051] The second epitaxial structure 216b is electrically connected to the well region 218, and therefore electrically connected to the reference voltage VSS supplied to the second conductor 234. Thus, in the same manner as the bit cell region 120 described above, the second bit cell 220b encodes a first logic value, such as logic "1". In other words, the presence of the non-isolated region of the first region 246a (where the second epitaxial structure 216b is on the well region 218) means that the second epitaxial structure 216b is electrically connected to the well region 218, and the second bit cell 220b encodes a first logic value, such as logic "1".

[0052] On the other hand, in the first element unit 220a, a non-isolated region is missing below the fifth epitaxial structure 216e (see Figures 2B and 2C). That is, the insulating structure 242 exists below the fifth epitaxial structure 216e, so that the fifth epitaxial structure 216e is not electrically connected to the well region 218. Therefore, the first element unit 220a encodes a second logic value, such as logic "0". In other words, the absence of the non-isolated region (where the fifth epitaxial structure 216e is on the well region 218) means that the fifth epitaxial structure 216e is electrically disconnected from the well region 218. Therefore, the first element unit 220a encodes a second logic value, such as logic "0". In Figures 2A to 2C, the sixth epitaxial structure 216f is electrically floating. In some embodiments, a voltage or signal may be applied to the sixth epitaxial structure 216f.

[0053] The logic value encoded by bit cell region 220, for example

[01] , is determined by the presence or absence of insulating structure 242, which isolates the fifth epitaxial structure 216e and the second epitaxial structure 216b from well region 218. In other words, the logic value encoded by bit cell region 220 is determined by the presence or absence of non-isolated region (where the fifth epitaxial structure 216e and the second epitaxial structure 216b are on well region 218).

[0054] In Figures 2A to 2C, conductor 238a is electrically connected to gate structures 222c and 222d and configured as the first word line WL0. Conductor 238b is electrically connected to gate structures 222a and 222b and configured as the second word line WL1. Conductors 238a and 238b are substantially aligned along the same virtual line or track in the second direction.

[0055] In the semiconductor device 200, address input is adjusted using a first word line WL0 and a second word line WL1, and conductor 230 is used as a bit line to receive data output from the transistor in the bit cell area 220 of the ROM, thereby reading ROM data, that is, data encoded in the first bit cell 220a and the second bit cell 220b of the bit cell area 220. In some embodiments, the second bit cell 220b having a non-isolated region 246b is set to correspond to logic "1", and the data read from the ROM of the semiconductor device 200 is

[01] . In some embodiments, the logic value is inverted, and the second bit cell 220b having a non-isolated region 246b is set to correspond to logic "0", and the data read from the ROM of the semiconductor device 200 is

[10] . In some embodiments, reading data from the semiconductor device 200 includes applying word line signals to a first word line WL0 and a second word line WL1 (i.e., conductors 238a, 238b), supplying VSS to the bit cell region 220 using conductor 234 and well region 218, reading a first logic value, such as logic "0", from the first bit cell 220a (where the sixth epitaxial structure 216f is not electrically connected to the well region 218, for example, floating), and reading a second logic value, such as logic "1", from the second bit cell 220b (where the second epitaxial structure 216b corresponds to the non-isolated region 246a and is therefore electrically connected to the well region 218, where the well region 218 is to be supplied with VSS).

[0056] The above description of semiconductor device 200 is an example of a two-bit ROM that encodes two different logic values ​​(e.g.,

[01] ). It should be understood that semiconductor device 200 may be manufactured such that both the second epitaxial structure 216b and the sixth epitaxial structure 216f are connected to well region 218 to encode two identical logic values, e.g.,

[11] , or that both the second epitaxial structure 216b and the sixth epitaxial structure 216f are isolated from well region 218 to encode two identical logic values, e.g.,

[00] . In various embodiments, semiconductor device 200 provides more or fewer transistors and / or bit cells, and the number of encoded bits is one or more. In at least one embodiment, semiconductor device 200 is implemented using a unit of 2 CPP. In other embodiments, larger or smaller CPPs are used.

[0057] Figure 3A is a schematic plan view of a semiconductor device 300 according to at least one embodiment, Figure 3B is a cross-sectional view corresponding to line A-A' in Figure 3A, and Figure 3C is a cross-sectional view corresponding to line B-B' in Figure 3A.

[0058] The components in semiconductor device 300 that are similar to those in semiconductor device 200 have corresponding component symbols, but with the addition of 100. The main focus will be on describing the differences between semiconductor device 300 and semiconductor device 200.

[0059] Referring to Figure 3A, the semiconductor device 300 is an example of a 2T cell type device, wherein the bit cell regions 320 encode first and second logic values ​​that are different from each other, for example

[01] . The first logic value, for example, logic "0", is encoded in the first bit cell 320a. The second logic value, for example, logic "1", is encoded in the second bit cell 320b. In the semiconductor device 300, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to the well region 318, respectively.

[0060] The first region 346a in Figure 3A is a region without an insulating structure 342 (see Figures 3B and 3C) or with an opening therein; therefore, the second epitaxial structure 316b (see Figures 2B and 2C) is electrically connected to the well region 318. The second region 346b in Figure 3A is a region without an insulating structure 342 or with an opening therein; therefore, the fourth epitaxial structure 316d (see Figures 3B and 3C) is electrically connected to the well region 318. The first region 346a and the second region 346b can be referred to as non-isolated regions.

[0061] In Figure 3A, the first conductor 330 extends in the second direction to overlap perpendicularly with the second region 346b. In Figures 3A to 3C, the first conductor 330 is configured as a bit line of the bit cell region 320. The first conductor 330 extends in the second direction on both the left and right sides of Figure 3A. By extending the first conductor 330, bit line connections are provided at both ends of the first conductor 330. Compared to the first conductor 230 of the bit cell region 220 of the semiconductor device 200, this results in additional connections to the bit lines, such as input / output (I / O) connections, and / or provides greater routing flexibility for connections to the bit lines.

[0062] In Figure 3A, a reference voltage (e.g., VSS) is provided to the bit cell region 320 by conductor 339, which extends in a second direction in a position aligned with the normals of word line conductors 338a and 338b. Conductor 339 is offset relative to the bit lines in the cell height direction, i.e., in the first direction. Therefore, in Figure 2A, the reference voltage conductor 234 is aligned with the bit line conductor 230 along the second direction, while in Figure 3A, the reference voltage conductor 339 is not aligned with the bit line conductor 330, but is offset in the first direction to align with the word line conductors 338a and 338b.

[0063] More specifically, a reference voltage (e.g., VSS) is supplied to conductor 339. Referring to Figure 3C, conductor 339 is electrically connected to the fourth conductive structure 326d via a third via 332c (e.g., in the VD layer). Therefore, a reference voltage is provided to the fourth conductive structure 326d. Referring to Figure 3B, the fourth conductive structure 326d is electrically connected to the fourth epitaxial structure 316d. The second region 346b in Figure 3B is a region without an insulating structure 342 or with an opening, and the fourth epitaxial structure 316d is electrically connected to the well region 318. Therefore, the reference voltage supplied to the fourth conductive structure 326d is electrically connected to the well region 318 via the fourth epitaxial structure 316d.

[0064] Figure 4A is a schematic plan view of a semiconductor device 400 according to at least one embodiment, Figure 4B is a cross-sectional view corresponding to line A-A' in Figure 4A, and Figure 4C is a cross-sectional view corresponding to line B-B' in Figure 4A.

[0065] The semiconductor device 400 has corresponding element symbols for elements similar to those in the semiconductor device 200, but with the addition of 200. The state of the semiconductor device 400 will be described with reference to the semiconductor device 200 in Figures 2A to 2C, that is, the state of the semiconductor device 400 that differs from that of the semiconductor device 200 will be mainly described.

[0066] Referring to Figure 4A, the semiconductor device 400 is an example of a 2T cell type device, wherein the bit cell regions 420 encode first and second logic values ​​that are different from each other, for example

[01] . The first logic value, for example, logic "0", is encoded in the first bit cell 420a. The second logic value, for example, logic "1", is encoded in the second bit cell 420b. In the semiconductor device 400, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to the well region 418, respectively.

[0067] In semiconductor device 400, conductor 430 is provided with a reference voltage VSS, while the first conductor 230 in semiconductor device 200 is configured as a bit line. On the other hand, in semiconductor device 400, conductor 434 is configured as a bit line, while the second conductor 234 in semiconductor device 200 is provided with a reference voltage VSS. Therefore, semiconductor device 200 encodes on the bit line, while semiconductor device 400 encodes on VSS. Other configurations of semiconductor device 400 are similar to those of semiconductor device 200.

[0068] Figure 5A is a schematic plan view of a semiconductor device 500 according to at least one embodiment, Figure 5B is a cross-sectional view corresponding to line A-A' in Figure 5A, and Figure 5C is a cross-sectional view corresponding to line B-B' in Figure 5A.

[0069] The semiconductor device 500 has corresponding element symbols for elements similar to those in the semiconductor device 200, but with the addition of 300. The state of the semiconductor device 500 will be described with reference to the semiconductor device 300 in Figures 3A to 3C, that is, the state of the semiconductor device 500 that differs from that of the semiconductor device 300 will be mainly described.

[0070] Referring to Figure 5A, the semiconductor device 500 is an example of a 2T cell type device, wherein the bit cell regions 520 encode first and second logic values ​​that are different from each other, for example

[01] . The first logic value, for example, logic "0", is encoded in the first bit cell 520a. The second logic value, for example, logic "1", is encoded in the second bit cell 520b. In the semiconductor device 500, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to the well region 518, respectively.

[0071] In semiconductor device 500, conductor 530 is provided with a reference voltage VSS, while the first conductor 330 in semiconductor device 300 is configured as a bit line. Conductor 530 extends in a second direction on both the left and right sides in Figure 5A, thus allowing reference voltage connections at both ends of conductor 530, resulting in additional connections and / or greater routing flexibility. On the other hand, in semiconductor device 500, conductor 539 is configured as a bit line, while conductor 339 in semiconductor device 300 is provided with a reference voltage VSS. Therefore, semiconductor device 300 encodes on the bit line, while semiconductor device 500 encodes on the VSS. Conductor 539 configured as a bit line is offset relative to conductor 530 providing VSS in the cell height direction, i.e., in the first direction. Therefore, in Figure 3A, bit line conductor 539 is aligned with word line conductors 538a and 538b. Other configurations of semiconductor device 500 are similar to those of semiconductor device 300.

[0072] Figure 6A is a schematic plan view of a semiconductor device 600 according to at least one embodiment, Figure 6B is a cross-sectional view corresponding to line A-A' in Figure 6A, and Figure 6C is a cross-sectional view corresponding to line B-B' in Figure 6A.

[0073] The semiconductor device 600 has corresponding element symbols for elements similar to those in the semiconductor device 200, but with the addition of 400. The state of the semiconductor device 600 will be described with reference to the semiconductor device 200 in Figures 2A to 2C, that is, the state of the semiconductor device 600 that differs from that of the semiconductor device 200 will be mainly described.

[0074] Semiconductor device 200 is an example of a ROM implemented as a 2T (2 transistors) device, while semiconductor device 600 is an example of a ROM implemented as a 1.5T cell-type device with a continuous active region structure. The continuous active region structure can also be referred to as a continuous oxide diffusion (CNOD) structure. In some embodiments with a CNOD configuration, the active region pattern is substantially continuous at the side boundaries of the cells, and the regions of the active region pattern that overlap with the side boundaries of the cells are designated for doping, resulting in filled regions in the corresponding semiconductor device. In some embodiments, implementing a ROM device with a CNOD structure reduces cell width while maintaining the integrity of transistor diffusion, thereby providing more uniform strain and / or performance characteristics than structures with disrupted transistor diffusion.

[0075] Referring to Figure 6A, the semiconductor device 600 includes a bit cell region 620 that encodes first and second logic values ​​that are different from each other, for example

[01] . The first logic value, for example, logic "0", is encoded in the first bit cell 320a. The second logic value, for example, logic "1", is encoded in the second bit cell 320b. In the semiconductor device 600, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to the well region 618, respectively.

[0076] Like semiconductor device 200, semiconductor device 600 includes a first conductor 630 extending in a second direction and perpendicularly overlapping with active region 614, configured as a bit line. Additionally, a second conductor 634 extends in the second direction along the same virtual line or track as the first conductor 630 and perpendicularly overlaps with active region 614, serving to provide VSS. In semiconductor device 600, the first conductor 630 is electrically connected to a first epitaxial structure 616a, while in semiconductor device 200, the first conductor 230 is electrically connected to a second epitaxial structure 216a, a third epitaxial structure 216c, and a fifth epitaxial structure 216e. Therefore, semiconductor device 600 has a bit line electrically connected only to the first epitaxial structure 616a among the first to sixth epitaxial structures 616a-616f.

[0077] Semiconductor device 600, like semiconductor device 200, includes a conductor 638a configured as a first word line WL0 and a conductor 638b configured as a second word line WL1. Semiconductor device 600 is configured as ROM memory, wherein bit cell area 620 is encoded with a first logic value (e.g., logic "0") for the first word line WL0 and a second logic value (e.g., logic "1") for the second word line WL1. In semiconductor device 600, conductor 638a is electrically connected to a gate structure 622d, while in semiconductor device 200, conductor 638a is electrically connected to two gate structures 222c and 222d. Furthermore, in semiconductor device 600, conductor 638b is electrically connected to a gate structure 622a, while in semiconductor device 200, conductor 638b is electrically connected to two gate structures 222a and 222b. Semiconductor device 600 further includes (relative to semiconductor device 200) a conductor 638c electrically connected to gate structure 622c and a conductor 638d electrically connected to gate structure 622b. Conductor 638c is used to provide VSS to gate structure 622c, and conductor 638d is used to provide VSS to gate structure 622d.

[0078] As described above, conductor 638a is configured as the first word line WL0 and electrically connected to gate structure 622d; conductor 638b is configured as the second word line WL1 and electrically connected to gate structure 622a; conductor 638c is used to provide VSS and is electrically connected to gate structure 622c; and conductor 638d is used to provide VSS and is electrically connected to gate structure 622b. Conductors 638a to 638d are substantially aligned along the same virtual line or track in the second direction.

[0079] In Figures 6A and 6B, the first region 646a is a region without an insulating structure 642 or an opening therein, therefore each of the second epitaxial structures 616b and the third epitaxial structure 616c is electrically connected to the well region 618. The second region 646b is a region without an insulating structure 642 or an opening therein, therefore the fourth epitaxial structure 616d is electrically connected to the well region 618. The third region 646c is a region without an insulating structure 642 or an opening therein, therefore the fifth epitaxial structure 616e is electrically connected to the well region 618. Therefore, the second epitaxial structure 616b, the third epitaxial structure 616c, the fourth epitaxial structure 616d, and the fifth epitaxial structure 616e are each short-circuited to the well region 618. The first, second, and third regions 646a-646c can be referred to as non-isolated regions. The sixth epitaxial structure 616f is electrically floating. In some embodiments, a voltage or signal can be applied to the sixth epitaxial structure 616f.

[0080] Figure 7A is a schematic plan view of a semiconductor device 700 according to at least one embodiment, Figure 7B is a cross-sectional view corresponding to line A-A' in Figure 7A, and Figure 7C is a cross-sectional view corresponding to line B-B' in Figure 7A.

[0081] The semiconductor device 700 has components similar to those in the semiconductor device 200, but with the addition of 500. The semiconductor device 700 includes the features of the semiconductor devices 300 and 600.

[0082] Semiconductor device 700 is an example of a ROM implemented as a 1.5T cell type device with a CNOD structure, similar to semiconductor device 600. In semiconductor device 700, bit cell region 720 encodes first and second logic values ​​that are different from each other, for example

[01] . In semiconductor device 700, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to well region 718, respectively.

[0083] Additionally, similar to semiconductor device 300, semiconductor device 700 includes conductors 730 extending in a second direction on both the left and right sides of Figure 7A. By extending conductors 730, bit line connections are provided at both ends of conductors 730, resulting in greater routing flexibility for additional bit line connections and / or for connections to bit lines. Furthermore, similar to semiconductor device 300, in semiconductor device 700, VSS is provided to bit cell region 720 via conductor 739, which extends in a second direction in a position aligned with the normals of word line conductors 738a, 738b and VSS conductors 738c, 738d, and is offset in the cell height direction, i.e., relative to bit line conductor 730 in a first direction.

[0084] Figure 8A is a schematic plan view of a semiconductor device 800 according to at least one embodiment, Figure 8B is a cross-sectional view corresponding to line A-A' in Figure 8A, and Figure 8C is a cross-sectional view corresponding to line B-B' in Figure 8A.

[0085] The semiconductor device 800 has components similar to those in the semiconductor device 200, but with the addition of component number 600. The semiconductor device 800 includes the features of semiconductor devices 400 and 600.

[0086] Semiconductor device 800 is an example of a ROM implemented as a 1.5T cell type device with a CNOD structure, similar to semiconductor device 600. In semiconductor device 800, bit cell region 820 encodes first and second logic values ​​that are different from each other, for example

[01] . In semiconductor device 800, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to well region 818, respectively.

[0087] Additionally, similar to semiconductor device 400, semiconductor device 800 includes a conductor 830 providing a reference voltage VSS. Also similar to semiconductor device 400, in semiconductor device 800, conductor 834 is configured as a bit line. Therefore, like semiconductor device 400, semiconductor device 800 is encoded on VSS. Conductors 830 and 834 are substantially centered along the same virtual line or track extending in a second direction.

[0088] Semiconductor device 800, like semiconductor device 400, includes a conductor 838a configured as a first word line WL0 and a conductor 838b configured as a second word line WL1. Semiconductor device 800 is configured as ROM memory, wherein bit cell area 820 is encoded with a first logic value (e.g., logic "0") for the first word line WL0 and a second logic value (e.g., logic "1") for the second word line WL1. In semiconductor device 800, conductor 838a is electrically connected to a gate structure 822d, while in semiconductor device 400, conductor 838a is electrically connected to two gate structures 422c and 422d. Furthermore, in semiconductor device 800, conductor 838b is electrically connected to a gate structure 822a, while in semiconductor device 400, conductor 838b is electrically connected to two gate structures 422a and 422b. The semiconductor device 800 further includes (relative to the semiconductor device 400) a conductor 838c electrically connected to a gate structure 822c and a conductor 838d electrically connected to a gate structure 822b. The conductor 838c is used to provide VSS to the gate structure 822c, and the conductor 838d is used to provide VSS to the gate structure 822d.

[0089] As described above, conductor 838a is configured as the first word line WL0 and electrically connected to gate structure 822d; conductor 838b is configured as the second word line WL1 and electrically connected to gate structure 822a; conductor 838c is used to provide VSS and is electrically connected to gate structure 822c; and conductor 838d is used to provide VSS and is electrically connected to gate structure 822b. Conductors 838a to 838d are substantially aligned along the same virtual line or track in the second direction.

[0090] The heights of conductors 830 and 834 are greater than the height of the third conductor 838 in the second direction. Increasing the height of conductors 830 and / or 834 helps to reduce the resistance of conductors 830 and / or 834, while decreasing the heights of conductors 838a-838d helps to maintain the gap between conductors 830 and conductors 838a-838d in the first direction and helps to reduce the grain area. In at least one embodiment, such as the embodiments in Figures 8A-8C, where conductor 830 is configured to provide VSS, increasing the height of conductor 830 helps to reduce the resistance of the VSS supply.

[0091] Figure 9A is a schematic plan view of a semiconductor device 900 according to at least one embodiment, Figure 9B is a cross-sectional view corresponding to line A-A' in Figure 9A, and Figure 9C is a cross-sectional view corresponding to line B-B' in Figure 9A.

[0092] Semiconductor device 900 has components similar to those in semiconductor device 200, but with the addition of component number 700. Semiconductor device 900 includes the features of semiconductor devices 500 and 600.

[0093] Semiconductor device 900 is an example of a ROM implemented as a 1.5T cell type device with a CNOD structure, similar to semiconductor device 600. In semiconductor device 900, bit cell region 920 encodes first and second logic values ​​that are different from each other, for example

[01] . In semiconductor device 900, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to well region 918, respectively.

[0094] Additionally, similar to semiconductor device 500, semiconductor device 900 includes conductor 930, which provides a reference voltage VSS and extends in a second direction on both the left and right sides of Figure 9A. This results in reference voltage connections at both ends of conductor 930, and allows for additional connections and / or provides greater routing flexibility. Like semiconductor device 500, semiconductor device 900 is coded on VSS.

[0095] Additionally, similar to semiconductor device 500, semiconductor device 900 includes a conductor 939 configured as a bit line. The bit line conductor 939 is offset relative to the conductor 930 providing VSS in the cell height direction, i.e., in a first direction. Therefore, in Figure 9A, the bit line conductor 939 is aligned with a conductor 938a configured as a first word line WL0, a conductor 938b configured as a second word line WL1, a conductor 938c providing VSS, and a conductor 938d providing VCC.

[0096] Figure 10A is a schematic plan view of a semiconductor device 1000 according to at least one embodiment, Figure 10B is a cross-sectional view corresponding to line A-A' in Figure 10A, and Figure 10C is a cross-sectional view corresponding to line B-B' in Figure 10A.

[0097] The semiconductor device 1000 has a component symbol similar to that of the semiconductor device 200, but with the addition of 800. The semiconductor device 1000 includes the features of the semiconductor devices 200 and 600.

[0098] Semiconductor device 1000 is an example of a ROM implemented as a 1.5T cell-type device having a continuous poly over diffusion edge (CPODE) structure. In some embodiments where a CPODE configuration exists, the active region pattern is substantially discontinuous at the side boundaries of the cell, and an insulator pattern is disposed above the region representing the interruption in the active region pattern at the cell side boundaries. In some embodiments, implementing a ROM device with a CPODE structure to isolate adjacent active regions helps to scale or reduce the CPP or center-to-center distance along a second direction between two adjacent gate regions, thereby resulting in an overall increase in circuit density.

[0099] Referring to Figure 10A, the semiconductor device 1000 includes a bit cell region 1020, which encodes first and second logic values ​​that are different from each other, for example

[01] . In the semiconductor device 1000, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to the well region 1018, respectively.

[0100] Like semiconductor device 200, semiconductor device 1000 includes a first conductor 1030 extending in a second direction and perpendicularly overlapping with active region 1014, configured as a bit line. Additionally, a second conductor 1034 extends in the second direction along the same virtual line or track as the first conductor 1030 and perpendicularly overlaps with active region 1014, serving to provide VSS. In semiconductor device 1000, the first conductor 1030 is electrically connected to a first epitaxial structure 1016a, while in semiconductor device 200, the first conductor 230 is electrically connected to a first epitaxial structure 216a, a third epitaxial structure 216c, and a fifth epitaxial structure 216e. Therefore, semiconductor device 1000 has a bit line electrically connected only to the first epitaxial structure 1016a among the first to sixth epitaxial structures 1016a-1016e.

[0101] Semiconductor device 1000, like semiconductor device 200, includes a conductor 1038a configured as a first word line WL0 and a conductor 1038b configured as a second word line WL1. Semiconductor device 600 is configured as ROM memory, wherein bit cell area 1020 is encoded with a first logic value (e.g., logic "0") for the first word line WL0 and a second logic value (e.g., logic "1") for the second word line WL1. In semiconductor device 1000, conductor 1038a is electrically connected to a gate structure 1022d, while in semiconductor device 200, conductor 238a is electrically connected to two gate structures 222c and 222d. Furthermore, in semiconductor device 1000, conductor 1038b is electrically connected to a gate structure 1022a, while in semiconductor device 200, conductor 238b is electrically connected to two gate structures 222a and 222b.

[0102] As described above, conductor 1038a is configured as the first word line WL0 and electrically connected to gate structure 1022d, and conductor 1038b is configured as the second word line WL1 and electrically connected to gate structure 1022a. Conductors 1038a and 1038b are substantially aligned along the same virtual line or track in the second direction.

[0103] In Figures 10A and 10B, the first region 1046a is a region without an insulating structure 1042 or an opening therein; therefore, each of the second epitaxial structures 1016b and the third epitaxial structure 1016c is electrically connected to the well region 1018. The second region 1046b is a region without an insulating structure 1042 or an opening therein; therefore, the fourth epitaxial structure 1016d is electrically connected to the well region 1018. The third region 1046c is a region without an insulating structure 1042 or an opening therein; therefore, the fifth epitaxial structure 1016e is electrically connected to the well region 1018. Therefore, the second epitaxial structure 1016b, the third epitaxial structure 1016c, the fourth epitaxial structure 1016d, and the fifth epitaxial structure 1016e are each short-circuited to the well region 1018. The first, second, and third regions 1046a-1046c can be referred to as non-isolated regions. The sixth epitaxial structure 1016f is electrically floating. In some embodiments, a voltage or signal may be applied to the sixth epitaxial structure 1016f.

[0104] Compared to semiconductor device 600, semiconductor device 1000 includes a first CPODE pattern 1050a between a fifth epitaxial structure 1016e and a sixth epitaxial structure 1016f, while semiconductor device 600 includes a gate structure 622c between a fifth epitaxial structure 616e and a second epitaxial structure 616f. Additionally, semiconductor device 1000 includes a second CPODE pattern 1050b between a second epitaxial structure 1016b and a third epitaxial structure 1016c, while semiconductor device 600 includes a gate structure 622b between the second epitaxial structure 616b and the third epitaxial structure 616c. In some embodiments, the first CPODE pattern 1050a and the second CPODE pattern 1050b include a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, oxygen-doped silicon carbonitride, silicon oxide, or one or more of the like. In some embodiments, the CPODE pattern is formed by removing the gate (e.g., dummy gate) and depositing one or more dielectric materials.

[0105] Figure 11A is a schematic plan view of a semiconductor device 1100 according to at least one embodiment, Figure 11B is a cross-sectional view corresponding to line A-A' in Figure 11A, and Figure 11C is a cross-sectional view corresponding to line B-B' in Figure 11A.

[0106] The semiconductor device 1100 has a component symbol similar to that of the semiconductor device 200, but with the addition of 900. The semiconductor device 1100 includes the features of the semiconductor devices 300 and 1000.

[0107] Semiconductor device 1100 is an example of a ROM implemented as a 1.5T cell type device with a CPODE structure, similar to semiconductor device 1000. In semiconductor device 1100, bit cell region 1120 encodes first and second logic values ​​that are different from each other, for example

[01] . In semiconductor device 1100, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to well region 1118, respectively.

[0108] Additionally, similar to semiconductor device 300, semiconductor device 1100 includes conductors 1130 extending in a second direction on both the left and right sides of Figure 11A. By extending conductors 1130, bit line connections are provided at both ends of conductors 1130, resulting in additional connections to bit lines and / or greater routing flexibility for connections to bit lines. Also similar to semiconductor device 300, in semiconductor device 1100, VSS is provided to bit cell region 1120 via conductor 1139, which extends in a second direction in a position aligned with the normals of word line conductors 1138a, 1138b, and is offset relative to bit line conductor 1130 in the cell height direction, i.e., in the first direction.

[0109] Figure 12A is a schematic plan view of a semiconductor device 1200 according to at least one embodiment, Figure 12B is a cross-sectional view corresponding to line A-A' in Figure 12A, and Figure 12C is a cross-sectional view corresponding to line B-B' in Figure 12A.

[0110] The semiconductor device 1200 has a component symbol similar to that of the semiconductor device 200, but with the addition of 1000. The semiconductor device 1200 includes the features of the semiconductor devices 400 and 1000.

[0111] Semiconductor device 1200 is an example of a ROM implemented as a 1.5T cell type device with a CPODE structure, similar to semiconductor device 1000. In semiconductor device 1200, bit cell region 1220 encodes first and second logic values ​​that are different from each other, for example

[01] . In semiconductor device 1200, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to well region 1218, respectively.

[0112] Additionally, similar to semiconductor device 400, semiconductor device 1200 includes conductor 1230 providing a reference voltage VSS. Also similar to semiconductor device 400, in semiconductor device 800, conductor 834 is configured as a bit line. Therefore, like semiconductor device 400, semiconductor device 800 is encoded on VSS. Conductors 1230 and 1234 are substantially centered along the same virtual line or track extending in a second direction.

[0113] Semiconductor device 1200, like semiconductor device 400, includes a conductor 1238a configured as a first word line WL0 and a conductor 1238b configured as a second word line WL1. Semiconductor device 1200 is configured as ROM memory, wherein bit cell area 1220 is encoded with a first logic value (e.g., logic "0") for the first word line WL0 and a second logic value (e.g., logic "1") for the second word line WL1. In semiconductor device 1200, conductor 1238a is electrically connected to a gate structure 1222d, while in semiconductor device 400, conductor 1238a is electrically connected to two gate structures 422c and 422d. Furthermore, in semiconductor device 1200, conductor 1238b is electrically connected to a gate structure 1222a, while in semiconductor device 400, conductor 1238b is electrically connected to two gate structures 422a and 422b. Conductors 1238a and 1238d are substantially aligned along the same virtual line or track in the second direction.

[0114] The heights of conductors 1230 and 1234 are greater than the heights of conductors 1238a and 1238b in the second direction. Increasing the height of conductors 1230 and / or 1234 helps reduce the resistance on conductors 1230 and / or 1234, while decreasing the heights of conductors 1238a and 1238b helps maintain the gap between the first conductor 1230 and conductors 1238a and 1238b in the first direction and helps reduce the grain area. In at least one embodiment, such as the embodiments in Figures 12A to 12C, where the first conductor 1230 is configured to provide VSS, increasing the height of the first conductor 1230 helps reduce the resistance of the VSS supply.

[0115] Figure 13A is a schematic plan view of a semiconductor device 1300 according to at least one embodiment, Figure 13B is a cross-sectional view corresponding to line A-A' in Figure 13A, and Figure 13C is a cross-sectional view corresponding to line B-B' in Figure 13A.

[0116] Semiconductor device 1300 has a component similar to that of semiconductor device 200, but with the addition of 1100. Semiconductor device 1200 includes the features of semiconductor devices 500 and 1000.

[0117] Semiconductor device 1300 is an example of a ROM implemented as a 1.5T cell type device with a CPODE structure, similar to semiconductor device 1000. In semiconductor device 1300, bit cell region 1320 encodes first and second logic values ​​that are different from each other, for example

[01] . In semiconductor device 1300, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to well region 1318, respectively.

[0118] Additionally, similar to semiconductor device 500, semiconductor device 1300 includes a conductor 1330 that provides a reference voltage VSS and extends in a second direction on both the left and right sides of Figure 13A. This results in reference voltage connections being provided at both ends of conductor 1330, and allows for additional connections and / or provides greater routing flexibility. Like semiconductor device 500, semiconductor device 1300 is coded on VSS.

[0119] Additionally, similar to semiconductor device 500, semiconductor device 1300 includes a conductor 1339 configured as a bit line. The conductor 1339 configured as a bit line is offset relative to the conductor 1330 providing the VSS in the cell height direction, i.e., in a first direction. Therefore, in Figure 13A, the bit line conductor 1339 is aligned with the conductor 1338a configured as a first word line WL0 and the conductor 1338b configured as a second word line WL1.

[0120] Figure 14A is a schematic plan view of a semiconductor device 1400 according to at least one embodiment, Figure 14B is a cross-sectional view corresponding to line A-A' in Figure 14A, Figure 14C is a cross-sectional view corresponding to line B-B' in Figure 14A, and Figure 14D is a cross-sectional view corresponding to line C-C' in Figure 14A.

[0121] The semiconductor device 1400 has a corresponding element symbol for elements similar to those in the semiconductor device 200, but with the addition of 1200. The state of the semiconductor device 1400 will be described with reference to the semiconductor device 200 in Figures 2A to 2C, that is, the state of the semiconductor device 1400 that differs from that of the semiconductor device 200 will be mainly described.

[0122] Referring to Figure 14A, the semiconductor device 1400 is an example of a 2T unit type device (2T = two transistors), wherein bit cell regions 1420 encode first and second logic values ​​that are different from each other, for example

[01] . The first logic value, for example, logic "0", is encoded in the first bit cell 1420a. The second logic value, for example, logic "1", is encoded in the second bit cell 1420b. In the semiconductor device 1400, the encoding of the first and second logic values ​​corresponds to being electrically disconnected from and electrically connected to well region 1418, respectively.

[0123] In semiconductor device 1400, a first conductor 1430 extends in a second direction and overlaps perpendicularly with the active region 1414, and is configured as a bit line. Additionally, a second conductor 1434 extends in the second direction along the same virtual line or track as the first conductor 1430 and overlaps perpendicularly with the active region 1414, and is used to provide VSS. The first conductor 1430 is electrically connected to a first epitaxial structure 1416a (via via 1432a and conductive structure 1426a), a third epitaxial structure 1416c (via via 1432b and conductive structure 1426c), and a fifth epitaxial structure 1416e (via via 1432d and conductive structure 1426e).

[0124] The first region 1446a in Figure 14A is a region without an insulating structure 1442 (see Figures 14B-14D) or with an opening therein. The epitaxial structure 1416b (see Figures 14B-14D) is electrically connected to the rear conductor 1454 via a rear via 1458a. The rear via 1458a passes through the well region 1418 and the substrate 1410, and is insulated from the well region 1418 and the substrate 1410 by an insulating structure 1462a. The second region 1446b in Figure 14A is a region without an insulating structure 1442 or with an opening therein. The epitaxial structure 1416d (see Figures 14B-14D) is electrically connected to the rear conductor 1454 via the rear via 1458b. The rear via 1458b passes through the well region 1418 and the substrate 1410, and is insulated from the well region 1418 and the substrate 1410 by an insulating structure 1462b. Connecting the epitaxial structures 1416b and 1416d together using the rear conductor 1454 allows for a reduction in the number of conductors in the metal layer (e.g., the M0 layer), thereby providing layout flexibility, such as allowing the use of wider, lower-resistance conductors for bit lines or the like, and / or reducing the overall cell height. The first region 1446a and the second region 1446b may be referred to as non-isolated regions.

[0125] Therefore, semiconductor device 200 electrically connects the second epitaxial structure 216b and the fourth epitaxial structure 216d to well region 218 and uses the well region as the conductor of VSS, while semiconductor device 1400 electrically connects epitaxial structures 1416b and 1416d to back conductor 1454 and uses back conductor 1454 as the conductor of VSS. In some embodiments, using back conductor 1454 instead of well region 1418 provides a lower resistance connection between epitaxial structures 1416b and 1416d, and / or provides greater routing flexibility compared to using well region 1418.

[0126] The rear conductor 1454 comprises one or more conductive materials, such as aluminum, copper, nickel, silver, tin, titanium, tungsten, or other metals. In Figures 14B-14D, the rear conductor 1454 is in a first metal layer, BMO, on the rear side of the substrate; however, in other embodiments, the rear conductor 1454 is in another rear metal layer, such as BMO, BMO, or another conductive layer. The rear conductor 1454 is embedded in an insulating structure 1464. In some embodiments, the insulating structure 1464 comprises a plurality of insulating layers or structures formed of the same or different insulating materials. In some embodiments, the insulating structure 1464 is or includes an oxide layer. In some embodiments, the insulating structure 142 comprises a dielectric material, such as silicon oxide, silicon nitride, SiOCN, or one or more of the like. In some embodiments, the dielectric material is formed by a process including atomic layer deposition, chemical vapor deposition, physical vapor deposition, or one or more of the like.

[0127] Epitaxial structure 1416b is electrically connected to rear conductor 1454, thereby electrically connected to the reference voltage VSS supplied to front second conductor 1434. Therefore, second bit cell 1420b encodes a first logic value, for example, logic "1". In other words, the presence of the non-isolated region of first region 1446a (where epitaxial structure 1416b is on well region 1418) and its electrical connection to rear conductor 1454 via rear via 1458a means that epitaxial structure 1416b is electrically connected to VSS, and second bit cell 1420b encodes a first logic value, for example, logic "1".

[0128] On the other hand, in the first element unit 1420a, a non-isolated region is missing below the fifth epitaxial structure 1416e (see Figures 14B-14D), that is, the insulating structure 1442 exists below the fifth epitaxial structure 1416e, so that the fifth epitaxial structure 1416e is not electrically connected to the well region 1418 or the back conductor 1454. Therefore, the first element unit 1420a encodes a second logic value, for example, logic "0". In other words, the absence of the non-isolated region (where the epitaxial structure 1416e is on the well region 1418) means that the fifth epitaxial structure 1416e is electrically disconnected from the well region 1418 and the back conductor 1454. Therefore, the first element unit 1420a encodes a second logic value, for example, logic "0". In Figures 14A-14D, the epitaxial structure 1416f is electrically floating. In some embodiments, a voltage or signal may be applied to the epitaxial structure 1416f.

[0129] In Figures 14A to 14D, conductor 1438a is electrically connected to gate structures 1422c and 1422d and configured as the first word line WL0. Conductor 1438b is electrically connected to gate structures 1422a and 1422b and configured as the second word line WL1. Conductors 1438a and 1438b are substantially aligned along the same virtual line or track in the second direction.

[0130] In various embodiments, the back conductor 1454 of semiconductor device 1400 is implemented in one or more of semiconductor devices 100 to 1300. For example, any one or more of semiconductor devices 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and / or 1300 may be implemented using a back conductor, such as back conductor 1454 in one or more back metal layers, such as BMO, BM1, BM2, or the like. In some embodiments, a back conductor is used instead of forming an electrical connection through a well region, and the back conductor is electrically isolated from the well region. In some embodiments, the well region is electrically connected to the back conductor.

[0131] Table 1 below summarizes the features of the ROM devices described in Figures 2A to 14D above, as well as the additional devices (columns 14 to 24) corresponding to Figures 3A to 13C but implemented with rear-side metal connections. Column 14 (Figures 14A to 14D) corresponds to the devices in column 1 (Figures 2A to 2C) implemented with rear-side metal connections. Columns 14 to 24 correspond to the devices in columns 2 to 12, respectively, implemented with rear-side metal connections. Table 1 List picture Unit types (2T, 1.5T CNOD, 1.5T CPODE) Encoding on (BL, VSS) M0 orbital (BL=VSS, BL≠VSS) Metal (M0, BM0) 1 Figures 2A to 2C 2T BL BL=VSS M0 2 Figures 3A to 3C 2T BL BL ≠ VSS M0 3 Figures 4A to 4C 2T VSS BL=VSS M0 4 Figures 5A to 5C 2T VSS BL ≠ VSS M0 5 Figures 6A to 6C 1.5T CNOD BL BL=VSS M0 6 Figures 7A to 7C 1.5T CNOD BL BL ≠ VSS M0 7 Figures 8A to 8C 1.5T CNOD VSS BL=VSS M0 8 Figures 9A to 9C 1.5T CNOD VSS BL ≠ VSS M0 9 Figures 10A to 10C 1.5T CPODE BL BL=VSS M0 10 Figures 11A to 11C 1.5T CPODE BL BL ≠ VSS M0 11 Figures 12A to 12C 1.5T CPODE VSS BL=VSS M0 12 Figures 13A to 13C 1.5T CPODE VSS BL ≠ VSS M0 13 Figures 14A to 14D 2T BL BL=VSS BM0 14 – 2T BL BL ≠ VSS BM0 15 – 2T VSS BL=VSS BM0 16 – 2T VSS BL ≠ VSS BM0 17 – 1.5T CNOD BL BL=VSS BM0 18 – 1.5T CNOD BL BL≠VSS BM0 19 – 1.5T CNOD VSS BL=VSS BM0 20 – 1.5T CNOD VSS BL≠VSS BM0 21 – 1.5T CPODE BL BL=VSS BM0 22 – 1.5T CPODE BL BL≠VSS BM0 23 – 1.5T CPODE VSS BL=VSS BM0 24 – 1.5T CPODE VSS BL≠VSS BM0

[0132] In some embodiments, one or more cell types are used in the same semiconductor device. In at least one embodiment, the ROM bit cell array uses cell types, such as a mixture of 2T, 1.5T CNOD, and / or 1.5T CPODE. In some embodiments, one or more transistors are used for the bit cell. In various embodiments, the bit cell transistor has one or more gate structures. Further, in various embodiments, some routing, such as routing for bit lines, word lines, and / or reference signals and / or voltages, moves from the front metal layer (such as MO) to one or more well regions or rear conductors. Additionally, in various embodiments, the ROM bit cell is implemented as an NMOS or PMOS. In some embodiments, a mesa-well architecture or similar is used to implement the ROM semiconductor device with one or more of gate-surround bit cell transistors, fork-structure transistors, and CFETs.

[0133] Figure 15 is a flowchart of a method 1500 for manufacturing a semiconductor device according to at least one embodiment.

[0134] Method 1500 includes an operation 1510 of forming bit cells on a substrate including an active region and a well region. The forming of the bit cells includes a sub-operation 1515, which includes forming first and second gate structures across the active region; forming a first conductive structure at a first side of the first gate structure; forming a second conductive structure between a second side of the first gate structure and a first side of the second gate structure, and electrically connecting it to the well region; and forming a third conductive structure at a second side of the second gate structure.

[0135] Method 1500 also includes operation 1520 of forming a fourth conductive structure that overlaps with and is electrically connected to the well area.

[0136] Method 1500 also includes operation 1530, which includes forming a first conductor connected to the first conductive structure and the third conductive structure; forming a second conductor connected to the fourth conductive structure; and forming a third conductor connected to the first and second gate structures.

[0137] Figure 16 is a block diagram of an IC device according to at least one embodiment.

[0138] In Figure 16, IC device 1600 includes macro 1602. In some embodiments, macro 1602 includes one or more of the following: memory, electrical grid, one or more cells, inverters, latches, buffers, and / or any other type of circuit configuration that can be digitally represented in a cell library. In some embodiments, macro 1602 can be understood as a similar concept to a modularized, programmed architectural hierarchy, where a subroutine / program is called by a main program (or by other subroutines) to perform a given computational function. In this context, IC device 1600 uses macro 1602 to perform one or more given functions. Therefore, in this context, in terms of architectural hierarchy, IC device 1600 is similar to a main program, and macro 1602 is similar to a subroutine / program. In some embodiments, macro 1602 is a soft macro. In some embodiments, macro 1602 is a hard macro. In some embodiments, macro 1602 is a soft macro described in register-transfer level (RTL) code bits. In some embodiments, macro 1602 is not yet composed, placed, and routed to allow for the composition, placement, and routing of soft macros for various process nodes. In some embodiments, macro 1602 is a hard macro digitally described in a binary file format (e.g., Graphic Database System II (GDSII) stream format), wherein the binary file format represents the planar geometry, text tags, other information, and the like of one or more layouts of macro 1602 in a hierarchical manner. In some embodiments, macro 1602 is composed, placed, and routed such that the hard macro is specific to a particular process node. In Figure 16, macro 1602 includes region 1604, which includes ROM, for example, corresponding to one or more of the ROM semiconductor devices represented above and / or in Table 1.

[0139] Figure 17 is a block diagram of an electronic design automation (EDA) system 1700 according to some embodiments.

[0140] In some embodiments, the EDA system 1700 includes an Automatic Place & Route (APR) system. According to at least one embodiment, the EDA system 1700 can be used to implement a method for laying out a routing configuration of a semiconductor device according to one or more embodiments.

[0141] In some embodiments, the EDA system 1700 is a general-purpose computing device including a hardware processor 1702 and a non-transitory computer-readable storage medium 1704. Among other things, the computer-readable storage medium 1704 is encoded with, i.e., stores, computer program code 1706 (i.e., a set of executable instructions). According to one or more embodiments, execution of the computer program code 1706 by the processor 1702 represents (at least partially) an EDA tool that implements part or all of a process and / or method (hereinafter referred to as the process and / or method mentioned) for the synthesis, placement, and routing of regions, such as ROM (e.g., corresponding one or more of the ROM semiconductor devices represented above and / or in Table 1).

[0142] Processor 1702 is electrically coupled to computer-readable storage medium 1704 via bus 1708. Processor 1702 is also electrically coupled to I / O interface 1710 via bus 1708. Network interface 1712 is also electrically connected to processor 1702 via bus 1708. Network interface 1712 is connected to network 1714, enabling processor 1702 and computer-readable storage medium 1704 to be connected to external components via network 1714. Processor 1702 is used to execute computer program code 1706 encoded in computer-readable storage medium 1704 so that EDA system 1700 can be used to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 1702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0143] In one or more embodiments, the computer-readable storage medium 1704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). Examples of the computer-readable storage medium 1704 include semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable storage medium 1704 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disc (DVD).

[0144] In one or more embodiments, computer-readable storage medium 1704 stores computer program code 1706 that enables EDA system 1700 (wherein such execution (at least partially) represents EDA tools) to perform some or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 1704 also stores information that facilitates the performance of some or all of the mentioned processes and / or methods. In one or more embodiments, computer-readable storage medium 1704 stores a standard cell library 1707 that includes such standard cells as disclosed herein.

[0145] EDA system 1700 includes an I / O interface 1710. The I / O interface 1710 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1710 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor keys for transmitting information and commands to processor 1702.

[0146] EDA system 1700 also includes a network interface 1712 coupled to processor 1702. Network interface 1712 allows EDA system 1700 to communicate with network 1714, to which one or more other computer systems are connected. Network interface 1712 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EDA systems 1700.

[0147] EDA system 1700 receives information through I / O interface 1710. The information received through I / O interface 1710 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1702. This information is transmitted to processor 1702 via bus 1708. EDA system 1700 also receives information related to the user interface (UI) through I / O interface 1710. This information is stored as user interface (UI) 1742 in computer-readable storage medium 1704.

[0148] In some embodiments, one or all of the mentioned processes and / or methods are implemented as standalone software applications for processor execution. In some embodiments, one or all of the mentioned processes and / or methods are implemented as software applications that are part of additional software applications. In some embodiments, one or all of the mentioned processes and / or methods are implemented as plug-ins to software applications. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, one or all of the mentioned processes and / or methods are implemented as software applications used by the EDA system 1700. In some embodiments, the layout including standard cells is generated using tools such as VIRTUOSO® from Cadence Design Systems, Inc. or another suitable layout generation tool.

[0149] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as at least one of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROMs, RAMs, memory cards, and the like.

[0150] Figure 18 is a block diagram of an integrated circuit (IC) manufacturing system 1800 and its associated IC manufacturing process according to at least one embodiment.

[0151] In some embodiments, based on the layout, at least one of the following is manufactured using the IC manufacturing system 1800: (A) one or more semiconductor masks or (B) at least one component in a layer of semiconductor integrated circuit.

[0152] In Figure 18, the IC manufacturing system 1800 includes entities such as a design room 1820, a mask room 1830, and an IC manufacturer / fab 1850. These entities interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices 1860 (e.g., corresponding to ROM devices described above with reference to Table 1). The entities in the IC manufacturing system 1800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as Ethernet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1820, mask room 1830, and IC fab 1850 are owned by a single larger company. In some embodiments, two or more of the design room 1820, the shielding room 1830, and the IC wafer fab 1850 coexist in a common facility and use common resources.

[0153] Design studio (or design team) 1820 generates IC design layout 1822. IC design layout 1822 includes various geometric patterns designed for IC device 1860. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1860 to be manufactured. Various layers are combined to form various IC features. For example, a portion of IC design layout 1822 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, UTM interconnect structures, or similar, passivation layer structures, openings for bonding pads, and conductive bumps to be formed in and on a semiconductor substrate (such as a silicon wafer). Design studio 1820 implements appropriate design procedures to form IC design layout 1822. Design procedures include one or more of logic design, physical design, or placement and routing operations. IC design layout 1822 is presented in one or more data files containing information on the geometric patterns. For example, IC design layout 1822 can be expressed in GDSII file format or DFII file format.

[0154] Masking chamber 1830 includes mask data preparation 1832 and mask fabrication 1844. Masking chamber 1830 uses IC design layout 1822 to fabricate one or more masks 1845 for use in fabricating various layers of IC device 1860 according to IC design layout 1822. Masking chamber 1830 performs mask data preparation 1832, in which IC design layout 1822 is translated into a representative data file (RDF). Mask data preparation 1832 provides the RDF to mask fabrication 1844. Mask fabrication 1844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 1845 or a semiconductor wafer 1853. IC design layout 1822 is manipulated by mask data preparation 1832 to conform to the specific characteristics of the mask writer and / or the requirements of IC wafer fab 1850. In Figure 18, mask data preparation 1832 and mask manufacturing 1844 are shown as separate elements. In some embodiments, mask data preparation 1832 and mask manufacturing 1844 may be collectively referred to as mask data preparation.

[0155] In some embodiments, mask data preparation 1832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as self-diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 1822. In some embodiments, mask data preparation 1832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0156] In some embodiments, mask data preparation 1832 includes checking the IC design layout 1822 using a mask rule checker (MRC) that has undergone a process in an OPC using a set of mask generation rules. These rules contain certain geometric and / or connectivity constraints to ensure sufficient margin, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1822 to compensate for constraints during mask manufacturing 1844, which may undo modifications performed by the OPC to satisfy the mask generation rules.

[0157] In some embodiments, mask data preparation 1832 includes lithography process checking (LPC), which simulates the process implemented by IC wafer fab 1850 to manufacture IC device 1860. LPC simulates this process based on IC design layout 1822 to produce a simulated manufactured device, such as IC device 1860. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors, or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by LPC, if the simulated device does not sufficiently approximate the design rules in shape, OPC and / or MRC are repeated to further refine the IC design layout 1822.

[0158] It should be understood that the above description of mask data preparation 1832 has been simplified for clarity. In some embodiments, mask data preparation 1832 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1822 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1822 during mask data preparation 1832 may be performed in a variety of different sequences.

[0159] Following mask data preparation 1832 and during mask manufacturing 1844, mask 1845 or a group of masks 1845 is manufactured based on a modified IC design layout 1822. In some embodiments, mask manufacturing 1844 includes performing one or more lithography exposures based on IC design layout 1822. In some embodiments, an electron beam or multiple electron beams are used to pattern the mask (photomask or master photomask) 1845 based on the modified IC design layout 1822. Mask 1845 can be formed using various techniques. In some embodiments, mask 1845 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose image-sensitive material layers (e.g., photoresist layers) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask version of mask 1845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas. In another example, mask 1845 is formed using a phase shift mask technique. In the phase shift mask (PSM) version of mask 1845, various features in the pattern formed on the phase shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) produced by mask fabrication 1844 are used in a variety of processes. For example, this mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer 1853, in an etching process to form various etched regions in semiconductor wafer 1853, and / or in other suitable processes.

[0160] IC wafer fab 1850 is an IC manufacturing business, including one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer fab 1850 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end-of-line, FEOL) of a plurality of IC products, while a second manufacturing facility may provide back-end manufacturing (back-end-of-line, BEOL) for interconnecting and packaging IC products, and a third manufacturing facility may provide other services for the foundry business.

[0161] IC wafer fab 1850 includes manufacturing tools 1852 for performing various manufacturing operations on semiconductor wafers 1853 to manufacture IC devices 1860 according to masks(e.g., mask 1845). In various embodiments, manufacturing tools 1852 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0162] IC wafer fab 1850 uses multiple masks 1845 manufactured via mask chamber 1830 to manufacture IC device 1860. Therefore, IC wafer fab 1850 uses IC design layout 1822 at least indirectly to manufacture IC device 1860. In some embodiments, semiconductor wafer 1853 is manufactured by IC wafer fab 1850 using multiple masks 1845 to form IC device 1860. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1822. Semiconductor wafer 1853 includes a silicon substrate, or other suitable substrate on which a material layer is formed. Semiconductor wafer 1853 further includes one or more of various doped regions, dielectric features, multi-quasi-interconnects, and the like (formed in subsequent manufacturing steps).

[0163] Detailed information regarding integrated circuit (IC) manufacturing systems (e.g., IC manufacturing system 1800 of Figure 18) and their associated IC manufacturing processes can be found in, for example, U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Publication No. 2015 / 0278429, published October 1, 2015; U.S. Pre-Publication No. 2014 / 0040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0164] In some embodiments, the semiconductor device includes a substrate and bit cells. The substrate includes an active region and a well region below the active region. The bit cells overlap the well region perpendicularly and include a first gate structure and a second gate structure extending across the active region in a first direction and spaced apart in a second direction, a first conductive structure at a first side of the first gate structure, a second conductive structure between a second side of the first gate structure and a first side of the second gate structure, and a third conductive structure at a second side of the second gate structure. The semiconductor device includes a fourth conductive structure overlapping the well region perpendicularly, a first conductor connected to the first and third conductive structures, a second conductor connected to the fourth conductive structure, and a third conductor connected to the first and second gate structures. The second and fourth conductive structures are electrically connected to the well region.

[0165] In some embodiments, the semiconductor device includes a substrate comprising an active region and a well region below the active region; a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure extending across the active region in a first direction and spaced apart in a second direction; a first conductive structure at a first side of the first gate structure; a second conductive structure between a second side of the first gate structure and a first side of the second gate structure; a third conductive structure between a second side of the second gate structure and a first side of the third gate structure; a fourth conductive structure between a second side of the third gate structure and a first side of the fourth gate structure; a fifth conductive structure at a second side of the fourth gate structure; a sixth conductive structure perpendicularly overlapping the well region; a first conductor connected to the first, third, and fifth conductive structures; a second conductor connected to the sixth conductive structure; a third conductor connected to the third and fourth gate structures; and a fourth conductor connected to the first and second gate structures. The fourth and sixth conductive structures are electrically connected to the well region.

[0166] In some embodiments, a method of manufacturing a semiconductor device includes forming bit cells on a substrate, the substrate including an active region and a well region below the active region, wherein the bit cells are formed to overlap the well region perpendicularly, and forming the bit cells includes: forming a first gate structure and a second gate structure extending across the active region in a first direction and spaced apart in a second direction; forming a first conductive structure at a first side of the first gate structure; forming a second conductive structure between a second side of the first gate structure and a first side of the second gate structure; forming a third conductive structure at a second side of the second gate structure; forming a fourth conductive structure that overlaps perpendicularly with the well region; forming a first conductor connected to the first conductive structure and the third conductive structure; forming a second conductor connected to the fourth conductive structure; and forming a third conductor connected to the first and second gate structures. The second and fourth conductive structures are formed to be electrically connected to the well region.

[0167] It should be understood that, unless otherwise specifically stated, the features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in connection with one or more other embodiments.

[0168] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0169] 100: Semiconductor devices 110:Substrate 112: Dielectric materials 114: Active Area 114a: First nanostructure / nanostructure 114b: Second nanostructure / nanostructure 114c: Third nanostructure / nanostructure 116a: First epitaxial structure 116b: Second epitaxial structure 116c: Third epitaxial structure 116d: Fourth epitaxial structure 118: Well Area 120: Bit cell area 122a: First gate structure 122a-1: First side 122a-2: Second side 122b: Second gate structure 122b-1: First side 122b-2: Second side 126a: First conductive structure 126b: Second conductive structure 126c: Third conductive structure 126d: Fourth conductive structure 130: First conductor 132a: First through hole 132b: Second through hole 132c: Third through hole 134: Second conductor 138: Third conductor 140a: First gate via 140b: Second gate via 142: Insulation Structure 146a: First Region 146b: Second Region 200: Semiconductor devices 210:Substrate 212: Dielectric materials 214: Active Region 216a: First epitaxial structure 216b: Second epitaxial structure 216c: Third epitaxial structure 216d: Fourth epitaxial structure 216e: Fifth epitaxial structure 216f: Sixth epitaxial structure 218: Well Area 220: Bit cell area 220a: First element 220b: Second bit unit 222a~222d: Gate structure 226a~226f: Conductive structure 230: First conductor 232a~232d: Through holes 234: Second conductor 238a~238b: Conductors 240a~240d: Gate through-hole 242: Insulation Structure 246a: First Region 246b: Second Region 300: Semiconductor Devices 310:Substrate 312: Dielectric materials 316a: Epitaxial structure 316b: Second epitaxial structure 316c~316f: Epitaxial structure 318: Well Area 320: Bit cell area 320a: First element 320b: Second bit unit 322a~322d: Gate structure 326a~326c: Conductive structure 326d: Fourth conductive structure 326e~326f: Conductive structure 330: First conductor 332a~332b: Through holes 332c: Third through hole 338a~338b: Character line conductors 339: Conductor 340a~340d: Gate through-hole 342: Insulation structure 346a: First Region 346b: Second Region 400: Semiconductor Devices 410:Substrate 412: Dielectric materials 416a~416f: Epitaxial structure 418: Well Area 420: Bit cell area 420a: First element 420b: Second bit unit 422a~422d: Gate structure 430: Conductor 434: Conductor 438a~438b: Conductors 446a~446b: Area 500: Semiconductor Devices 510:Substrate 512: Dielectric materials 516a~516f: Epitaxial structure 518: Well Area 520: Bit cell area 520a: First element 520b: Second bit unit 530: Conductor 538a~538b: Character line conductor 539: Bit Line Conductor 546a~546b: Area 600: Semiconductor Devices 610:Substrate 612: Dielectric materials 614: Active Area 616a: First epitaxial structure 616b: Second epitaxial structure 616c: Third epitaxial structure 616d: Fourth epitaxial structure 616e: Fifth epitaxial structure 616f: Sixth epitaxial structure 618: Well Area 620: Bit cell area 622a~622d: Gate structure 630: First Conductor 634: Second Conductor 638a~638d: Conductors 642: Insulation Structure 646a: First Region 646b: Second Region 646c: Third Region 700: Semiconductor Devices 710:Substrate 712: Dielectric materials 714: Active Region 716a~716f: Epitaxial structure 718: Well Area 720: Bit cell area 730: Conductor 738a~738b: Character line conductor 738c~738d: VSS conductor 739: Conductor 742: Insulation Structure 746a~746c: Area 800: Semiconductor Device 810:Substrate 812: Dielectric materials 814: Active Region 816a~816f: Epitaxial structure 818: Well Area 820: Bit cell area 822a~822d: Gate structure 830: Conductor 834: Conductor 838a~838d: Conductor 842: Insulation Structure 846a~846c: Region 900: Semiconductor Device 910:Substrate 912: Dielectric materials 914: Active Area 916a~916f: Epitaxial structure 918: Well Area 920: Bit cell area 930: Conductor 938a~938d: Conductor 939: Conductor 942: Insulation Structure 946a~946c: Area 1000: Semiconductor Devices 1010:Substrate 1012: Dielectric Materials 1014: Active Region 1016a: First epitaxial structure 1016b: Second epitaxial structure 1016c: Third epitaxial structure 1016d: Fourth epitaxial structure 1016e: Fifth epitaxial structure 1016f: Sixth epitaxial structure 1018: Well Area 1020: Bit cell area 1022a~1022d: Gate structure 1030: First Conductor 1034: Second conductor 1038a~1138b: Conductors 1042: Insulation Structure 1046a: Region 1 1046b: Second Region 1046c: Third Region 1050a: First CPODE pattern 1050b: Second CPODE pattern 1100: Semiconductor Device 1110:Substrate 1112: Dielectric materials 1114: Active Region 1116a~1116f: Epitaxial structure 1118: Well Area 1120: Bit cell area 1130: Conductor 1138a~1138b: Conductors 1139: Conductor 1142: Insulation structure 1146a~1146c: Region 1150a~1150b: CPODE pattern 1200: Semiconductor Device 1210:Substrate 1212: Dielectric materials 1214: Active Region 1216a~1216f: Epitaxial structure 1218: Well Area 1220: Bit cell area 1222a~1222d: Gate structure 1230: Conductor 1234: Conductor 1238a~1238b: Conductors 1242: Insulation structure 1250a~1250b: CPODE pattern 1300: Semiconductor Device 1310:Substrate 1312: Dielectric materials 1314: Active Region 1316a~1316f: Epitaxial structure 1318: Well Area 1320: Bit cell area 1322: IC Design Layout 1322a~1322d: Gate structure 1330: Conductor 1338a~1338b: Conductors 1339: Bit line conductor / conductor 1342: Insulation structure 1346a~1346c: Region 1350a~1350b: CPODE pattern 1400: Semiconductor Device 1410:Substrate 1412: Dielectric materials 1414: Active Region 1416a: First epitaxial structure 1416b: Epitaxial structure 1416c: Third epitaxial structure 1416d: Epitaxial structure 1416e: Fifth epitaxial structure 1416f: Epitaxial structure 1418: Well Area 1420: Bit cell area 1420a: First element 1420b: Second bit unit 1422a~1422d: Gate structure 1426a~1426f: Conductive structure 1430: First Conductor 1432a~1432d: Through holes 1434: Second Conductor 1438a~1438b: Conductor 1442: Insulation structure 1446a: First Region 1446b: Second Region 1454: Rear Conductor 1458a~1458b: Rear through hole 1462a~1462b: Insulation structure 1464: Insulation Structure 1500: Method 1510~1530: Operation 1600: IC device 1602: Mega Collection 1604: District 1700: EDA System 1702: Hardware Processor / Processor 1704: Non-transitory computer-readable storage media / Computer-readable storage media 1706: Computer Program Code 1707: Standard Unit Library 1708: Busbar 1710:I / O interface 1712: Network Interface 1714: Internet 1742:UI 1800: IC Manufacturing System 1820: Design Studio 1822: IC Design Layout 1830: The Covered Room 1832: Preparation of Masking Data 1844: Mask Manufacturing 1845: Cover 1850: IC wafer fab 1852: Manufacturing Tools 1853: Semiconductor wafer 1860: IC device BL: Bitline H1~H3: Height P1: First pitch P2: Second pitch VSS: Reference Voltage WL0: First character line WL1: Second character line

Claims

1. A semiconductor device, comprising: A substrate includes an active region and a well region below the active region; A bit cell, perpendicularly overlapping the well region, includes: a first gate structure and a second gate structure extending across the active region in a first direction and spaced apart in a second direction; a first conductive structure at a first side of the first gate structure; a second conductive structure between a second side of the first gate structure and a first side of the second gate structure; and a third conductive structure at a second side of the second gate structure; a fourth conductive structure, perpendicularly overlapping the well region; a first conductor connected to the first conductive structure and the third conductive structure; a second conductor connected to the fourth conductive structure; and a third conductor connected to the first gate structure and the second gate structure, wherein the second conductive structure and the fourth conductive structure are electrically connected to the well region; a first epitaxial structure below the second conductive structure and in contact with the well region; and a second epitaxial structure below the fourth conductive structure and in contact with the well region.

2. The semiconductor device as described in claim 1, further comprising: A third gate structure and a fourth gate structure; A fifth conductive structure is formed on a first side of the third gate structure; A sixth conductive structure is formed between a second side of the third gate structure and a first side of the fourth gate structure; and a seventh conductive structure is formed between a second side of the fourth gate structure and the first side of the first gate structure.

3. The semiconductor device as claimed in claim 1, wherein: The well area conducts a first reference voltage between the second conductive structure and the fourth conductive structure, and a bit cell encodes a first logic value.

4. The semiconductor device as described in claim 1, further comprising: An insulating structure is provided in the well region, wherein the first epitaxial structure and the second epitaxial structure extend through a plurality of openings in the insulating structure to contact the well region.

5. The semiconductor device as claimed in claim 1, wherein: The first conductor is configured as a single-bit line, the second conductor is used to provide a first reference voltage, and the third conductor is configured as a single-bit line.

6. The semiconductor device as claimed in claim 1, wherein: The first conductor is used to provide a first reference voltage, the second conductor is configured as a bit line, and the third conductor is configured as a word line.

7. A semiconductor device, comprising: A substrate includes an active region and a well region below the active region; a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure extending across the active region in a first direction and spaced apart in a second direction; a first conductive structure at a first side of the first gate structure; a second conductive structure between a second side of the first gate structure and a first side of the second gate structure; a third conductive structure between a second side of the second gate structure and a first side of the third gate structure; a fourth conductive structure between a second side of the third gate structure and a first side of the fourth gate structure; a fifth conductive structure at a second side of the fourth gate structure; a sixth conductive structure perpendicularly overlapping the well region; a first conductor connected to the first conductive structure, the third conductive structure, and the fifth conductive structure; and a second conductor connected to the sixth conductive structure. A third conductor is connected to the third gate structure and the fourth gate structure; and a fourth conductor is connected to the first gate structure and the second gate structure, wherein the fourth conductive structure and the sixth conductive structure are electrically connected to the well region.

8. The semiconductor device as claimed in claim 7, wherein: The well region conducts a first reference voltage between the fourth conductive structure and the sixth conductive structure. A bit cell corresponding to the first conductor is used to store a first logic value, and a bit cell corresponding to the second conductor is used to store a second logic value that is different from the first logic value.

9. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a bit cell on a substrate including an active region and a well region below the active region, wherein: The bit cell is formed to overlap perpendicularly with the well region, and the step of forming the bit cell includes the following steps: forming a first gate structure and a second gate structure, extending across the active region in a first direction and spaced apart in a second direction; forming a first conductive structure on a first side of the first gate structure; forming a second conductive structure between a second side of the first gate structure and a first side of the second gate structure; and forming a third conductive structure on a second side of the second gate structure; forming a fourth conductive structure to overlap perpendicularly with the well region; forming a first conductor connected to the first conductive structure and the third conductive structure; forming a second conductor connected to the fourth conductive structure; forming a third conductor connected to the first gate structure and the second gate structure, wherein the second conductive structure and the fourth conductive structure are electrically connected to the well region; forming a first epitaxial structure in contact with the well region, the second conductive structure being above the first epitaxial structure; and forming a second epitaxial structure in contact with the well region, the second epitaxial structure being below the fourth conductive structure.

10. The method as described in claim 9, further comprising the steps of: forming a third gate structure and a fourth gate structure; forming a fifth conductive structure at a first side of the third gate structure; forming a sixth conductive structure between a second side of the third gate structure and a first side of the fourth gate structure; and forming a seventh conductive structure between a second side of the fourth gate structure and the first side of the first gate structure.

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