Semiconductor memory devices and methods for manufacturing semiconductor memory devices

Abstract

An embodiment of a semiconductor memory device includes a multilayer and contacts. The multilayer includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers include a first gate electrode layer and a second gate electrode layer. The first gate electrode layer is connected to the contacts in a second direction. The second gate electrode layer is located away from the contacts in the second direction. The first gate electrode layer includes a first conductive portion and a first insulating film. The second gate electrode layer includes a second conductive portion and a second insulating film. The shortest distance in the second direction between the center of the contacts in the second direction and the first insulating film is the same as or smaller than the shortest distance in the second direction between the center of the contacts in the second direction and the second insulating film.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. [Previous Technology]

[0002] It is known that memory cells are configured as three-dimensional inverse (Not AND, NAND) type flash memory (for example, see Japanese Patent Application Publication No. 2022-41054). [Summary of the Invention]

[0003] One embodiment of a semiconductor memory device includes a stacked body and contacts. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers and the plurality of insulating layers are stacked alternately in a first direction. The contacts extend within the stacked body in the first direction. The contacts are conductive. The plurality of gate electrode layers include a first gate electrode layer and a second gate electrode layer. In the first gate electrode layer, the contacts penetrate in the first direction. The first gate electrode layer is connected to the contacts in a second direction intersecting the first direction. The second gate electrode layer is disposed beside the first gate electrode layer in the first direction among the plurality of gate electrode layers. In the second gate electrode layer, the contacts penetrate in the first direction. The second gate electrode layer is located away from the contacts in the second direction. The plurality of insulating layers include a first insulating layer disposed between the first gate electrode layer and the second gate electrode layer in the first direction. The first gate electrode layer has a first conductive portion and a first insulating film, the first insulating film including a portion disposed between the first conductive portion and the first insulating layer and extending in the second direction. The second gate electrode layer has a second conductive portion and a second insulating film, the second insulating film including a portion disposed between the second conductive portion and the first insulating layer and extending in the second direction. The shortest distance in the second direction between the center of the contact in the second direction and the first insulating film is the same as or smaller than the shortest distance in the second direction between the center of the contact in the second direction and the second insulating film.

Implementation Method

[0005] Hereinafter, a semiconductor memory device according to an embodiment and a method for manufacturing a semiconductor memory device will be described with reference to the drawings. In the following description, structures having the same or similar functions are labeled with the same symbols. Moreover, repeated descriptions of these structures are sometimes omitted. In the following description, for reference symbols that end with numbers or letters for distinction, the numbers or letters at the end are sometimes omitted where they can be ignored.

[0006] In this application, the terms are defined as follows: "parallel," "orthogonal," or "identical" may respectively include cases of "generally parallel," "generally orthogonal," or "generally identical." "Connection" is not limited to mechanical connections and may include electrical connections. That is, "connection" is not limited to the direct connection of multiple components, but may include the connection of multiple components with another component intervening between them. "Overlapping" is not limited to the contact of multiple components, but may include the separation of multiple components (where the projected images of multiple components overlap when viewed from a certain direction).

[0007] The +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction is the direction in which the character line WL extends (see Figure 3). The -X direction is the opposite direction of the +X direction. Without distinguishing between the +X and -X directions, it is simply referred to as the X direction. The +Y direction is the direction that intersects (e.g., is orthogonal) the X direction. The +Y direction is the direction in which the bit line BL extends (see Figure 7). The -Y direction is the opposite direction of the +Y direction. Without distinguishing between the +Y and -Y directions, it is simply referred to as the Y direction. The +Z direction is the direction that intersects (e.g., is orthogonal) both the X and Y directions. The +Z direction is the direction from the bit line BL (described later) toward the stack 40 (see Figure 3). The -Z direction is the opposite direction of the +Z direction. Without distinguishing between the +Z and -Z directions, it is simply referred to as the Z direction. In this application, the +Z direction side is sometimes referred to as "upper" and the -Z direction side as "lower". Furthermore, in this application, the position in the Z-direction is sometimes referred to as "height." These terms are for ease of explanation and do not specify the direction of gravity. The Z-direction is an example of a "first direction." The X-direction is an example of a "second direction." In the diagrams described below, illustrations of structures unrelated to the description are sometimes omitted.

[0008] (Embodiment Embodiment) <1. Structure of Semiconductor Memory Device> Figure 1 is a block diagram showing a portion of a semiconductor memory device 1 according to an embodiment. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device. The semiconductor memory device 1 is a NAND flash memory. The semiconductor memory device 1 can be connected to an external host device. The semiconductor memory device 1 can be used as the memory space of the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequence generator) 14, a driver module 15, a column decoder module 16, and a sense amplifier module 17.

[0009] The memory cell array 11 contains multiple blocks BLK0 to BLK(k-1) (where k is an integer greater than or equal to 1). A block BLK is a collection of memory cell transistors. Blocks BLK are used as units for data erasure. Multiple bit lines and multiple word lines are provided in the memory cell array 11. Each memory cell transistor is associated with one bit line and one word line.

[0010] Command register 12 holds the command CMD received by semiconductor memory device 1 from the host device. Address register 13 holds the address information ADD received by semiconductor memory device 1 from the host device. The address information ADD is used to select block BLK, word line, and bit line. Control circuit 14 controls various operations of semiconductor memory device 1. For example, based on the command CMD held in command register 12, control circuit 14 performs data writing, reading, or erasing operations, etc.

[0011] The driver module 15 includes a voltage generation circuit that generates voltages used in various operations of the semiconductor memory device 1. The column decoder module 16 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies the desired voltage to each word line during the write operation. During the read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage of each word line and transmits the determination result as read data DAT to the host device.

[0012] <2. Electrical Structure of Memory Cell Array> Figure 2 is a diagram showing the equivalent circuit of a portion of the memory cell array 11. Figure 2 shows a block BLK contained in the memory cell array 11. The block BLK contains multiple strings STR (e.g., five strings STR0 to STR4).

[0013] Each string STR contains multiple NAND strings NS that are associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes multiple memory cell transistors MT0 to MTn (where n is an integer greater than or equal to 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.

[0014] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge accumulation section. The control gate of the memory cell transistor MT is connected to any one of the word lines WL0 to WLn. In each memory cell transistor MT, charge is accumulated in the charge accumulation section according to the voltage applied to the control gate via the word line WL. In this way, each memory cell transistor MT keeps the data non-volatile.

[0015] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the memory cell transistors MT0 to MTn, which are connected in series. The control gate of the drain-side select transistor STD is connected to any one of the drain-side select gate lines SGD0 to SGD3. The drain-side select transistor STD is electrically connected to the column decoder module 16 via the drain-side select gate line SGD. When a specified voltage is applied to the corresponding drain-side select gate line SGD, the drain-side select transistor STD connects the NAND string NS to the bit line BL.

[0016] The drain of the source-side select transistor STS is connected to the other end of the memory cell transistors MT0 to MTn, which are connected in series. The source of the source-side select transistor STS is connected to the source line SL. The control gate of the source-side select transistor STS is connected to the source-side select gate line SGS. When a specified voltage is applied to the source-side select gate line SGS, the source-side select transistor STS connects the NAND string NS to the source line SL.

[0017] Within the same block BLK, the control gates of memory cell transistors MT0 to MTn are connected to their respective word lines WL0 to WLn. Within the same string STR, the control gate of the drain-side select transistor STD is connected to its corresponding drain-side select gate line SGD. The control gate of the source-side select transistor STS is connected to its source-side select gate line SGS. In the memory cell array 11, the bit line BL is shared by NAND strings NS that have been allocated the same row address in multiple string STRs.

[0018] <3. Structure of Semiconductor Memory Device> Next, the structure of semiconductor memory device 1 will be described. Figure 3 is a cross-sectional view showing a portion of semiconductor memory device 1. Semiconductor memory device 1, for example, has a first wafer 2 and a second wafer 3. The second wafer 3 is a wafer bonded to the first wafer 2.

[0019] <3.1 First Chip> The first chip 2 is a circuit chip that includes peripheral circuitry. The first chip 2 includes, for example, a semiconductor substrate 21, peripheral circuitry 22, insulating portion 23, and multiple pads 24.

[0020] The semiconductor substrate 21 is, for example, a substrate that forms the basis of the first wafer 2. At least a portion of the semiconductor substrate 21 has a plate-like shape that extends along the X and Y directions. The semiconductor substrate 21 is formed, for example, by means of a semiconductor material such as silicon.

[0021] Peripheral circuitry 22 is circuitry used to enable the memory cell array 11 to function. Peripheral circuitry 22 includes multiple transistors 22a and multiple wirings 22b. Peripheral circuitry 22 includes one or more of the command register 12, address register 13, control circuitry 14, driver module 15, column decoder module 16, and sense amplifier module 17. Insulating portion 23 covers peripheral circuitry 22. Multiple pads 24 are disposed on the surface of insulating portion 23. Each pad 24 is electrically connected to peripheral circuitry 22.

[0022] <3.2 Second Chip> The second chip 3 is an array chip that includes a memory cell array 11. The second chip 3, for example, has a memory cell array 11, an insulating portion 31, and a plurality of pads 32. Here, the insulating portion 31 and the plurality of pads 32 will be described, and the memory cell array 11 will be described in detail later.

[0023] An insulating portion 31 covers the memory cell array 11 from the -Z direction side. Multiple pads 32 are disposed on the surface of the insulating portion 31. Each pad 32 is electrically connected to wiring (e.g., wiring 71 or wiring 72) included in the wiring portion 70 of the memory cell array 11, described later. In this embodiment, multiple pads 24 of the first chip 2 and multiple pads 32 of the second chip 3 are bonded face-to-face. This integrates the first chip 2 and the second chip 3.

[0024] <4. Memory Cell Array> Next, the memory cell array 11 will be described. As shown in FIG3, the memory cell array 11 includes an array region AR and a wiring region FR. A plurality of memory pillars MH, which will be described later, are provided in the array region AR. The array region AR is a region capable of storing data. A plurality of contacts CC, which will be described later, are provided in the wiring region FR. The array region AR is a region connecting the plurality of gate electrode layers 41, which will be described later, and the wiring portion 70. The wiring region FR is, for example, provided on both sides of the array region AR in the X direction.

[0025] As shown in FIG3, the memory cell array 11 includes, for example, a stacked layer 40, a source line SL, multiple memory pillars MH, multiple bit lines BL, multiple contacts CH for memory pillars, multiple contacts VY for memory pillars, contacts CC for conductive layers, wiring section 70, support body HR, and multiple partitions 80 (see FIG7).

[0026] <4.1 Stacked Layer> First, the stacked layer 40 will be described. FIG4 is an enlarged cross-sectional view showing the area enclosed by line F4 of the memory cell array 11 shown in FIG3. The stacked layer 40 includes, for example, a plurality of gate electrode layers 41, a plurality of insulating layers 42, an insulating layer 43, and an insulating portion 44. The plurality of gate electrode layers 41 and the plurality of insulating layers 42 are stacked alternately in the Z direction.

[0027] The gate electrode layer 41 extends along the X and Y directions. Each gate electrode layer 41 contains a conductive material (e.g., tungsten, molybdenum, or silicon doped with impurities).

[0028] One or more (e.g., multiple) of the lower gate electrode layers 41 function as drain-side select gate lines (SGDs). The drain-side select gate lines (SGDs) are provided together with respect to multiple memory pillars (MHs) arranged in the X or Y direction. The intersection of the drain-side select gate lines (SGDs) with the channel layers 52 (described later) of each memory pillar (MH) functions as the drain-side select transistor (STD).

[0029] One or more (e.g., multiple) of the gate electrode layers 41 located at the top function as source-side select gate lines (SGS). The source-side select gate lines (SGS) are provided together with respect to multiple memory pillars (MH) arranged in the X or Y direction. The intersection of the source-side select gate lines (SGS) with the channel layers 52 of each memory pillar (MH) functions as the source-side select transistor (STS).

[0030] The gate electrode layer disposed between the gate electrode layer 41 that functions as a drain-side selected gate line (SGD) and the gate electrode layer 41 that functions as a source-side selected gate line (SGS) is called the remaining gate electrode layer 41. This remaining gate electrode layer 41 may also be referred to as a clamping gate electrode layer. At least a portion of this remaining gate electrode layer 41 functions as a word line (WL). The word line (WL) is disposed together with respect to a plurality of memory pillars (MH) arranged in the X and Y directions. In this embodiment, the intersection of the word line (WL) and the channel layer 52 of each memory pillar (MH) functions as a memory cell transistor (MT). The memory cell transistor (MT) will be described in detail later.

[0031] An insulating layer 42 is disposed between two adjacent gate electrode layers 41 in the Z direction. The insulating layer 42 is an interlayer insulating film that insulates the two gate electrode layers 41. The insulating layer 42 extends along the X and Y directions. The insulating layer 42 is formed, for example, from a film containing silicon and oxygen (e.g., a silicon oxide film).

[0032] The insulating layer 43 is an insulating layer disposed above the uppermost gate electrode layer 41. In other words, the insulating layer 43 can also be referred to as an insulating layer disposed above the uppermost gate electrode layer. The insulating layer 43 is disposed between the uppermost gate electrode layer 41 and the source line SL. The insulating layer 43 extends along the X and Y directions. The insulating layer 43 is formed, for example, of a film containing silicon and oxygen (e.g., a silicon oxide film). For example, the thickness of the insulating layer 43 in the Z direction is greater than the thickness of the insulating layer 42 in the Z direction.

[0033] The insulating portion 44 is an insulating portion provided in the wiring area FR described later. The insulating portion 44 covers the ends of a plurality of gate electrode layers 41 and a plurality of insulating layers 42 arranged in a stepped manner from the -Z direction side. The insulating portion 44 is formed, for example, using TEOS (tetraethyl orthosilicate (Si(OC2H5)4)).

[0034] <4.2 Source Line> A source line SL is disposed on the insulating layer 43. The source line SL is formed, for example, by a conductive layer or a semiconductor layer extending in the X and Y directions. The source line SL is formed of a conductive material such as tungsten or molybdenum, or a semiconductor material containing silicon.

[0035] <4.3 Memory Columns> Multiple memory columns MH are arranged in the X and Y directions (see Figure 3). Each memory column MH extends in the Z direction within the stack 40. Multiple memory columns MH penetrate the stack 40. The memory column MH is an example of a "column".

[0036] FIG5 is a cross-sectional view of the memory cell array 11 shown in FIG4 along line F5-F5. The memory cell column MH has, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating portion 53, a void portion (air gap) 54, and a cover portion 55 (see FIG4).

[0037] A memory film 51 is disposed on the outer periphery of the channel layer 52. The memory film 51 is located between the multiple gate electrode layers 41 and the channel layer 52. The memory film 51 includes, for example, a block insulating film 61, a charge trap film 62, and a tunnel insulating film 63.

[0038] A block insulating film 61 is disposed between multiple gate electrode layers 41 and a charge trap film 62. The block insulating film 61 is an insulating film that suppresses reverse tunneling. Reverse tunneling is the phenomenon of charge returning from the word line WL to the charge trap film 62. The block insulating film 61 is formed in a ring shape. The block insulating film 61 extends in the Z direction. For example, the block insulating film 61 is disposed to cover the entire length of the memory pillar MH in the Z direction except for the end MHe1 on the +Z direction side of the memory pillar MH, which will be described later. The block insulating film 61 is, for example, a laminated structure film containing multiple insulating films such as films containing silicon and oxygen or films containing metal and oxygen. An example of a film containing metal and oxygen is an aluminum oxide film. The block insulating film 61 may contain high-k materials such as silicon nitride or hafnium oxide.

[0039] The charge trap film 62 is located between the block insulating film 61 and the tunnel insulating film 63. The charge trap film 62 is formed in a ring shape. The charge trap film 62 extends in the Z direction. For example, the charge trap film 62 is configured to cover the entire length of the memory pillar MH in the Z direction except for the end MHe1 on the +Z direction side of the memory pillar MH. The charge trap film 62 is a functional film having multiple crystal defects (capture energy levels) and being able to capture charges in the crystal defects. The charge trap film 62 is formed, for example, from a film containing silicon and nitrogen. The portion of the charge trap film 62 adjacent to each character line WL is an example of a "charge accumulation section" that can store information by accumulating charges.

[0040] A tunnel insulating film 63 is disposed between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63, for example, has an annular shape disposed along the outer peripheral surface of the channel layer 52. The tunnel insulating film 63 extends along the channel layer 52 in the Z direction. The tunnel insulating film 63, for example, is disposed to cover the entire length of the memory pillar MH in the Z direction, except for the end MHe1 on the +Z direction side of the memory pillar MH. The tunnel insulating film 63 acts as a potential barrier between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0041] Channel layer 52 is disposed inside memory film 51. Channel layer 52 is formed in a ring shape. Channel layer 52 extends in the Z direction. Channel layer 52 is disposed, for example, to cover the entire length of memory pillar MH in the Z direction. Channel layer 52 is formed, for example, from a semiconductor material such as polysilicon. Channel layer 52 may be doped with impurities. When a voltage is applied to word line WL, channel layer 52 forms a channel and electrically connects bit line BL to source line SL.

[0042] Accordingly, at the same height as each word line WL, a metal-al-nitrogen-oxygen-silicon (MANOS) type memory cell transistor MT is formed by the edge of the word line WL adjacent to the memory pillar MH, the block insulating film 61, the charge trap film 62, the tunnel insulating film 63, and the channel layer 52. Furthermore, the memory film 51 can also replace the charge trap film 62 and have a charge storage section (floating gate electrode) as the charge storage section. The floating gate type charge storage section is formed, for example, from polycrystalline silicon containing impurities.

[0043] An insulating portion 53 is disposed inside the channel layer 52. The insulating portion 53 fills at least a portion of the interior of the channel layer 52. The insulating portion 53 is formed of a film containing silicon and oxygen. In this embodiment, the insulating portion 53 is formed in an annular shape along the inner peripheral surface of the channel layer 52 to form a void (air gap) 54 inside. Alternatively, the void 54 may not be present. The insulating portion 53 extends in the Z direction. For example, the insulating portion 53 is configured to extend along the entire length of the memory cylinder MH in the Z direction, except for the end on the -Z direction side (see Figure 4).

[0044] FIG6 is an enlarged cross-sectional view showing the area enclosed by line F6 of the memory cell array 11 shown in FIG4. In this embodiment, each gate electrode layer 41 includes, for example, a conductive portion 45, a barrier metal film 46, and an insulating film 47.

[0045] The conductive portion 45 is the main portion forming the gate electrode layer 41. The conductive portion 45 extends in layers in the X and Y directions. The conductive portion 45 contains the conductive material (e.g., tungsten, molybdenum, or silicon doped with impurities).

[0046] The barrier metal film 46 is a film used to suppress the diffusion of the conductive material contained in the conductive portion 45. The barrier metal film 46 may contain, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen. The barrier metal film 46 is disposed along the surface of the conductive portion 45. The barrier metal film 46 is disposed between the conductive portion 45 and the insulating film 47. The barrier metal film 46 has a first film portion 46a, a second film portion 46b, and a third film portion 46c.

[0047] A first film portion 46a is disposed between the surface of the conductive portion 45 on the -Z direction side and the insulating layer 42 located on the -Z direction side of the conductive portion 45. The first film portion 46a extends along the surface of the conductive portion 45 on the -Z direction side in the X and Y directions.

[0048] The second film portion 46b is disposed between the surface of the conductive portion 45 on the +Z direction side and the insulating layer 42 located on the +Z direction side of the conductive portion 45. The second film portion 46b extends along the surface of the conductive portion 45 on the +Z direction side in the X and Y directions.

[0049] The third film portion 46c is disposed along the edge of the conductive portion 45 facing the memory pillar MH. The third film portion 46c is located between the conductive portion 45 and the memory pillar MH. The third film portion 46c extends in the Z direction.

[0050] The insulating film 47 is an insulating film that improves the withstand voltage of the gate electrode layer 41. The insulating film 47 is formed, for example, from a film containing aluminum and oxygen (e.g., an aluminum oxide film). The insulating film 47 is disposed along the surface of the barrier metal film 46. The insulating film 47 is disposed along the surface of the gate electrode layer 41. The insulating film 47 has a first film portion 47a, a second film portion 47b, and a third film portion 47c.

[0051] A first film portion 47a is disposed between the first film portion 46a of the barrier metal film 46 and the insulating layer 42 located on the -Z direction side of the conductive portion 45. That is, the first film portion 47a is disposed between the surface of the conductive portion 45 on the -Z direction side and the insulating layer 42 located on the -Z direction side of the conductive portion 45. The first film portion 47a extends along the surface of the first film portion 46a of the barrier metal film 46 in the X and Y directions.

[0052] The second film portion 47b is disposed between the second film portion 46b of the barrier metal film 46 and the insulating layer 42 located on the +Z direction side of the conductive portion 45. That is, the second film portion 47b is disposed between the surface of the conductive portion 45 on the +Z direction side and the insulating layer 42 located on the +Z direction side of the conductive portion 45. The second film portion 47b extends along the surface of the second film portion 46b of the barrier metal film 46 in the X and Y directions.

[0053] The third film portion 47c is disposed between the third film portion 46c of the barrier metal film 46 and the charge trap film 62 of the memory pillar MH. That is, the third film portion 47c is disposed between the edge of the conductive portion 45 facing the memory pillar MH and the charge trap film 62 of the memory pillar MH. The third film portion 47c extends in the Z direction along the surface of the third film portion 46c of the barrier metal film 46.

[0054] In this embodiment, the block insulating film 61 includes a first portion 61a and a second portion 61b. The first portion 61a is formed in a ring shape along the outer periphery of the charge trap film 62. The first portion 61a extends in the Z direction. For example, the first portion 61a is configured to cover the entire length of the memory pillar MH in the Z direction except for the end MHe1 on the +Z direction side of the memory pillar MH.

[0055] On the other hand, the second portion 61b is formed from the third film portion 47c of the insulating film 47 of the plurality of gate electrode layers 41. The second portion 61b is formed in a ring shape along the outer periphery of the first portion 61a of the block insulating film 61. The second portion 61b exists at a height corresponding to the gate electrode layers 41. In this embodiment, the block insulating film 61 is formed by the first portion 61a and the second portion 61b.

[0056] Next, referring back to FIG. 4, the cover portion 55 will be described. The cover portion 55 is disposed below the insulating portion 53. The cover portion 55 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polycrystalline silicon. The cover portion 55 may also be doped with impurities. The cover portion 55 is disposed on the inner peripheral side of the end of the memory film 51 in the -Z direction direction. The cover portion 55 is integrally formed with the channel layer 52. The cover portion 55 and the lower end of the channel layer 52 together form the end of the memory pillar MH in the -Z direction direction. The contact CH is in contact with the cover portion 55 from the -Z direction direction side.

[0057] Next, the +Z direction side end MHe1 of the memory column MH will be described. In this embodiment, the end MHe1 of the memory column MH protrudes from the stacked body 40 in the +Z direction. The end MHe1 of the memory column MH is connected to the source line SL. At the end MHe1 of the memory column MH, there is no memory film 51, and the channel layer 52 is exposed outside the memory column MH. Herein, the channel layer 52 is connected to the source line SL.

[0058] <4.4 Bit Line> Next, returning to Figure 3, the bit line BL will be explained. The bit line BL is a wiring used to select one memory cylinder MH from multiple memory cylinders MH. Multiple bit lines BL are arranged on the lower side (-Z direction side) relative to the stack 40. The multiple bit lines BL are arranged at intervals in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends below the corresponding multiple memory cylinders MH.

[0059] Each bit line BL is connected to the channel layer 52 of the memory cell pillar MH via contact VY and contact CH. In this way, by combining the word line WL and the bit line BL, the memory cell transistor MT can be arbitrarily selected from multiple memory cell transistors MT that can be configured into three dimensions.

[0060] <4.5 Contacts for Gate Electrode Layer> As shown in FIG3, the contact CC is an electrical connection portion that electrically connects the gate electrode layer 41 to the wiring 72 (described later) included in the wiring portion 70. Multiple contacts CC are provided, for example, in the wiring area FR of the memory cell array 11. Multiple contacts CC extend in the Z direction within the stacked body 40. Multiple contacts CC are connected to different gate electrode layers 41. Contact CC contains a conductive material (e.g., tungsten, molybdenum, or silicon doped with impurities). Contact CC is conductive. Furthermore, the structure of the wiring area FR will be described in detail later.

[0061] <4.6 Wiring Section> Next, the wiring section 70 will be described. The wiring section 70 is disposed, for example, between the laminate 40 and the semiconductor substrate 21. The wiring section 70 includes, for example, a plurality of wirings 71, a plurality of through-holes V1, and a plurality of wirings 72.

[0062] Wiring 71 is an electrical connection portion that electrically connects bit lines BL to pads 32. Multiple wirings 71 are arranged below, for example, relative to multiple bit lines BL. Each wiring 71 extends, for example, along the X or Y direction. A through-hole V1 is provided between the wiring 71 and the bit line BL to electrically connect the wiring 71 and the bit line BL.

[0063] Wiring 72 is an electrical connection that electrically connects the contact CC of the conductive layer to the pad 32. Wiring 72 is electrically connected to the gate electrode layer 41 via the contact CC of the conductive layer. Regarding wiring 72, a voltage is applied to select the gate electrode layer 41 (word line WL, drain-side select gate line SGD, or source-side select gate line SGS).

[0064] <4.7 Support Body> Next, the support body HR will be described. The support body HR is provided in the wiring area FR. The support body HR extends through the laminate 40 in the Z direction in the wiring area FR. The support body HR is formed, for example, of an insulating material. The support body HR supports a plurality of insulating layers 42 in the replacement step described later.

[0065] <5. Dividing Section> Next, the dividing section 80 will be described. FIG7 is a cross-sectional view of the semiconductor memory device 1 shown in FIG3 along line F7-F7. In this embodiment, a plurality of dividing sections 80 are provided on the stacked body 40. The plurality of dividing sections 80 are arranged separately in the Y direction. The plurality of dividing sections 80 extend in the Z direction within the stacked body 40, dividing one or more gate electrode layers 41, including the bottommost layer, in the Y direction. The plurality of dividing sections 80 include, for example, a plurality of dividing sections ST and a plurality of dividing sections SHE.

[0066] <5.1 Dividing Section ST> The dividing section ST is a wall portion that divides the laminate 40 in the Y direction. Multiple dividing sections ST are arranged separately in the Y direction. The dividing section ST extends through the laminate 40 in the Z direction and extends in the X direction. That is, the dividing section ST is a wall portion provided along both the Z and X directions. The dividing section ST divides all the gate electrode layers 41 contained in the laminate 40 in the Y direction.

[0067] <5.2 Segmentation Section SHE> The segmentation section SHE is a segmentation section that is shorter in length in the Z direction compared to the segmentation section ST. The segmentation section SHE is a wall portion that divides the lower end of the laminate 40 in the Y direction. Multiple segmentation sections SHE are arranged separately in the Y direction. In this embodiment, there are multiple (e.g., 4) segmentation sections SHE between two adjacent segmentation sections ST in the Y direction. The segmentation section SHE is provided at the lower end of the laminate 40. The segmentation section SHE extends in the Z direction to the middle of the laminate 40 and extends in the X direction. That is, the segmentation section SHE is a wall portion provided along both the Z and X directions.

[0068] The dividing section SHE penetrates a portion of the gate electrode layer 41, including the lowest layer, among the multiple gate electrode layers 41. The dividing section SHE divides said portion of the gate electrode layer 41 in the Y direction. For example, the dividing section SHE penetrates each of all the gate electrode layers 41 that function as drain-side selected gate lines (SGD). On the other hand, the dividing section SHE does not reach the gate electrode layer 41 that functions as a character line (WL). The dividing section SHE only divides the gate electrode layer 41 that functions as a drain-side selected gate line (SGD) in the Y direction. The dividing section SHE is formed, for example, from a film containing silicon and oxygen.

[0069] <6. Wiring Area> Next, the wiring area FR will be described. In the following diagram, for ease of explanation, the structure related to the six gate electrode layers 41 is shown.

[0070] <6.1 Structure of the Wiring Area> Figure 8 shows a cross-sectional view of the memory cell array 11 viewed from above. The wiring area FR is the area where memory pillars MH are not provided. The wiring area FR has multiple contacts CC and multiple supports HR. The contacts CC are electrical connection parts that electrically connect the gate electrode layer 41 to the wiring 72 included in the wiring section 70. The supports HR are supports that support the multiple insulating layers 42 in the replacement step described later.

[0071] FIG9 is a cross-sectional view of the memory cell array 11 shown in FIG8 along line F9-F9. In the wiring region FR, the lengths of the multiple gate electrode layers 41 in the X direction are different from each other. For example, regarding the length of each of the multiple gate electrode layers 41 in the X direction, the gate electrode layer 41 located on the -Z direction side is shorter in the X direction. In other words, regarding the multiple gate electrode layers arranged in the Z direction, the length of each of the multiple gate electrode layers 41 gradually increases towards the -Z direction side.

[0072] In this embodiment, each gate electrode layer 41 has a stepped portion 101 and a non-stepped portion 102. The stepped portion 101 is the portion that does not overlap with other gate electrode layers 41 located on the -Z side when viewed from the Z direction. The non-stepped portion 102 is the portion that overlaps with other gate electrode layers 41 located on the -Z side when viewed from the Z direction.

[0073] In this embodiment, each gate electrode layer 41 has a stepped portion 101 that protrudes in the -Z direction. The thickness of the stepped portion 101 in the Z direction in the portion with the protrusion 105 is greater than the thickness of the non-stepped portion 102 in the Z direction.

[0074] In this embodiment, the plurality of contacts CC have the same length in the Z direction. Each contact CC extends through the laminate 40 in the Z direction. Each contact CC extends through one or more (e.g., multiple) gate electrode layers 41 that overlap with the contact CC when viewed from the Z direction.

[0075] For example, each contact CC is positioned to overlap with the protrusion 105 of the gate electrode layer 41 to which the contact CC is connected when viewed from the Z direction. Each contact CC penetrates the protrusion 105 of the gate electrode layer 41 to which the contact CC is connected in the Z direction. Each contact CC also penetrates the non-stepped portion 102 of the gate electrode layer 41 (non-connection gate electrode layer 41) to which the contact CC is connected in the Z direction.

[0076] Each contact CC is located away from the gate electrode layer 41 of the non-connected object. An insulating portion 111 is provided between each contact CC and the gate electrode layer 41 of the non-connected object. The insulating portion 111 is disposed at the same height as the gate electrode layer 41 of the non-connected object. The insulating portion 111 is formed in a ring shape along the outer periphery of the contact CC. Each contact CC and the gate electrode layer 41 of the non-connected object are electrically insulated from each other by the insulating portion 111.

[0077] FIG10 is an enlarged cross-sectional view showing the area enclosed by line F10 of the memory cell array 11 shown in FIG9. For ease of explanation, FIG10 is illustrated in the opposite orientation to FIG9. The plurality of gate electrode layers 41 include, for example, a first gate electrode layer 41A, a second gate electrode layer 41B, and a third gate electrode layer 41C. The second gate electrode layer 41B is a gate electrode layer 41 disposed beside the +Z direction side of the first gate electrode layer 41A. The length of the second gate electrode layer 41B in the X direction is greater than the length of the first gate electrode layer 41A in the X direction. The third gate electrode layer 41C is a gate electrode layer 41 disposed beside the +Z direction side of the second gate electrode layer 41B. The length of the third gate electrode layer 41C in the X direction is greater than the length of the second gate electrode layer 41B in the X direction.

[0078] The plurality of insulating layers 42 include a first insulating layer 42A and a second insulating layer 42B. The first insulating layer 42A is an insulating layer 42 disposed in the Z direction between the first gate electrode layer 41A and the second gate electrode layer 41B. The second insulating layer 42B is an insulating layer 42 disposed in the Z direction between the second gate electrode layer 41B and the third gate electrode layer 41C.

[0079] The plurality of contacts CC includes a first contact CCA and a second contact CCB. The first contact CCA is a contact CC electrically connected to the first gate electrode layer 41A. The first contact CCA is disposed at a position that overlaps with the protrusion 105 of the first gate electrode layer 41A when viewed from the Z direction. The first contact CCA penetrates the protrusion 105 of the first gate electrode layer 41A in the Z direction. The first contact CCA penetrates the non-stepped portion 102 of the second gate electrode layer 41B and the non-stepped portion 102 of the third gate electrode layer 41C in the Z direction.

[0080] The second contact CCB is configured to be farther away from the array region AR than the first contact CCA. The second contact CCB is a contact CC electrically connected to the second gate electrode layer 41B. The second contact CCB is configured to overlap with the protrusion 105 of the second gate electrode layer 41B when viewed from the Z direction. The second contact CCB penetrates the protrusion 105 of the second gate electrode layer 41B in the Z direction. The second contact CCB penetrates the non-stepped portion 102 of the third gate electrode layer 41C in the Z direction.

[0081] Each contact CC has, for example, a columnar portion 121 and a bulge 122. The columnar portion 121 is formed into a cylindrical shape, for example. The columnar portion 121 extends along the Z direction in a manner that covers the entire length of the contact CC in the Z direction. The bulge 122 is a portion that protrudes radially outward from the circumference of the columnar portion 121 towards the contact CC. The bulge 122 is provided in a portion of the contact CC in the Z direction. The bulge 122 of each contact CC is provided at the same height as the gate electrode layer 41, which is the connection destination of the contact CC. The bulge 122 of each contact CC protrudes from the columnar portion 121 toward the gate electrode layer 41, which is the connection destination of the contact CC. For example, the bulge 122 of the first contact CCA is provided at the same height as the first gate electrode layer 41A and protrudes from the columnar portion 121 toward the first gate electrode layer 41A. The bulge 122 of the second contact CCB is disposed at the same height as the second gate electrode layer 41B, and protrudes from the columnar portion 121 toward the second gate electrode layer 41B. The columnar portion 121 is an example of a "third conductive portion". The columnar portion 121 may also be referred to as a "first portion". The bulge 122 is an example of a "fourth conductive portion". The bulge 122 may also be referred to as a "second portion".

[0082] In addition, each contact CC includes a conductive portion 125 and a barrier metal film 126. The conductive portion 125 is the part that forms the main portion of the contact CC. The conductive portion 125 extends in the Z direction. The conductive portion 125 contains a conductive material (e.g., tungsten, molybdenum, or silicon doped with impurities).

[0083] The barrier metal film 126 is a film used to suppress the diffusion of conductive material contained in the conductive portion 125. The barrier metal film 126 may contain, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen. The barrier metal film 126 is disposed along the surface of the conductive portion 125. The barrier metal film 126 may include, for example, a first film portion 126a and a second film portion 126b. The first film portion 126a is disposed on the surface of the columnar portion 121 of the contact element CC. The second film portion 126b is disposed on the surface of the bulge portion 122 of the contact element CC.

[0084] In Figure 10, a virtual center line CL1 passing through the center of the first contact member CCA in the X direction is shown. Hereinafter, for ease of explanation, the center of the first contact member CCA in the X direction will sometimes be referred to as "center CL1". Center CL1 refers to a point located on center line CL1.

[0085] <6.2 First Gate Electrode Layer> Next, the first gate electrode layer 41A will be described. In the first gate electrode layer 41A, the first contact CCA extends through in the Z direction. The first gate electrode layer 41A is adjacent to and connected to the bulge 122 of the first contact CCA in both the X and Y directions. The first gate electrode layer 41A is connected to the bulge 122 of the first contact CCA in both the X and Y directions.

[0086] As described above, the first gate electrode layer 41A includes a conductive portion 45, a barrier metal film 46, and an insulating film 47. The conductive portion 45 of the first gate electrode layer 41A is an example of a "first conductive portion". The barrier metal film 46 of the first gate electrode layer 41A is an example of a "first barrier metal film". The insulating film 47 of the first gate electrode layer 41A is an example of a "first insulating film".

[0087] The insulating film 47 of the first gate electrode layer 41A has a first film portion 47a and a second film portion 47b. The first film portion 47a of the first gate electrode layer 41A is disposed along the surface of the first gate electrode layer 41A in the -Z direction. A portion of the first film portion 47a of the first gate electrode layer 41A extends in the X direction along the surface of the protrusion 105 of the first gate electrode layer 41A. The second film portion 47b of the first gate electrode layer 41A is disposed along the surface of the first gate electrode layer 41A in the +Z direction. The second film portion 47b of the first gate electrode layer 41A is disposed between the conductive portion 45 of the first gate electrode layer 41A and the first insulating layer 42A. The second film portion 47b extends in the X direction.

[0088] The shortest distance in the X direction between the insulating film 47 of the first gate electrode layer 41A and the center CL1 of the first contact CCA is the distance L1. For example, the distance L1 is defined by the following shortest distance L1A or shortest distance L1B. The shortest distance L1A is the shortest distance in the X direction between the first film portion 47a of the first gate electrode layer 41A and the center CL1 of the first contact CCA. The shortest distance L1B is the shortest distance in the X direction between the second film portion 47b of the first gate electrode layer 41A and the center CL1 of the first contact CCA.

[0089] In addition to the first film portions 46a to 46c, the barrier metal film 46 of the first gate electrode layer 41A also has a fourth film portion 46d. The fourth film portion 46d is disposed between the conductive portion 45 of the first gate electrode layer 41A and the bulge 122 of the first contact member CCA. The fourth film portion 46d extends in the Z direction. The fourth film portion 46d is in contact with the second film portion 126b of the barrier metal film 126 of the first contact member CCA in the X direction. The first film portion 46a or the second film portion 46b is an example of "the first portion of the first barrier metal film". The fourth film portion 46d is an example of "the second portion of the first barrier metal film".

[0090] In this embodiment, a boundary B is formed between the first contact CCA and the first gate electrode layer 41A. The boundary B is formed by at least one of the fourth film portion 46d of the barrier metal film 46 of the first gate electrode layer 41A and the second film portion 126b of the barrier metal film 126 of the first contact CCA.

[0091] <6.2 Second Gate Electrode Layer> Next, the second gate electrode layer 41B will be described. In the second gate electrode layer 41B, the contact CCA and the contact CCB extend through in the Z direction. The second gate electrode layer 41B is adjacent to and connected to the bulge 122 of the second contact CCB in the X and Y directions. The second gate electrode layer 41B is connected to the bulge 122 of the second contact CCB in the X and Y directions. On the other hand, the second gate electrode layer 41B is away from the first contact CCA in the X and Y directions. An insulating portion 111 is provided between the second gate electrode layer 41B and the first contact CCA.

[0092] As described above, the second gate electrode layer 41B includes a conductive portion 45, a barrier metal film 46, and an insulating film 47. The conductive portion 45 of the second gate electrode layer 41B is an example of a "second conductive portion". The insulating film 47 of the second gate electrode layer 41B is an example of a "second insulating film". In addition to the first film portions 47a to the third film portions 47c, the insulating film 47 of the second gate electrode layer 41B also has a fourth film portion 47d.

[0093] A first film portion 47a of the second gate electrode layer 41B is disposed along the surface of the second gate electrode layer 41B on the -Z direction side. The first film portion 47a of the second gate electrode layer 41B is disposed between the conductive portion 45 of the second gate electrode layer 41B and the first insulating layer 42A. The first film portion 47a extends in the X direction.

[0094] The second film portion 47b of the second gate electrode layer 41B is disposed along the surface of the second gate electrode layer 41B on the +Z direction side. The second film portion 47b of the second gate electrode layer 41B is disposed between the conductive portion 45 of the second gate electrode layer 41B and the second insulating layer 42B. The second film portion 47b extends in the X direction.

[0095] The fourth film portion 47d of the second gate electrode layer 41B extends in the Z direction such that it covers the edges of the first film portion 47a and the second film portion 47b of the second gate electrode layer 41B. The fourth film portion 47d of the second gate electrode layer 41B is disposed beside the insulating portion 111 in the X direction. The fourth film portion 47d is in contact with the insulating portion 111 in the X direction. The fourth film portion 47d of the second gate electrode layer 41B extends along the insulating portion 111 in the Z direction.

[0096] The shortest distance between the insulating film 47 of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction is distance L2. For example, distance L2 is defined by the following shortest distances L2A, L2B, or L2C. Shortest distance L2A is the shortest distance in the X direction between the first film portion 47a of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction. Shortest distance L2B is the shortest distance in the X direction between the second film portion 47b of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction. Shortest distance L2C is the shortest distance in the X direction between the fourth film portion 47d of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction.

[0097] <6.3 Third Gate Electrode Layer> Next, the third gate electrode layer 41C will be described. In the third gate electrode layer 41C, the first contact CCA and the second contact CCB extend through each other in the Z direction. For example, the third gate electrode layer 41C is located away from the first contact CCA in the X and Y directions. An insulating portion 111 is provided between the third gate electrode layer 41C and the first contact CCA.

[0098] As described above, the third gate electrode layer 41C includes a conductive portion 45, a barrier metal film 46, and an insulating film 47. In addition to the first film portion 47a and the second film portion 47b, the insulating film 47 of the third gate electrode layer 41C also has a fourth film portion 47d.

[0099] The first film portion 47a of the third gate electrode layer 41C is disposed along the surface of the third gate electrode layer 41C on the -Z direction side. The first film portion 47a of the third gate electrode layer 41C is disposed between the conductive portion 45 of the third gate electrode layer 41C and the second insulating layer 42B. The first film portion 47a extends in the X direction.

[0100] The second film portion 47b of the third gate electrode layer 41C is disposed along the surface of the third gate electrode layer 41C on the +Z direction side. The second film portion 47b of the third gate electrode layer 41C is disposed between the conductive portion 45 of the third gate electrode layer 41C and other insulating layers 42 (the insulating layers 42 located on the +Z direction side of the third gate electrode layer 41C). The second film portion 47b extends in the X direction.

[0101] The fourth film portion 47d of the third gate electrode layer 41C extends in the Z direction such that it covers the edges of the first film portion 47a and the second film portion 47b of the third gate electrode layer 41C. The fourth film portion 47d of the third gate electrode layer 41C is disposed beside the insulating portion 111 in the X direction. The fourth film portion 47d is in contact with the insulating portion 111 in the X direction. The fourth film portion 47d of the third gate electrode layer 41C extends along the insulating portion 111 in the Z direction.

[0102] The shortest distance between the insulating film 47 of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction is distance L3. Distance L3 is, for example, the same as distance L2. For example, distance L3 is defined by the following shortest distances L3A, L3B, or L3C. Shortest distance L3A is the shortest distance between the first film portion 47a of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction. Shortest distance L3B is the shortest distance between the second film portion 47b of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction. Shortest distance L3C is the shortest distance between the fourth film portion 47d of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction.

[0103] <6.4 Positional Relationship of Insulating Film> In this embodiment, the shortest distance in the X direction (distance L1) between the insulating film 47 of the first gate electrode layer 41A and the center CL1 of the first contact CCA in the X direction is smaller than the shortest distance in the X direction (distance L2) between the insulating film 47 of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction. In this embodiment, in at least a portion of the region overlapping with the protrusion 105 of the first gate electrode layer 41A when viewed from the Z direction, distance L1 is smaller than distance L2. For example, distance L1 is more than 20 nm smaller than distance L2. However, the embodiment is not limited to the examples of the aforementioned values. Furthermore, several examples of dimensional relationships are shown below. The embodiment is not limited to examples of structures having the dimensional relationships described below. The embodiment may also include structures having dimensional relationships different from those described below.

[0104] In another viewpoint, the shortest distance in the X direction (distance L11) between the insulating film 47 of the first gate electrode layer 41A and the columnar portion 121 of the first contact CCA is smaller than the shortest distance in the X direction (distance L12) between the insulating film 47 of the second gate electrode layer 41B and the columnar portion 121 of the first contact CCA. For example, distance L11 is less than half of distance L12.

[0105] For example, the distance L11 is smaller than the thickness (e.g., maximum thickness) T1 in the Z direction of the stepped portion 101 of the first gate electrode layer 41A. On the other hand, the distance L12 is larger than the thickness (e.g., maximum thickness) T1 in the Z direction of the stepped portion 101 of the first gate electrode layer 41A.

[0106] For example, the distance L11 is smaller than the thickness (e.g., maximum thickness) T2 in the Z direction of the non-stepped portion 102 of the second gate electrode layer 41B. On the other hand, the distance L12 is larger than the thickness (e.g., maximum thickness) T2 in the Z direction of the non-stepped portion 102 of the second gate electrode layer 41B.

[0107] For example, the distance L11 is smaller than the thickness (e.g., maximum thickness) T3 in the Z direction of the first insulating layer 42A. On the other hand, the distance L12 is larger than the thickness (e.g., maximum thickness) T3 in the Z direction of the first insulating layer 42A.

[0108] According to another viewpoint, the shortest distance in the X direction (distance L1) between the insulating film 47 of the first gate electrode layer 41A and the center CL1 of the first contact CCA in the X direction is smaller than the shortest distance in the X direction (distance L4) between the conductive portion 45 of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction.

[0109] According to another viewpoint, the shortest distance in the X direction (distance L5) between the fourth film portion 46d of the barrier metal film 46 of the first gate electrode layer 41A and the center CL1 of the first contact CCA in the X direction is smaller than the shortest distance in the X direction (distance L2) between the insulating film 47 of the second gate electrode layer 41B and the center CL1 of the first contact CCA in the X direction. In this embodiment, the shortest distance in the X direction between the boundary B (the boundary between the first contact CCA and the first gate electrode layer 41A) and the center CL1 of the first contact CCA in the X direction corresponds to the distance L5.

[0110] According to another viewpoint, the shortest distance in the X direction (distance L1) between the insulating film 47 of the first gate electrode layer 41A and the center CL1 of the first contact CCA in the X direction is smaller than the shortest distance in the X direction (distance L3) between the insulating film 47 of the third gate electrode layer 41C and the center CL1 of the first contact CCA in the X direction.

[0111] Furthermore, the implementation is not limited to the examples described. For example, the distance L1 may be the same as the distance L2 or the distance L3. The distance L11 may also be the same as the distance L12. The distance L1 may also be the same as the distance L4. The distance L5 may also be the same as the distance L2.

[0112] FIG11 is a cross-sectional view along line F11-F11 of the memory cell array shown in FIG10. In this embodiment, the edges of the first film portion 47a and the second film portion 47b (only the second film portion 47b is shown in FIG12) of the first gate electrode layer 41A are formed in a ring shape centered on the center line CL1. In addition, the fourth film portion 46d of the second gate electrode layer 41B and the fourth film portion 46d of the third gate electrode layer 41C are formed in a ring shape centered on the center line CL1.

[0113] FIG12 is a cross-sectional view of the memory cell array shown in FIG10 along line F12-F12. In this embodiment, the cross-section along the Y direction (the cross-section shown in FIG11) also has the same structure as the cross-section along the X direction (the cross-section shown in FIG10). Therefore, in the description relating to the cross-section along the Y direction, in the description relating to the cross-section along the X direction, simply replace "X direction" with "Y direction".

[0114] <7. Manufacturing Method of Semiconductor Memory Device> Next, the manufacturing method of semiconductor memory device 1 will be described. Figures 13A to 13H and Figures 14A to 14E are cross-sectional views used to explain the manufacturing method of semiconductor memory device 1. Furthermore, for ease of explanation, the structure shown on the left side of Figures 13A to 13H shows a cross-section of the contact CC and the support HR formed by cutting through the wiring area FR with a cutting line.

[0115] First, the overall process will be described with reference to FIGS. 13A to 13H. As shown in FIG. 13A, an insulating layer 43 is formed on a semiconductor substrate 201. Next, insulating layers 202 and 42 are deposited alternately on the insulating layer 43. The insulating layer 202 is, for example, a sacrificial layer that is replaced by the gate electrode layer 41 in a replacement step described later. The insulating layer 202 is, for example, formed of a film containing nitrogen and silicon (e.g., a silicon nitride film). Thereby, a laminate 40A is formed. The insulating layer 202 is an example of a "first insulating layer". The insulating layer 42 is an example of a "second insulating layer".

[0116] Next, a resist (not shown) is applied to the laminate 40A, and resist refinement and vertical processing based on anisotropic etching are performed alternately and repeatedly to remove unwanted portions of the insulating layer 202 and the insulating layer 42. This creates a step region SR on the laminate 40A. In the step region SR, the lengths of the plurality of insulating layers 202 in the X direction are different.

[0117] Next, as shown in FIG13B, in the step region SR, an insulating layer 203 is provided on the respective ends 202a of the plurality of insulating layers 202. The insulating layer 203 is formed, for example, of the same insulating material as the insulating layer 202. The insulating layer 203 is formed, for example, of a film containing nitrogen and silicon (e.g., a silicon nitride film).

[0118] Next, as shown in FIG13C, unwanted portions of the insulating layer 203 are removed by etching. This forms multiple insulating layers 203a from the insulating layer 203. The insulating layers 203a are formed on the ends 202a of the insulating layer 202. The insulating layer 203a is a sacrificial layer replaced by the protrusions 105 of the gate electrode layer 41 in the replacement step described later. The insulating layer 203a is an example of a "third insulating layer". Next, an insulating portion 44 is formed in the step region SR by burying the ends 202a of the insulating layer 202 and the insulating layers 203a. This forms a laminate 40B.

[0119] Next, as shown in FIG13D, a plurality of holes h1 for forming the contact CC are formed in the laminate 40B. The holes h1 penetrate the laminate 40B in the Z direction. Then, a semiconductor material (e.g., amorphous silicon) is supplied into the interior of the holes h1. Thereby, a semiconductor portion 211 is formed inside the holes h1. The semiconductor portion 211 is a sacrificial portion that is replaced by the contact CC in the steps described later. Similarly, a plurality of holes h2 for forming the support HR are formed in the laminate 40B. The holes h2 penetrate the laminate 40B in the Z direction. Then, an insulating material is supplied into the interior of the holes h2. Thereby, the support HR is formed inside the holes h2.

[0120] Next, as shown in FIG13E, the semiconductor portion 211 is removed by etching from the inside of the hole h1. Then, by etching the hole h1, the edge portions of the insulating layer 202 and the insulating layer 203a adjacent to the hole h1 are removed. Thereby, a first space S1 and a second space S2 communicating with the hole h1 are provided inside the laminate 40B. The first space S1 removes the edge portions of the insulating layer 203a and the edge portions of the insulating layer 202 connected to the insulating layer 203a. Thereby, the first space S1 is formed in the region where the edge portions of the insulating layer 203a and the edge portions of the insulating layer 202 connected to the insulating layer 203a exist. This region is an example of a first region. On the other hand, the second space S2 removes the edge portions of the insulating layer 202 that are not connected to the insulating layer 203a. Thereby, the second space S2 is formed in the region where the edge portions of the insulating layer 202 exist. This region is an example of a second region. The width of the first space S1 in the Z direction is greater than the width of the second space S2 in the Z direction.

[0121] Next, as shown in FIG13F, insulating material is supplied to the interior of the hole h1. This forms an insulating portion 221 that fills the second space S2 and is disposed along the inner surface of the hole h1. The insulating portion 221 is formed, for example, of a film containing silicon and oxygen (e.g., a silicon oxide film). At this time, the width of the first space S1 in the Z direction is greater than the width of the second space S2 in the Z direction. Therefore, the interior of the first space S1 cannot be completely filled by the insulating portion 221.

[0122] Next, as shown in FIG13G, unwanted portions of the insulating portion 221 are removed by etching through the hole h1. Thereby, an insulating portion 111 is formed from the insulating portion 221 in the portion corresponding to the second space S2. The insulating portion 111 is the insulating portion that fills the second space S2. The insulating portion 111 is an example of a "first insulating portion". On the other hand, the insulating portion 221 existing in the first space S1 is removed, and the first space S1 is re-formed.

[0123] Next, as shown in FIG13H, a replacement step is performed in which the gate electrode layer 41 replaces the insulating layer 202 and the insulating layer 203a. For example, the insulating layer 202 and the insulating layer 203a are removed by etching a trench (not shown) (e.g., a trench with a dividing portion ST) that penetrates the stacked body 40B in the Z direction. Thereby, a third space S3 corresponding to the insulating layer 202 and the insulating layer 203a is formed in the stacked body 40B.

[0124] Then, firstly, insulating material for forming insulating film 47 is supplied to the third space S3, forming insulating film 47. Next, metallic material for forming barrier metal film 46 is supplied to the third space S3, forming barrier metal film 46 (not shown in FIG13H). Next, conductive material for forming conductive portion 45 is supplied to the third space S3, forming conductive portion 45. Herein, insulating layer 202 and insulating layer 203a are replaced by gate electrode layer 41. Next, contact element CC is formed by supplying conductive material into the interior of hole h1.

[0125] Next, a second wafer 3 is formed by removing the semiconductor substrate 201 (see Figure 3). Then, a semiconductor memory device 1 is formed by bonding the separately prepared first wafer 2 and the second wafer 3 together.

[0126] Next, referring to Figures 14A to 14E, the detailed process of the manufacturing method will be described. Figures 14A to 14E are enlarged cross-sectional views of the area enclosed by line F14, which shows the structure shown in Figure 13G.

[0127] FIG14A is a diagram corresponding to the steps in FIG13G. That is, by etching through the hole h1, the unwanted part of the insulating portion 221 is removed. Thereby, the insulating portion 111 filling the second space S2 is formed. The insulating portion 111 is an example of the "first insulating portion". On the other hand, the insulating portion 221 existing in the first space S1 is removed, and the first space S1 is formed again.

[0128] Next, as shown in FIG14B, insulating material is supplied to the first space S1 to form an insulating portion 301 continuous with insulating layer 202 or insulating layer 203a. Hereby, at least a portion of the first space S1 is backfilled by the insulating portion 301. The insulating portion 301 is formed, for example, of the same material as insulating layer 202 or insulating layer 203a. The insulating portion 301 is formed, for example, of a film containing nitrogen and silicon (e.g., silicon nitride film). The insulating portion 301 may also be formed, for example, by selective growth using insulating layer 202 and insulating layer 203a as a substrate. Alternatively, the insulating portion 301 may also be formed, for example, by deposition of insulating material in the first space S1 followed by etching to remove unwanted portions. Furthermore, the insulating portion 301 may also be formed by a method different from the examples described above. The insulating portion 301 is an example of a "second insulating portion".

[0129] Next, as shown in FIG14C, the replacement step is performed with the hole h1 filled by the semiconductor portion 212. For example, multiple insulating layers 202, multiple insulating layers 203a, and insulating portions 301 are removed to form a third space S3 within the laminate 40B. Then, a gate electrode layer 41 is formed within the third space S3. Herein, the first gate electrode layer 41A is formed extending beyond the insulating layers 202 and 203a to the region where the insulating portion 301 is provided.

[0130] Next, as shown in FIG14D, the semiconductor portion 212 is removed by etching through the aperture h1. Then, the edge portion 47e of the insulating film 47 exposed in the first space S1 in the first gate electrode layer 41A is removed by etching through the aperture h1 (see FIG14C). Thereby, the barrier metal film 46 or the conductive portion 45 is exposed in the first space S1.

[0131] Next, as shown in FIG14E, the metal material of the barrier metal film 126 forming the contact CC is supplied to the hole h1 to form the barrier metal film 126. Next, the conductive material of the conductive portion 125 forming the contact CC is supplied to the hole h1 to form the conductive portion 125. Thereby, the contact CC is formed inside the hole h1.

[0132] <8. Advantages> As a comparative example, consider a semiconductor memory device manufactured in a step where the insulating portion 301 is not provided. In the structure of the comparative example, in the step corresponding to FIG. 14D, a portion of the insulating film 47 of the first gate electrode layer 41A is removed, and compared to the insulating film 47 of the second gate electrode layer 41B, sometimes the insulating film 47 of the first gate electrode layer 41A only exists in the region away from the contact CC. In this case, a portion of the conductive portion 45 of the first gate electrode layer 41A or a portion of the barrier metal film 46 becomes a state where it is not covered by the insulating film 47 in the +Z direction or -Z direction. As a result, sometimes the withstand voltage between the first gate electrode layer 41A and the second gate electrode layer 41B decreases, and the electrical characteristics of the semiconductor memory device deteriorate.

[0133] On the other hand, in this embodiment, the semiconductor memory device 1 includes a multilayer 40 and a contact CCA. The multilayer 40 includes a plurality of gate electrode layers 41 and a plurality of insulating layers 42. The plurality of gate electrode layers 41 include a first gate electrode layer 41A and a second gate electrode layer 41B. In the first gate electrode layer 41A, the contact CCA extends through in the Z direction. The first gate electrode layer 41A is connected to the contact CCA in the X direction. The second gate electrode layer 41B is disposed beside the first gate electrode layer 41A in the Z direction among the plurality of gate electrode layers 41. In the second gate electrode layer 41B, the contact CCA extends through in the Z direction. The second gate electrode layer 41B is located away from the contact CCA in the X direction. The first gate electrode layer 41A has a conductive portion 45 and an insulating film 47, the insulating film 47 including a portion disposed between the conductive portion 45 and the first insulating layer 42A and extending in the X direction. The second gate electrode layer 41B has a conductive portion 45 and an insulating film 47, the insulating film 47 including a portion disposed between the conductive portion 45 and the first insulating layer 42A and extending in the X direction. The shortest distance in the X direction (distance L1) between the center CL1 of the contact CCA in the X direction and the insulating film 47 of the first gate electrode layer 41A is the same as or smaller than the shortest distance in the X direction (distance L2) between the center CL1 of the contact CCA in the X direction and the insulating film 47 of the second gate electrode layer 41B.

[0134] According to this structure, the first gate electrode layer 41A extends toward the inside of the contact CC in the same or greater manner than the second gate electrode layer 41B. Therefore, the amount of conductive portion 45 covered by the insulating film 47 of the first gate electrode layer 41A can be increased. This improves the withstand voltage between the first gate electrode layer 41A and the second gate electrode layer 41B, thereby enhancing the electrical characteristics of the semiconductor memory device 1.

[0135] <9. Embodiment> <9.1 First Embodiment> Next, the first embodiment related to the described embodiment will be described. FIG15 is a cross-sectional view showing a portion of the semiconductor memory device 1 of the first embodiment. In the first embodiment, the conductive portion 45 of the first gate electrode layer 41A has a first edge 401 facing the first contact CCA in the X and Y directions. The first edge 401 has a first end portion 401e1 on the -Z direction side and a second end portion 401e2 on the +Z direction side. The first end portion 401e1 has an arc-shaped curved portion 411 that is inclined towards the -Z direction side and protrudes outward toward the conductive portion 45. On the other hand, the second end portion 401e2 has an arc-shaped curved portion 412 that is inclined towards the +Z direction side and protrudes outward toward the conductive portion 45.

[0136] Figures 16A to 16D are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 1 according to the first embodiment. The steps in Figures 16A to 16D correspond to the steps described in Figures 14B to 14E. As shown in Figure 16A, in this embodiment, the insulating portion 301 is formed, for example, by selective growth using insulating layers 202 and 203a as substrates.

[0137] In this case, the insulating portion 301 has a first edge 501 facing the first space S1 in both the X and Y directions. The first edge 501 has a first end portion 501e1 on the -Z direction side and a second end portion 501e2 on the +Z direction side. The first end portion 501e1 has an arc-shaped curved portion 511 that is inclined towards the -Z direction side and protrudes outward toward the outside of the insulating portion 301. On the other hand, the second end portion 501e2 has an arc-shaped curved portion 512 that is inclined towards the +Z direction side and protrudes outward toward the outside of the insulating portion 301.

[0138] In this embodiment, the insulating portion 301 having curved portions 511 and 512 is replaced by a portion of the first gate electrode layer 41A through a replacement step. Therefore, the shape of the first gate electrode layer 41A has rounded corners in the regions corresponding to the curved portions 511 and 512 of the insulating portion 301.

[0139] <9.2 Second Embodiment> Next, a second embodiment related to the described embodiment will be described. FIG17 is a cross-sectional view showing a portion of the semiconductor memory device 1 of the second embodiment. In the second embodiment, the conductive portion 45 of the first gate electrode layer 41A has a first edge 401 facing the first contact CCA in the X and Y directions. The center portion of the first edge 401 in the Z direction has a recessed portion 431 that is recessed in a direction away from the first contact CCA.

[0140] Figures 18A to 18D are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 1 according to the second embodiment. The steps in Figures 18A to 18D correspond to the steps described in Figures 14B to 14E. As shown in Figure 18A, in this embodiment, the insulating portion 301 is formed by depositing insulating material into the first space S1 and then etching to remove unwanted portions.

[0141] In this case, the insulating portion 301 has a first edge 501 facing the first space S1 in the X and Y directions. The central portion of the first edge 501 in the Z direction has a recessed portion 531 that is recessed in a direction away from the first space S1.

[0142] In this embodiment, the insulating portion 301 having the recess 531 is replaced by a portion of the first gate electrode layer 41A through a replacement step. Therefore, the first gate electrode layer 41A has a recess 431 in the region corresponding to the recess 531 of the insulating portion 301.

[0143] The above describes one embodiment and several embodiments, but the embodiments are not limited to the examples described.

[0144] According to at least one embodiment described above, a semiconductor memory device includes a multilayer and a contact. The multilayer includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers have a first gate electrode layer and a second gate electrode layer. The first gate electrode layer is connected to the contact in a second direction. The second gate electrode layer is located away from the contact in the second direction. The plurality of insulating layers includes a first insulating layer disposed between the first gate electrode layer and the second gate electrode layer in the first direction. The first gate electrode layer has a first conductive portion and a first insulating film, the first insulating film including a portion disposed between the first conductive portion and the first insulating layer and extending in the second direction. The second gate electrode layer has a second conductive portion and a second insulating film, the second insulating film including a portion disposed between the second conductive portion and the first insulating layer and extending in the second direction. The shortest distance in the second direction between the first insulating film and the contact is the same as or smaller than the shortest distance in the second direction between the second insulating film and the contact. According to this structure, the electrical characteristics of the semiconductor memory device can be improved.

[0145] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or their variations are included in the scope or spirit of the invention as well as in the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0004] Figure 1 is a block diagram showing a portion of an embodiment of a semiconductor memory device. Figure 2 is a diagram showing an equivalent circuit of a portion of an embodiment of a memory cell array. Figure 3 is a cross-sectional view showing a portion of an embodiment of a semiconductor memory device. Figure 4 is an enlarged cross-sectional view showing the area enclosed by line F4 of the memory cell array shown in Figure 3. Figure 5 is a cross-sectional view along line F5-F5 of the memory cell array shown in Figure 4. Figure 6 is an enlarged cross-sectional view showing the area enclosed by line F6 of the memory cell array shown in Figure 4. Figure 7 is a cross-sectional view along line F7-F7 of the memory cell array shown in Figure 3. Figure 8 is a cross-sectional view of the embodiment of the memory cell array viewed from above. Figure 9 is a cross-sectional view along line F9-F9 of the memory cell array shown in Figure 8. Figure 10 is an enlarged cross-sectional view showing the area enclosed by line F10 of the memory cell array shown in Figure 9. Figure 11 is a cross-sectional view along line F11-F11 of the memory cell array shown in Figure 10. Figure 12 is a cross-sectional view along line F12-F12 of the memory cell array shown in Figure 10. Figure 13A is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 13B is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 13C is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 13D is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 13E is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 13F is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 13G is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 13H is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 14A is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 14B is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 14C is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 14D is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 14E is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figure 15 is a cross-sectional view showing a portion of the semiconductor memory device of the first embodiment. Figure 16A is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 16B is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 16C is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 16D is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 17 is a cross-sectional view showing a portion of the semiconductor memory device according to the second embodiment.Figure 18A is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 18B is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 18C is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 18D is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

Claims

1. A semiconductor memory device, comprising: A multilayer assembly includes a plurality of gate electrode layers and a plurality of insulating layers, formed by alternately stacking the plurality of gate electrode layers and the plurality of insulating layers in a first direction; and a contact extending in the first direction and having conductivity within the multilayer assembly. The plurality of gate electrode layers include: a first gate electrode layer through which the contact extends in the first direction and is connected to the contact in a second direction intersecting the first direction; and a second gate electrode layer disposed beside the first gate electrode layer in the first direction, wherein the contact extends in the first direction and is located away from the contact in the second direction. The plurality of insulating layers include a first insulating layer disposed between the first gate electrode layer and the second gate electrode layer in the first direction. The first gate electrode layer has a first conductive portion and a first insulating film, the first insulating film including a portion disposed between the first conductive portion and the first insulating layer and extending in the second direction. The second gate electrode layer has a second conductive portion and a second insulating film, the second insulating film including a portion disposed between the second conductive portion and the first insulating layer and extending in the second direction. The shortest distance in the second direction between the center of the contact in the second direction and the first insulating film is the same as or smaller than the shortest distance in the second direction between the center of the contact in the second direction and the second insulating film. The laminate has wiring regions of different lengths in the second direction of the plurality of gate electrode layers. In the wiring regions, the length in the second direction of the first gate electrode layer is smaller than the length in the second direction of the second gate electrode layer. The first gate electrode layer has a protrusion in the wiring region protruding toward the side opposite to the second gate electrode layer. The contact extends through the protrusion in the first direction. In at least a portion of the area overlapping the protrusion when viewed from the first direction, the shortest distance in the second direction between the center of the contact in the second direction and the first insulating film is the same as or smaller than the shortest distance in the second direction between the center of the contact in the second direction and the second insulating film.

2. The semiconductor memory device as claimed in claim 1, wherein, The shortest distance in the second direction between the center of the contact in the second direction and the first insulating film is the same as or smaller than the shortest distance in the second direction between the center of the contact in the second direction and the second conductive portion.

3. The semiconductor memory device as described in claim 1 or claim 2, wherein, The contact has: a columnar portion extending in the first direction, and a bulge portion bulging out from the columnar portion toward the first gate electrode layer, wherein the shortest distance in the second direction between the columnar portion of the contact and the first insulating film is the same as or smaller than the shortest distance in the second direction between the columnar portion of the contact and the second insulating film.

4. The semiconductor memory device as claimed in claim 3, wherein, The shortest distance in the second direction between the columnar portion of the contact and the first insulating film is less than half of the shortest distance in the second direction between the columnar portion of the contact and the second insulating film.

5. The semiconductor memory device as claimed in claim 1 or claim 2, wherein, The first conductive portion has a first edge facing the contact member in the second direction, and the end of the first edge in the first direction has a curved portion that is inclined toward the first direction and protrudes toward the outside of the first conductive portion.

6. The semiconductor memory device as claimed in claim 1 or claim 2, wherein, The first conductive portion has a first edge facing the contact member in the second direction, and the central portion of the first edge in the first direction has a recessed portion that is recessed in a direction away from the contact member.

7. A method for manufacturing a semiconductor memory device, comprising alternately depositing first insulating layers and second insulating layers in a first direction to form a laminate containing a plurality of first insulating layers and a plurality of second insulating layers, forming a step region in the laminate containing the plurality of first insulating layers with different lengths in a second direction intersecting the first direction, forming a third insulating layer at each end of the plurality of first insulating layers in the step region, forming a hole penetrating the third insulating layer, the plurality of first insulating layers and the plurality of second insulating layers in the first direction, etching through the hole to remove the edge portions of the third insulating layer adjacent to the hole and the edge portions of the plurality of first insulating layers adjacent to the hole, thereby forming a first space in a first region containing the edge portions of the third insulating layer and the edge portions of the first insulating layers connected to the third insulating layer, forming a second space in a second region containing the edge portions of the first insulating layers not connected to the third insulating layer, forming a first insulating portion filling the second space, and forming a second insulating portion continuous with the third insulating layer and the first insulating layer in at least a portion of the first space. A third space is formed by removing the second insulating portion, the third insulating layer, and the plurality of first insulating layers, and a plurality of gate electrode layers, each containing an insulating film and a conductive portion, are formed in the third space.

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