Multiple-chip system and timing synchronization method

Abstract

A timing synchronization method for a multi-chip system. The multi-chip system includes multiple chips. The multiple chips include a first chip and at least one second chip. The multiple chips are interconnected via the same input / output bus. The timing synchronization method includes: the multiple chips sequentially sending multiple detection sample data to the input / output bus, wherein each second chip sequentially sends the detection sample data first, and then the first chip sends the detection sample data; the first chip sends synchronization sample data to the input / output bus; each second chip monitors the synchronization sample data from the input / output bus; and each chip performs a predetermined function based on the synchronization sample data.

Claims

1. A timing synchronization method for a multi-chip system, wherein the multi-chip system includes multiple chips, the multiple chips including a first chip and at least one second chip, and the multiple chips are interconnected via the same input / output bus, the timing synchronization method comprising: The plurality of chips sequentially send a plurality of detection patterns to the input / output bus, wherein each second chip first sequentially sends the detection patterns, and then the first chip sends the detection patterns; the first chip sends synchronization patterns to the input / output bus; each second chip monitors the synchronization patterns from the input / output bus; and each chip performs a predetermined function based on the synchronization patterns.

2. The timing synchronization method as described in request item 1, wherein the plurality of detection sample data are all different.

3. The timing synchronization method as described in claim 2, wherein the step of the plurality of chips sequentially sending the plurality of detection sample data to the input / output bus further includes: When each of the aforementioned chips detects specific detection sample data from the input / output bus, each of the aforementioned chips sends the detection sample data to the input / output bus, wherein the specific detection sample data is the detection sample data sent by the preceding chip of each of the aforementioned chips.

4. The timing synchronization method as described in claim 1 further includes: When each of the chips is powered on, each of the chips sends a power-on signal to the input / output bus.

5. The timing synchronization method as described in claim 1 further includes: In response to an anomaly in one of the plurality of chips, the anomaly chip sends an error signal to the input / output bus.

6. The timing synchronization method as described in claim 1 further includes: When each of the chips performs the predetermined function, each of the chips sends a standby signal to the input / output bus.

7. The timing synchronization method as described in claim 1 further includes: Each of the aforementioned chips receives a restart signal from the input / output bus, wherein the restart signal is used to instruct each of the aforementioned chips to restart.

8. A multi-chip system, comprising: Multiple chips are interconnected via a single input / output bus, and the multiple chips include a first chip and at least one second chip. The at least one second chip sequentially sends at least one detection sample data to the input / output bus, with each second chip sending the detection sample data first, followed by the first chip sending the detection sample data. The first chip sends synchronization sample data to the input / output bus. Each second chip monitors the synchronization sample data from the input / output bus, and each chip performs a predetermined function based on the synchronization sample data.

9. The multi-chip system as described in claim 8, wherein the plurality of detection sample data are all different.

10. The multi-chip system of claim 9, wherein when each of the chips detects specific detection data from the input / output bus, each of the chips sends the detection data to the input / output bus, wherein the specific detection data is the detection data sent by the preceding chip of each chip.

11. The multi-chip system of claim 8, wherein each of the chips sends a power-on signal to the input / output bus when each of the chips is powered on.

12. The multi-chip system as claimed in claim 8, wherein in response to an anomaly in one of the plurality of chips, the anomaly chip sends an error signal to the input / output bus.

13. The multichip system of claim 8, wherein each of the chips sends a standby signal to the input / output bus when the predetermined function is performed by each of the chips.

14. The multi-chip system of claim 8, wherein each of the chips receives a restart signal from the input / output bus, wherein the restart signal is used to instruct each of the chips to restart.

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