Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for manufacturing resistive random access memory (RAM). The method mainly involves first forming an interlayer dielectric layer on a substrate, then forming a contact plug within the interlayer dielectric layer, forming a resistive RAM on the contact plug, forming a first cover layer and a second cover layer on the resistive RAM, and then removing a portion of the second cover layer to form a sidewall.

Claims

1. A method for manufacturing resistive random access memory, characterized in that it comprises: forming an interlayer dielectric layer on a substrate; forming a contact plug within the interlayer dielectric layer; forming a resistive random access memory on the contact plug; forming a first cover layer and a second cover layer on the resistive random access memory; and removing a portion of the second cover layer to form a sidewall, wherein the top surface of the sidewall is flush with the top surface of the first cover layer.

2. The method as described in claim 1, wherein the resistive random access memory comprises: a lower electrode disposed on the contact plug; an impedance conversion layer disposed on the lower electrode; and an upper electrode disposed on the impedance conversion layer.

3. The method as described in claim 1 further comprises: forming the sidewall next to the first cover layer; forming a first intermetallic dielectric layer on the sidewall and the first cover layer; planarizing the first intermetallic dielectric layer; forming a second intermetallic dielectric layer on the first intermetallic dielectric layer; and forming a metal interconnect in the second intermetallic dielectric layer and connecting it to the resistive random access memory.

4. The method as described in claim 3, wherein the top surface of the sidewall sub-side is flush with the top surface of the first intermetallic dielectric layer.

5. The method as described in claim 3, wherein the top surface of the first cover layer is flush with the top surface of the first intermetallic dielectric layer.

6. The method as described in claim 1, wherein the first covering layer comprises an L-shape.

7. The method as described in claim 1, wherein the sidewall comprises an I-shape.

8. A resistive random access memory (RAM), characterized in that it comprises: an interlayer dielectric layer disposed on a substrate; a contact plug disposed within the interlayer dielectric layer; a resistive RAM disposed on the contact plug; a cover layer disposed beside the resistive RAM; and a sidewall disposed beside the cover layer, wherein the top surface of the sidewall is flush with the top surface of the cover layer; a first intermetallic dielectric layer surrounding the sidewall; a second intermetallic dielectric layer disposed on the first intermetallic dielectric layer; and a metal interconnect disposed within the second intermetallic dielectric layer and connected to the resistive RAM, wherein the top surface of the cover layer is flush with the top surface of the first intermetallic dielectric layer.

9. The resistive random access memory as described in claim 8, wherein the resistive random access memory comprises: a lower electrode disposed on the contact plug; an impedance conversion layer disposed on the lower electrode; and an upper electrode disposed on the impedance conversion layer.

10. The resistive random access memory as described in claim 8, wherein the overlay layer comprises an L-shape.

11. The resistive random access memory as described in claim 8, wherein the sidewall comprises an I-shape.

12. The resistive random access memory as described in claim 8, wherein the cover layer and the sidewalls comprise different materials.

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