Semiconductor structure and its preparation method

Abstract

A semiconductor structure and its fabrication method are disclosed. The semiconductor structure includes: bit lines extending in a first direction and spaced apart in a second direction, the first direction intersecting the second direction; shielding lines located between two adjacent bit lines and extending in the first direction, alternating with the bit lines in the second direction; active pillars located on the bit lines and arranged in an array in the first and second directions; and bit line contact structures located between the bit lines and the active pillars and connecting the bit lines and the active pillars, wherein the width of the bit line contact structure in the second direction is smaller than the width of the bit lines and the active pillars in the second direction.

Description

[Technical Field]

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. [Previous Technology]

[0002] With the development of Dynamic Random Access Memory (DRAM) technology, the size of storage cells is getting smaller and smaller, and its array architecture has changed from 8F2 to 6F2 and then to 4F2 (F: the smallest pattern size that can be obtained under given process conditions).

[0003] However, in the 4F2 design structure, how to minimize the area of ​​a single array region transistor and pursue a higher wafer area utilization rate is still an urgent problem to be solved. [Summary of the Invention]

[0004] Based on this, this application provides a semiconductor structure and its fabrication method, which can reduce the device size and reduce the difficulty of the fabrication process.

[0005] In one aspect, according to some embodiments, this application provides a semiconductor structure, characterized in that it includes: active pillars arranged in an array in a first direction and a second direction, the first direction intersecting the second direction; bit lines extending in the first direction, spaced apart in the second direction, and connected to the active pillars arranged along the first direction; shielding lines located between two adjacent bit lines, extending in the first direction, and alternating with the bit lines in the second direction; and bit line contact structures located between the bit lines and the active pillars and connecting the bit lines and the active pillars, wherein the width of the bit line contact structure in the second direction is smaller than the width of the bit lines and the active pillars in the second direction.

[0006] In some embodiments, the bit line contact structure is connected to two adjacent active posts in the second direction.

[0007] In some embodiments, the width of the shielding line in the third direction is not less than the width of the bit line in the third direction, and the third direction intersects with the first direction and the second direction.

[0008] In some embodiments, the width of the bit line decreases as the bit line extends toward the bit line contact structure.

[0009] In some embodiments, the semiconductor structure further includes: a bit line protection layer, the bit line protection layer being located on the side of the bit line away from the bit line contact structure; a bit line isolation layer, the bit line isolation layer being located between two adjacent bit lines, and the shielding line being located in the bit line isolation layer; the bit line protection layer and the bit line isolation layer are made of different materials.

[0010] In some embodiments, the bit line includes at least one layer of metal material; the shielding line includes at least one layer of metal material.

[0011] In some embodiments, the semiconductor structure further includes: a shielding line blocking layer, the shielding line blocking layer covering the shielding line layer.

[0012] In some embodiments, there is a gap between the bit line isolation layer and the shielding line.

[0013] In some embodiments, the cross-sectional shape of the shielding wire perpendicular to the first direction is conical, elongated, elliptical, star-shaped or other suitable shape.

[0014] In some embodiments, the semiconductor structure further includes: word lines extending in the second direction and spaced apart in the first direction, the word lines being connected to the active pillars in the second direction; and a storage structure connected to the active pillars and located at the end of all the source pillars away from the bit lines.

[0015] On the other hand, according to some embodiments, this application also provides a method for fabricating a semiconductor structure, comprising: forming active pillars, the active pillars being arranged in an array in a first direction and a second direction, the first direction intersecting the second direction; forming bit lines, the bit lines extending in the first direction, being spaced apart in the second direction, and connecting the active pillars arranged along the first direction; forming shielding lines, the shielding lines being located between two adjacent bit lines, extending in the first direction, and alternating with the bit lines in the second direction; forming a bit line contact structure; the bit line contact structure connecting the bit lines and the active pillars, the width of the bit line contact structure in the second direction being smaller than the width of the bit lines and the active pillars in the second direction.

[0016] In some embodiments, forming the bit line includes: providing a substrate having a first surface and a second surface in a third direction, the third direction intersecting the first direction and the second direction; patterning and etching bit line isolation trenches on the first surface, the bottom dimension of the bit line isolation trench being larger than the top dimension of the bit line isolation trench, the bit line isolation trenches extending along the first direction and spaced apart in the second direction; filling the bit line isolation trenches to form a bit line isolation layer; grinding the second surface to expose the bit line isolation layer, and etching the substrate to form the bit line trenches with the bit line isolation layer as a mask; filling at least one layer of metal material in the bit line trenches to form the bit line; and forming a bit line protective layer on the bit line, the bit line protective layer being made of a different material than the bit line isolation layer.

[0017] In some embodiments, forming the shielding line includes: etching the bit line isolation layer on the second surface using the bit line protection layer as a masking layer to form a shielding line trench, wherein the depth of the shielding line trench is not less than the depth of the bit line trench; and filling at least one layer of metal material into the shielding line trench to form the shielding line.

[0018] In some embodiments, the bit line contact structure includes a metal silicate, and forming the metal silicate includes: depositing a metal material layer at the bottom of the bit line trench and then performing high-temperature treatment to form the metal silicate; or depositing a metal material layer at the bottom of the bit line isolation trench and then performing high-temperature treatment to form the metal silicate.

[0019] In some embodiments, after filling the bit line isolation trench to form a bit line isolation layer, the method further includes: patterning and etching word line isolation trenches on the first surface, wherein the depth of the word line isolation trenches is less than the depth of the bit line isolation trenches, the bit line isolation trenches extend along a second direction and are spaced apart in a first direction, and the word line isolation trenches and the bit line isolation trenches form the active pillars; after forming the active pillars, the method further includes: forming word lines in the word line isolation trenches, wherein the word lines extend in the second direction and are spaced apart in the first direction, and the word lines are connected to the active pillars in the second direction; and forming a storage structure at the end of the active pillars away from the bit lines.

[0020] The semiconductor structure and its fabrication method provided in this application have at least the following beneficial effects:

[0021] The semiconductor structure and its fabrication method provided in this application can reduce bit line resistance by forming metal bit lines on the back side of the wafer, and reduce the coupling capacitance between adjacent bit lines by forming metal shielding lines between the bit lines, thereby improving device stability. By using different materials for the substrate, bit line isolation layer, and bit line protection layer, and setting different etch selectivity ratios, the use of a self-aligned etching process can reduce the number of photomask operations and lower production costs. In addition, adjacent bit lines can share a single bit line, which can reduce the complexity of equipment fabrication.

[0022] In order to more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those who are skilled in the art, other drawings can be obtained based on these drawings without creative effort.

Implementation Method

[0024] Cross-reference to related applications

[0025] This application claims priority to Chinese Patent Application No. 202410452734.7, filed on April 15, 2024, entitled "Semiconductor Structure and Preparation Method Thereof", the entire contents of which are incorporated herein by reference.

[0026] To facilitate understanding of this application, a more complete description of the application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the application. However, the application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to," it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions.

[0029] Spatial relation terms such as "on" can be used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as "on" will be oriented "below" other elements or features. Thus, the exemplary term "on" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] As used herein, the singular forms "a," "an," and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms "compose" and / or "comprise" are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application, thus allowing for the expectation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0032] Referring to Figure 1a, in some related embodiments, the semiconductor structure may include multiple bit lines (BL) 3 extending along a first direction (e.g., the X direction) and arranged along a second direction (e.g., the Y direction), and multiple word lines (WL) 2 extending along the second direction and arranged along the first direction. The bit lines 3 and word lines 2 intersect in space at active pillars 4. The multiple active pillars 4 may extend along a third direction perpendicular to the substrate 1 (e.g., the Z direction) and be arranged in an array. During the fabrication of the bit lines 3, bit line isolation trenches 6 are first formed and filled, referring to Figure 1c, and then word line isolation trenches 5 are etched to form, referring to Figure 1b. In the word line isolation trenches, the substrate is modified by ion implantation, doping, or metal diffusion to form the bit lines 3. As the size of the bit lines 3 becomes smaller, the resistance of the bit lines 3 becomes larger, and the distance between adjacent bit lines 3 also becomes smaller, resulting in a larger coupling effect, which greatly affects the performance of the semiconductor structure. In addition, the process of forming bit line 3 also causes some damage to word line isolation trenches, storage contacts and active pillars, which greatly limits the development of semiconductor structure fabrication processes.

[0033] This application provides a semiconductor structure and its fabrication method, which can reduce the size of the device. The details will be described in the following embodiments.

[0034] On the one hand, this application provides a semiconductor structure according to some embodiments.

[0035] Referring to FIG2, in some embodiments, the semiconductor structure may include multiple bit lines 3, multiple active pillars 4, multiple shielding lines 16, and bit line contact structures 10. The multiple bit lines 3 extend in a first direction (e.g., the X direction) and are spaced apart in a second direction (e.g., the Y direction), with the first direction intersecting the second direction; the multiple shielding lines 16 are located between adjacent bit lines 3 and extend in the first direction, alternating with the bit lines 3 in the second direction; the multiple active pillars 4 extend in a third direction (e.g., the Z direction) away from the bit lines 3 and are arranged in an array in the first and second directions; the bit line contact structure 10 is located between the bit lines 3 and the active pillars 4 and connects the bit lines 3 and the active pillars 4, and the width of the bit line contact structure 10 in the second direction is smaller than the width of the bit lines and the active pillars in the second direction.

[0036] In the semiconductor structure provided in the above embodiments, the shielding line 16 is located between adjacent bit lines 3 and is arranged alternately with the bit lines in the second direction. The shielding line 16 can reduce the coupling effect between two adjacent bit lines 3 and provide stability to the semiconductor structure. The width of the bit line contact structure 10 in the second direction is smaller than the width of the bit line 3 and the active pillar 4 in the second direction, which can increase the width of the bit line 3 in the second direction, reduce the resistance of the bit line 3, and at the same time reduce the fabrication difficulty of the bit line 3.

[0037] Please refer to Figures 2 and 3a. In some embodiments, a bit line contact structure can connect to an active post 4, and a bit line contact structure 10 can also connect to two adjacent active posts 4 in the second direction. Referring to Figure 2, two adjacent active posts 4 share a bit line contact structure 10 and a bit line 3. This can reduce bit line density, increase integration, and increase the spacing between bit lines. At the same time, it can also increase the width of bit line 3, reduce the resistance of bit line 3, and improve the performance of the device.

[0038] Please continue to refer to Figure 2. In some embodiments, the width D1 of the shielding line 16 in the third direction (e.g., the Z direction) is not less than the width D2 of the bit line 3 in the third direction (e.g., the Z direction). The width D1 of the shielding line 16 in the third direction (e.g., the Z direction) is greater than the width D2 of the bit line 3 in the third direction (e.g., the Z direction). Optionally, the width D1 of the shielding line 16 in the third direction (e.g., the Z direction) is greater than the sum of the widths of the bit line 3 and the bit line contact structure 10 in the third direction (e.g., the Z direction). In this way, the shielding line 16 can completely shield the coupling effect between adjacent bit lines 3 and improve the performance of the device.

[0039] Please continue to refer to Figure 2. In some embodiments, the width of the bit line 3 in the second direction (e.g., the Y direction) decreases as the bit line extends toward the bit line contact structure. This can be understood as the bit line being an inverted trapezoid. This can reduce the resistance of the bit line 3 and also reduce the difficulty of the bit line 3 fabrication process.

[0040] Please continue referring to FIG2. In some embodiments, the semiconductor structure may include a bit line protection layer 14 and a bit line isolation layer 8. The bit line protection layer 14 is located on the side of the bit line 3 away from the bit line contact structure 10 and extends along a first direction (e.g., X) and is arranged in a second direction (e.g., Y). The bit line isolation layer 8 is located between adjacent bit lines 3 to provide insulation between adjacent bit lines. The materials of the bit line protection layer 14 and the bit line isolation layer 8 are not specifically limited. As an example, the material of the bit line protection layer 14 may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide, or combinations thereof. The material of the bit line isolation layer 8 may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide, or combinations thereof. However, the materials of the bit line isolation layer 8 and the bit line protection layer 14 must be different. For example, the bit line protection layer 14 can be silicon nitride and the bit line isolation layer can be silicon oxide. In this way, when etching the bit line isolation layer 8, a self-aligned method can be used to selectively etch the bit line isolation layer 8 using the bit line protection layer 14 as a template, which can reduce the difficulty of the process and save costs.

[0041] Please continue to refer to Figures 2 and 3c. In some embodiments, the bit line 3 and the shielding line 16 can be a single layer or multiple layers. For example, in Figure 3c, the bit line 3 includes a first bit line material layer 301 and a second bit line material layer 302. The positional relationship between the first bit line material layer 301 and the second bit line material layer 302 is not specifically limited. As an example, the first bit line material layer 301 and the second bit line material layer 302 can be stacked, surrounded, or semi-surrounded, etc. The shielding line 16 can include a first shielding line material layer 1601 and a second shielding line material layer 1602. The positional relationship between the first shielding line material layer 1601 and the second shielding line material layer 1602 is not specifically limited. As an example, the first shielding line material layer 1601 and the second shielding line material layer 1602 can be stacked, surrounded, or semi-surrounded, etc. The materials of bit line 3 and shielding line 16 are not specifically limited. For example, the material of bit line 3 may include, for example, doped polycrystalline silicon, metal, conductive metal nitride, conductive metal silicate, conductive metal oxide, or a combination thereof. For instance, bit line 3 may include, but is not limited to, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. The material of shielding line 16 may include, for example, doped polycrystalline silicon, metal, conductive metal nitride, conductive metal silicate, conductive metal oxide, or a combination thereof. For example, shielding line 16 may include, but is not limited to, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof. Bit line 3 and shielding line 16 each include at least one metallic material layer, which can reduce the resistance of bit line 3 and shielding line 16 and improve device performance.

[0042] Please continue to refer to Figure 2. In some embodiments, the semiconductor structure may include a direct current bias (DC bias) power supply. The DC bias and the shielding line 16 can be connected by a connection contact (not shown) to provide a stable voltage to the shielding line 16, so that the shielding line 16 forms a conductive barrier, thereby reducing or eliminating the influence of the other two adjacent bit lines 3 when one of them is energized or de-energized.

[0043] Please refer to Figure 3b. In some embodiments, at least a portion of the shielding line 16 and the bit line isolation layer 8 are not in complete contact, and there is a gap 17 between the shielding line 16 and the bit line isolation layer 8. The relative position of the gap 17 between the shielding line 16 and the bit line isolation layer 8 is not specifically limited. As an example, the gap 17 can be located at the bottom of the shielding line, on one side wall, or partially surrounding the shielding line, etc. The size and shape of the gap 17 are also not specifically limited. As an example, the gap can be spherical, teardrop-shaped, short tubular, ellipsoidal, elongated, or other suitable shapes. Since the dielectric constant of air is 1.001, close to the dielectric constant of a vacuum, the gap 17 and the bit line isolation layer 8 together exhibit a low dielectric constant effect to reduce the overall dielectric constant. This can reduce parasitic capacitance and avoid capacitive coupling effects between the bit line 3 and adjacent bit lines 3, thereby reducing the impact of parasitic capacitance on device performance parameters.

[0044] Please refer to FIG3d. In some embodiments, the cross-sectional shape of the shielding line 16 in the direction perpendicular to the first direction is irregular. For example, it can be conical, strip-shaped, elliptical, star-shaped or other suitable shapes. The shielding line is formed in the bit line isolation layer 8. The size of the shielding line 16 is affected by the material of the bit line isolation layer 8 and the etching capability of the equipment. The irregular structure of the shielding line 16 can increase the process preparation window and reduce the preparation process cost.

[0045] Please refer to Figure 3e. In some embodiments, a shielding wire blocking layer 18 may be provided above the shielding wire 16. The shielding wire blocking layer 18 covers the shielding wire 16 and can protect the shielding wire 16 from damage in subsequent processes. The material of the shielding wire blocking layer 18 is not limited and can be the same as or different from the material of the bit line protection layer 14.

[0046] Please continue to refer to Figures 2 and 3a-3e. In some embodiments, the semiconductor structure further includes word lines 2, storage contacts 9 at one end of the active pillar, storage structure 11, and back-end interconnects and a protective layer (not shown in the figures) located on the storage structure 11. Specifically, the word lines 2 extend along a second direction and are arranged in a first direction. The word lines surround the active pillar 4, on one, two, or three sides of the active pillar, controlling the charge movement of the active pillar 4. The material of the word lines is not specifically limited. As an example, the material of the word lines 2 may include, for example, doped polycrystalline silicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the word lines 2 may include, but are not limited to, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof.

[0047] The storage contact 9 is located at the end of the active pillar 4 away from the bit line contact 10, and connects the active pillar 4 and the storage structure 11. The material of the storage contact 9 is not specifically limited. As an example, the material of the storage contact 9 may include at least one of the following: doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof, which can reduce the contact resistance between the active pillar 4 and the storage structure 11.

[0048] The storage structure 11 may be a capacitor structure, the capacitor including upper and lower electrode plates and a high-k dielectric material located between the upper and lower electrode plates; it may also be a variable resistance storage structure, which switches to two resistance states by applying an electrical pulse to the memory element. For example, the variable resistance storage structure may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material or antiferromagnetic material whose crystal state changes according to the amount of current.

[0049] On the other hand, this application also provides a method for fabricating a semiconductor structure according to some embodiments. To more clearly illustrate the methods for fabricating the semiconductor structure in some embodiments of this application, the following description of some embodiments can be understood in conjunction with Figures 1a-1c to 3a-3e.

[0050] Figures 4a-4l are views illustrating intermediate steps of a method for manufacturing a semiconductor memory device according to some embodiments.

[0051] Referring to FIG4a, a substrate 1 is provided, the substrate having opposing first and second surfaces in a third direction (e.g., the Z direction), and an initial bit line isolation trench 601 is patterned and etched on the first surface.

[0052] Specifically, in some embodiments, the material of the substrate 1 is not specifically limited. For example, the material of the substrate 1 may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other III / V semiconductor materials or II / VI semiconductor materials, etc.

[0053] In some embodiments, patterning etching to form the initial bit line isolation trench 601 may include forming a mask layer on the first surface of the substrate 1. The mask layer may include one, two, or more material layers. A photoresist layer is deposited, and after exposure and development, the mask layer and the substrate 1 are etched to form the initial bit line isolation trench 601. The etching method may be dry etching, wet etching, or a combination of both, without specific limitation. Referring to Figures 2 and 3a, a column of active pillars 4 can be connected to a column of bit lines 3, or two adjacent columns of active pillars 4 can share a column of bit lines 3. In this way, two adjacent columns of active pillars 4 sharing a bit line can reduce the space between adjacent bit lines, thereby reducing the device size and making the internal layout of the semiconductor structure more reasonable, thus effectively improving the storage density of the semiconductor structure. In this embodiment, two columns of active pillars 4 sharing a bit line 3 is used as an example. The initial bit line isolation trench 601 formed adopts double spacing, that is, the substrate between adjacent initial bit line isolation trenches 601 is twice the distance of an active pillar 4 and a bit line isolation trench 6. This can increase the process fabrication window and improve the stability of device performance.

[0054] Referring to FIG4b, in some embodiments, the mask layer that has not been etched away is modified to make its size conform to the width of the bit line isolation trench 6, or to make the width of the exposed unetched substrate equivalent to the width of the active pillar 4. The specific width is not limited and can be any width between 10nm and 40nm according to process requirements. A sidewall protection layer 7 is deposited in the initial bit line isolation trench 601 and on the first surface of the substrate and the surface of the mask layer that has not been etched away on the first surface of the substrate. The sidewall protection layer 7 can protect the first surface of the substrate and the surface of the mask layer that has not been etched away on the first surface of the substrate from being damaged in subsequent processes. The sidewall protection layer 7 is etched to open the sidewall protection layer at the bottom of the initial bit line isolation trench 601. Then, co-directional etching is used to form the first bit line isolation trench 602. Co-directional etching can be dry etching, wet etching, or a combination of both, without specific limitation. Because of the use of co-directional etching, the width of the first bit line isolation trench 602 in the second direction is larger than the width of the initial bit line isolation trench 601 in the second direction, and the substrate on both sides of the first bit line isolation trench 602 is etched away.

[0055] Referring to FIG. 4c, in some embodiments, insulating material is filled in the initial bit line isolation trench 601 and the first bit line isolation trench 602, and planarization is performed to expose the mask layer that has not been etched away. Specifically, in some embodiments, the insulating material may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide, or combinations thereof, and the material of the insulating material is different from that of the mask layer. The deposition method may include, but is not limited to, chemical vapor deposition, flowable chemical vapor deposition, atomic layer deposition, spin coating, and high-intensity deposition, or combinations thereof. The mask layer that has not been removed is selectively etched. Since the mask layer and the bit line isolation layer 8 are made of different materials, etching can be performed without a photomask using a self-aligned method. The etching method may be dry etching, wet etching, or a combination of both. The mask layer is modified so that its size is consistent with the bit line isolation trench 6. After removing the mask layer, the pattern of the second bit line isolation trench 603 is formed.

[0056] Referring to FIG4d, in some embodiments, a second bit-line isolation trench 603 is formed according to the pattern of the second bit-line isolation trench 603 formed in the above steps. The second bit-line isolation trench 603 extends along a first direction and is located between adjacent first bit-line isolation trenches 602, and is spaced apart from the first bit-line isolation trenches 602 in a second direction. Since the first bit-line isolation trenches 602 and the second bit-line isolation trenches 603 are spaced apart and formed in steps, the distance between adjacent bit-line isolation trenches 602 is larger when the first bit-line isolation trenches 602 and the second bit-line isolation trenches 603 are prepared separately, which increases the view window of the process fabrication and improves the stability of the device.

[0057] Referring to FIG4e, in some embodiments, a bit line contact 10 is formed at the bottom of the second bit line isolation trench 603 and a storage contact 9 is formed at the top of the active pillar. The bit line contact 10 is located at the bottom of the second bit line isolation trench 603 and connected to the substrate on both sides, and contacts the adjacent first bit line isolation trench 602 in the second direction. Specifically, a sidewall protective layer is formed on the second bit line isolation trench 603 and the substrate surface to prevent damage or influence on the substrate by subsequent processes. The protective layer at the bottom of the second bit line isolation trench 603 and the substrate surface is removed by etching to expose the substrate. The bit line contact 10 and the storage contact 9 are formed by suitable methods such as ion implantation, deposition of high-concentration doped material for diffusion, or deposition of metal material for metal silicide reaction. The bit line contact 10 and the storage contact 9 can be formed stepwise or in one step, without specific limitation. The material of storage contact 9 is not specifically limited. As an example, the material of storage contact 9 may include at least one of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof. The material of bit line contact 10 is not specifically limited. As an example, the material of bit line contact 10 may include at least one of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0058] Referring to FIG4f, in some embodiments, an insulating material is filled in the second bit line isolation trench 603 to form a bit line isolation layer 8, which is planarized, and the bit line isolation structure 8 extends along a first direction and is spaced apart in a second direction.

[0059] Referring to Figures 1b and 4g, in some embodiments, word line isolation trenches 5 are patterned and etched on a first surface of the substrate. Word line isolation trenches 5 and bit line isolation trenches 6 form active pillars 4. Word lines 2 are formed in the word line isolation trenches 5, extending along a second direction and arranged in a first direction. The word lines surround the active pillars 4, on one, two, or three sides of the active pillars, controlling the charge movement of the active pillars 4. The material of the word lines is not specifically limited. As an example, the material of the word lines 2 may include, for example, doped polycrystalline silicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the word lines 2 may include, but are not limited to, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof.

[0060] A storage structure 11 is formed on the storage contact 9, and a rear connection line (not shown in the figure) is formed on the storage structure 11. The storage structure 11 may be a capacitor structure, the capacitor including an upper electrode plate, a lower electrode plate and a high-k dielectric material located between the upper electrode plate and the lower electrode plate; it may also be a variable resistance storage structure, which switches to two resistance states by an electrical pulse applied to the memory element. For example, the variable resistance storage structure may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material or antiferromagnetic material whose crystal state changes according to the amount of current.

[0061] Referring to FIG4h, in some embodiments, the substrate is flipped and the second surface of the substrate is thinned by a grinding process, with the bit line isolation layer 8 as the etch termination layer.

[0062] Referring to FIG4i, in some embodiments, since the bit line isolation layer 8 is made of a different material from the substrate, a self-aligned process can be used to selectively etch away the substrate material to form the bit line trench 12. The self-aligned process can reduce the number of exposures and lower the process cost.

[0063] Referring to FIG4j, in some embodiments, a bit line material layer 13 is deposited in the bit line trench 12. The material of the bit line material is not specifically limited. As an example, the bit line material layer 13 may include, but is not limited to, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi or combinations thereof.

[0064] Referring to FIG4k, in some embodiments, the bit line material layer 13 is etched back to form the bit line 3, and a bit line protection layer 14 is formed on the bit line 3. The bit line protection layer 14 is planarized using a grinding process. Specifically, a portion of the bit line material layer 13 is etched away using a selective etching method, so that the bit line material layer 13 is formed only within the bit line trench 12 to form the bit line 3. Dry etching, wet etching, or a combination of both can be used. The bit line protection layer 14 is deposited on the bit line 3. The material of the bit line protection layer 14 can be, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide, or combinations thereof. The material of the bit line protection layer 14 is different from the material of the bit line isolation layer 8.

[0065] Referring to FIG41, in some embodiments, the bit line isolation layer 8 is etched to form a shielding trench 15 in the bit line isolation layer 8. Specifically, since the bit line isolation layer 8 and the bit line protection layer 14 are made of different materials, a self-aligned etching method can be used to etch away part of the bit line isolation layer 8 to form the shielding trench 15. Dry etching, wet etching, or a combination of both can be used. In some embodiments, dry etching can be used first to form a trench of a certain depth, and then wet etching can be used to etch in the same direction at the bottom of the trench to make the bottom of the trench wider, forming different trenches. This prevents the problem of open circuit caused by the small shielding material at the bottom of the trench not being able to fill. The self-aligned etching process can reduce the number of photolithography processes, reduce production costs, and improve the stability of the device.

[0066] As described in the preceding steps, the greater the width of the bit line isolation layer 8 in the second direction, the larger the process window of the shielding trench 15. Simultaneously, the greater the depth of the shielding trench 15 in the third direction, the lower the bottom of the shielding trench 15 is compared to the lowest plane of the bit line 3 in the third direction. This allows the subsequently formed bit line shielding line 16 to effectively protect the bit line 3 from signal interference from adjacent bit lines. In some embodiments, the bottom of the shielding trench 15 may be lower than the lowest plane of the bit line contact 10 in the third direction, thereby improving device stability. The shape of the shielding trench 15 is not specifically limited. As an example, the cross-sectional shape of the shielding trench 15 in the second direction can be conical, elongated, elliptical, star-shaped, or other suitable shapes.

[0067] Please continue to refer to Figures 2 and 3a-3e. Conductive material is deposited in the shielding trench 15 to form a shielding wire 16. In some embodiments, the shielding wire 16 can be a single layer or multiple layers. For example, in Figure 3c, the shielding wire 16 may include a first shielding material layer 1601 and a second shielding material layer 1602. The positional relationship between the first shielding material layer 1601 and the second shielding material layer 1602 is not specifically limited. As an example, the first shielding material layer 1601 and the second shielding material layer 1602 can be stacked, surrounded, or semi-surrounded, etc. The material of the shielding wire 16 may include, for example, doped polycrystalline silicon, metal, conductive metal nitride, conductive metal silicate, conductive metal oxide, or a combination thereof. For example, the shielding line 16 may include, but is not limited to, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof. The shielding line 16 includes at least one metallic material layer, which can reduce the resistance of the shielding line 16 and improve device performance.

[0068] Please continue to refer to Figure 3b. In some embodiments, at least a portion of the shielding line 16 and the bit line isolation layer 8 are not in complete contact. There is a gap 17 between the shielding line 16 and the bit line isolation layer 8. The relative position of the gap 17 between the shielding line 16 and the bit line isolation layer 8 is not specifically limited. As an example, the gap 17 can be located at the bottom of the shielding line, on one side wall, or partially surrounding the shielding line, etc. The size and shape of the gap 17 are also not specifically limited. As an example, the gap can be spherical, teardrop-shaped, short tubular, ellipsoidal, strip-shaped, or other suitable shapes. Since the dielectric constant of air is 1.001, close to the dielectric constant of a vacuum, the gap 17 and the bit line isolation layer 8 together exhibit a low dielectric constant effect to reduce the overall dielectric constant. This can reduce parasitic capacitance and avoid capacitive coupling effects between the bit line 3 and adjacent bit lines 3, thereby reducing the impact of parasitic capacitance on device performance parameters.

[0069] Please continue to refer to Figure 3d. In some embodiments, the cross-sectional shape of the shielding line 16 on the third party can be an irregular structure, for example, it can be a cone, a strip, an ellipse, a star or other suitable shape. The shielding line is formed in the bit line isolation layer 8. The size of the shielding line 16 is affected by the material of the bit line isolation layer 8 and the etching capability of the equipment. The irregular structure of the shielding line 16 can increase the process preparation window and reduce the preparation process cost.

[0070] Please continue to refer to Figure 3e. In some embodiments, a shielding wire blocking layer 18 may be provided above the shielding wire 16. The shielding wire blocking layer 18 covers the shielding wire 16 and can protect the shielding wire 16 from damage in subsequent processes. The material of the shielding wire blocking layer 18 is not limited and may be the same as or different from the material of the bit line protection layer 14.

[0071] Please continue to refer to Figure 2. In some embodiments, the width D1 of the shielding line 16 in the third direction (e.g., the Z direction) is not less than the width D2 of the bit line 3 in the third direction (e.g., the Z direction). The width D1 of the shielding line 16 in the third direction (e.g., the Z direction) is greater than the width D2 of the bit line 3 in the third direction (e.g., the Z direction). Optionally, the width D1 of the shielding line 16 in the third direction (e.g., the Z direction) is greater than the sum of the widths of the bit line 3 and the bit line contact structure 10 in the third direction (e.g., the Z direction). In this way, the shielding line 16 can completely shield the coupling effect between adjacent bit lines 3, thereby improving the performance of the device.

[0072] Please continue to refer to Figure 2. In some embodiments, the semiconductor structure may include a direct current bias (DC bias) power supply. The DC bias and the shielding line 16 can be connected by a connection contact (not shown) to provide a stable voltage to the shielding line 16, so that the shielding line 16 forms a conductive barrier, thereby reducing or eliminating the influence of the other one when one of the two adjacent bit lines 3 is energized or de-energized.

[0073] Figures 5a-5f are views illustrating intermediate steps in a method for manufacturing a semiconductor memory device according to some embodiments. For ease of description, portions that overlap with those described with reference to Figures 4a-4l will be briefly described or omitted. For reference, Figure 5a is a view illustrating intermediate steps following Figure 4d.

[0074] Referring to FIG5a, in some embodiments, the second bit line isolation trench 603 is directly filled. The material of the second bit line isolation trench 603 is not specifically limited and can be the same as or different from the material of the first bit line isolation trench 602. Planarization is performed to expose the first surface of the substrate 1, or it is not completely filled to expose the top of the active pillar 4. A storage contact 9 is formed at the top of the active pillar. Specifically, the storage contact 9 is formed by suitable methods such as ion implantation, diffusion by depositing a high concentration of doped material, or metallization reaction by depositing a metal material. The material of the storage contact 9 is not specifically limited. As an example, the material of the storage contact 9 may include at least one of the following: doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0075] Referring to Figures 1b and 5b, in some embodiments, word line isolation trenches 5 are patterned and etched on a first surface of the substrate. Word line isolation trenches 5 and bit line isolation trenches 6 form active pillars 4. Word lines 2 are formed in the word line isolation trenches, extending along a second direction and arranged in a first direction. The word lines surround the active pillars 4, on one, two, or three sides of the active pillars, controlling the charge movement of the active pillars 4. The material of the word lines is not specifically limited. As an example, the material of the word lines 2 may include, for example, doped polycrystalline silicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the word lines 2 may include, but are not limited to, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof.

[0076] A storage structure 11 is formed on the storage contact 9, and a rear connection line (not shown in the figure) is formed on the storage structure 11. The storage structure 11 may be a capacitor structure, the capacitor including upper and lower electrode plates and a high-k dielectric material located between the upper and lower electrode plates; it may also be a variable resistance storage structure, which switches to two resistance states by an electrical pulse applied to the memory element. For example, the variable resistance storage structure may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material or antiferromagnetic material whose crystal state changes according to the amount of current.

[0077] Referring to Figures 5c and 5d, in some embodiments, the substrate is flipped, the second surface of the substrate 1 is thinned and planarized, and the first line isolation layer 8 is used as the etch termination layer.

[0078] Referring to FIG5e, in some embodiments, since the bit line isolation layer 8 is made of a different material from the substrate, a self-aligned process can be used to selectively etch away the substrate material to form the bit line trench 12. The self-aligned process can reduce the number of exposures and lower the process cost.

[0079] Referring to FIG5f, in some embodiments, a bit line contact 10 is formed at the bottom of the bit line trench 12. The bit line contact 10 is formed by suitable methods such as ion implantation, deposition of high concentration doped material for diffusion, or deposition of metal material for metal silicide reaction. The material of the bit line contact 10 is not specifically limited. As an example, the material of the bit line contact 10 may include at least one of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi and combinations thereof.

[0080] Subsequently, referring to FIGS. 4j to 4l, bit lines 3 and shielding lines 16 are formed. Thus, a semiconductor memory device described with reference to FIGS. 2 and 3a to 3e can be manufactured.

[0081] It should be noted that the semiconductor structure preparation methods in the embodiments of this application can all be used to prepare the corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structure embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can understand the technical content of this application.

[0082] The technical features of the above embodiments can be combined in any way. In order to simplify the description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The embodiments described above are merely examples of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended patent application scope. [Simplified Explanation of the Diagram]

[0023] Figure 1a is a top view schematic diagram of a semiconductor structure provided in some disclosed embodiments; Figures 1b and 1c are cross-sectional structural schematic diagrams along the bit line and word line directions, respectively; Figure 2 is a cross-sectional structural schematic diagram of a semiconductor structure provided in some embodiments of this application along the word line direction; Figures 3a-3e are cross-sectional structural schematic diagrams of a semiconductor structure provided in other embodiments of this application along the word line direction; Figures 4a-4l are cross-sectional structural schematic diagrams of each stage of a method for preparing a semiconductor structure provided in some embodiments of this application along the word line direction; Figures 5a-5f are cross-sectional structural schematic diagrams of each stage of a method for preparing a semiconductor structure provided in other embodiments of this application along the word line direction.

Claims

1. A semiconductor structure, comprising: The active columns are arranged in an array in a first direction and a second direction, wherein the first direction intersects the second direction; Bit lines, extending in a first direction and spaced apart in a second direction, connecting active posts arranged along the first direction; shielding lines, located between adjacent bit lines and extending in the first direction, alternating with the bit lines in the second direction; bit line contact structures, located between and connecting the bit lines and the active posts, wherein the width of the bit line contact structure in the second direction is smaller than the width of the bit lines and the active posts in the second direction; bit line isolation layers, located between adjacent bit lines, with the shielding lines located within the bit line isolation layers; wherein the width of the bit line isolation layer in the second direction is greater than the width between adjacent active posts in the second direction.

2. The semiconductor structure as described in claim 1, wherein, The bit line contact structure connects two adjacent active posts in the second direction.

3. The semiconductor structure as described in claim 1, wherein, The width of the shielding line in the third direction is not less than the width of the bit line in the third direction, and the third direction intersects with the first direction and the second direction.

4. The semiconductor structure as described in claim 3, wherein, The width of the bit line in the second direction decreases as the bit line extends toward the bit line contact structure.

5. The semiconductor structure as described in any one of claims 1 to 3, further comprising: Bit line protection layer, the bit line protection layer is located on the side of the bit line away from the bit line contact structure; the bit line protection layer and the bit line isolation layer are made of different materials.

6. The semiconductor structure as described in any one of claims 1 to 3, wherein, The bit line includes at least one layer of metal material; the shielding line includes at least one layer of metal material.

7. The semiconductor structure as described in claim 1, further comprising: A shielding barrier layer that covers the shielding wire.

8. The semiconductor structure as claimed in claim 1, wherein, There is a gap between the bit line isolation layer and the shielding line.

9. The semiconductor structure as claimed in claim 1, wherein, The shielding wire has a cross-sectional shape perpendicular to the first direction that is conical, elongated, elliptical, star-shaped, or other suitable.

10. The semiconductor structure of claim 1, further comprising word lines extending in the second direction and spaced apart in the first direction, the word lines being connected to the active pillars in the second direction; and a storage structure connected to the active pillars and located at one end of all the source pillars away from the bit lines.

11. A method for fabricating a semiconductor structure, comprising: Active columns are formed, and the active columns are arranged in an array in a first direction and a second direction, wherein the first direction and the second direction intersect. A bit line is formed, which extends in a first direction, is spaced apart in a second direction, and connects to active pillars arranged along the first direction; Forming a shielding line, the shielding line being located between two adjacent bit lines and extending in a first direction, alternating with the bit lines in a second direction; forming a bit line contact structure; the bit line contact structure connecting the bit line and the active post, the width of the bit line contact structure in the second direction being smaller than the width of the bit line and the active post in the second direction; wherein, forming the bit line includes: providing a substrate, the substrate having a first surface and a second surface in a third direction, the third direction intersecting the first direction and the second direction; patterning and etching bit line isolation trenches on the first surface, the bottom dimension of the bit line isolation trench being larger than the top dimension of the bit line isolation trench, the bit line isolation trenches extending along the first direction and spaced apart in the second direction; filling the bit line isolation trenches to form a bit line isolation layer; grinding the second surface to expose the bit line isolation layer, etching the substrate with the bit line isolation layer as a mask to form the bit line trenches; filling the bit line trenches with at least one layer of metal material to form the bit line; A bit line protection layer is formed on the bit line, and the bit line protection layer and the bit line isolation layer are made of different materials.

12. The method for fabricating a semiconductor structure as described in claim 11, wherein, The formation of the shielding line includes: etching the bit line isolation layer on the second surface using the bit line protection layer as a masking layer to form a shielding line trench, wherein the depth of the shielding line trench is not less than the depth of the bit line trench; and filling the shielding line trench with at least one layer of metal material to form the shielding line.

13. A method for fabricating a semiconductor structure as described in any one of claims 11 to 12, wherein, The bit line contact structure includes a metal silicate, and forming the metal silicate includes: depositing a metal material layer at the bottom of the bit line trench and heat-treating to form the metal silicate; or depositing a metal material layer at the bottom of the bit line isolation trench and heat-treating to form the metal silicate.

14. The method for fabricating a semiconductor structure as described in claim 11, wherein, After filling the bit line isolation trench to form the bit line isolation layer, the method further includes: patterning and etching word line isolation trenches on the first surface, wherein the depth of the word line isolation trenches is less than the depth of the bit line isolation trenches, the bit line isolation trenches extend along the second direction and are spaced apart in the first direction, and the word line isolation trenches and the bit line isolation trenches form the active pillars; after forming the active pillars, the method further includes: forming word lines in the word line isolation trenches, the word lines extending in the second direction and spaced apart in the first direction, the word lines connecting the active pillars in the second direction; and forming a storage structure at the end of the active pillars away from the bit lines.

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