Semiconductor structure and method of fabricating the same

Abstract

A semiconductor structure includes a semiconductor fin protruding from a substrate and extending across the substrate along a first lateral direction. The semiconductor structure includes a plurality of gate structures disposed above the substrate, wherein each gate structure extends along a second lateral direction perpendicular to the first lateral direction. The semiconductor structure includes a gate isolation structure disposed above the gate structures. The gate isolation structure includes a first portion and a second portion connected to the first portion. The first portion extends above the gate structures along the first lateral direction. The second portion extends partially into the semiconductor fin along the second lateral direction.

Description

Technical Field

[0001] none Prior Technology

[0002] As the semiconductor industry moves towards nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, the challenges posed by manufacturing and design issues have led to the development of multi-gate devices, such as fin field-effect transistors (FinFETs) and gate-all-around (GAA) transistors. To continue providing the required scaling and increased density for multi-gate devices in advanced technology nodes, reducing device area while maintaining device performance is desirable. While various approaches have been implemented to provide area-saving benefits in integrated circuit (IC) manufacturing, they are not entirely satisfactory in every case. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figures 1A, 2A, 3A, 4A, 5A, 6A, and 7A illustrate top view layouts of portions or the entirety of example semiconductor devices according to some embodiments of this disclosure. Figures 1B, 2B, 3B, 4B, 6B, and 7B are cross-sectional views of portions or the entirety of an example semiconductor device taken along line AA' of Figures 1A, 2A, 3A, 4A, 5A, 6A, and 7A, respectively, according to some embodiments of the present disclosure. Figures 1C, 3D, 4C, 6D, and 7D are cross-sectional views of portions or the entirety of an example semiconductor device taken along line BB' of Figures 3A, 4A, 6A, and 7A, respectively, according to some embodiments of the present disclosure. Figures 3E, 4D, 6E, and 7E are cross-sectional views of portions or the entirety of an example semiconductor device taken along line CC' of Figures 3A, 4A, 6A, and 7A, respectively, according to some embodiments of the present disclosure. Figures 3C, 6C, and 7C each illustrate a cross-sectional view of a portion or the entirety of an example semiconductor device taken along line DD' of Figures 3A, 6A, and 7A, respectively, according to some embodiments of the present disclosure. Figure 5B illustrates a cross-sectional view of a portion or the entirety of an example semiconductor device taken along line AA' or line DD' of Figure 5A, according to some embodiments of the present disclosure. Figures 2C and 5C illustrate cross-sectional views of portions or the entirety of an example semiconductor device taken along line BB' or line CC' of Figures 2A and 5A, respectively, according to some embodiments of the present disclosure. Figure 8A illustrates a schematic diagram of an example of a portion or the entirety of a memory device according to some embodiments of the present disclosure. Figures 8B and 8C illustrate example layouts of a portion of a memory device corresponding to Figure 8A, according to some embodiments of this disclosure. Figure 9A illustrates an example circuit diagram of a portion of a memory device according to some embodiments of the present disclosure. Figures 9B, 9C, 9D, and 9E illustrate example layouts of the portion of the memory device corresponding to Figure 9A according to some embodiments of this disclosure. Figure 10A illustrates an example circuit diagram of a portion or the entirety of a logic device according to some embodiments of the present disclosure. Figures 10B and 10C illustrate example layouts of logic devices corresponding to Figure 10A according to some embodiments of this disclosure. Figure 11A illustrates an example circuit diagram of a portion or the entirety of a logic device according to some embodiments of the present disclosure. Figures 11B and 11C illustrate example layouts of logic devices corresponding to Figure 11A according to some embodiments of this disclosure. Figure 12 illustrates a portion or integral of an example semiconductor device according to some embodiments of the present disclosure. Figure 13 illustrates a flowchart of an example method for manufacturing part or all of an example semiconductor device according to some embodiments of the present disclosure. Figures 14, 17, 18, and 19 illustrate cross-sectional views of a portion or the entirety of an example semiconductor device taken along line XX' of Figure 12 and during an intermediate step of the method in Figure 13, according to some embodiments of this disclosure. Figures 15 and 16 illustrate cross-sectional views of portions or the entirety of an example semiconductor device taken along line YY' of Figure 12 and during an intermediate step of the method in Figure 13, according to some embodiments of this disclosure. Figure 20 illustrates a portion or the entirety of an example semiconductor device during an intermediate step of the method in Figure 13, according to some embodiments of the present disclosure. Figure 21 illustrates a flowchart of a method for manufacturing a semiconductor device according to some embodiments. Figure 22 illustrates a block diagram of a system for generating IC layout designs according to some embodiments. Figure 23 illustrates a block diagram of an IC manufacturing system according to some embodiments and the associated IC manufacturing process. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," "top," "bottom," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0007] Referring to Figures 1A, 1B, and 1C, a semiconductor device 10A (hereinafter referred to as device 10A) is provided above a semiconductor substrate 8 (hereinafter referred to as substrate 8). Figure 1A depicts a top view of device 10A, Figure 1B depicts a cross-sectional view of device 10A taken along line AA', and Figure 1C depicts a cross-sectional view of device 10A taken along line BB'.

[0008] Device 10A includes at least one active region 12A disposed on or above substrate 8, wherein the active region 12A extends longitudinally along a first lateral direction (i.e., the X-axis). As will be described in detail below, device 10A includes one or more metal-oxide-semiconductor (MOS) devices (e.g., MOS field-effect transistors or MOSFETs) formed on or above the active region 12A. Although only one active region 12A is depicted in Figures 1A through 1C, device 10A may include any suitable number of active regions extending parallel to the active region 12A. The MOS devices depicted in Figures 1A through 1C may be PMOS transistors or NMOS transistors. In some embodiments, the active region 12A is configured as a three-dimensional semiconductor structure protruding from substrate 8 and may be referred to as semiconductor fin 12A, fin structure 12A, or the like.

[0009] In some embodiments, substrate 8 includes semiconductor materials such as silicon (Si), silicon-germanium (SiGe), compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, any other suitable materials, or combinations thereof. In some embodiments, substrate 8 includes an epitaxial layer. For example, substrate 8 may include an epitaxial layer of an overlying semiconductor. Furthermore, substrate 8 may include a semiconductor-on-insulator (SOI) structure. For example, substrate 8 may include a buried oxide (BOX) layer formed by processes such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and polishing. Substrate 8 may include one or more doped wells, such as p-type doped wells (p-wells) and n-type doped wells.

[0010] Referring to Figure 1B, the active region 12A can be configured as a semiconductor fin structure comprising a plurality of nanostructures 13A stacked along a vertical direction (i.e., the Z-axis). The nanostructures 13A comprise semiconductor material and are configured as a plurality of channels of a MOS device engaging with one or more active gate structures. In this disclosure, the nanostructure 13A may alternatively be referred to as semiconductor layer 13A or channel layer 13A. Although the nanostructure 13A is depicted as a nanosheet in this embodiment, the nanostructure 13A may also be alternatively shaped into other types of structures, such as, for example, nanorods or nanowires.

[0011] Nanostructure 13A may comprise any suitable semiconductor material, such as silicon (Si), silicon-germanium (SiGe), compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, any other suitable material, or combinations thereof. In some embodiments, nanostructure 13A is substantially free of any dopant (e.g., p-type or n-type dopant). In some embodiments, nanostructure 13A is intentionally doped. For example, nanostructure 13A may be doped with p-type dopant, such as boron (B), aluminum (Al), indium (In), gallium (Ga), other p-type dopant, or combinations thereof. Alternatively, nanostructure 13A may be doped with n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), other n-type dopant, or combinations thereof.

[0012] Although not depicted here, device 10A also includes an isolation structure disposed above substrate 8 and surrounding the bottom portion of active region 12A. The isolation structure is configured to electrically isolate adjacent active regions (e.g., active region 12A) from each other. In some embodiments, the isolation structure includes a shallow-trench isolation (STI) structure.

[0013] Referring to Figures 1A through 1C, device 10A includes source / drain features 14A, each electrically coupled along a first lateral direction to one end of nanostructure 13A, such that the source / drain features 14A together with nanostructure 13A form active region 12A. Thus, each source / drain feature 14A extends vertically over the entire stack of nanostructure 13A and shares the same dimension with nanostructure 13A along a second lateral direction. In other words, the width of active region 12A defines the width of nanostructure 13A and source / drain features 14A along the second lateral direction. For embodiments where the MOS device is configured as an NMOS transistor, the source / drain features 14A may comprise Si doped with the n-type dopant described herein. For embodiments where the MOS device is configured as a PMOS transistor, the source / drain features 14A may comprise SiGe doped with the p-type dopant described herein. According to various embodiments disclosed herein, each of the source / drain features 14A can be configured as a source feature or a drain feature.

[0014] In some embodiments, referring to Figures 1B and 1C, device 10A includes a bottom isolation layer 15 embedded in substrate 8. The bottom isolation layer 15 is disposed beneath source / drain features 14A such that the top surface of the bottom isolation layer 15 abuts against the bottom surface of the source / drain features 14A. The bottom isolation layer 15 is used to reduce or prevent current leakage between adjacent source / drain features 14A. In some embodiments, the bottom isolation layer 15 includes any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, other suitable dielectric materials, or combinations thereof.

[0015] Referring again to Figures 1A and 1B, device 10A includes a plurality of active gate structures 16A, 16B, and 16C (collectively referred to as active gate structures 16), each active gate structure having at least a bottom (or lower) portion that surrounds each nanostructure 13A. In this respect, the bottom portions of the active gate structures 16 are staggered with the stack of nanostructures 13A. Furthermore, the active gate structures 16 include a top (or upper) portion disposed above the topmost nanostructure 13A in the stack. Each active gate structure 16 extends along a second lateral direction (i.e., the Y-axis) and is generally perpendicular to the active region 12A. Although only three active gate structures 16 are depicted in Figures 1A through 1C, device 10A may include any suitable number of active gate structures 16.

[0016] In some embodiments, the active gate structure 16 includes a gate dielectric layer and a gate metal above the gate dielectric layer (not depicted separately in Figures 1A and 1B). The gate dielectric layer may include any suitable dielectric material, such as a high-k dielectric material (e.g., having a dielectric constant greater than that of silicon oxide (approximately 3.9)). Examples of high-k dielectric materials include metal oxides or metal silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and Pb, any other suitable material, or combinations thereof. Alternatively, the gate dielectric layer may include silicon oxide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The gate dielectric layer may include a stack of multiple different dielectric materials.

[0017] Gate metal may comprise a stack of multiple metallic materials. For example, gate metal may comprise at least a work function layer (not depicted separately) and a conductive fill layer (not depicted separately) disposed above the work function layer. The work function layer may comprise a p-type work function layer, an n-type work function layer, multiple layers thereof, any other suitable material, or a combination thereof. The work function layer may also be referred to as work function metal. Examples of work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable materials, or combinations thereof. The conductive fill layer may comprise any suitable conductive material, such as polysilicon, tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), platinum (Pt), other suitable conductive materials, or combinations thereof (or alloys thereof). The active gate structure 16 may further include additional layers, such as an adhesive layer, a cap layer, a barrier layer, other suitable layers, or combinations thereof.

[0018] Referring to Figure 1B, device 10A includes an internal spacer 11 inserted along a first lateral direction between a portion of the active gate structure 16 and the source / drain feature 14A. Device 10A further includes gate spacers 17, each extending along a sidewall of the top portion of the active gate structure 16. The internal spacer 11 and gate spacer 17 may each comprise any dielectric material, such as silicon oxide, silicon nitride, silicon oxycarbonitride, other suitable materials, or combinations thereof. The internal spacer 11 and gate spacer 17 may each comprise multiple layers of different dielectric materials. The internal spacer 11 and gate spacer 17 may comprise the same or different dielectric materials(s). It should be noted that, for simplicity, gate spacer 17 is omitted in the depiction in Figure 1A.

[0019] Referring again to Figures 1A through 1C, device 10A further includes various source / drain contacts 18A, 18B, and 18C (collectively referred to as source / drain contacts 18), each contact being electrically coupled to and covering a corresponding one of the source / drain features 14A. Each source / drain contact 18 extends along a second lateral direction and is spaced apart from each other along a first lateral direction. In this respect, the source / drain contacts 18 extend parallel to the active gate structure 16 and perpendicular to the active region 12A. In the depicted embodiment, each source / drain contact 18 is disposed between two adjacent active gate structures 16.

[0020] The source / drain contact 18 may include a conductive fill layer (not depicted separately) having a conductive material such as W, Cu, Co, Ru, Al, Ti, Ta, Au, Ag, Pt, other suitable conductive materials, or combinations thereof (or alloys thereof). The source / drain contact 18 may include a barrier layer (not depicted) separating the conductive fill layer from surrounding components. The barrier layer may include Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof. The source / drain contact 18 may further include a metal silicate layer (not depicted) disposed between the conductive fill layer and the underlying source / drain feature 14A. The metal silicate layer may include, for example, NiSi.

[0021] In some embodiments, referring to Figure 1C, device 10A further includes an interlayer dielectric (ILD) layer 19 disposed above the source / drain feature 14A and surrounding or embedded in the top portion of the MOS device. The ILD layer 19 may include any dielectric material, such as oxides, nitrides, low-k dielectric materials (examples above), other suitable dielectric materials, or combinations thereof.

[0022] In this embodiment, device 10A further includes a plurality of gate isolation structures 50 and 52 (or gate cleaving features 50 and 52) that at least partially extend across the active gate structure 16. In some embodiments, gate isolation structures 50 and 52 are used to segment the active gate structure to provide the required scaling and increased density for devices at advanced technology nodes (such as the depicted MOS device). In some embodiments, each of gate isolation structures 50 and 52 abuts against a sidewall of the active gate structure 16 extending in a first lateral direction. Gate isolation structures 50 and 52 may each include any suitable dielectric material, such as silicon oxide, silicon nitride, other suitable materials, or combinations thereof. Although two gate isolation structures are depicted in Figures 1A through 1C, device 10A may include any suitable number of gate isolation structures similar to gate isolation structures 50 and / or gate isolation structures 52.

[0023] Referring to Figure 1A, for example, the gate isolation structure 50 includes a first portion 50A (or horizontal portion 50A) and a second portion 50B (or first lateral portion 50B) extending from the first portion 50A along a second lateral direction and connected to the first portion 50A. The first portion 50A generally extends along the first lateral direction and is parallel to the active region 12A. In this embodiment, the first portion 50A is disposed between two adjacent active regions, one of which is depicted as active region 12A. Referring to Figures 1A to 1C, the second portion 50B generally extends along the second lateral direction from the first portion 50A toward the active region 12A, thereby intersecting with one of the source / drain features 14A. Thus, the second portion 50B is generally perpendicular to the first portion 50A. In the depicted embodiment, the second portion 50B is disposed between active gate structures 16B and 16C. Furthermore, in some embodiments, the second portion 50B is equidistant from each of the active gate structures 16B and 16C along the first lateral direction.

[0024] As depicted in Figure 1A, the second portion 50B partially penetrates or cuts off the source / drain feature 14A, such that the end portion of the second portion 50B is surrounded by a portion of the source / drain feature 14A. In other words, referring to Figures 1B and 1C, the end portion of the second portion 50B replaces a portion of the source / drain feature 14A. Furthermore, as the second portion 50B extends along a second lateral direction, a portion of the source / drain contact 18B overlaps with the second portion 50B (and a segment of the first portion 50A as depicted herein). Referring to Figure 1C, the sidewall of the second portion 50B abuts against and directly contacts the sidewall of the source / drain feature 14A in a vertical direction. In some embodiments, as depicted in Figures 1A to 1C, one of the source / drain contacts 18 extends above and directly contacts the top surface of the second portion 50B. Furthermore, the bottom surface of the second portion 50B abuts against the top surface of the bottom insulating layer 15. In this regard, at least in some embodiments, the second portion 50B selectively replaces a portion of one of the source / drain features 14A without penetrating the bottom isolation layer 15.

[0025] Referring to Figure 1A, the gate isolation structure 52 includes a first portion 52A (or horizontal portion 52A) that generally extends along a first lateral direction and is parallel to the first portion 50A of the gate isolation structure 50. The first portion 50A of the gate isolation structure 50 and the first portion 52A of the gate isolation structure 52 are spaced apart along a second lateral direction, with the active region 12A disposed therebetween. As depicted in device 10A, the gate isolation structure 52 differs from the gate isolation structure 50 in that the gate isolation structure 52 does not include any lateral portion similar to the second portion 50B of the gate isolation structure 50. In other words, the gate isolation structure 52 does not contact the active region 12A at all, as depicted in Figures 1A to 1C.

[0026] In this embodiment, the active region 12A has a width W1 extending along the second lateral direction. In this regard, the stack of nanostructures 13A engaging with each active gate structure 16 has a width W1, and the first of the source / drain features 14A disposed between the first portion 50A and the gate isolation structure 52 also has this width W1. Referring to Figures 1A and 1C, a portion of the second source / drain feature 14A disposed between the second portion 50B and the gate isolation structure 52 has a width W2 extending along the second lateral direction, wherein the width W2 is smaller than the width W1. In this regard, as the second portion 50B intersects with the source / drain feature 14A, it reduces the width of the active region 12A, such that the width W2 is a small fraction of the width W1. In this embodiment, the width W2 is greater than 0 and less than the width W1, that is, the second portion 50B does not completely truncate or replace the second of the source / drain features 14A along the second lateral direction. In other words, the ratio of W2 / W1 is greater than 0 and less than 1.

[0027] The current Id (or drain current) of the MOS device described in this article can generally be defined by the mathematical expression in Equation I: (I), Where µ represents the carrier mobility applicable to the type of MOS device (e.g., n-channel or n-type MOS device, p-channel or p-type MOS device, etc.), W represents the width of the active region (e.g., the dimension along the width direction of the active region), L is the length of the active region (e.g., the dimension along the length direction of the active region), Cox represents the capacitance of the gate dielectric layer (e.g., gate oxide) of the active gate structure, VGS represents the gate-source voltage of the MOS device, and VT represents the threshold voltage of the MOS device. In this respect, the current Id is generally proportional to the width of the active region and inversely proportional to the length of the active region. In other words, the current Id can be tuned by adjusting the size of the MOS device, among other factors. Still referring to Equation I, the device 10A can be represented by an equivalent circuit such that the current Id can be defined by the following Equation II: (II), Where Ve and Re represent the voltage and resistance of the equivalent circuit, respectively. For example, Re can be defined as the sum of the resistance Rch of the channel (i.e., the stack of nanostructures 13A), the resistance RS of the source (i.e., one of the source / drain features 14A), and the resistance RD of the drain (i.e., the other of the source / drain features 14A), as shown in Equation II' below: (II')

[0028] In various situations, reducing the current Id generated by MOS devices can be beneficial, while, according to Equation I, all other factors remain constant to achieve a specific design goal. Because the channel width in conventional nanodevices (e.g., GAA devices) is generally fixed and quantized, the options for tuning the current Id that affects the device's timing margin are limited. For example, existing techniques generally employ the method of series-coupled large numbers of MOS devices, thereby increasing the length L of the active region to reduce the current Id of the resulting equivalent device. For example, multiple series-coupled PMOS transistors can be used to generate low leakage current in the retrieval circuitry (peripheral circuitry) of memory devices. While this approach is generally sufficient, it is not entirely satisfactory in all cases. For example, increasing the number of series-coupled MOS devices may come at the cost of increasing the device footprint (i.e., area), making it difficult to scale devices at advanced technology nodes.

[0029] In this disclosure, embodiments provide a structure for a MOS device that allows adjustment of the current Id by utilizing a two-dimensional gate isolation structure (e.g., as depicted in the top view) that partially cuts or truncates the active region of the MOS device along a second lateral direction (i.e., the width direction of the active region). In this respect, the width W of the active region decreases, and the current Id (related to the width W by Equation I) also decreases. In the prior art, gate isolation structures generally extend parallel to two adjacent active regions and are disposed between the two adjacent active regions. Thus, each gate isolation structure is used to isolate one or more active gate structures (e.g., electrically and / or physically) into two separate regions or segments disposed along the second lateral direction. In some cases, the gate isolation structure, also referred to as a gate cleaving feature, truncates the originally continuous active gate structure into isolated segments.

[0030] However, in this embodiment, at least one of the gate isolation structures (e.g., gate isolation structure 50 in Figures 1A to 1C) includes a horizontal portion (e.g., first portion 50A) and a lateral portion extending from the horizontal portion (e.g., second portion 50B). In this respect, the horizontal portion extends along a first lateral direction, i.e., parallel to the active region (e.g., active region 12A), and the lateral portion extends along a second lateral direction, i.e., parallel to the active gate structure (e.g., active gate structure 16). The lateral portion replaces a portion rather than the entirety of the source / drain feature (e.g., source / drain feature 14A) disposed in the active region, effectively reducing the width W of the active region of a given MOS device. In various embodiments, the two-dimensional gate isolation structures provided herein can improve the design flexibility of MOS devices without incurring additional area costs for device footprint, which is particularly beneficial at advanced technology nodes. Furthermore, this approach, which modifies existing structural features (e.g., gate isolation structures), reduces or eliminates the need for additional photomasks and / or additional manufacturing steps to obtain active areas in different dimensions, thereby reducing the overall complexity and cost of the device manufacturing process.

[0031] In this embodiment, referring to Figures 1A to 1C, the second portion 50B reduces the width W1 of the active region 12A to a width W2, thereby generating an adjustment current Id_adj smaller than the current Id. In some embodiments, replacing a portion of the active region 12A (e.g., the first of the source / drain features 14A) with the second portion 50B, which includes an electrically insulating material, effectively increases the resistance of one of the source / drain features 14A (i.e., RS or RD as defined in Equation II' above) to RS_cmg1 or RD_cmg1, thus increasing the resistance portion Re of the equivalent series circuit. Therefore, the adjustment current Id_adj can be defined as... (III) or (III'), This is less than the current Id defined in Equations I and II above. In this respect, this reduction in current Id is generally related to the resistance RD_cmg1 (or RS_cmg1), which can be positively correlated with (e.g., proportionally varied) the length Lcmg1 of the second part 50B, which is the length of the second part 50B that replaces a portion of the first source / drain feature 14A. Mathematically, the length Lcmg1 is the difference between width W1 and width W2. As a result, a decrease in width W2 corresponds to an increase in length Lcmg1, which leads to an increase in resistance RD_cmg1, thereby leading to a further decrease in the adjustment current Id_adj. In other words, a decrease in width W2 leads to a decrease in the adjustment current Id_adj.

[0032] In some embodiments, additional resistance can be effectively introduced or contributed to the resistive portion Re of the equivalent series circuit by utilizing one or more lateral portions of a gate isolation structure similar to gate isolation structure 50, thereby increasing the resistive portion Re and reducing the adjustment current Id_adj. For example, referring to Figures 2A, 2B, and 2C, a semiconductor device 10B (hereinafter referred to as device 10B) is provided. Figure 2A depicts a top view of device 10B, Figure 2B depicts a cross-sectional view of device 10B taken along line AA', and Figure 2C depicts a cross-sectional view of device 10B taken along line BB' or line CC'.

[0033] Device 10B is substantially similar to device 10A, except that the gate isolation structure 50 in device 10B further includes a third portion 50C (or a second lateral portion 50C) that extends along a second lateral direction from the first portion 50A toward the second of the source / drain features 14A. In this respect, as shown in Figure 2A, the second portion 50B and the third portion 50C are substantially parallel to each other. Referring to Figures 2A through 2C, the third portion 50C truncates or replaces a portion of the second of the source / drain features 14A, thereby reducing the width W1 of the active region 12A to a width W3, wherein the width W3 is smaller than the width W1.

[0034] Therefore, similar to the effect of the second part 50B on the adjustment current Id_adj, the ratio of W3 / W1 is greater than 0 and less than 1. Furthermore, considering the second part 50B, which reduces the width W1 of the active region 12A (in the first of the source / drain features 14A) to a width W2, the adjustment current Id_adj of the MOS device shown in Figures 2A to 2C can be determined according to the following equation IV, based on the resistance contribution (cmg1) of the second part 50B to the source feature 14A (or drain feature 14A) and the resistance contribution (cmg2) of the third part 50C to the drain feature 14A (or source feature 14A): (IV).

[0035] In some embodiments, the adjustment current Id_adj can be tuned by independently changing the widths W2 and W3. In other words, the adjustment current Id_adj can be tuned by configuring the shape and dimensions of the gate isolation structure 50. For example, by changing the length Lcmg1 of the second portion 50B (i.e., changing the width W2) and the length Lcmg2 of the third portion 50C (i.e., changing the width W3), respectively, one of the resistors RS_cmg and RD_cmg can be tuned independently. Advantageously, without utilizing the gate isolation structure described herein, in order to achieve an adjustment current Id_adj that is a fraction of the current Id, multiple MOS devices need to be connected in series along the active region 12A, thereby increasing the area occupied by the device 10B, such as the area defined by a number of center-poly pitch (CPP) segments of the active gate structure 16.

[0036] Referring to Figures 3A, 3B, 3C, 3D, and 3E, a semiconductor device 10C (hereinafter referred to as device 10C) is provided. Figure 3A depicts a top view of device 10C, Figure 3B depicts a cross-sectional view of device 10C taken along line AA', Figure 3C depicts a cross-sectional view of device 10C taken along line DD', Figure 3D depicts a cross-sectional view of device 10C taken along line BB', and Figure 3E depicts a cross-sectional view of device 10C taken along line CC'.

[0037] Device 10C is substantially similar to device 10B, except that the gate isolation structure 52 in device 10C includes a second portion 52B (or a first lateral portion 52B) that extends along a second lateral direction from the first portion 52A toward the first of the source / drain features 14A, and the gate isolation structure 50 does not include a second portion 50B as in device 10B. As shown in Figure 3A, the third portion 50C is substantially parallel to and faces the second portion 52B. Referring to Figures 3A through 3E, the second portion 52B truncates or replaces a portion of the first of the source / drain features 14A, thereby reducing the width W1 of the active region 12A to a width W4.

[0038] Therefore, similar to the effect of the second part 50B on the adjustment current Id_adj, the ratio of W4 / W1 is greater than 0 and less than 1. Furthermore, considering the third part 50C, which reduces the width W1 of the active region 12A (in the second of the source / drain features 14A) to a width W3, the adjustment current Id_adj of the MOS device depicted in Figures 3A to 3E can be determined according to the following equation V, based on the resistance contribution (cmg2) of the third part 50C to the source feature 14A and the resistance contribution (cmg3) of the second part 52B to the drain feature 14A: (V), The resistance RS_cmg2 increases with the increase of length Lcmg2 and the decrease of width W3, while the resistance RD_cmg3 increases with the increase of length Lcmg3 and the decrease of width W4.

[0039] Referring to Figures 4A, 4B, 4C, and 4D, a semiconductor device 10D (hereinafter referred to as device 10D) is provided. Figure 4A depicts a top view of device 10D, Figure 4B depicts a cross-sectional view of device 10D taken along line AA', Figure 4C depicts a cross-sectional view of device 10D taken along line BB', and Figure 4D depicts a cross-sectional view of device 10D taken along line CC'.

[0040] Device 10D is substantially similar to device 10B, except that the gate isolation structure 52 in device 10D includes a third portion 52C (or a second lateral portion 52C) that extends from the first portion 52A toward the second of the source / drain features 14A along a second lateral direction. In this respect, as shown in Figure 4A, the third portion 52C of the gate isolation structure 52 is substantially parallel to the second portion 50B of the gate isolation structure 50, and the third portion 52C extends in a direction facing the third portion 50C of the gate isolation structure 50. Furthermore, the gate isolation structure 52 does not include the second portion 52B as shown in Figures 3A to 3E.

[0041] Referring to Figures 4A through 4D, each of the third portions 50C and 52C truncates or replaces a portion of the second source / drain feature 14A, thereby reducing the width W1 of the active region 12A to a width W5. In the depicted embodiment, the third portions 50C and 52C replace the opposite end portions of the second source / drain feature 14A along a second lateral direction.

[0042] Therefore, similar to the effect of the second part 50B on the adjustment current Id_adj, the ratio of W5 / W1 is greater than 0 and less than 1. Furthermore, considering the second part 50B, which reduces the width W1 of the active region 12A (in the first of the source / drain features 14A) to a width W2, the adjustment current Id_adj of the MOS device depicted in Figures 4A to 4D can be determined according to the following equation VI, based on the resistance contribution (cmg1) of the second part 50B to the drain feature 14A, the resistance contribution (cmg2) of the third part 50C to the source feature 14A, and the resistance contribution (cmg4) of the third part 52C to the source feature 14A: (VI), Among them, the resistance RD_cmg1 increases as the width W2 decreases, and the resistance RS_cmg2+cmg4 increases as the width W5 decreases.

[0043] Similar to the embodiments depicted in Figures 2A through 2C, the adjustment current Id_adj in device 10D can be tuned by independently changing the widths W2 and W5 to achieve the desired reduction in current Id without incorporating an additional MOS device. In some instances, the embodiments depicted in Figures 4A through 4D allow for additional design and manufacturing flexibility for device 10D, as the width W5 can be changed by configuring the dimensions of one or both of the third parts 50C and 52C.

[0044] Referring to Figures 5A, 5B, and 5C, a semiconductor device 10E (hereinafter referred to as device 10E) is provided. Figure 5A depicts a top view of device 10E, Figure 5B depicts a cross-sectional view of device 10E taken along line AA' or line DD', and Figure 5C depicts a cross-sectional view of device 10E taken along line BB' or line CC'.

[0045] Device 10E is substantially similar to device 10D, except that the gate isolation structure 52 in device 10D additionally includes a second portion 52B that extends along a second lateral direction from the first portion 52A toward the first of the source / drain features 14A. In this respect, as shown in Figure 5A, the second portion 52B of the gate isolation structure 52 is substantially parallel to the third portion 52C, and the second portion 52B of the gate isolation structure 52 extends in a direction facing the second portion 50B of the gate isolation structure 50.

[0046] Referring to Figures 5A through 5C, each of the second portion 50B of the gate isolation structure 50 and the second portion 52B of the gate isolation structure 52 cuts off or replaces a portion of the first source / drain feature 14A, thereby reducing the width W1 of the active region 12A to a width W6, wherein the width W6 is smaller than the width W1. In the depicted embodiment, the second portions 50B and 52B replace the opposite end portions of the first source / drain feature 14A along a second lateral direction.

[0047] Therefore, similar to the effect of the second part 50B on the adjustment current Id_adj, the ratio of W6 / W1 is greater than 0 and less than 1. Furthermore, considering the third part 50C and the third part 52C of the gate isolation structure 50 that cuts off or replaces a portion of the second of the source / drain features 14A, the adjustment current Id_adj in the MOS device depicted in Figures 5A to 5C can be determined according to the following equation VII, based on the resistance contribution (cmg1) of the second part 50B to the drain feature 14A, the resistance contribution (cmg2) of the third part 50C to the source feature 14A, the resistance contribution (cmg3) of the second part 52B to the drain feature 14A, and the resistance contribution (cmg4) of the third part 52C to the source feature 14A: (VII), Among them, the resistance RD_cmg1+cmg3 increases as the width W6 decreases, and the resistance RS_cmg2+cmg4 increases as the width W5 decreases.

[0048] In some instances, if width W5 is substantially similar to or the same as width W3, and width W6 is substantially similar to or the same as width W2, assuming other factors of Equation I remain constant, then the MOS devices depicted in Figures 5A to 5C and Figures 2A to 2C are used to generate the same adjustment current Id_adj according to the expression of Equation I. Furthermore, if width W6 is substantially similar to or the same as width W2, assuming other factors of Equation I remain constant, then the MOS devices depicted in Figures 5A to 5C and Figures 4A to 4D are used to generate the same adjustment current Id_adj according to the expression of Equation I. Furthermore, if width W5 is substantially similar to or the same as width W3, and width W6 is substantially similar to or the same as width W4, assuming other factors of Equation I remain constant, then the MOS devices depicted in Figures 5A to 5C and the MOS devices depicted in Figures 3A to 3E are used to generate the same adjustment current Id_adj according to the expression of Equation I. Therefore, the same adjustment current Id_adj can be achieved using various configurations and dimensions of gate isolation structures provided in this paper, thereby providing more flexible current tuning options for devices at advanced technology nodes.

[0049] Referring to Figures 6A, 6B, 6C, 6D, and 6E, a semiconductor device 10F (hereinafter referred to as device 10F) is provided. Figure 6A depicts a top view of device 10F, Figure 6B depicts a cross-sectional view of device 10F taken along line AA', Figure 6C depicts a cross-sectional view of device 10F taken along line DD', Figure 6D depicts a cross-sectional view of device 10F taken along line BB', and Figure 6E depicts a cross-sectional view of device 10F taken along line CC'.

[0050] Device 10F, while having components similar to device 10A, includes an additional active region 12B extending parallel to active region 12A and an additional active gate structure 16D extending parallel to active gate structures 16A-16C. Active region 12B includes a stack of nanostructures 13B similar to nanostructure 13A and source / drain features 14A, respectively, and source / drain features 14B (although they may include dopants of different conductivity types). Active region 12A may be defined by width W1, and active region 12B may be defined by width W8, which may be the same as or different from width W1. For embodiments where active regions 12A and 12B are used to provide MOS devices with different conductivity types, width W1 may be different from width W8. In this embodiment, the various gate isolation structures described herein provide design options for further tuning the widths of the active regions, similar to the design options described above with respect to devices 10A-10E of Figures 1A to 5C.

[0051] The device 10F further includes a plurality of movable gate structures 16E, 16F, 16G, and 16H extending along a second lateral direction from movable gate structures 16A, 16B, 16C, and 16D (collectively referred to as movable gate structures 16). Each pair of movable gate structures 16 arranged along the second lateral direction is separated by a gate isolation structure 62, which extends above the first end of each of the movable gate structures 16A-16D, which is opposite to the second end of each of the movable gate structures 16A-16D. Similarly, the gate isolation structure 62 is disposed on the first end of each of the movable gate structures 16E-16H, which is opposite to the second end of each of the movable gate structures 16E-16H. The device 10F further includes a gate isolation structure 60 extending above the second end of each of the active gate structures 16A-16D and a gate isolation structure 64 extending above the second end of each of the active gate structures 16E-16H. Therefore, the horizontal portions of the gate isolation structures 60, 62, and 64 extend parallel to each other along a first lateral direction and are used to isolate adjacent active gate structures 16 along a second lateral direction, similar to the structure and function of the gate isolation structures 50 and 52 described herein.

[0052] In the depicted embodiment, referring to Figures 6A to 6E, the gate isolation structure 60 includes a first portion 60A (or horizontal portion 60A), a second portion 60B (or first lateral portion 60B), and a third portion 60C (or second lateral portion 60C), each of the second portion 60B and the third portion 60C extending from the first portion 60A along a second lateral direction. The first portion 60A extends along a first lateral direction and is perpendicular to the second portion 60B and the third portion 60C. The second portion 60B and the third portion 60C are spaced apart from each other along the first lateral direction. Specifically, the second portion 60B is disposed between the movable gate structures 16B and 16C, and the third portion 60C is disposed between the movable gate structures 16C and 16D. The gate isolation structure 64 includes a first portion 64A (or horizontal portion 64A) and a second portion 64B (or lateral portion 64B) extending from the first portion 64A along a second lateral direction. The gate isolation structure 62 includes a first portion 62A (or horizontal portion 62A) extending along a first lateral direction. In the depicted embodiment, referring to Figures 6A and 6E, a third portion 60C extends through the active region 12A (i.e., replacing an entire portion of one of the source / drain features 14A) and couples the first portion 60A of the gate isolation structure 60 to the gate isolation structure 62 along a second lateral direction.

[0053] In some embodiments, active regions 12A and 12B engage with active gate structures 16A-16D and 16E-16H, respectively, to provide MOS devices with different conductivity types. For example, active region 12A (i.e., a stack of nanostructures 13A) engages with active gate structure 16B to form a first MOS device MOS1, and a pair of source / drain features 14A are disposed on or across the sidewalls of active gate structure 16B. On the other hand, active region 12B (i.e., a stack of nanostructures 13B) engages with active gate structure 16F to form a second MOS device MOS2, and engages with active gate structure 16G to form a third MOS device MOS3, and a pair of source / drain features 14B are disposed on each side of active gate structure 16F and active gate structure 16G, respectively. In some embodiments, source / drain feature 14A includes one or more p-type dopants as described herein, causing MOS1 to behave as a PMOS transistor, and source / drain feature 14B includes one or more n-type dopants as described herein, causing MOS2 and MOS3 to behave as PMOS transistors.

[0054] Similar to the effect of the second portion 50B and / or the third portion 50C of the gate isolation structure 50, the second portion 60B of the gate isolation structure 60 and the second portion 64B of the gate isolation structure 64 are used to reduce the widths of the active regions 12A and 12B, respectively. For example, referring to Figures 6A, 6B, and 6D, the second portion 60B truncates or replaces a portion of the first of the source / drain features 14A, thereby reducing the width W1 of the active region 12A to a width W9, where the ratio of W9 / W1 is greater than 0 and less than 1. Similarly, referring to Figures 6A and 6C, the second portion 64B truncates or replaces a portion of the first of the source / drain features 14B, thereby reducing the width W8 of the active region 12B to a width W10, where the ratio of W10 / W8 is greater than 0 and less than 1. Furthermore, referring to Figures 6A and 6E, the third part 60C completely replaces the second of the source / drain features 14A, thereby bridging or coupling the gate isolation structure 60 and the gate isolation structure 62, and effectively isolating MOS1 from adjacent devices (not depicted here).

[0055] Therefore, the adjustment current Id_adj of MOS1 can be determined according to the following equation VIII, based on the resistance contribution (cmg5) of the drain characteristic 114A (or source characteristic 14A) of MOS1 in part 60B: (VIII), The resistance RD_cmg5 increases with the increase of length Lcmg5 and the decrease of width W9. Similarly, the adjustment current Id_adj of MOS3 can be determined according to the following equation IX, based on the resistance contribution (cmg6) of the source feature 14A (or drain feature 14A) of MOS3 in Part 2 64B: (IX), The resistance RS_cmg6 increases as the length Lcmg6 increases and the width W10 decreases.

[0056] In an embodiment where MOS1 is configured as a PMOS transistor and MOS2 and MOS3 are configured as NMOS transistors, according to Equations I, VIII, and IX described herein, by changing the dimension (e.g., width W9 and / or W10) of one or more of the lateral portions of the gate isolation structures 60, 62, and / or 64, the adjustment current Id_adj in MOS devices of different conductivity types can be independently tuned.

[0057] Referring to Figures 7A, 7B, 7C, 7D, and 7E, a semiconductor device 10G (hereinafter referred to as device 10G) is provided. Figure 7A depicts a top view of device 10G, Figure 7B depicts a cross-sectional view of device 10G taken along line AA', Figure 7C depicts a cross-sectional view of device 10G taken along line DD', Figure 7D depicts a cross-sectional view of device 10G taken along line BB', and Figure 7E depicts a cross-sectional view of device 10G taken along line CC'.

[0058] Device 10G includes components substantially similar to those of device 10F, except that the gate isolation structure 60 does not include a third portion 60C extending from the first portion 60A toward the second of the source / drain features 14A. The active region 12A engages with the active gate structure 16C to form a fourth MOS device MOS4, wherein a pair of source / drain features 14A spans the sidewalls of the active gate structure 16C. In the depicted embodiment, because MOS1 and MOS4 share a common source / drain feature 14A, a portion of which is replaced by the second portion 60B, the regulating current Id_adj of MOS4 can be defined by Equation VIII above.

[0059] Figures 8A to 11C further illustrate examples of the concepts embodied in devices 10A to 10G.

[0060] In one example, referring to Figures 8A, 8B, and 8C, a memory device 100 is provided. Referring to Figure 8A, which depicts a schematic diagram of the memory device 100, the memory device (or macro) 100 includes input / output (I / O) circuitry 110, control logic circuitry 120, word line (WL) drivers 130, and a memory array 101. The I / O circuitry 110, control logic circuitry 120, and WL drivers 130 can be collectively referred to as peripheral circuitry of the memory device 100. The memory array 101 includes a plurality of bit cells 102 arranged in a two-dimensional or three-dimensional array, wherein each bit cell 102 may include, for example, a static random-access memory (SRAM) cell. Each of the bit cells 102 can be accessed via a plurality of access lines, such as corresponding word lines and corresponding pairs of bit lines (BL). Although not explicitly shown in Figure 8A, the various components in memory device 100 can be electrically (or operatively) coupled to each other and to control logic circuitry 120.

[0061] WL driver 130 may include a column decoder and a WL voltage supply unit responsible for enabling word lines within memory array 101. I / O circuitry 110 is a hardware component capable of accessing (e.g., reading, programming) each of the bit units 102 determined by region decoders (such as column decoders and row decoders). Control logic circuitry 120 is a hardware component controlling various coupled components (e.g., components 110, 120, and 130) within memory device 100. In some embodiments, control logic circuitry 120 includes a BL controller (not depicted herein), wherein the BL controller may further include a holder circuitry 140 and a precharge circuitry (not depicted herein). In various embodiments, the precharge circuitry may precharge the BL to a high logic state (e.g., VDD) using a precharge signal during a phase when memory array 101 is not being read or written; the holder circuitry 140 may maintain the voltage level present on the BL at an assumed voltage level when reading memory array 101 by supplying holder current.

[0062] Generally, memory bits in a memory array can be coupled to a hold circuit that helps to "hold" a bit line charged to a voltage level when the bit line is falsely charged to that voltage level. For example, when a logic 0 is read from a memory cell, the hold circuit can maintain a voltage level on the bit line coupled to the memory cell that is substantially close to the voltage level corresponding to logic 0; when a logic 1 is read from a memory cell, the hold circuit can maintain a voltage level on the bit line coupled to the memory cell that is substantially close to the voltage level corresponding to logic 1. In existing memory technologies, implementing such a hold circuit typically involves series coupling of a large number of PMOS transistors, which can adversely lead to an increase in device area or footprint.

[0063] Figure 8B depicts an example layout of the holder circuit 140 according to Figure 8A. The holder circuit 140 includes a plurality of PMOS transistors, including PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, and PMOS6 connected in series and provided on the active region OD1 (e.g., active region 12A). Each of PMOS1 to PMOS6 includes a channel region CR (e.g., nanostructure 13A) of OD1, which engages with active gate structures AG2, AG3, AG4, AG5, AG6, and AG7, respectively, and a pair of source / drain features SD (e.g., source / drain feature 14A) disposed in OD1 and spanning the sidewalls of each active gate structure AG.

[0064] The retainer circuit 140 depicted in Figure 8B has a length L1 along a first lateral direction, wherein the length L1 is defined by seven CPPs. The active region OD1 has a width WP along a second lateral direction. The retainer circuit 140 further includes gate isolation structures CMG1 and CMG2 extending along the first lateral direction and abutting the opposite ends of each active gate structure AG. Each of the gate isolation structures CMG1 and CMG2 includes only a horizontal portion extending along the first lateral direction (e.g., the first portion 50A of gate isolation structure 50) and does not include any lateral portion (e.g., the second portion 50B of gate isolation structure 50). The gate isolation structures CMG1 and CMG2 (and the gate isolation structures described below) may be substantially similar or identical in composition to the gate isolation structures 50, 52, 60, 62, and 64 described herein. Furthermore, the retainer circuit 140 may include a plurality of source / drain contacts MD1, MD2, MD3, MD4, MD5, MD6, and MD7, each contact being electrically coupled to one of the source / drain characteristics SD and inserted between two adjacent active gate structures AG.

[0065] To operate the holder circuit 140, according to the mathematical expression of Equation I, a plurality of PMOS transistors PMOS1 to PMOS6 are connected in series to increase the length L1, resulting in a low current through the PMOS transistors PMOS1 to PMOS6. However, this also increases the area occupied by the holder circuit 140 (i.e., the device footprint). To reduce the device area without significantly affecting device performance, an improved holder circuit 140' is provided with reference to Figure 8C. In this regard, by utilizing the two-dimensional gate isolation structure described herein, the circuit current Id (e.g., leakage current) can be reduced (or kept to a minimum) without increasing the number of PMOS transistors coupled in the circuit.

[0066] Figure 8C depicts an example layout of an improved hold circuit 140', which is operationally equivalent to the hold circuit 140 depicted in Figure 8B, but has the advantage of saving area. Compared to the structure of the hold circuit 140, the improved hold circuit 140' includes gate isolation structures CMG3 and CMG4, each gate isolation structure having a horizontal portion and at least one lateral portion extending from the horizontal portion toward the source / drain feature SD. For example, the gate isolation structure CMG3 includes a horizontal portion CMG3_A, a first lateral portion CMG3_B, and a second lateral portion CMG3_C. The lateral portions CMG3_B and CMG3_C each truncate or replace a portion of the source / drain feature SD, thereby reducing the width WP of the active region OD1 to widths WP1 and WP2, respectively. Similarly, the gate isolation structure CMG4 includes a horizontal portion CMG4_A and a lateral portion CMG4_B, such that the lateral portion CMG4_B also reduces the width WP to the width WP3 as shown herein. By applying expressions similar to any of Equations III to IX, the adjustment current Id_adj of the improved holder circuit 140' (which is less than the current Id of the holder circuit 140) can be determined according to the following Equation X, based on the resistance contribution (cmg7) of the first lateral portion CMG3_B of the gate isolation structure CMG3 to the source / drain characteristic SD of transistor PMOS1, the resistance contribution (cmg8) of the second lateral portion CMG3_C of the gate isolation structure CMG3 to the source / drain characteristic SD of transistor PMOS2, and the resistance contribution (cmg9) of the lateral portion CMG4_B of the gate isolation structure CMG4 to the source / drain characteristic SD of transistor PMOS1: (X), Among them, the resistance RD_cmg7 increases as the width WP2 decreases, the resistance RS_cmg8 increases as the width WP3 decreases, and the resistance RS_cmg9 increases as the width WP1 decreases.

[0067] Advantageously, by using the lateral portions of the gate isolation structures CMG3 and / or CMG4 to reduce the width of the active region OD1, the number of PMOS transistors in the improved hold circuit 140 can be reduced, for example, from six PMOS transistors to two PMOS transistors. This results in a reduction in the length of the circuit structure, for example, from the length L1 of 7 CPPs to the length L2 of 3 CPPs, as shown in Figure 8C, thus providing an area saving benefit. In various embodiments, the degree of area reduction occupied by the improved hold circuit 140 depends on the values ​​of the widths WP1, WP2, and WP3, which may have the same or different values ​​and can be independently adjusted by configuring the gate isolation structures CMP3 and CMP4. In some instances, the widths WP1, WP2, and WP3 may each be greater than 0 and less than the width WP.

[0068] In another example, referring to Figures 9A, 9B, 9C, 9D, and 9E, an embodiment of a portion 150 (hereinafter referred to as portion 150) of the peripheral circuitry of a memory device is provided. Figure 9A depicts an example circuit diagram of portion 150, and Figure 9B depicts a layout example of portion 150 according to Figure 9A. In some embodiments, referring together to Figures 9A and 9B, portion 150 includes different device regions over which PMOS transistors (such as PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, PMOS6, and PMOS7) are configured with different dimensions (relative to the active region), and therefore have different current output capabilities. In some examples, PMOS1 and PMOS2 are cross-coupled PMOS transistors to provide lower current output than PMOS3 to PMOS7. In some examples, PMOS3 and PMOS4 are used to control signals provided to data lines DL and DLB. In some instances, PMOS4 and PMOS5 are configured as the pre-charge circuit of this section 150.

[0069] Specifically, in the depicted embodiment, PMOS1 and PMOS2 are cross-coupled and provided in the first region R1 of the portion 150, and PMOS3 to PMOS7 are series-coupled and provided in the second region R2 of the portion 150. Referring to Figure 9B, the first region R1 and the second region R2 are separated by a third region R3 along a first lateral direction, wherein the third region R3 is considered a dummy region or inactive region that substantially has no active region OD, and generally needs to comply with specific design rules. Adjacent regions of the portion 150 are separated by active region isolation structures DG1, DG2, DG3, and DG4, each active region isolation structure extending along a second lateral direction and spaced apart from each other along the first lateral direction. The active region isolation structures DG1 to DG4 (and any additional active region isolation structures described below) may include any suitable dielectric material, such as silicon oxide, silicon nitride, other suitable materials, or combinations thereof. For simplicity, certain components in this section 150, such as the source / drain contacts of various PMOS transistors, are omitted in Figures 9A to 9E.

[0070] The first region R1 includes a first active region OD3 and a second active region OD4, each active region extending along a first lateral direction and spaced apart from each other along a second lateral direction. Each of PMOS1 and PMOS2 includes a channel region CR (e.g., nanostructure 13A) of its individual OD, which engages with active gate structures AG11 and AG12 respectively, and a pair of source / drain features SD (e.g., source / drain feature 14A) disposed in the individual active region OD and spanning the sidewalls of the individual active gate structure AG. Each of the active regions OD3 and OD4 has a width WP4 along the second lateral direction.

[0071] The second region R2 includes a third active region OD5 extending along a first lateral direction and spaced apart from each of the active regions OD3 and OD4 along the first lateral direction. Each of PMOS3 to PMOS7 includes a channel region CR (e.g., nanostructure 13A) of the third active region OD5, which engages with active gate structures AG15, AG16, AG17, AG18, and AG19, respectively, and a pair of source / drain features SD (e.g., source / drain feature 14A) disposed in the third active region OD5 and spanning the sidewalls of the individual active gate structures AG. The third active region OD5 has a width WP5 along a second lateral direction, wherein the width WP5 is greater than the width WP4.

[0072] Part 150 includes gate isolation structures CMG5 and CMG7, which extend along a first lateral direction and cross regions R1-R3, abutting the opposite ends of each active gate structure AG. Part 150 further includes an additional isolation structure CMG6 disposed along a second lateral direction between active regions OD3 and OD4. Each of the gate isolation structures CMG5-CMG7 includes only a horizontal portion extending along the first lateral direction (e.g., the first portion 50A of gate isolation structure 50), and does not include any lateral portion (e.g., the second portion 50B of gate isolation structure 50).

[0073] To isolate various PMOS transistors with different active region dimensions and maintain a certain device density according to design rules, a third region R3 is included in section 150, above which are additional active gate structures AG13 and AG14 (although no active devices are formed) and active region isolation structures DG2 and DG3 disposed above it, thereby increasing the area or footprint of section 150. In some instances, as depicted in Figure 9B, the area occupied by section 150 is defined by a minimum length L3 of 12 CPPs.

[0074] To reduce the device area without significantly affecting device performance, an improved portion 150' is provided with reference to Figure 9C. In this regard, by utilizing the two-dimensional gate isolation structure described herein, the circuit current Id can be reduced (or kept to a minimum) without increasing the number of PMOS transistors coupled in the circuit. Specifically, Figure 8C depicts an example layout of the improved portion 150', which is operationally equivalent to portion 150 depicted in Figure 9B, but has the advantage of saving area. In contrast to the structure of portion 150, the improved portion 150' includes a single active region OD6 with a width WP5. Therefore, as shown outside the dashed box, a portion of the active region OD6 is suitable for forming PMOS3 to PMOS7 with the desired functions according to Figures 9A and 9B.

[0075] To accommodate the cross-coupled PMOS1 and PMOS2 requiring lower current for operation, the modified portion 150' includes gate isolation structures CMG8 and CMG9, each gate isolation structure having a horizontal portion and at least one lateral portion extending from the horizontal portion toward the source / drain characteristic SD. In some embodiments, gate isolation structure CMG8 includes a horizontal portion CMG8_A and a lateral portion CMG8_B, and gate isolation structure CMG9 includes a horizontal portion CMG9_A and a lateral portion CMG9_B. Each horizontal portion extends along a first lateral direction, and each lateral portion extends from the corresponding horizontal portion along a second lateral direction.

[0076] In this respect, the lateral portions CMG8_B and CMG9_B each truncate or replace a portion of the same source / drain feature SD in the active region OD6 shared by PMOS1 and PMOS2, thereby reducing the width WP5 of the active region OD6 to the width WP6. By applying an expression similar to any of Equations III to IX, the adjustment current Id_adj of the modified portion 150' can be determined according to Equation XI, based on the resistance contribution (cmg10) of the lateral portion CMG8_B of the gate isolation structure CMG8 to the shared source / drain feature SD (e.g., shared drain feature) of PMOS1 / PMOS2, and the resistance Rcmg11 of the lateral portion CMG9_B of the gate isolation structure CMG9 to the shared source / drain feature SD (e.g., common drain feature) of PMOS1 / PMOS2: (XI), The resistance RD_cmg10+cmg11 increases as the width WP6 decreases. In this respect, the current Id_adj can be adjusted by adjusting the width WP6, i.e., by adjusting the resistance RD_cmg10+cmg11. In some embodiments, the resistance RD_cmg10+cmg11 can be adjusted by adjusting the length of one or both of the lateral portions CMG8_B and CMG9_B extending into the source / drain characteristics SD, as described in detail above. In this embodiment, the width WP6 is greater than 0 and less than the width WP5.

[0077] In some embodiments, the position of one or more of the lateral portions(s) of the gate isolation structures CMG8 and CMG9 is altered to obtain the adjustment current Id_adj as described above with respect to Figure 9C. For example, referring to Figure 9D, another embodiment of the modified portion 150' includes components substantially similar to those depicted in Figure 9C, except that the lateral portions CMG8_B and CMG9_B are positioned such that they cut off or replace a portion of one of the two distinct source / drain characteristics SD in the active region OD6. The adjustment current Id_adj can be determined based on the resistance introduced by the lateral portions CMG8_B and CMG9_B in a manner similar to that described above with respect to Figure 9C.

[0078] In some embodiments, referring to Figure 9E, another example of the modified portion 150' includes components substantially similar to those depicted in Figure 9C, except that the gate isolation structure CMG8 includes two lateral portions CMG8_B and CMG8_C extending along both sides of the active gate structure AG12, and the gate isolation structure CMG9 includes two lateral portions CMG9_B and CMG9_C extending along both sides of the active gate structure AG11. In this respect, a portion of each of the source / drain characteristics S / D of PMOS1 and PMOS3 in the active region OD6 is replaced by a portion of a corresponding one of the lateral portions CMG8_B, CMG8_C, CMG9_B, and CMG9_C. The adjustment current Id_adj can be determined based on the resistance introduced by the lateral portions CMG8_B, CMG8_C, CMG9_B, and CMG9_C in a manner similar to that described above with respect to Figure 9C.

[0079] Advantageously, by using the lateral portions of the gate isolation structures CMG8 and / or CMG9 to reduce the width of a portion of the active region OD6, PMOS transistors with different functions and output current levels can be formed in the same active region, thereby eliminating the need for a dummy region (e.g., the third region R3). Therefore, the length of the circuit structure is reduced, for example, from the length L3 of 12 CPPs to the length L4 of 8 CPPs, as depicted in Figures 9C to 9E, thus saving area.

[0080] In another example, referring to Figures 10A, 10B, and 10C, an embodiment of a logic circuit 160 (hereinafter referred to as circuit 160) is provided. Figure 10A depicts an example circuit diagram of circuit 160, and Figure 10B depicts an example layout of circuit 160 according to Figure 10A. In some embodiments, circuit 160 represents an inverse OR (NOR) logic circuit.

[0081] Referring together to Figures 10A and 10B, circuit 160 includes at least active regions OD7 and OD8, ​​each extending along a first lateral direction and spaced apart from each other along a second lateral direction. Active region OD7 is formed in an N-well having a width WP7 along the second lateral direction and is used to provide a plurality of PMOS transistors PMOS1 and PMOS2, while active region OD8 is formed in a P-well having a width WN1 along the second lateral direction and is used to provide a plurality of NMOS transistors NMOS1 and NMOS2. Widths WP7 and WN1 may be the same or different. In the depicted embodiment, PMOS1 and PMOS2 are series-coupled, and two pairs of PMOS1 and PMOS2 are parallel-coupled. The PMOS transistors are then coupled to the parallel-coupled NMOS1 and NMOS2.

[0082] Each of PMOS1 and PMOS2 includes a channel region PCR (e.g., nanostructure 13A) in the active region OD7 that engages with active gate structures AG21, AG22, AG23, and AG24, respectively, and a pair of source / drain features PSD (e.g., source / drain features 14A) spanning the sidewalls of the individual active gate structures AG. Each of NMOS1 and NMOS2 includes a channel region NCR (e.g., nanostructure 13A) in the active region OD8 that engages with active gate structures AG21 and AG22, respectively, and a pair of drain / source features NSD (e.g., source / drain regions 14A) spanning the sidewalls of the individual active gate structures AG.

[0083] Referring to Figure 10B, circuit 160 includes gate isolation structures CMG10 and CMG11 extending along a first lateral direction and abutting the opposite ends of each active gate structure AG. Circuit 160 further includes an additional isolation structure CMG12 disposed between active regions OD7 and OD8 along a second lateral direction. Each of the gate isolation structures CMG10 to CMG12 includes only a horizontal portion extending along the first lateral direction (e.g., the first portion 50A of gate isolation structure 50), and does not include any lateral portion (e.g., the second portion 50B of gate isolation structure 50).

[0084] Circuit 160 may include active region isolation structures DG11, DG12, DG13, and DG14, each extending along a second lateral direction and spaced apart from each other along a first lateral direction. Active region isolation structures DG11-DG14 can be used to separate adjacent device regions along the first lateral direction. In the depicted embodiment, active region isolation structures DG12 and DG13 are formed above the active region OD8 and extend from active gate structures AG23 and AG24 along the second lateral direction, respectively. For simplicity, certain components in circuit 160, such as the source / drain contacts of various PMOS and NMOS transistors, are omitted in Figures 10B and 10C.

[0085] For the embodiments depicted in Figures 10A and 10B, multiple pairs of PMOS1 and PMOS2 (two pairs depicted here) are electrically coupled in parallel to achieve a higher Id_pmos, thereby matching the current Id_nmos of NMOS1 and NMOS2. In the depicted embodiments, the current Id_nmos is equivalent to twice the current through each pair of PMOS1 and PMOS2. Therefore, this configuration requires at least four active gate structures AG21~AG24 above the active region OD7, resulting in a circuit length L5 of at least 5 CPPs, and the active region isolation structures DG12 and DG13 occupying additional area that does not contribute to the operation of the active device. Therefore, it may be desirable to reduce the device area without significantly affecting device performance.

[0086] Referring to Figure 10C, an improved circuit 160' is provided. In some embodiments, by utilizing the two-dimensional gate isolation structure described herein, the current Id_nmos of the improved circuit 160' of the NMOS transistors can be reduced without increasing the number of PMOS transistors coupled in the circuit. Specifically, Figure 10C depicts an example layout of the improved circuit 160', which is operationally equivalent to the circuit 160 depicted in Figure 10B, but has the advantage of saving area. The improved circuit 160' includes the same active regions OD7 and OD8, ​​with only one pair of PMOS1 and PMOS2 formed above the active region OD7, a reduction from the two pairs depicted in circuit 160, and NMOS1 and NMOS2 formed above the active region OD8 in the same configuration as in circuit 160.

[0087] To accommodate the reduced number of series-coupled PMOS1 and PMOS2, which corresponds to the lower current required for the operation of parallel-coupled NMOS1 and NMOS2, the improved circuit 160' includes gate isolation structures CMG13 and CMG14. Each of the gate isolation structures CMG13 and CMG14 includes a horizontal portion, wherein the gate isolation structure CMG14 also includes a lateral portion extending from the horizontal portion toward the source / drain characteristic NSD. In some embodiments, the gate isolation structure CMG14 includes a horizontal portion CMG14_A and a lateral portion CMG14_B, and the gate isolation structure CMG13 includes a horizontal portion CMG13_A. Each horizontal portion extends from its corresponding horizontal portion along a first lateral direction, and each lateral portion extends along a second lateral direction.

[0088] In this respect, the lateral portion CMG14_B truncates or replaces a portion of the common source / drain characteristic NSD between NMOS1 and NMOS2 in the active region OD8, ​​thereby reducing the width WN1 of the active region OD8 to the width WN2. By applying an expression similar to any of Equations II to IX, the adjustment current Id_adj_nmos of the parallel-coupled NMOS1 and NMOS2 (which is less than the current Id_nmos) can be determined according to Equation XII, based on the resistive contribution (cmg12) of the lateral portion CMG14_B of the gate isolation structure CMG14 to the common source / drain characteristic NSD (e.g., common drain characteristic) of NMOS1 / NMOS2: (XII), The resistance RD_cmg12 increases as the width WN2 decreases. In this respect, the adjustment current Id_adj_nmos can be tuned by adjusting the width WN2, i.e., adjusting the resistance RD_cmg12. In some embodiments, adjusting the resistance RD_cmg12 can be achieved by adjusting the length of the lateral portion CMG14_B extending into the source / drain feature NSD, as described in detail above. In this embodiment, the width WN2 is greater than 0 and less than the width WN1.

[0089] Advantageously, by using the lateral portion of the gate isolation structure CMG14 to reduce the width of a portion of the active region OD8, ​​the width WN2 can be reduced to ½WN1. As described herein, the current through NMOS1 and NMOS2 is reduced by approximately 50%, effectively lowering the required current level provided by the PMOS transistor. In this respect, the number of PMOS1s coupled to the NMOS transistor is correspondingly reduced by approximately 40% from the length L5 of 5 CPPs to the length L6 of 3 CPPs, as shown in Figure 10C, thereby saving area.

[0090] In yet another example, referring to Figures 11A, 11B, and 11C, an embodiment of a logic circuit 170 (hereinafter referred to as circuit 170) is provided. Figure 11A depicts an example circuit diagram of circuit 170, and Figure 11B depicts an example layout of circuit 170 according to Figure 11A. In some embodiments, circuit 170 represents an inverse NAND logic circuit.

[0091] Referring to Figure 11B, circuit 170 is similar to circuit 160, except that circuit 170 includes a pair of parallel-coupled PMOS1 and PMOS2 formed above the active region OD7 and coupled to the pair of series-coupled NMOS1 and NMOS2 formed above the active region OD8, ​​instead of having two pairs of series-coupled PMOS1 and PMOS2 formed above the pair of parallel-coupled NMOS1 and NMOS2 formed above the active region OD7 and coupled to the pair of parallel-coupled NMOS1 and NMOS2 formed above the active region OD8. In this respect, active region isolation structures DG12 and DG13 are formed above the active region OD7, and active gate structures AG23 and AG24 are formed above the active region OD8, ​​thereby forming a second pair of series-coupled NMOS1 and NMOS2.

[0092] For the embodiments depicted in Figures 11A and 11B, two pairs of NMOS1 and NMOS2 are electrically coupled in parallel to achieve a higher Id_nmos, thereby matching the current Id_pmos of PMOS1 and PMOS2. In the depicted embodiments, the current Id_pmos is equivalent to twice the current through each pair of NMOS1 and NMOS2. Therefore, this configuration requires at least four active gate structures AG21~AG24 above the active region OD8, ​​resulting in a circuit length L7 of at least 5 CPPs. The active region isolation structures DG12 and DG13 occupy additional area and do not contribute to the operation of the active device. Therefore, it may be desirable to reduce the device area without significantly affecting device performance.

[0093] Referring to Figure 11C, an example layout of the modified circuit 170' is provided. In some embodiments, the modified circuit 170' is operationally equivalent to the circuit 170 depicted in Figure 11B, but has the advantage of saving area, similar to the embodiments depicted in Figures 10A to 10C. For example, the modified circuit 170' includes the same active regions OD7 and OD8, ​​wherein only one pair of NMOS1 and NMOS2 is formed above the active region OD8, ​​which is a reduction of the two pairs depicted in circuit 170, and PMOS1 and PMOS2 are formed above the active region OD7 in the same configuration as in circuit 170.

[0094] To accommodate the inclusion of only one pair of series-coupled NMOS1 and NMOS2, corresponding to the lower current required for the operation of parallel-coupled PMOS1 and PMOS2, the improved circuit 170' includes gate isolation structures CMG15 and CMG16, each gate isolation structure having a horizontal portion, wherein gate isolation structure CMG15 also includes a lateral portion extending from the horizontal portion toward the source / drain characteristic NSD. In some embodiments, gate isolation structure CMG15 includes a horizontal portion CMG15_A and a lateral portion CMG15_B, and gate isolation structure CMG16 includes a horizontal portion CMG16_A. Each horizontal portion extends from its corresponding horizontal portion along a first lateral direction, and each lateral portion extends from its corresponding horizontal portion along a second lateral direction.

[0095] In this respect, the lateral portion CMG15_B truncates or replaces a portion of the common source / drain feature PSD in the active region OD7 between PMOS1 and PMOS2, thereby reducing the width WP7 of the active region OD7 to the width WP9. By applying an expression similar to any of Equations III to VI, the adjustment current Id_adj_pmos of the parallel-coupled PMOS1 and PMOS2 (which is less than the current Id_pmos) can be determined according to Equation XIII, based on the resistive contribution (cmg13) of the lateral portion CMG15_B of the gate isolation structure CMG15 to the common source / drain feature PSD (e.g., the common drain feature): (XIII), The resistance RD_cmg13 increases as the width WP9 decreases. In this respect, the adjustment current Id_adj_pmos can be tuned by adjusting the width WP9, i.e., adjusting the resistance RD_cmg13. Similar to the embodiments depicted in Figures 10A to 10C, adjusting the resistance RD_cmg13 can be achieved by adjusting the length of the lateral portion CMG15_B extending into the source / drain feature PSD, as described in detail above. In this embodiment, the width WP9 is greater than 0 and less than the width WP7.

[0096] Advantageously, by using the lateral portion of the gate isolation structure CMG15 to reduce the width of a portion of the active region OD7, the current through PMOS1 and PMOS2 is reduced by approximately 50%, effectively lowering the required current level provided by the NMOS transistor. In this respect, the number of NMOS1 transistors that need to be coupled to the PMOS transistor is correspondingly reduced by approximately 40%, for example, as shown in Figure 11C, from the length L7 of 5 CPPs to the length L8 of 3 CPPs, thereby saving area.

[0097] In yet another example, this disclosure provides methods for tuning the rise or fall slope of different MOS transistors in various applications. For instance, by reducing the current through an NMOS transistor, the rise slope of the NMOS transistor can be improved, which is related to the rate at which the current rises (e.g., reaching a set level). Similarly, by reducing the current through a PMOS transistor, the fall slope of an NMOS transistor can be improved, which is related to the rate at which the current falls (e.g., falling to a set level).

[0098] Figure 12 illustrates a three-dimensional perspective view of an example semiconductor device 1000 according to various embodiments. Device 1000 may be similar to any of the MOS devices depicted in Figures 1A through 11C. Semiconductor device 1100 includes a substrate 1102 and fins 1104 (optionally referred to as fin structure 1104 or active region 1104) projecting from the substrate 1102 along a vertical direction (e.g., the Z-axis). In some embodiments, fins 1104 comprise a single layer of semiconductor material. In some embodiments, fins 1104 comprise a plurality of semiconductor layers (e.g., nanosheets, nanorods, etc.) stacked along a vertical direction. Isolation regions 1106 are formed on opposite sides of fins 1104, with fins 1104 projecting over isolation regions 1106. A gate dielectric layer 1108 runs along the sidewalls of fins 1104 and above their top surface, and a gate electrode layer 1110 is above the gate dielectric layer 1108, together forming a gate structure. In some embodiments, the lower portion of the gate structure is staggered (i.e., arranged in an alternating pattern) with a plurality of semiconductor layers along a vertical direction, such that the semiconductor device 1000 presents as a multi-gate device, such as a GAA device. Source features 1112S and drain features 1112D (collectively referred to as source / drain features 1112S / D) are in (or extend from) the fin 1104 and on opposite sides of the gate structure. Figure 12 is provided for reference to illustrate numerous cross-sections of a similar semiconductor device 300 (hereinafter referred to as device 300) in subsequent figures. For example, a cross-sectional view taken along line X-X' is along the longitudinal axis of the fin 1104 and in the current direction, for example, between the source / drain features 1112S / D. A cross-sectional view taken along line Y-Y' is perpendicular to cross-section X-X' and along the longitudinal axis of the gate structure, which includes the gate dielectric layer 1108 and the gate electrode layer 1110. These reference cross-sections are referenced in subsequent figures for clarity.

[0099] Figure 13 illustrates a flowchart of an example method 200 for manufacturing apparatus 300 according to some embodiments. It should be noted that method 200 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that additional steps / operations may be provided before, during, and after method 200 of Figure 13, and only a few other operations may be briefly described herein. The various manufacturing stages of method 200 can be associated with cross-sectional views of apparatus 300 taken along a line equivalent to line X-X' in Figure 12 (see Figures 14 and 17 through 19), cross-sectional views of apparatus 300 taken along a line equivalent to line Y-Y' in Figure 12 (see Figures 15 and 16), and a top view of apparatus 300 (see Figure 20), which will be described in further detail below.

[0100] Briefly, referring to Figure 13, according to some embodiments, the device 300 can be formed by performing operations 202 to 222. For example, method 200 begins at operation 202, providing a substrate overlaid on a multilayer stack of alternating first and second semiconductor layers. Method 200 continues to operation 204, forming a fin structure protruding from the substrate and extending along a first lateral direction in the multilayer stack. Method 200 continues to operation 206, forming an isolation structure above the substrate and adjacent to the fin structure. Method 200 continues to operation 208, forming a dummy gate structure extending along a second lateral direction above the fin structure. Next, method 200 proceeds to operation 210, forming source / drain recesses adjacent to each dummy gate structure. Method 200 continues to operation 212, forming source / drain features to fill the source / drain recesses. Method 200 continues to operation 214, removing the dummy gate structures. Next, method 200 proceeds to operation 216, removing the first semiconductor layer. Method 200 then proceeds to operation 218, forming an active gate structure to replace the dummy gate structure and the first semiconductor layer. Method 200 then proceeds to operation 220, forming a gate isolation structure including a first portion extending along a first lateral direction and a second portion extending along a second lateral direction, wherein the second portion partially replaces one of the source / drain features. Method 200 then proceeds to operation 222, performing any additional operations to complete the fabrication of device 300.

[0101] Referring to Figures 13 and 14, at operation 202, a substrate 302 is provided in device 300. In some embodiments, substrate 302 is substantially similar to or identical to substrate 8 described herein. Substrate 302 is covered with a multilayer structure (ML) of alternating first semiconductor layers 304 and second semiconductor layers 306. In other words, the first semiconductor layers 304 and second semiconductor layers 306 are stacked alternately as MLs on the top surface of substrate 302. It should be understood that device 300 may include any number of first semiconductor layers 304 and any number of second semiconductor layers 306 (used as channel layers), either of which is the top layer, while still within the scope of this disclosure.

[0102] Semiconductor layers 304 and 306 have different compositions. In various embodiments, semiconductor layers 304 and 306 have compositions that provide different oxidation rates and / or different etch selectivity between the layers. In this embodiment, the first semiconductor layer 304 comprises silicon germanium (Si1-xGex), and the second semiconductor layer 306 comprises silicon (Si). In some embodiments, the second semiconductor layer 306 is substantially similar to or identical to the nanostructure 13A (or 13B) described herein. The first semiconductor layer 304 may comprise other materials, for example, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; any other suitable materials, or combinations thereof.

[0103] Semiconductor layers 304 and 306 may have different thicknesses. The first semiconductor layer 304 may have different thicknesses from one layer to another. The second semiconductor layer 306 may have different thicknesses from one layer to another. The first layer of ML may be thicker than the other semiconductor layers 304 and 306. The first semiconductor layer 304 or the second semiconductor layer 306 may be the top layer (or the layer furthest from the substrate 302). In an embodiment, the first semiconductor layer 304 may be the bottom layer of ML (or the layer closest to the substrate 302).

[0104] Semiconductor layers 304 and 306 can be grown from substrate 302. For example, each of semiconductor layers 304 and 306 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD, MOCVD), and / or other suitable growth processes. During epitaxial growth, the crystal structure of substrate 302 extends upward, resulting in semiconductor layers 304 and 306 having the same crystal orientation as substrate 302.

[0105] Referring to Figures 13 and 15, at operation 204, fin structures 400A, 400B, and 400C (collectively referred to as fin structures 400, fins 400, or active areas 400) are formed in ML. Each of the fin structures 400 extends along a first lateral direction (e.g., the X-axis) and is spaced apart from each other along a second lateral direction perpendicular to the first lateral direction (e.g., the Y-axis). It should be understood that the device 300 may include any suitable number of fin structures 400, while still remaining within the scope of this disclosure.

[0106] The fin structure 400 is formed by patterning the top of the semiconductor layers 304 and 306 (ML) and the substrate 302 using techniques such as optical lithography and etching. For example, a mask layer (which may include multiple layers, such as, for example, a pad oxide layer and an overlying pad nitride layer; not depicted) is formed over the top surface of the ML. For example, the pad oxide and pad nitride can be formed using thermal oxidation, CVD, low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). The mask layer can then be patterned using optical lithography. Generally, optical lithography uses a photoresist material (not shown) deposited, exposed, and developed via an optical lithography mask to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, photoresist material is used to pattern the pad oxide layer and the pad nitride layer to form a patterned mask. After the patterned mask layer, the photoresist material can be removed by suitable methods, such as plasma ashing or resist stripping.

[0107] The exposed portions of semiconductor layers 304 and 306 and substrate 302 are then patterned using a patterned mask to form trenches (or openings) 410, thereby defining fin structures 400 between adjacent trenches 410. The trenches 410 extend continuously along a first lateral direction. When multiple fin structures 400 are formed, this trench 410 can be disposed between any adjacent fin structures. In some embodiments, the fin structures 400 are formed by etching the trenches 410 in semiconductor layers 304 and 306 and substrate 302 using, for example, a dry etching process (e.g., reactive ion etching (RIE), neutral beam etching (NBE), other suitable processes, or combinations thereof). The etching process can be anisotropic.

[0108] Referring to Figures 13 and 16, an isolation structure 504 (also referred to as isolation region 505) is formed at operation 206. The isolation structure 504 may be formed between adjacent fin structures 400 and partially embedded in or surrounding the lower portion of adjacent fin structures 400. In some embodiments, the isolation structure 504 is used to electrically isolate adjacent active structures (e.g., adjacent stacks of adjacent fin structures or nanostructure channel layers) from each other. The isolation structure 504 may include oxides such as silicon oxide, nitrides, low-k dielectric materials (e.g., dielectric materials with a dielectric constant less than that of silicon oxide (which is approximately 3.9), such as silicon phosphate glass (PSG), borosilicate glass (BSG), borosilicate silica glass (BPSG), silica-free glass (USG), other suitable materials, or combinations thereof.

[0109] The isolation structure 504 can be formed by first depositing an insulating material using any suitable process, such as high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition processes in remote plasma systems followed by curing to transform it into another material, such as oxides), other suitable processes, or combinations thereof. Once the insulating material is formed, an annealing process can be performed. A planarization process, such as chemical mechanical polishing (CMP) or any other suitable process, can be performed to remove any excess insulating material to expose the top surface of the fin structure 400 or a patterned mask (if present). In some other embodiments, the patterned mask can be removed by a planarization process. Subsequently, the insulating material is recessed to form the isolation structure 504, which is sometimes referred to as shallow-trench isolation (STI). The isolation structure 504 is recessed, causing the fin structure 400 to protrude from between adjacent isolation structures 504. The isolation structure 504 may be recessed to a position where its top surface is below the substrate 302. The isolation structure 504 may be recessed using a suitable etching process, such as an etching process selective for the material of the isolation structure 504. For example, a dry etching process or a wet etching process using dilute hydrofluoric acid (dHF) may be performed to recess the isolation structure 504.

[0110] Referring to Figures 13 and 17, at operation 208, dummy gate structures 600A, 600B, and 600C (collectively referred to as dummy gate structures 600) are formed above the fin structure 400. Each of the dummy gate structures 600 extends along a second lateral direction and is spaced apart along a first lateral direction. In this respect, the dummy gate structures 600 are generally disposed perpendicular to the fin structure 400. In this embodiment, the dummy gate structures 600 are positioned at locations where movable (e.g., metallic) gate structures can be later formed. It should be understood that the device 300 may include any suitable number of dummy gate structures 600, while still remaining within the scope of this disclosure.

[0111] In some embodiments, forming the dummy gate structure 600 includes depositing an etch stop layer (not depicted) over the top surface of the fin structure 400, wherein the etch stop layer serves to protect the underlying fin structure 400 and may include silicon oxide or any other suitable material. Next, a dummy gate electrode layer 602 comprising, for example, polysilicon is deposited as a blanket layer over the etch stop layer. In some embodiments, a hard mask 604 is deposited over the dummy gate electrode layer 602 and subsequently patterned using the optical lithography process described herein. The dummy gate electrode layer 602 is then patterned using the patterned hard mask 604 as an etch mask to form the dummy gate structure 600.

[0112] In some embodiments, although not depicted, each of the dummy gate structures 600 further includes a dummy gate dielectric layer (not shown) disposed between the etch stop layer and the dummy gate electrode layer. The dummy gate dielectric layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, multilayers thereof, other suitable dielectric materials, or combinations thereof, and may be formed by thermal oxidation, chemical oxidation, CVD, ALD, other suitable methods, or combinations thereof.

[0113] Referring again to Figures 13 and 18, gate spacers 702 are formed on the opposing sidewalls of each dummy gate structure 600. Gate spacers 702 (or top gate spacers 702) may comprise any suitable dielectric material disposed above one or more spacer layers of each dummy gate structure 600. In some embodiments, gate spacers 702 are substantially similar to or identical to gate spacers 17 described herein. Gate spacers 702 (or their respective spacer layers) may be formed by first conformally depositing one or more dielectric materials above the dummy gate structure 600. Any suitable deposition method, such as thermal oxidation, chemical oxidation, CVD, ALD, other suitable methods, or combinations thereof, may be used to deposit the dielectric material. Subsequently, suitable etching processes (such as anisotropic dry etching processes) may be used to etch the dielectric material(s) to form gate spacers 702 along the opposing sidewalls of the dummy gate structure 600.

[0114] Referring to Figures 13 and 18, at operation 210, portions of each fin structure 400 are removed from the device 300 to form source / drain recesses 706. Each source / drain recess 706 is inserted between two adjacent dummy gate structures 600 along a first lateral direction, thereby providing space for the subsequent formation of corresponding source / drain features. In various embodiments, the source / drain recesses 706 are formed by performing an etching process (such as an anisotropic etching process) to remove the portions of the ML inserted between the dummy gate structures. The etching process can selectively remove material from the ML and the substrate, and can be implemented using the dummy gate structures as etching masks.

[0115] Subsequently, referring to Figures 13, 18, and 19, source / drain features 802 are formed in the source / drain recess 706 above an internal spacer 704, the internal spacer being formed by replacing the end portions of each of the first semiconductor layers 304 exposed in the source / drain recess 706 at operation 212. The internal spacer 704 (or bottom gate spacer 704) may comprise any suitable dielectric material disposed in one or more spacer layers. In some embodiments, the internal spacer 704 is substantially similar to or identical to the internal spacer 11 described herein.

[0116] In some embodiments, referring to Figures 13 and 18, forming the internal spacer 704 includes performing an etching process (or etch-back process) to selectively remove the end portions of the first semiconductor layer 304 without removing or substantially removing the second semiconductor layer 306. In some embodiments, the etch-back process is performed until a desired etch-back distance is achieved, thereby aligning the etched first semiconductor layer 304 with the dummy gate structure 600 (i.e., the dummy gate electrode layer 602). Subsequently, the internal spacer 704 is formed over the etched end portions of the first semiconductor layer 304 in the source / drain recess 706. The internal spacer 704 may be formed by depositing one or more layers of dielectric material as described herein using any suitable method, such as CVD, ALD, physical vapor deposition (PVD), other suitable methods, or combinations thereof. Next, the dielectric material can be etched using a suitable etching process (e.g., anisotropic dry etching process) to remove excess dielectric material from the sidewalls of the second semiconductor layer 306, the gate spacer 702, and the top surface of the substrate 302.

[0117] Subsequently, referring to Figures 13 and 19, a source / drain feature 802 is formed in a source / drain recess 706 above the internal spacer 704. In some embodiments, the source / drain feature 802 is substantially similar to or identical to the source / drain feature 14A (or 14B) described herein. In some embodiments, the sidewalls of the source / drain feature 802 are aligned vertically with the sidewalls of the internal spacer 704 and the second semiconductor layer 306. The source / drain feature 802 can be formed on each of the second semiconductor layer 306 and on the exposed ends of the exposed substrate 302 using an epitaxial layer growth process. For example, the growth process may include selective epitaxial growth (SEG), CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial processes, or combinations thereof. In some embodiments, the bottom surface of the source / drain feature 802 is lower than the top surface of the isolation structure 504. In some embodiments, dopants are introduced in situ during the growth process. Alternatively, an implantation process may be performed after the growth process to introduce dopants. After the source / drain feature 802 is formed, an annealing process is performed to activate the dopants.

[0118] In some embodiments, as shown in Figures 1B and 19, for example, the bottom portion of each source / drain recess is formed below the top surface of the substrate 302, such that the bottommost portion of each of the source / drain features 802 is embedded in the substrate 302. In some embodiments, referring to Figure 19, a bottom isolation layer 804 is formed at the bottom portion of each of the source / drain recesses 706 before the formation of the corresponding source / drain feature 802. In some embodiments, the bottom isolation layer 804 is substantially similar to or the same as the bottom isolation layer 15 described herein. The bottom isolation layer 804 may be formed by depositing a dielectric material in the source / drain recess 706 by any suitable process (such as CVD, ALD, other processes, or combinations thereof). Subsequently, the dielectric material is etched back to expose the top portion of the source / drain recess 706, thereby leaving the bottom isolation layer 804 on the bottom portion of the source / drain recess 706. The dielectric material can be etched using any suitable process, such as dry etching, wet etching, or a combination thereof. The etching process can be controlled to ensure that a sufficient amount of bottom isolation layer 804 remains in the source / drain recess 706 before the source / drain feature 802 is formed. In some embodiments, the bottom isolation layer 804 is used to reduce or prevent current leakage between the bottom portions of adjacent source / drain features 802. In some embodiments, the bottom isolation layer 804 is omitted from the device 300.

[0119] Referring to Figures 13 and 19, at operation 214, a dummy gate structure 600 is removed from device 300 to form a gate trench (not depicted). Replacing the dummy gate structure 600 involves first forming an ILD layer 806 over the source / drain feature 802. In some embodiments, the ILD layer 806 is substantially similar to or identical to the ILD layer 19 described herein. The ILD layer 806 may be deposited by any suitable method, such as CVD, PECVD, FCVD, other suitable methods, or combinations thereof. Next, a planarization process, such as CMP, may be performed to achieve a flush top surface of the ILD layer 806. CMP may also remove the patterned hard mask 604. After performing the planarization process, the top surface of the ILD layer 806 may be substantially flush with or coplanar with the top surface of the dummy gate structure 600.

[0120] The dummy gate structure 600 can then be removed by performing an etching process, such as a dry etching process, a wet etching process, other suitable processes, or a combination thereof. In various embodiments, an etchant is used to perform the etching process to remove the dummy gate electrode layer 602, including the polysilicon layer, for example, without removing or substantially removing other components of the device 300, such as the gate spacer 702 and the topmost second semiconductor layer 306.

[0121] Subsequently, at operation 216, the first semiconductor layer 304 exposed by the gate trench is selectively removed to form openings (not depicted), each opening inserted between pairs of internal spacers 704 in a first lateral direction and between the second semiconductor layers 306 in a vertical direction. The first semiconductor layer 304 can be removed by a wet etching process or a dry etching process. In some embodiments, after the etching process is performed, the second semiconductor layer 306, the internal spacers 704, and the gate spacers 702 (or at least a portion thereof) remain substantially intact. In this respect, the top and bottom surfaces of the second semiconductor layer 306 are exposed in the openings.

[0122] Subsequently, still referring to Figures 13 and 19, at operation 218, a movable gate structure 900 is formed in the gate trench and opening. In this embodiment, the top portions of the movable gate structures 900A, 900B, and 900C (collectively referred to as movable gate structure 900) are formed in the gate trench. Furthermore, the bottom portions of the movable gate structures 900 are formed in the openings below the corresponding top portions and between the internal spacers 704, such that each bottom portion covers the stack surrounding the corresponding second semiconductor layer 306. In other words, each bottom portion of the movable gate structure 900 is staggered with the second semiconductor layer 306. In some embodiments, the movable gate structure 900 is substantially similar to or identical to the movable gate structure 16 described herein.

[0123] The gate dielectric layer can be deposited using conformal processes such as ALD, CVD, other suitable processes, or combinations thereof. Various layers of the gate metal can be deposited using any suitable method such as ALD, CVD, PVD, electroless plating, electroplating, other suitable methods, or combinations thereof. Subsequently, the deposited gate dielectric layer and gate metal are planarized using a suitable process (such as CMP), thereby exposing the top surface of the ILD layer 806.

[0124] Referring to Figures 13 and 20, at operation 220, gate isolation structures 920 and 922 are formed above the active gate structure 900. Although two gate isolation structures 920 and 922 are depicted in Figure 20, the device 300 may include any suitable number of gate isolation structures similar to gate isolation structure 920 or gate isolation structure 922. It should be further noted that, for simplicity, certain parts of the device 300, such as the ILD layer 806 and the gate spacer 702, are omitted in the top view depicted in Figure 20.

[0125] In some embodiments, gate isolation structures 920 and 922 are substantially similar to or identical to gate isolation structures 50 and 52 (or gate isolation structures 60 and 64), respectively. For example, at least one of the gate isolation structures of device 300, such as gate isolation structure 920, includes a first portion 920A (or horizontal portion 920A) and a second portion 920B (or transverse portion 920B) extending from the first portion 920A along a second lateral direction. The first portion 920A generally extends along a first lateral direction and parallel to the fin 400. In this embodiment, the first portion 920A is disposed between two adjacent fins 400, one of which is depicted in Figure 20. The second portion 920B generally extends from the first portion 920A toward the fin 400 along a second lateral direction, thereby intersecting with one of the source / drain features 802. Thus, the second portion 920B is generally perpendicular to the first portion 920A. In the depicted embodiment, the second portion 920B is disposed between two adjacent active gate structures 900. As depicted in Figure 20, the gate isolation structure 922 includes only the first or horizontal portion 922A and does not include any second or lateral portion.

[0126] In some embodiments, the second portion 920B partially penetrates the source / drain feature 802, such that the end portion of the second portion 920B is surrounded by a portion of the source / drain feature 802. In other words, similar to the embodiments of the second portion 50B of the gate isolation structure 50 depicted in Figures 1A to 1C, the end portion of the second portion 920B replaces a portion of the source / drain feature 802. In this respect, by the penetration of the second portion 920B, the width W13 of the fin 400 along the second lateral direction is reduced to a width W14, where the width W14 is greater than 0 but less than the width W13. In other words, the second portion 920B does not completely truncate or replace the source / drain feature 802 along the second lateral direction. In some embodiments, the portion of the second portion 920B that penetrates the fin 400 may be defined by a length Lcmg14, the value of which determines the degree of reduction in current through the final MOS device formed in the fin 400.

[0127] In some embodiments, forming gate isolation structures 920 and 922 at operation 220 includes patterning device 300 to form a first trench (not depicted; corresponding to first portions 920A and 922A) and at least one second trench (not depicted; corresponding to second portion 920B) extending from one of the first trenches toward fin 400. Each of the first trenches extends along a first lateral direction and over the active gate structure 900, thereby truncating or separating the active gate structure 900 into portions along a second lateral direction. The second trench extends along a second direction and is inserted along the first lateral direction between two adjacent active gate structures 900 (e.g., active gate structures 900B and 900C). In some embodiments, the second trench is equidistant from each of the two active gate structures 900. In some embodiments, forming the first and second trenches includes performing a series of optical lithography and etching techniques described herein. Specifically, after forming a patterned mask layer (not shown) above device 300 and using the patterned mask as an etching mask, at least a portion of the active gate structure 900, gate spacer 702, and ILD layer 806 is removed or etched (e.g., by dry or wet etching processes) to form a first trench, and at least a portion of either the ILD layer 806 or the source / drain feature 802 is removed to form a second trench. In this embodiment, the source / drain feature 802 is only partially removed or etched, such that the remaining portion of the source / drain feature 802 has a width W14 along the second lateral direction. In this embodiment, the second trench is formed simultaneously with the first trench, i.e., patterned using the same photomask and the same etching process.

[0128] Subsequently, a dielectric layer is deposited over device 300 to fill the first and second trenches. The dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, other suitable materials, or combinations thereof, and may be deposited by any suitable process, such as CVD, FCVD, ALD, other processes, or combinations thereof. A planarization process, such as CMP, may then be performed to planarize the top surfaces of the resulting gate isolation structures 920 and 922 and the top surface of the active gate structure 900.

[0129] As described in detail herein, forming a gate isolation structure similar to gate isolation structure 920 provides a means to reduce the width of fin 400 without additional manufacturing steps (e.g., additional optical lithography processes), thereby reducing the complexity and cost of the overall manufacturing process. Furthermore, reducing the current of the MOS device in this manner provides area-saving benefits for increasing device density at advanced technology nodes.

[0130] Subsequently, referring to Figures 13 and 20, additional operations can be performed at operation 222. For example, referring to Figure 20, source / drain contacts 930A and 930B (collectively referred to as source / drain contacts 930) can be formed to electrically couple components of device 300 (such as source / drain feature 802) to interconnect features formed above device 300. In some embodiments, source / drain contacts 930 are substantially similar to or identical to source / drain contacts 18 described herein. Source / drain contacts 930 can be formed by a series of patterning, etching, deposition, and planarization processes. In some embodiments, the top surface of each of the source / drain contacts 930 is substantially planar with the top surfaces of the active gate structure 900 and the gate isolation structures 920 (and 922). Interconnect features may be formed in individual dielectric layers (e.g., intermetallic dielectric layers) formed above device 300, wherein the interconnect features may include a plurality of vertical interconnect features (e.g., vias) and horizontal interconnect features (e.g., conductive lines). The interconnect features may include any suitable conductive material, such as W, Cu, Co, Ru, Al, Ti, TiN, Ta, TaN, Au, Ag, Pt, other suitable materials, or combinations thereof. The dielectric layer may include any suitable material similar to the components of ILD layer 806.

[0131] Figure 21 is a flowchart of a method 1400 for forming or manufacturing a semiconductor device according to some embodiments, such as any of the following: devices 10A-10G, 300, and 1000; memory device 100; circuits 150, 160, and 170; and modified circuits 150', 160', and 170'. It should be understood that additional operations may be performed before, during, and / or after the method 1400 depicted in Figure 21.

[0132] In operation 1410 of method 1400, a layout design for a semiconductor device is generated. Operation 1410 is performed by a processing device (e.g., processor 1502 of Figure 22) for executing instructions for generating the layout design. In one method, the layout design is generated by placing one or more standard cells via a user interface. In another method, the layout design is automatically generated by a processor executing a synthesis tool that converts a logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is presented in a graphic database system (GDSII) file format. In some embodiments, the layout design includes a layout similar to any of the example layouts depicted in Figures 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8B, 8C, 9B through 9E, 10B, 10C, 11B, and 11C.

[0133] In operation 1420 of method 1400, a semiconductor device is manufactured based on a layout design. In some embodiments, operation 1420 of method 1400 includes manufacturing at least one mask based on a layout design, and manufacturing a semiconductor device based on the at least one mask. The example manufacturing operation of operation 1420 may include patterning, implantation, deposition, etching, planarization, similar operations, or combinations thereof, to form a plurality of front-end device features (e.g., active regions 12A, 12B, OD1, OD3~OD8, and 400; active gate structures 16, AG1~AG8, AG12~AG18, AG21~24, and 600; source / drain features 14A, 14B, SD, PSD, NSD, and 802; gate isolation structures 50, 52, 54, 60, 62, 64, and CMG1~CMG16; active region isolation structures DG1~DG4 and DG11~DG14; etc.), device-level contacts (e.g., source / drain contacts 18 and MD1~MD7), and interconnect features including vias and wires.

[0134] In some embodiments, method 1400 is implemented as a standalone software application executed by a processor. In some embodiments, method 1400 is implemented as a software application as part of an additional software application. In some embodiments, method 1400 is implemented as a plugin for a software application. In some embodiments, method 1400 is implemented as a software application as part of an EDA tool. In some embodiments, method 1400 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer-readable medium. In some embodiments, the layout design is generated based on a netlist, which is generated based on a schematic design.

[0135] Figure 22 is a schematic diagram of a system 1500 for designing and manufacturing IC layout designs according to some embodiments. As described herein, system 1500 generates or places one or more IC layout designs. In some embodiments, system 1500 manufactures one or more semiconductor devices based on one or more IC layout designs, as described herein. System 1500 includes (e.g., hardware) a processor 1502 and a non-transitory computer-readable storage medium 1504 encoded, i.e., storing computer program code 1506 (e.g., a set of executable instructions). The computer-readable storage medium 1504 is used to interface with manufacturing machinery for producing semiconductor devices. Processor 1502 is electrically coupled to computer-readable storage medium 1504 via bus 1508. Processor 1502 is also electrically coupled to I / O interface 1510 via bus 1508. Network interface 1512 is also electrically connected to processor 1502 via bus 1508. Network interface 1512 is connected to network 1514, allowing processor 1502 and computer-readable storage medium 1504 to be connected to external components via network 1514. Processor 1502 is used to execute computer program code 1506 encoded in computer-readable storage medium 1504, so that system 1500 can be used to perform some or all of the operations described in method 1400.

[0136] In some embodiments, the processor 1502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0137] In some embodiments, the computer-readable storage medium 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disc. In some embodiments using optical discs, the computer-readable storage medium 1504 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0138] In some embodiments, computer-readable storage medium 1504 stores computer program code 1506 for causing system 1500 to perform method 1400. In some embodiments, computer-readable storage medium 1504 also stores information required to perform method 1400 and information generated during the performance of method 1400, such as layout design 1516, user interface 1518, manufacturing unit 1520, and / or a set of executable instructions for performing the operation of method 1400.

[0139] In some embodiments, computer-readable storage medium 1504 stores instructions (e.g., computer code 1506) for interfacing with a manufacturing machine. The instructions (e.g., computer code 1506) enable processor 1502 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement method 1400 during the manufacturing process.

[0140] System 1500 includes an I / O interface 1510. The I / O interface 1510 is coupled to an external circuit system. In some embodiments, the I / O interface 1510 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or directional keys for transmitting information and commands to the processor 1502.

[0141] System 1500 also includes a network interface 1512 coupled to processor 1502. Network interface 1512 allows system 1500 to communicate with a network 1514 to which one or more other computer systems are connected. Network interface 1512 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPR, or WCDMA; or wired network interfaces such as Ethernet, USB, or IEEE-13154. In some embodiments, method 1400 is implemented in two or more systems 1500, and information such as layout design, user interface, and manufacturing unit information is exchanged between the different systems 1500 via network 1514.

[0142] System 1500 receives layout-related information via I / O interface 1510 or network interface 1512. This information is transferred to processor 1502 via bus 1508 to determine a layout design for IC production. The layout design is then stored as layout design 1516 in computer-readable storage medium 1504. System 1500 also receives user interface-related information via I / O interface 1510 or network interface 1512. This information is stored as user interface 1518 in computer-readable storage medium 1504. System 1500 receives manufacturing unit-related information via I / O interface 1510 or network interface 1512. This information is stored as manufacturing unit 1520 in computer-readable storage medium 1504. In some embodiments, manufacturing unit 1520 includes manufacturing information utilized by system 1500.

[0143] In some embodiments, method 1400 is implemented by a manufacturing apparatus to fabricate an integrated circuit using a set of masks fabricated based on one or more layout designs generated by system 1500. In some embodiments, system 1500 includes a manufacturing apparatus (e.g., manufacturing tool 1522) for fabricating the integrated circuit using a set of masks fabricated based on one or more layout designs disclosed herein. In some embodiments, system 1500 of Figure 22 produces a smaller IC layout design than other methods. In some embodiments, system 1500 of Figure 22 produces a layout design for a semiconductor device that occupies a smaller area than other methods.

[0144] Figure 23 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 1600 and its associated IC manufacturing process according to at least one embodiment of the present disclosure.

[0145] In Figure 23, the IC manufacturing system 1600 includes entities such as a design room 1620, a mask room 1630, and an IC manufacturer / wafer fab (“fab”) 1640. These entities interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices (semiconductor devices) 1660 (e.g., devices 10A-10G, 300, and 1000, memory device 100, circuits 150, 160, and 170, and improved circuits 150', 160', and 170'). The entities in the IC manufacturing system 1600 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1620, the masking room 1630, and the IC wafer fab 1640 are owned by a single larger company. In some embodiments, two or more of the design room 1620, the masking room 1630, and the IC wafer fab 1640 coexist in a common facility and use common resources.

[0146] Design studio (or design team) 1620 generates IC design layout 1622. IC design layout 1622 includes various geometric patterns designed for IC device 1660. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1660 to be manufactured. Various layers are combined to form various IC features. For example, a portion of IC design layout 1622 includes various IC features such as active regions, gate structures, source / drain regions, interconnect structures, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers disposed on the semiconductor substrate. Design studio 1620 implements appropriate design procedures to form IC design layout 1622. Design procedures include one or more of logic design, physical design, or placement and routing. IC design layout 1622 is presented in the form of one or more data files containing information about the geometric patterns. For example, IC design layout 1622 may be expressed in GDSII file format or DFII file format.

[0147] Masking chamber 1630 includes mask data preparation 1632 and mask fabrication 1634. Masking chamber 1630 uses IC design layout 1622 to fabricate one or more masks for manufacturing various layers of IC device 1660 according to IC design layout 1622. Masking chamber 1630 performs mask data preparation 1632, in which IC design layout 1622 is transferred into a representative data file (RDF). Mask data preparation 1632 provides the RDF to mask fabrication 1634. Mask fabrication 1634 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) or semiconductor wafer. The design layout is controlled by mask data preparation 1632 to conform to the specific characteristics of the mask writer and / or the requirements of IC wafer fab 1640. In Figure 23, mask data preparation 1632 and mask fabrication 1634 are illustrated as separate components. In some embodiments, mask data preparation 1632 and mask manufacturing 1634 can be collectively referred to as mask data preparation.

[0148] In some embodiments, mask data preparation 1632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as self-diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 1622. In some embodiments, mask data preparation 1632 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0149] In some embodiments, mask data preparation 1632 includes a mask rule checker (MRC) that examines the IC design layout. This MRC has undergone processing in an OPC (Optical Process Control) that applies a set of mask generation rules, which contain certain geometric and / or connectivity constraints to ensure sufficient margin, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 1634, which may undo modifications performed by the OPC to satisfy the mask generation rules.

[0150] In some embodiments, mask data preparation 1632 includes lithography process checking (LPC), which simulates the process to be implemented by IC wafer fab 1640 to manufacture IC device 1660. LPC simulates this process based on IC design layout 1622 to produce a simulated manufactured device, such as IC device 1660. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as virtual image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by LPC, if the simulated device does not sufficiently approximate the design rules in shape, OPC and / or MRC may be repeated to further refine the IC design layout 1622.

[0151] It should be understood that the above description of mask data preparation 1632 has been simplified for clarity. In some embodiments, mask data preparation 1632 includes additional features, such as logic operations (LOPs), to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 1622 during mask data preparation 1632 can be performed in a variety of different sequences.

[0152] After mask data preparation 1632 and during mask manufacturing 1634, the mask or mask group is manufactured based on a modified IC design layout. In some embodiments, an electron beam (e-beam) or multiple e-beams are used to pattern the mask (photomask or master photomask) based on the modified IC design layout. The mask can be formed using various techniques. In some embodiments, the mask is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer, is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the mask. In another example, the mask is formed using a phase transfer technique. In a phase shift mask (PSM), various features in a pattern formed on the mask are used to achieve an appropriate phase difference to enhance resolution and image quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. Multiple masks manufactured using the mask fabrication method are used in a variety of processes. For example, these masks are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0153] IC wafer fab 1640 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer fab 1640 is a semiconductor foundry. For example, there may be a first manufacturing facility for front-end manufacturing of a plurality of IC products (e.g., active regions 12A, 12B, OD1, OD3~OD8, and 400; active gate structures 16, AG1~AG8, AG12~AG18, AG21~24, and 600; source / drain features 14A, 14B, SD, PSD, NSD, and 802; gate isolation structures 50, 52, 54, 60, 62, 64, and CMG1~CMG16; active region isolation structures DG1~DG4, and DG11~DG14; etc.); a second manufacturing facility may provide intermediate manufacturing for interconnects of IC products (e.g., source / drain contacts 18 and MD1~MD7); a third manufacturing facility may provide back-end manufacturing for interconnects and packaging of IC products; and a fourth manufacturing facility may provide other services for foundry entities.

[0154] IC wafer fab 1640 uses a mask (or multiple masks) manufactured by mask chamber 1630 to manufacture IC device 1660. Therefore, IC wafer fab 1640 uses IC design layout 1622 at least indirectly to manufacture IC device 1660. In some embodiments, IC wafer fab 1640 uses a mask (or multiple masks) to manufacture semiconductor wafer 1642 to form IC device 1660. Semiconductor wafer 1642 includes a silicon substrate or other suitable substrate on which a material layer is formed. The semiconductor wafer further includes various doped regions, dielectric features, multilevel interconnects, and one or more of the like (formed in subsequent manufacturing steps).

[0155] IC manufacturing system 1600 is shown as having a design room 1620, a mask room 1630, and an IC wafer fab 1640 as separate components or entities. However, it should be understood that one or more of the design room 1620, the mask room 1630, and the IC wafer fab 1640 are parts of the same component or entity.

[0156] In one embodiment of this disclosure, a semiconductor structure is provided. The semiconductor structure includes semiconductor fins protruding from a substrate and extending across the substrate along a first lateral direction. The semiconductor structure includes a plurality of gate structures disposed above the substrate, wherein each gate structure extends along a second lateral direction perpendicular to the first lateral direction. The semiconductor structure includes a gate isolation structure disposed above the gate structures. The gate isolation structure includes a first portion and a second portion connected to the first portion. The first portion extends above the gate structures along the first lateral direction. The second portion extends partially into the semiconductor fins along the second lateral direction.

[0157] In another embodiment disclosed herein, a semiconductor structure is provided. The semiconductor structure includes a semiconductor active region disposed above a substrate and extending across the substrate along a first lateral direction. The semiconductor active region includes a first source / drain feature and a second source / drain feature. The semiconductor structure includes gate structures disposed above the substrate, wherein each gate structure extends along a second lateral direction perpendicular to the first lateral direction. The first and second source / drain features are separated by one of the gate structures. The semiconductor structure includes a gate cleaving feature disposed above the substrate. The gate cleaving feature includes a first portion and a second portion extending from the first portion along the second lateral direction. The second portion replaces a portion of the first source / drain feature.

[0158] In yet another embodiment disclosed herein, a method for manufacturing a semiconductor device is provided. The method includes forming semiconductor fins that protrude from a substrate and extend across the substrate along a first lateral direction. The method includes forming a plurality of gate structures over the substrate, wherein each gate structure extends along a second lateral direction perpendicular to the first lateral direction. The method includes forming a gate isolation structure over the substrate. The gate isolation structure includes a first portion and a second portion extending from the first portion, wherein the first portion cuts through the gate structures and the second portion cuts through the semiconductor fins.

[0159] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0160] 8:Substrate 10A~10G: Device 11: Internal spacers 12A~12B: Activity Area 13A~13B: Nanostructure 14A~14B: Source / Drain Characteristics 15: Bottom isolation layer 16: Active gate structure 16A~16H: Active gate structure 17: Gate spacer 18: Source / Drain Contacts 18A~18C: Source / Drain Contacts 19: ILD layer 50: Gate isolation structure 50A: Part 1 / Horizontal Section 50B: Part Two / First Lateral Section 50C: Part 3 / Second Lateral Section 52: Gate isolation structure 52A: Part 1 / Horizontal Section 52B: Part Two / First Lateral Section 52C: Part Three / Second Horizontal Section 60: Gate isolation structure 60A: Part 1 / Horizontal Section 60B: Part Two / First Lateral Section 60C: Part 3 / Second Horizontal Section 62: Gate isolation structure 62A: Part 1 / Horizontal Section 64: Gate isolation structure 64A: Part 1 / Horizontal Section 64B: Part Two / Horizontal Section 100: Memory Device 101: Memory Array 102: Bit unit 110:I / O circuit 120: Control logic circuit 130:WL drive 140: Holder circuit 140': Improved Holder Circuit 150: Part of the peripheral circuitry 150': Improved section 160: Logic Circuits 160': Improved section 170: Circuit 170': Improved circuit 200: Method 202~222: Operation 300: Device 302:Substrate 304: First semiconductor layer 306: Second semiconductor layer 400: Fin structure 400A~400C: Fin structure 410: Trench 504: Isolation Structure 505: Quarantine Zone 600: Virtual gate structure 600A~600C: Virtual gate structure 602: Dummy gate electrode layer 604: Hard mask 702: Gate spacer 704: Internal spacers 706: Source / Drain Groove 802: Source / Drain Characteristics 804: Bottom isolation layer 806: ILD layer 900: Active gate structure 900A~900C: Active gate structure 920: Gate isolation structure 920A: Part 1 / Horizontal Section 920B: Part Two / Horizontal Section 922: Gate isolation structure 922A: First or horizontal section 930: Source / Drain Contact 930A~930B: Source / Drain Contacts 1000: Semiconductor Devices 1100: Semiconductor Device 1102:Substrate 1104: Fins 1106: Quarantine Zone 1108: Gate dielectric layer 1110: Gate electrode layer 1112D: Drainage Characteristics 1112S: Source Characteristics 1400: Method 1410~1420: Operation 1500: System 1502: Processor 1504: Non-transitory computer-readable storage media 1506: Computer program code 1508: Busbar 1510:I / O interface 1512: Network Interface 1514: Internet 1516: Layout Design 1518: User Interface 1520: Manufacturing Unit 1522: Manufacturing Tools 1600: IC Manufacturing System 1620: Design Studio 1622: IC Design Layout 1630: Shielded Room 1632: Preparation of Masking Data 1634: Mask Manufacturing 1640: Wafer fab 1642: Semiconductor wafer 1660: IC Manufacturing System AG1~AG19: Active gate structure CMG1~CMG16: Gate isolation structure CMG3_A: Horizontal section CMG3_B: First horizontal section CMG3_C: Second horizontal section CMG4_A: Horizontal section CMG4_B: Horizontal section CMG8_A: Horizontal section CMG8_B~CMG8_C: Horizontal section CMG9_A: Horizontal section CMG9_B~CMG9_C: Horizontal section CMG13_A: Horizontal section CMG14_A: Horizontal section CMG14_B: Horizontal section CMG15_A: Horizontal section CMG15_B: Horizontal section CMG16_A: Horizontal section CR: Channel Area DG1~DG4: Isolation structure for the activity area DG11~DG14: Isolation structure for active areas Lcmg1~Lcmg3: Length Lcmg5~Lcmg6: Length Lcmg14: Length MD1~MD7: Source / Drain Contacts MOS1: First MOS device MOS2: Second MOS device MOS3: Third MOS device MOS4: Fourth MOS device OD1: Activity Area OD3: First Activity Zone OD4: Second Activity Zone OD5: Third Activity Zone OD6~OD9: Activity Area PSD: Source / Drain Characteristics SD: Source / Drain Characteristics W1~W6: Width W8~W10: Width W13~W14: Width WP1~WP7: Width WP9: Width

[0161] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor structure comprising: a semiconductor fin projecting from a substrate and extending across the substrate along a first lateral direction; a plurality of gate structures disposed above the substrate, each gate structure extending along a second lateral direction perpendicular to the first lateral direction; and a gate isolation structure disposed above the gate structures, the gate isolation structure including a first portion and a second portion connected to the first portion, wherein the first portion extends above the gate structures along the first lateral direction, and wherein the second portion extends partially into the semiconductor fin along the second lateral direction, wherein the semiconductor fin includes a source / drain feature inserted between two adjacent gate structures, and wherein the second portion replaces a portion of the source / drain feature.

2. The semiconductor structure as claimed in claim 1, wherein the second portion extends between two adjacent gate structures separated along the first lateral direction.

3. The semiconductor structure as described in claim 2, wherein the second portion is equidistant from each of the two adjacent gate structures.

4. The semiconductor structure as claimed in claim 1, further comprising: a source / drain contact extending between two adjacent gate structures and above the top surface of one of the second portions.

5. The semiconductor structure as claimed in claim 4, further comprising a bottom isolation layer disposed on one bottom surface of the source / drain feature and on one bottom surface of the second portion.

6. A semiconductor structure comprising: a semiconductor active region disposed above a substrate and extending across the substrate along a first lateral direction, the semiconductor active region including a first source / drain feature and a second source / drain feature; a plurality of gate structures disposed above the substrate, each gate structure extending along a second lateral direction perpendicular to the first lateral direction, the first and second source / drain features being separated by one of the gate structures; and a gate cleaving feature disposed above the substrate, the gate cleaving feature including a first portion and a second portion extending from the first portion along the second lateral direction, wherein the second portion replaces a portion of the first source / drain feature.

7. The semiconductor structure as described in claim 6, wherein: The gate cleaving feature is a first gate cleaving feature extending above a first end of one of the gate structures. The semiconductor structure further includes a second gate cleaving feature extending above a second end of the gate structures opposite to the first end, and the second gate cleaving feature includes a third portion and a fourth portion extending from the third portion toward the first gate cleaving feature.

8. The semiconductor structure as described in claim 6, wherein: The semiconductor active region has a width along the second lateral direction, the portion of the first source / drain feature replaced by the second portion has a length along the second lateral direction, and a difference between the width and the length is greater than 0.

9. A method of manufacturing a semiconductor structure, comprising the steps of: forming a semiconductor fin protruding from a substrate and extending across the substrate along a first lateral direction; forming a plurality of gate structures above the substrate, each gate structure extending along a second lateral direction perpendicular to the first lateral direction; forming a gate isolation structure above the substrate, the gate isolation structure including a first portion and a second portion extending from the first portion, wherein the first portion cuts the gate structures, and wherein the second portion cuts the semiconductor fin; and forming a source / drain feature inserted between two adjacent gate structures among the gate structures, wherein the second portion replaces a portion of the source / drain feature.

10. The manufacturing method as claimed in claim 9, wherein the step of forming the gate isolation structure includes the following steps: forming a first trench corresponding to the first portion and extending along the first lateral direction; forming a second trench corresponding to the second portion and extending along the second lateral direction; depositing a dielectric layer to fill the first trench and the second trench; and planarizing the dielectric layer to form the first and second portions of the gate isolation structure.

Images