Semiconductor device and method for forming the same

Abstract

A method includes: forming a lower source / drain region above a substrate; forming a gate stack next to the lower source / drain region; forming an upper source / drain region above the lower source / drain region; performing a back-side thinning process to thin the substrate and expose a sacrificial region; removing the sacrificial region to expose the lower source / drain region; and forming a back-side contact plug for electrical connection to the lower source / drain region.

Description

Technical Field

[0001] none. Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate; and using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise and need to be addressed. Summary of the Invention

[0004] none. Simple Explanation of the Diagram

[0005] The present invention is best understood by reading it in conjunction with the accompanying drawings from the following detailed description. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration. Figures 1 through 9 are views of intermediate stages in the formation of the CFET and back-side interconnect structure according to some embodiments. Figures 10 through 16 are views of an intermediate stage in the formation of the CFET and back-side interconnect structure according to an alternative embodiment. Figures 17 through 20 are views of an intermediate stage in the formation of the CFET and back-side interconnect structure according to an alternative embodiment. Figure 21 illustrates a flowchart of forming a CFET and a back-side connection structure according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, spatial relative terms such as “under,” “below,” “lower,” “overlapping,” “upper,” and similar terms may be used herein for ease of description to describe the relationship between one element or feature and another, as illustrated in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0008] A complementary field-effect transistor (CFET), a back-side interconnect structure, and a method for forming both are provided. According to some embodiments, the CFET is formed on the front side of a wafer, and the back-side interconnect structure is formed on the back side of the wafer. Forming the back-side interconnect structure includes: pre-forming a sacrificial region to align with an underlying source / drain region; removing the sacrificial region to expose the underlying source / drain region; and forming a back-side contact plug (also referred to as a back-side contact) in the recess left by removing the sacrificial region. Through the pre-forming of the sacrificial region, the back-side contact plug can be accurately aligned with the underlying source / drain region. The overlap displacement of the back-side contact plug from the underlying source / drain region is thus reduced. [, , ]

[0009] It should be understood that although Gate-All-Around (GAA) transistors (such as nanostructured FETs) have been discussed, the concepts disclosed herein can also be applied to the formation of back-side contacts of CFETs formed from other types of transistors, such as planar transistors, Fin Field-Effect Transistors (FinFETs), and similar types. Throughout the description, the terms "FET" and "transistor" are used interchangeably.

[0010] Figure 1 illustrates an example of a CFET 10 (including nanostructured field-effect transistors (FETs) 10U and 10L) according to some embodiments. Individual process illustrations are shown as process 202 in process flow 200 as illustrated in Figure 21. The CFET may include vertically stacked FETs. For example, the CFET 10 may include a lower nanostructured FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructured FET 10U of a second device type (e.g., p-type / n-type), opposite to the first device type. The nanostructured FETs 10U and 10L include semiconductor nanostructures 26' (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26' acts as a channel region of the nanostructured FET. The lower semiconductor nanostructure 26'L is used in the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26'U is used in the upper nanostructure FET 10U.

[0011] As illustrated in Figure 1, a wafer 2 including a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, such as a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; or the like, or combinations thereof.

[0012] In the illustrated example, each of the upper FET 10U and the lower FET 10L includes two semiconductor layers 26'U and 26'L as channels, respectively. It should be understood that the upper FET 10U and the lower FET 10L may include any number, such as 1, 2, 3, or more than 3 channel regions. A portion of the gate stack 90 covering and / or underlying the channel regions 26 forms a multilayer stack with the corresponding channel regions 26'U and 26'L.

[0013] Gate stacks 90 (including upper gate stack 90U and lower gate stack 90L) are formed between semiconductor layers 26. The upper gate stack 90U includes a gate dielectric 78 and an upper gate electrode 80U. The lower gate stack 90L includes a gate dielectric 78 and a lower gate electrode 80L. The gate dielectric 78 encloses (when viewed in a side view) each semiconductor nanostructure 26. Gate electrodes 80 (including lower gate electrode 80L and upper gate electrode 80U) are positioned above the gate dielectric 78. A dielectric isolation layer 56 is formed to isolate the gate stack 90U of the upper FET 10U from the gate stack 90L of the lower FET 10L. A dummy semiconductor layer 26'M may be formed to contact the dielectric isolation layer 56.

[0014] Source / drain regions 62 (including lower source / drain region 62L and upper source / drain region 62U) are disposed on opposite sides of gate dielectric 78 and individual gate electrodes 80. The source / drain regions may refer individually or collectively to the source or drain depending on the context.

[0015] Internal spacers 54, which are dielectric spacers, are formed on opposite sides of portions of the gate stack 90, which are located between semiconductor layers 26. The internal spacers 54 electrically insulate the source / drain regions 62L and 62U from their corresponding portions of the gate stack 90 to prevent and reduce leakage.

[0016] Gate spacer 44 is formed on the sidewall of the gate stack 90 above the multilayer stack. Gate spacer 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

[0017] Epitaxial source / drain regions 62L and 62U are laterally formed between multiple layers including channel region 26 and gate stack 90. ​​The lower epitaxial source / drain region 62L is formed above and in contact with the substrate, which includes semiconductor substrate 20 and sacrificial region 102. The lower epitaxial source / drain region 62L is in further contact with the lower semiconductor nanostructure 26'L, but not with the upper semiconductor nanostructure 26'U.

[0018] The lower epitaxial source / drain region 62L is epitaxially grown and has a conduction type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the individual materials may include silicon or carbon-doped silicon, with the carbon-doped silicon doped with n-type dopants such as phosphorus, arsenic, or the like. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the individual materials may include silicon or silicon-germanium, with the silicon-germanium doped with p-type dopants such as boron, indium, or the like. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not have corresponding p-type or n-type dopants implanted.

[0019] The first contact etch stop layer 66 and the first interlayer dielectric layer 68 are formed above the lower epitaxial source / drain region 62L. Suitable dielectric materials for the first interlayer dielectric layer 68 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like. The first contact etch stop layer 66 may be formed of a dielectric material with high etch selectivity relative to the etching of the first interlayer dielectric layer 68. For example, the first contact etch stop layer 66 may comprise silicon nitride, silicon oxide, silicon oxynitride, or the like, and the first contact etch stop layer 66 may be formed by any suitable deposition process, such as CVD, ALD, or the like.

[0020] An upper epitaxial source / drain region 62U is formed, thereby overlapping with the first contact etch-stop layer 66 and the first interlayer dielectric layer 68, and also overlapping with the lower source / drain region 62L. Depending on the desired conduction type of the upper epitaxial source / drain region 62U, the material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L.

[0021] The conduction type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. In other words, the upper epitaxial source / drain region 62U can be doped in the opposite way to the lower epitaxial source / drain region 62L. The upper epitaxial source / drain region 62U can be in-situ doped and / or may be implanted with n-type or p-type dopants.

[0022] The second contact etch stop layer 70 and / or the second interlayer dielectric layer 72 are also formed on the upper epitaxial source / drain region 62U. The materials may be similar to and may be the same as or different from the materials and formation methods of the first contact etch stop layer 66 and the first interlayer dielectric layer 68, and are not discussed in detail herein.

[0023] A gate mask 92 is formed over a gate stack 90. ​​The formation process may include: recessing the gate stack 90; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like; and performing a planarization process to remove excess dielectric material over the second interlayer dielectric layer 72. Further dielectric layers (such as etch stop layers, interlayer dielectrics, or the like, as illustrated but not labeled) may be formed over the gate mask 92 and the second interlayer dielectric layer 72.

[0024] Silicon oxide region 94 and source / drain contact plugs 96U and 96L are formed to be electrically coupled to upper source / drain region 62U and lower source / drain region 62L, respectively. Contact plug 96L can penetrate upper source / drain region 62U to reach lower source / drain region 62L. Although not illustrated, according to some embodiments, lower source / drain contact plug 96L can be enclosed by a dielectric liner. Source / drain contact plug 96L can therefore be electrically decoupled from upper source / drain region 62U through which source / drain contact plug 96L penetrates.

[0025] According to an alternative embodiment, a dielectric liner is formed to enclose the lower source / drain contact plug 96L. Therefore, the lower source / drain contact plug 96L can be further electrically coupled to the upper source / drain region 62U, and can electrically interconnect the upper source / drain region 62U and the lower source / drain region 62L.

[0026] As further illustrated in Figure 1, a sacrificial region 102 is formed in the substrate 20 and lies beneath and overlaps the lower source / drain region 62L. According to some embodiments, the sacrificial region 102 comprises a semiconductor material and may include sacrificial layers 102A and 102B, wherein sacrificial layer 102B is located between sacrificial layer 102A and the overlying lower source / drain region 62L. The sacrificial region 102 may also be in physical contact with the lower source / drain region 62L.

[0027] According to some embodiments, the sacrificial region 102 is formed before the formation of the overlying CFET 10. The formation of the sacrificial region 102 may be performed before or after the formation of shallow trench isolation (STI) regions (not shown), which are formed below the CFETs to separate adjacent CFETs from each other. The sacrificial region 102 may also be formed when wafer 2 is a blank wafer.

[0028] According to some embodiments, forming the sacrificial region 102 includes etching the semiconductor substrate 20 to form a recess, and filling the recess with a desired material. According to some embodiments, the sacrificial layer 102A comprises silicon germanium, and the percentage of germanium atoms may be in the range of about 10% to about 40%. The formation process may include epitaxy, and therefore the sacrificial layer 102A may have a crystalline structure.

[0029] The sacrificial layer 102A may not be doped with any p-type dopant (such as boron, indium, or the like) or n-type dopant (such as phosphorus, arsenic, or the like). Alternatively, the sacrificial layer 102A may be in situ doped with p-type or n-type dopant, which helps stabilize the doping concentration in the well region. Doping the sacrificial layer 102A also prevents the doping concentration in the well region from being undesirably reduced due to diffusion into the sacrificial region 102 during the formation of the CFET.

[0030] A sacrificial layer 102B is formed above a sacrificial layer 102A. The sacrificial layer 102B comprises a material different from that of the lower source / drain region 62L and the material of the sacrificial layer 102A. According to some embodiments, the sacrificial layer 102B comprises silicon and is germanium-free. The sacrificial layer 102B may further comprise a dopant such as boron. According to alternative embodiments, the sacrificial layer 102B comprises silicon-germanium having a lower percentage of germanium atoms compared to the sacrificial layer 102A. The sacrificial layer 102B may also be formed via epitaxy and therefore also has a crystalline structure.

[0031] After the sacrificial layer 102B is formed, a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process, can be performed to make the top surface of the sacrificial layer 102B flush with the top surface of the substrate 20. The resulting structure including the substrate 20 (which may be a semiconductor substrate) and the sacrificial region 102 can also be referred to as a (composite) substrate.

[0032] According to alternative embodiments, the sacrificial region 102 may comprise materials other than semiconductor materials. For example, the sacrificial region 102 may be formed or comprise a dielectric material. According to some embodiments, the entire sacrificial region 102 may be formed of a homogeneous dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like. According to alternative embodiments, the sacrificial region 102 may also comprise one or more layers such as sacrificial layers 102A and 102B. The corresponding sacrificial layers 102A and 102B may be formed of different dielectric materials selected from silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, and the like.

[0033] According to an alternative embodiment, the sacrificial layer 102B is formed of a different type of material than the sacrificial layer 102A. For example, the sacrificial layer 102A may be formed of a semiconductor material different from the material of the substrate 20, and the sacrificial layer 102B may be formed of a dielectric material, such that the sacrificial layer 102B can serve as an effective etch stop layer in the subsequent removal of the sacrificial layer 102A.

[0034] According to some embodiments, the sacrificial region 102 is formed directly beneath both the illustrated lower source / drain regions 62L. According to an alternative embodiment, the sacrificial layer 102A is formed directly beneath and overlaps the source / drain regions 62L. On the other hand, a non-sacrificial region 102 is formed in the dashed region 104. In other words, the non-sacrificial region 102 is formed directly beneath and connected to the lower source / drain region 62L, which is electrically connected to the source / drain contacts 96L. Since the lower source / drain region 62L is electrically connected from the front, it is unnecessary to form a back contact plug in the dashed region 104.

[0035] According to some embodiments, the width of the sacrificial region 102 may be greater than the width corresponding to the lower source / drain region 62L. The sacrificial region 102 may therefore extend laterally beyond the corresponding edge of the lower source / drain region 62L, as illustrated in Figure 1 in one example.

[0036] According to an alternative embodiment, the width of the sacrificial region 102 is equal to the width of the lower source / drain region 62L. The edge 102E1 of the sacrificial region 102 may be perpendicularly aligned with the corresponding edge of the corresponding overlying lower source / drain region 62L. According to yet another alternative embodiment, the width of the sacrificial region 102 is less than the width of the lower source / drain region 62L, and the edge 102E2 of the sacrificial region 102 may be laterally recessed from the corresponding edge of the lower source / drain region 62L.

[0037] Since the sacrificial region 102 can be formed by etching the substrate 20 and then filling the substrate 20, the sacrificial region 102 can have a top width W1 and a bottom width W2 that is smaller than the top width W1. The edges of the sacrificial region 102 can therefore be straight and sloping.

[0038] Referring to Figure 2, wafer 2 is flipped upside down. Backside thinning processes, such as CMP or mechanical polishing, are performed to remove portions of substrate 20. Individual process illustrations are shown as process 204 in process flow 200 as illustrated in Figure 21. Sacrificial region 102 is thus exposed.

[0039] Next, as illustrated in Figure 3, substrate 20 is removed via an etching process. The specific process illustration is process 206 in process flow 200 illustrated in Figure 21. After the etching process, the internal spacer 54 and gate dielectric 78 are exposed. The etching process is selective, allowing substrate 20 to be removed while the sacrificial region 102 remains intact. The etching process is also selective, ensuring that the internal spacer 54 and gate dielectric 78 are not damaged.

[0040] Figure 4 illustrates the formation of dielectric layer 106, also referred to as dielectric substrate 106. Various process illustrations are shown as process 208 in process flow 200 as illustrated in Figure 21. The formation process includes depositing dielectric material until the sacrificial region 102 is completely embedded in the dielectric material, wherein all surfaces of the substantial dielectric material are above the bottom surface of the sacrificial region 102. According to some embodiments, dielectric layer 106 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or the like. The deposition process may be performed via ALD, CVD, plasma-enhanced chemical vapor deposition (PECVD), or the like.

[0041] Next, a planarization process, such as CMP or mechanical polishing, is performed to remove the portion of the dielectric material above the sacrificial region 102. The top surface of the sacrificial region 102 is thus exposed again. The remaining dielectric material then forms the dielectric layer 106.

[0042] Figure 5 illustrates an etching process 108 for removing the sacrificial layer 102A and forming the contact opening 110. A separate process illustration is shown as process 210 in process flow 200 as illustrated in Figure 21. The etching process 108 can be performed via a dry etching process, which can be an isotropic or anisotropic. The contact opening 110 is thus formed in the dielectric layer 106. The etching process can also be performed via a wet etching process. The etching chemical (gas or wet solution) is selectively used to attack the sacrificial layer 102A but not the dielectric layer 106. The etching rate of the sacrificial layer 102B is also lower than that of the sacrificial layer 102A. Therefore, the sacrificial layer 102B serves as an etching stop layer to terminate the etching process 108.

[0043] Referring to Figure 6, etching process 112 is performed to remove the sacrificial layer 102B, thereby exposing the underlying lower source / drain region 62L. The process is illustrated as process 212 in process flow 200 as shown in Figure 21. Etching process 112 can be a dry etching process, which can be an isotropic etching process. Alternatively, etching process 112 can be a wet etching process.

[0044] As shown in Figure 6, the opening 110 may have a bottom width W1' and a top width W2'. Since the bottom width W1' and the top width W2' are determined by the top width W1 (Figure 1) and the bottom width W2 (and may be equal to the top width W1 and the bottom width W2), the top width W2' may be smaller than the bottom width W1'. The edge of the dielectric layer 106 facing the opening 110 may also be slanted and straight.

[0045] In an embodiment where no sacrificial region 102 is formed in the dashed region 104, the opening 110 in the dashed region 104 in Figure 6 will also not be formed. Alternatively, the dashed region 104 will have a dielectric layer 106 covering each underlying source / drain region 62L.

[0046] Referring to Figure 7, dielectric contact spacers 116 are formed in the contact opening 110 and on the sidewalls of the dielectric layer 106. Individual process illustrations are shown as process 214 in process flow 200 as illustrated in Figure 21. According to some embodiments, the formation of the dielectric contact spacers includes conformal deposition processes such as CVD or ALD to form a conformal dielectric layer. The material of the dielectric contact spacers 116 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like. The dielectric contact spacers 116 may also have a dielectric constant (k value) greater than 3.9, thereby providing good isolation capabilities. Candidate materials may include AlxOy, HfO2, or the like. For example, the thickness of the dielectric contact spacers 116 may be in the range of about 2 nm to about 6 nm. [, , ]

[0047] After depositing the conformal dielectric layer, an anisotropic etching process is performed, which removes the horizontal portion of the conformal dielectric layer and leaves the vertical portion of the conformal dielectric layer within the contact opening 110 to form the dielectric contact spacer 116. The dielectric contact spacer 116 can form a ring enclosing the contact opening 110 when viewed from the top of the wafer 2. [, , ]

[0048] Depending on the width of the sacrificial region 102, as discussed, the bottom surface of the dielectric contact spacer 116 may contact one or more of several possible regions (materials). According to some embodiments, the bottom surface of the dielectric contact spacer 116 contacts the top surface of the inner spacer 54 and may or may not contact the top surface of the lower source / drain region 62L. Due to the accurate alignment of the subsequently formed back contact plug 122 (Figure 8) with the lower source / drain region, it is possible to extend the width of the back contact plug without the risk of overlap displacement problems. The width of the contact opening 110 may be greater than, equal to, or less than the corresponding width of the lower source / drain region 62L. [, , ]

[0049] According to some embodiments, the bottom surface of the dielectric contact spacer 116 contacts the top surface of the lower source / drain region and does not contact the top surface of the internal spacer 54. The width of the contact opening 110 can therefore be smaller than the corresponding width of the lower source / drain region 62L. [, , ]

[0050] Referring to Figure 8, a silicate layer 120 is formed on the top surface of the lower source / drain region 62L. The respective process illustration is process 216 in process flow 200 as shown in Figure 21. The formation process may include, for example, depositing a metal layer (not shown) using a conformal deposition process such as physical vapor deposition (PVD). A metal nitride layer, such as a titanium nitride layer or a tantalum nitride layer, or a barrier layer (not shown), may then be deposited on the metal layer. An annealing process is then performed to react the metal layer with silicon (and germanium, if present) in the lower source / drain region 62L. Thus, the source / drain silicate layer 120 is formed. The annealing process may be performed via rapid thermal annealing (RTA), furnace annealing, or similar methods.

[0051] According to some embodiments, as illustrated in Figures 5, 6, and 8, the sacrificial layer 102B is removed, and the silicate layer 120 is formed by reacting a metal with the lower source / drain region 62L. According to an alternative embodiment, the sacrificial layer 102B is not removed and remains in the structure illustrated in Figures 6 and 7. The silicate layer 120, as illustrated in Figures 8 and 9, can therefore be formed by reacting a metal with the sacrificial layer 102B (and possibly with the lower source / drain region 62L), and the silicate layer can be a silicon layer. [, , ]

[0052] The barrier layer and the remaining metal layer can then be removed. Next, a back-side contact plug 122 is formed to fill the contact opening 110 and is electrically connected to the silicon layer 120. A process illustration is shown as process 218 in process flow 200 as illustrated in Figure 21. According to some embodiments, forming the back-side contact plug 122 may include forming a barrier layer, which may comprise titanium nitride, tantalum nitride, or the like. Next, a metal material is deposited over and in contact with the barrier layer. The metal material may include tungsten, cobalt, or the like. A planarization process, such as a CMP process or a mechanical polishing process, is then performed to remove excess portions of the barrier layer and metal material, leaving the back-side contact plug 122. [, , ]

[0053] Referring to Figure 9, an etch stop layer 124 and a dielectric layer 126 are formed. The respective process diagrams are shown as process 220 in process flow 200 as illustrated in Figure 21. Each etch stop layer 124 may comprise AlN, AlO, SiOC, or similar materials, or multiple layers thereof. The dielectric layer 126 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or similar materials.

[0054] Conductive features 130, such as metal wiring or metal through-holes, are then formed above and in contact with the back contact plug 122. Individual process illustrations are shown as process 222 in process flow 200 as illustrated in Figure 21. According to some embodiments, a dielectric liner 128 may be formed to enclose the conductive features 130. According to alternative embodiments, the dielectric liner 128 is not formed.

[0055] According to some embodiments, the conductive feature 130 is formed of a homogeneous conductive material such as tungsten, cobalt, aluminum, or the like. According to alternative embodiments, the conductive feature 130 includes a resistivity barrier layer and a conductive region above the resistivity barrier layer. The resistivity barrier layer may comprise Ti, TiN, Ta, TaN, or the like. The conductive region may comprise copper. The formation process of the conductive feature 130 may include an damascene process.

[0056] It should be understood that the back contact plug 122 in the dashed area 104 may not be used for conducting current. Since the lower source / drain region 62L on the left side of Figure 9 is electrically connected to the source / drain contact plug 96L, the current flowing through the lower transistor 10L on the left side of Figure 9 is conducted through the source / drain contact plug 96L. The back contact plug 122 in the dashed area 104 may have the same voltage as the respective lower source / drain region 62L. However, the current flowing through the lower source / drain region 62L on the left side of Figure 9 will not flow through the back contact plug 122 in the dashed area 104.

[0057] According to some embodiments, the entire top surface of the back contact plug 122 in the dashed area 104 is in contact with the etch stop layer 124, and current cannot flow through each individual back contact plug 122. In other words, the back contact plug 122 in the dashed area 104 is the endpoint feature where current and voltage terminate.

[0058] According to an alternative embodiment, the back-side contact plug 122 in the dashed area 104 is further connected to a back-side metal wiring (not shown). Therefore, the back-side contact plug 122 in the dashed area 104 is electrically connected to the contact plug 96L, and current can flow between the back-side contact plug 122 and the contact plug 96L, wherein the lower source / drain region 62L acts as an interconnect.

[0059] According to some embodiments, the bottom width W1'' of the back contact plug 122 may be greater than, equal to, or less than the top width W3 of the lower source / drain region 62L. The external width W4 of the combined features including the dielectric contact spacer 116 and the back contact plug 122 may also be greater than, equal to, or less than the top width W3 of the lower source / drain region 62L. Since the back contact plug 122 is formed based on the sacrificial region 102 (Figure 1), the top width W2'' of the back contact plug 122 may be less than or equal to the bottom width W1'' of the back contact plug 122.

[0060] According to an alternative embodiment where the contactless opening 110 is formed in region 104 (Figure 6), a silicon-free layer 120 and a back-side contact plug 122 are formed in the dashed region 104. Therefore, the dielectric layer 106 will make solid contact with the top surface of the lower source / drain region 62L to form an interface. Electrical connections to the lower source / drain region 62L are also made through the source / drain contact plug 96L.

[0061] The back contact plug 122 is self-aligned with the sacrificial region 102, which is precisely vertically aligned to the lower source / drain region 62L. Therefore, the back contact plug 122 is aligned to the lower source / drain region 62L without concern for overlap shift or misalignment. It is also possible to form a wider back contact plug 122 without the risk of misalignment (which would cause an electrical short circuit from the lower source / drain region 62L to the metal gate). The back contact plug 122 can therefore be formed to extend laterally beyond the respective edges of the respective underlying lower source / drain regions 62L. However, if the back contact plug 122 is not formed via a self-alignment process according to the embodiments disclosed herein, the bottom width W1'' of the back contact plug 122 must be formed smaller than the top width W3 of the lower source / drain region 62L to allow for process leeway and overlap shift. [, , ]

[0062] Figures 10 through 16 illustrate the formation of back-side contact plugs according to alternative embodiments of the present disclosure. These embodiments are similar to those illustrated in Figures 1 through 9, except that the two back-side contact plugs are formed in a separation process and thus can extend to different heights. Unless otherwise specified, the materials, construction, and formation processes of the components in these embodiments (and other embodiments throughout the present disclosure) are substantially the same as those of the similar components indicated by similar reference numerals in the foregoing embodiments. The details relating to materials, construction, and formation processes provided throughout the description in each of the embodiments can be applied to any other embodiment where appropriate. [, , ]

[0063] The initial process of these embodiments is substantially the same as that illustrated in Figures 1 through 4. Next, as illustrated in Figure 10, an etch mask 134 is formed and patterned. The etch mask 134 may contain patterned photoresist and may or may not include a rigid mask. The etch mask 134 covers the sacrificial region 102 on the left side of Figure 10 and exposes some other sacrificial regions 102, such as the sacrificial region 102 on the right side of Figure 4.

[0064] Next, as illustrated in Figure 10, etching process 108 is performed to remove the right-side sacrificial layer 102A (as illustrated in Figure 4), thereby exposing the underlying sacrificial layer 102B, which serves as the etch stop layer. This forms the contact opening 110. The sacrificial layer 102B is thus exposed. The etch mask 134 is then removed. In removing the etch mask 134, the sacrificial layer 102B protects the underlying lower source / drain region 62L.

[0065] Figure 11 illustrates etching process 112, through which the sacrificial layer 102B is removed, thereby exposing the underlying lower source / drain region 62L. The lower source / drain region 62L is attributed to the material difference between the sacrificial layer 102B and the lower source / drain region 62L, which also serves as the etching termination layer.

[0066] Next, as illustrated in Figure 12, a dielectric contact spacer 116 is formed, which includes performing a conformal deposition process to deposit a dielectric layer and etching the dielectric layer via an anisotropic etching process.

[0067] Figure 13 illustrates the formation of a silicon layer 120 (also referred to as silicon layer 120A) and a back contact plug 122 (also referred to as back contact plug 122A). The materials, structure and formation process are described in the foregoing embodiments and are not repeated herein.

[0068] Next, referring to Figure 14, an etch stop layer 124 and a dielectric layer 126 are deposited. Subsequently, as illustrated in Figure 15, a contact opening 110' is formed via an etching process 113. The contact opening 110' includes portions of the dielectric layer 126 and the etch stop layer 124, thereby exposing the underlying sacrificial region 102 (Figure 14). The exposed sacrificial layer 102A is then removed, followed by an etching process to remove the sacrificial layer 102B, thus exposing the underlying source / drain region 62L. The etching of the sacrificial region 102 can be performed using the etch stop layer 124, sacrificial layer 102A, and sacrificial layer 102B as etch stop layers in a series of etch processes.

[0069] In subsequent processes, as shown in Figure 16, a silicon layer 120 (also referred to as silicon layer 120B) is formed on the top surface of the lower source / drain region 62L. A back-side contact plug 122 (also referred to as back-side contact plug 122B) is also formed. Silicon layers 120A and 120B are individually and collectively referred to as silicon layer 120. Back-side contact plugs 122A and 122B are individually and collectively referred to as back-side contact plug 122.

[0070] According to some embodiments, the bottom width W1'' of the back contact plug 122, the top width W2'' of the back contact plug 122, the top width W3 of the lower source / drain region 62L, and the outer width W4, which includes the combined features of the dielectric contact spacer 116 and the back contact plug 122, may have the same relationship as described with reference to Figure 9.

[0071] Figures 17 through 20 illustrate the formation of a back-side contact plug according to an alternative embodiment of the present disclosure. These embodiments are similar to those illustrated in Figures 10 through 16, except that the back-side contact plug is formed in a double-insertion structure, which also includes metal wiring for horizontal wiring.

[0072] The initial process of these embodiments is essentially the same as that shown in Figures 1 through 4. The resulting structure is shown in Figure 17. Next, an etch mask 134 is formed and patterned, and an opening 136 is formed in the etch mask 134. The opening 136 extends laterally beyond the edge of the underlying sacrificial region 102 in the opposite direction.

[0073] Next, as illustrated in Figure 18, dielectric layer 126 is etched, and the etching terminates on etch stop layer 124. The etching is anisotropic. Etch stop layer 124 is then etched to expose underlying sacrificial layer 102A, and the etching can be anisotropic or isotropic.

[0074] According to some embodiments, the etch mask 134 is removed, followed by etching of the sacrificial layer 102A to form the contact opening 110. The resulting structure is illustrated in Figure 19. According to an alternative embodiment, the etch mask 134 is removed after the removal of the sacrificial layer 102A and before the removal of the sacrificial layer 102B. During the removal of the etch mask 134, the sacrificial layer 102A or sacrificial layer 102B protects the lower source / drain region 62L from damage.

[0075] Referring to Figure 20, a metal wiring 142 and a through-hole 144 are formed. The through-hole 144 also serves as a back-side contact plug. According to some embodiments, the metal wiring 142 and the through-hole 144 include a barrier layer 146 and a metal material 148 above the barrier layer 144. The barrier layer 146 may contain Ti, TiN, Ta, TaN, or the like. The metal material 148 may contain copper or other materials, such as tungsten, cobalt, or the like.

[0076] According to some embodiments, the bottom width W1'' of the back contact plug 122, the top width W2'' of the back contact plug 122, the top width W3 of the lower source / drain region 62L, and the outer width W4, which includes the combined features of the dielectric contact spacer 116 and the back contact plug 122, may have the same relationship as discussed with reference to Figure 9. The relative values ​​can be applied to the through-hole 144 and the back contact plug 122.

[0077] In the embodiments illustrated in Figures 10 to 20, the sacrificial layer 102B (Figures 10, 14 and 18) may also be removed or not removed, so that the remaining sacrificial layer 102B can be used to form the silicate layer 120.

[0078] The embodiments disclosed herein have several advantageous features. By pre-forming a sacrificial region in the substrate, and forming a lower source / drain region above and perpendicularly aligned with the sacrificial region, the back-side contact plug can be self-aligned with the sacrificial region and thus perpendicularly aligned to the lower source / drain region. Alignment is therefore accurate, and problems such as short circuits or leakage from the source / drain to the metal gate are eliminated. By replacing the semiconductor substrate with a dielectric layer, undesirable leakage from the back-side contact plug to the substrate is also eliminated. [, , ]

[0079] According to some embodiments of this disclosure, a method includes: forming a lower source / drain region over a substrate; forming a gate stack adjacent to the lower source / drain region; forming an upper source / drain region over the lower source / drain region; performing a back-side thinning process to thin the substrate and expose a sacrificial region; removing the sacrificial region to expose the lower source / drain region; and forming a back-side contact plug for electrical connection to the lower source / drain region. In one embodiment, removing the sacrificial region includes removing a semiconductor region.

[0080] In one embodiment, removing the semiconductor region includes removing a silicon-germanium layer. In one embodiment, removing the sacrificial region further includes etching a silicon layer after removing the semiconductor region. In one embodiment, removing the sacrificial region includes an isotropic etching process. In one embodiment, the method further includes removing a semiconductor substrate of the semiconductor substrate after the back-side thinning process and before the sacrificial region is removed; and forming a dielectric substrate to embed the sacrificial region in the dielectric substrate.

[0081] In one embodiment, the sacrificial region is removed from the dielectric substrate. In one embodiment, the method further includes forming a dielectric contact spacer after the back-side contact plug is formed, wherein the back-side contact plug is enclosed by the dielectric contact spacer. In one embodiment, the gate stack includes a lower portion adjacent to and contacting an internal spacer, wherein the dielectric contact spacer contacts the internal spacer to form an interface. In one embodiment, the back-side contact plug extends laterally beyond one edge of the lower source / drain region.

[0082] According to some embodiments of the present disclosure, a method includes: forming a sacrificial region in a semiconductor substrate; forming a lower transistor including a lower source / drain region, wherein the lower source / drain region is above and contacts the sacrificial region; a gate stack; and a dielectric internal spacer between the gate stack and the lower source / drain region; forming an upper transistor including an upper source / drain region, wherein the upper source / drain region overlaps with the lower source / drain region; forming a front contact plug above the upper source / drain region and electrically coupled to the upper source / drain region; thinning the semiconductor substrate to expose the sacrificial region; replacing the semiconductor substrate with a dielectric substrate; removing the sacrificial region to form a recess in the dielectric substrate; and forming a back contact plug in the recess to electrically couple to the lower source / drain region.

[0083] In one embodiment, the method further includes forming a dielectric contact spacer in the recess, wherein the back contact plug is enclosed by the dielectric contact spacer. In one embodiment, the dielectric contact spacer contacts the dielectric inner spacer. In one embodiment, the back contact plug body contacts the dielectric inner spacer. In one embodiment, a portion of the back contact plug forms an interface with the dielectric inner spacer. In one embodiment, the method further includes forming a silicon layer, wherein the silicon layer is intermediate between the back contact plug and the lower source / drain region.

[0084] According to some embodiments disclosed herein, a method includes: forming a lower source / drain region over a semiconductor substrate; forming a dielectric region over and in contact with the lower source / drain region; forming an upper source / drain region over and in contact with the dielectric region; thinning the semiconductor substrate from a back side to expose a sacrificial region; replacing the semiconductor substrate with a dielectric substrate; performing an isotropic etching process to remove the sacrificial region; and forming a back-side contact plug in a space left by the anisotropic etching process.

[0085] In one embodiment, the isotropic etching process includes a first etching process for etching a first semiconductor layer. In another embodiment, the isotropic etching process further includes a second etching process for etching a second semiconductor layer to expose the lower source / drain region. In one embodiment, the sacrificial region comprises a crystalline semiconductor material.

[0086] According to some embodiments of this disclosure, an apparatus includes a lower transistor comprising a lower source / drain region, a gate stack, and a dielectric internal spacer between the gate stack and the lower source / drain region. An upper transistor includes an upper source / drain region, wherein the upper source / drain region overlaps with the lower source / drain region. A front contact plug is positioned above and electrically coupled to the upper source / drain region. A back contact plug lies beneath and is electrically coupled to the lower source / drain region, wherein the back contact plug has a first width measured at a first reference level and a second width measured at a second reference level, wherein the first reference level is closer to the lower source / drain region than the second reference level, and the first width is greater than the second width.

[0087] In one embodiment, a dielectric contact spacer is further included, which encloses and contacts the back contact plug. In one embodiment, the dielectric contact spacer contacts an internal dielectric spacer. In one embodiment, the back contact plug body contacts the internal dielectric spacer. In one embodiment, a portion of the back contact plug forms an interface with the internal dielectric spacer. In one embodiment, a silicon layer is further included, wherein the silicon layer is located between the back contact plug and the lower source / drain region.

[0088] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0089] 2: Wafer 10: Complementary Field-Effect Transistor (CFET) 10L: Nanostructured Field-Effect Transistor (FET) 10U: Nanostructured Field-Effect Transistor (FET) 20:Substrate 26: Passage Area 26': Semiconductor nanostructure 26'M: Dummy Semiconductor Layer 26'L: Lower semiconductor nanostructure 26'U: Upper semiconductor nanostructure 44: Gate spacer 54: Internal spacers 56: Dielectric isolation layer 62: Source / Drain Region 62L: Lower source / drain region 62U: Upper source / drain region 66: First contact point etching termination layer 68: First interlayer dielectric layer 70: Second contact etched termination layer 72: Second interlayer dielectric layer 78: Gate Dielectric 80: Gate electrode 80U: Upper gate electrode 80L: Lower gate electrode 90: Gate Stacking 90U: Upper gate stack 90L: Lower gate stack 92: Gate shield 94: Silicon oxide region 96U: Source / Drain Contact Plug 96L: Source / Drain Contact Plug 102: Sacrifice Zone 102A: Sacrificial Layer 102B: Sacrificial Layer 102E1: Edge 102E2: Edge 104: Dashed line area 106: Dielectric layer / dielectric substrate 108: Etching Process 110: Contact opening 110': Contact opening 112: Etching process 113: Etching Process 116: Dielectric contact spacer 120: Silicon layer 120A: Silicon layer 120B: Silicone layer 122: Backside contact plug 122A: Backside contact plug 122B: Backside contact plug 124: Etching stop layer 126: Dielectric layer 128: Dielectric liner 130: Electrical conductivity characteristics 134: Etching Mask 136: Opening 142: Metal wiring 144: Through hole 146: Barrier Layer 148: Metallic Materials 200: Manufacturing Process 202: Process 204: Process 206: Manufacturing Process 208: Process 210: Manufacturing Process 212: Manufacturing Process 214: Manufacturing Process 216: Manufacturing Process 218: Manufacturing Process 220: Process 222: Manufacturing Process W1: Top width W1': Bottom width W1'': Bottom width W2: Bottom width W2': Top width W2'': Top width W3: Top width W4: Outer width

Claims

1. A method of forming a semiconductor device, comprising the steps of: forming a lower source / drain region above a substrate; forming a gate stack next to the lower source / drain region; forming an upper source / drain region above the lower source / drain region; performing a back-side thinning process to thin the substrate and expose a sacrificial region; removing the sacrificial region to expose the lower source / drain region; and forming a back-side contact plug for electrical connection to the lower source / drain region, wherein the back-side contact plug has a first width measured at a first level and a second width measured at a second level, and wherein the first level is closer to the lower source / drain region than the second level, and the first width is greater than the second width.

2. The method as described in claim 1, wherein the step of removing the sacrificial region includes the following steps: removing a semiconductor region.

3. The method as described in claim 2, wherein the step of removing the semiconductor region comprises the following steps: removing a silicon-germanium layer.

4. The method as described in claim 2, wherein the step of removing the sacrificial region further comprises the step of etching a silicon layer after removing the semiconductor region.

5. The method as described in claim 1 further comprises the following steps: removing the substrate after the back-side thinning process and before the sacrificial region is removed; and forming a dielectric substrate to embed the sacrificial region in the dielectric substrate.

6. The method as described in claim 5, wherein the sacrificial region is removed from the dielectric substrate.

7. A method of forming a semiconductor device, comprising the steps of: forming a lower source / drain region above a semiconductor substrate; forming a dielectric region above the lower source / drain region and contacting the lower source / drain region; forming an upper source / drain region above the dielectric region and contacting the dielectric region; thinning the semiconductor substrate from a back side to expose a sacrificial region; replacing the semiconductor substrate with a dielectric substrate; performing an etching process to remove the sacrificial region; and forming a back contact plug in a space left by the etching process, wherein the back contact plug has a first width measured at a first level and a second width measured at a second level, and wherein the first level is closer to the lower source / drain region than the second level, and the first width is greater than the second width.

8. A semiconductor device comprising: a lower transistor including: a lower source / drain region; a gate stack; and a dielectric internal spacer between the gate stack and the lower source / drain region; an upper transistor including an upper source / drain region, wherein the upper source / drain region overlaps with the lower source / drain region; a front contact plug located above and electrically coupled to the upper source / drain region; and a back contact plug located beneath and electrically coupled to the lower source / drain region, wherein the back contact plug has a first width measured at a first reference level and a second width measured at a second reference level, and wherein the first reference level is closer to the lower source / drain region than the second reference level, and the first width is greater than the second width.

9. The device as claimed in claim 8 further includes a dielectric contact spacer that encloses and contacts the back contact plug.

10. The apparatus of claim 9, wherein the dielectric contact spacer is in contact with the dielectric internal spacer.

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