Method of controlling non-volatile memory

Abstract

The embodiments provide a memory system and a memory element with high performance and high reliability. A method for controlling non-volatile memory is also provided. The non-volatile memory includes a memory cell configured to store data in a non-volatile manner. The method includes: issuing a first command sequence to the non-volatile memory to perform a first write operation, wherein n bits of first data are written to the memory cell; selecting one of a first method and a second method for preparing m bits of second data for a second write operation based on an index related to the reliability of the first data stored in the memory cell, the second data including n bits of the first data; and issuing a second command sequence to the non-volatile memory to perform a second write operation, wherein the second data is written to the memory cell, the second command sequence indicating the selected method for preparing the second data. In the first method, the second data for the second write operation is prepared inside the non-volatile memory, and in the second method, the second data for the second write operation is prepared outside the non-volatile memory.

Description

Methods for controlling non-volatile memory The embodiments described herein are generally related to a memory system and a memory element. A solid-state drive (SSD), which includes a memory controller and memory elements, is referred to as a type of memory system. Memory elements are, for example, non-volatile memory. Non-volatile memory includes, for example, inverse and flash memory. The embodiments provide a memory system and a memory element with high performance and high reliability. Generally, according to one embodiment, a memory system includes a non-volatile memory and a memory controller electrically connected to the non-volatile memory. The non-volatile memory includes: a memory cell configured to store data in a non-volatile manner; and control circuitry configured to write n bits (n is a real number greater than 1) of first data to the memory cell via a first write operation and to write m bits (m is a real number greater than n) of second data, including the n bits of the first data, to the memory cell via a second write operation. The memory controller is configured to: issue a first command sequence to the non-volatile memory to perform the first write operation; select one of a first method and a second method for preparing second data for the second write operation based on an index related to the reliability of the first data stored in the memory cell; and issue a second command sequence to the non-volatile memory to perform the second write operation, the second command sequence representing the selected method for preparing the second data. The memory system of the embodiment will be described with reference to Figures 1 to 37. In the following description, components with the same function and configuration are represented by the same reference symbols. Additionally, in each of the following embodiments, a distinguishing number / letter may be used at the end of the reference symbol for components (e.g., circuits, wiring, various voltages and signals). When it is possible not to distinguish components from each other, a reference symbol without such a number / letter at the end is used. (1) First Embodiment The memory system of the first embodiment will be described with reference to Figures 1 to 23. (a) Configuration example (a-1) Information processing system As shown in Figure 1, the information processing system 9 includes a memory system 1 and a host 2. Memory system 1 is a component used for storing data. Memory system 1 is, for example, a solid-state drive (SSD), universal flash storage (UFS) component, universal serial bus (USB) memory, a multi-media card (MMC), or an SD® card. Memory system 1 can be connected to host 2 via host bus (HBS). Memory system 1 performs processing based on requests received from host 2 (e.g., commands or host commands) or spontaneous processing requests generated within memory system 1. Host 2 is a computing element used to control memory system 1. Host 2 is, for example, a personal computer, server system, mobile device, on-vehicle device, or digital camera. (a-1-1) Internal configuration of the memory system The memory system 1 includes a memory controller 10 and a memory element 30. The memory element 30 is, for example, a non-volatile memory. The memory element 30 is, for example, a non-volatile semiconductor memory (e.g., inverse flash memory). Hereinafter, the memory element 30 is referred to as non-volatile memory 30 or inverse memory 30. Memory controller 10 is a component used to control the memory 30. Memory controller 10 is configured to connect to host 2 via host bus HBS. Memory controller 10 receives requests from host 2 via host bus HBS. The type of host bus HBS depends on the application applied to memory system 1. When memory system 1 is an SSD, the host bus HBS conforms to, for example, the Serial Attached SCSI (SAS) standard, the Serial Advanced Technology Attachment (ATA) standard, or the Peripheral Component Interconnect Express (PCIe) standard. TM The host bus HBS conforms to the M-PHY standard when the memory system 1 is a UFS device. When the memory system 1 is USB memory, the host bus HBS conforms to the USB standard. When the memory system 1 is MMC, the host bus HBS conforms to the embedded multimedia card (eMMC) standard. When the memory system 1 is SD... TMWhen the card is in use, the host bus HBS conforms to SD. TM standard. The memory controller 10 controls the reverse memory 30 via the reverse bus NBS based on requests received from the host 2 or spontaneous processing requests generated within the memory system 1. The reverse bus NBS conforms to, for example, the Toggle NAND Flash Interface standard or the Open NAND Flash Interface standard. The reverse memory 30 is a data storage element. The reverse memory 30 includes a plurality of memory cells. Each of the plurality of memory cells stores data in a non-volatile manner according to a threshold voltage of the memory cell. The reverse memory 30 stores data received from the memory controller 10 in the plurality of memory cells in a non-volatile manner. The reverse memory 30 outputs data read from the plurality of memory cells to the memory controller 10. (a-1-2) Memory Controller An example of the internal configuration of the memory controller 10 will be described. As shown in Figure 1, the memory controller 10 includes a host interface (I / F) circuitry 11, a processor 12, buffer memory 13, error checking and correcting (ECC) circuitry 14, read-only memory (ROM) 15, random access memory (RAM) 16, reverse interface (I / F) circuitry 17, and write management circuitry 18. The host interface circuitry 11, processor 12, buffer memory 13, ECC circuitry 14, ROM 15, reverse interface circuitry 17, and write management circuitry 18 can be configured, for example, as a system-on-a-chip (SoC) 100. In the example shown in Figure 1, RAM 16 is implemented externally to the SoC 100, but RAM 16 can also be implemented internally to the SoC 100. The memory controller 10 can be configured with multiple chips. The functionality of each part of the memory controller 10 can be implemented by dedicated hardware circuitry, a processor for executing programs (firmware), or a combination thereof. The host interface circuit 11 is a circuit used to control communication between the memory controller 10 and the host 2. The host interface circuit 11 is configured to be connected to the host 2 via the host bus HBS. Processor 12 is the control circuitry for memory controller 10. Processor 12 is, for example, a central processing unit (CPU). Processor 12 controls the operation of the entire memory controller 10 by executing programs (firmware) stored in ROM 15. For example, processor 12 controls write operations based on write requests received from host 2. The same applies to read and erase operations. Buffer memory 13 is a memory used for temporary storage of data. Buffer memory 13 is, for example, static random access memory (SRAM). Buffer memory 13 temporarily stores write data, read data, and similar data. Write data is data to be written to the inverted memory 30. Read data is data read from the inverted memory 30. ECC circuit 14 is a circuit used to perform error checking and correction (ECC) processing to correct data errors. During a data write operation, ECC circuit 14 generates an error correction code based on the written data. ECC circuit 14 generates a corrector based on the error correction code in a predetermined cell and detects errors during a data read operation. ECC circuit 14 corrects the detected errors. ROM 15 is non-volatile memory. ROM 15 is, for example, electrically erasable programmable read-only memory (EEPROM). TM ROM 15 stores programs such as firmware. RAM 16 is volatile memory. RAM 16 is, for example, SRAM or dynamic random access memory (DRAM). RAM 16 is used as the working area of ​​processor 12. RAM 16 stores firmware for managing memory 30 and various management information blocks. RAM 16 stores, for example, various tables TBL1. The inverter interface circuit 17 is a circuit used to control communication between the memory controller 10 and the inverter memory 30. The inverter interface circuit 17 is connected to the inverter memory 30 via the inverter bus NBS. For example, the inverter interface circuit 17 controls the transmission of data, commands, addresses and similar information between the memory controller 10 and the inverter memory 30. The write management circuit 18 manages various aspects of the write operation to be performed by the reverse flash memory 30 based on the state of the data in the reverse flash memory 30. (a-1-3) Reverse Flash Memory The configuration of the reverse and memory 30 will be described with reference to Figure 2. Figure 2 is a block diagram illustrating an example configuration of the reverse memory 30. The reverse memory 30 includes a memory cell array 31, an input / output circuit 32, a logic control circuit 33, a ready / busy control circuit 34, a register 35, a sequencer 36, a driver module 37, a column decoder module 38, a sense amplifier module 39, and a data latch 40. The memory cell array 31 includes one or more blocks BLK0, BLK1, ..., BLKk-1. Here, k is an integer of 1 or greater than 1. A block BLK is, for example, a set of memory cells in which data stored is collectively erased. For example, a block BLK is used as a unit for data erasure operations. Multiple bit lines and multiple word lines are provided in the memory cell array 31. Each memory cell is associated with, for example, one bit line and one word line. The memory cell array 31 will be described in detail later. Input / output circuitry 32 is used for communication with memory controller 10. Input / output circuitry 32 transmits input / output signals DQ (e.g., 8-bit signals DQ0 to DQ7) and data select signals DQS to memory controller 10. Signal DQ contains data transferred between inverter memory 30 and memory controller 10. Signal DQ can be, for example, a command CMD, an address ADD, a status information STS, or data DAT. Signal DQS is a signal (e.g., a synchronization signal) used to control the timing of the transmission of signal DQ. For example, during data writing, signal DQS, along with signal DQ containing the data being written, is transmitted from memory controller 10 to inverter memory 30. Inverter memory 30 receives signal DQ containing the data being written, synchronized with signal DQS. During data reading, signal DQS, along with signal DQ containing the data being read, is transmitted from inverter memory 30 to memory controller 10. The memory controller 10 receives a signal DQ, which includes data read, synchronized with the signal DQS. The input / output circuit 32 can receive the signal DQS from the memory controller 10 via the logic control circuit 33. Input / output circuit 32 transmits the command CMD from signal DQ to command register 35A. Input / output circuit 32 transmits the address ADD from signal DQ to address register 35B. Input / output circuit 32 receives status information STS from status register 35C. Input / output circuit 32 transmits data DAT from signal DQ to data latch 40 and receives data DAT from data latch 40. The logic control circuit 33 is used to control the input / output circuit 32 and the sequencer 36 based on control signals. The logic control circuit 33 receives a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the memory controller 10. Signal CEn is used to enable the inverter and memory 30. Signal CLE indicates that the signal DQ received by the inverter and memory 30 contains the command CMD. Signal ALE indicates that the signal DQ received by the inverter and memory 30 contains the address ADD. Signal WEn indicates the input signal DQ of the inverter and memory 30. Signal REn indicates the output signal DQ of the inverter and memory 30. The inverter and memory 30 generates the signal DQS based on signal REn. The memory 30 outputs the signal DQ to the memory controller 10 based on the generated signal DQS. The ready / busy control circuit 34 is used to notify the memory controller 10 of the operating state of the sequencer 36. The ready / busy control circuit 34 transmits a ready / busy signal RBn to the memory controller 10 based on the operating state of the sequencer 36. The signal RBn indicates whether the reverse memory 30 is in a ready state or a busy state. When the reverse memory 30 is in a ready state, the signal level of the signal RBn is set to, for example, a high level ("H" level). The ready state is a state in which the reverse memory 30 can receive commands from the memory controller 10. When the reverse memory 30 is in a busy state, the signal level of the signal RBn is set to, for example, a low level ("L" level). The busy state is a state in which the reverse memory 30 cannot receive commands from the memory controller 10. The temporary register 35 is a circuit used to temporarily store information. The temporary register 35 includes a command register 35A, an address register 35B, and a status register 35C. Command register 35A is a circuit used to store commands (CMD). Commands (CMD) include, for example, commands that cause sequencer 36 to perform read, write, or erase operations. Address register 35B is a circuit used to store addresses ADD. Address ADD includes, for example, column addresses and row addresses CAd. Column addresses include block addresses BAd and page addresses PAd (page address PAd is also a word line address). For example, block address BAd, page address PAd, and row address CAd are used to select block BLK, word line, and bit line, respectively. The status register 35C is a circuit used, for example, to temporarily store status information STS during read, write, or erase operations. The status information STS is used to notify the memory controller 10 whether the operation has been completed normally. Sequencer 36 is a circuit used to control the operation of another circuit according to a predetermined program. Sequencer 36 controls the operation of the entire inverted memory 30. For example, sequencer 36 controls the ready / busy control circuit 34, driver module 37, column decoder module 38, and sense amplifier module 39 based on the command CMD stored in command register 35A. For example, sequencer 36 performs read operations, write operations, and erase operations. Driver module 37 is a circuit used to generate the voltages used in read, write, and erase operations. Driver module 37 applies the generated voltage to the signal line corresponding to the selected word line based on the page address PAd stored in address register 35B. The column decoder module 38 is a circuit used to select a block BLK in the memory cell array 31 based on the block address Bad stored in the address register 35B. The column decoder module 38 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK. During a write operation, the sense amplifier module 39 receives write data DAT from the input / output circuit 32 via the data latch 40. The sense amplifier module 39 applies a voltage based on the received write data DAT to the bit lines. During a read operation, the sense amplifier module 39 determines the data stored in the memory cell based on the presence of current or voltage in the bit lines. The sense amplifier module 39 transmits the determination result as read data DAT to the input / output circuit 32 via the data latch 40. The data latch (also known as a data cache) 40 includes multiple latching circuits (not shown). Each latching circuit temporarily stores write data or read data. During a write operation, for example, the data latch 40 temporarily stores write data received from the input / output circuit 32 and transmits the write data to the sense amplifier module 39. Similarly, during a read operation, the data latch 40 temporarily stores read data received from the sense amplifier module 39 and transmits the read data to the input / output circuit 32. Example of a memory cell array configuration. The circuit configuration of the memory cell array 31 will be described with reference to Figure 3. Figure 3 is a circuit diagram of the memory cell array 31. Figure 3 shows the circuit configuration of block BLK0 provided in the memory cell array 31 as an example of the circuit configuration of the memory cell array 31. Other blocks BLK also have the same configuration as in Figure 3. Block BLK0 includes, for example, five string cells SU0, SU1, SU2, SU3, and SU4. Each string cell SU is a set of multiple inverse strings NS collectively selected, for example, in a write or read operation. Each string cell SU includes multiple inverse strings NS associated with bit lines BL0, BL1, ..., BLm-1, respectively. Here, m is an integer of 1 or greater than 1. The inverse strings NS are a set of multiple memory cells connected in series. Each inverse string NS includes, for example, memory cells MC0, MC1, MC2, MC3, ..., MCn-2 and MCn-1, and select transistors ST1 and ST2. Here, n is an integer of 1 or greater than 1. The memory cell MC (also referred to as the memory cell transistor) is a field-effect transistor including a control gate and a charge storage layer. Select transistors ST1 and ST2 are switching components. Each of the select transistors ST1 and ST2 is used to select the string cell SU at various operation times. In each series and serial number NS, memory cells MC0, ..., MCn-1 are connected in series. The drain of selector ST1 is connected to the associated bit line BL. The source of selector ST1 is connected to one end of the series-connected memory cells MC0, ..., MCn-1. The drain of selector ST2 is connected to the other end of the series-connected memory cells MC0, ..., MCn-1. The source of selector ST2 is connected to the source line SL. Within the same block BLK, the control gates of memory cells MC0, MC1, MC2, MC3, ..., MCn-2 and MCn-1 are respectively connected to the word lines WL0, WL1, WL2, WL3, ..., WLn-2 and WLn-1 that share the multiple inverse and string connections. The gates of the select transistor ST1 in string units SU0, SU1, SU2, SU3 and SU4 are respectively connected to the select gate lines SGD0, SGD1, SGD2, SGD3 and SGD4 that share the multiple inverse and string connections. The gate of the select transistor ST2 provided within the same block BLK is shared by the select gate line SGS that shares the multiple inverse and string connections. In the circuit configuration of the memory cell array 31 described above, bit lines BL are shared, for example, by inverse strings NS, which are assigned the same row address CAd in each string cell SU. Source lines SL are shared, for example, among the multiple blocks BLK. A collection of multiple memory cells (MCs) that are commonly connected to the word line WL in a serial unit (SU) is called, for example, a cell (CU). A block (BLK) includes multiple cell CUs. The data stored in a cell CU, which includes multiple memory cells (MCs), corresponds to one page of data, and each of the multiple memory cells (MCs) stores one bit of data based on a threshold voltage. A cell CU can store two or more pages of data based on the number of bits of data stored in each memory cell (MC). In this disclosed embodiment, a memory cell (MC) can store 4 bits of data. That is, the memory cell (MC) in this disclosed embodiment is a quad-level cell (QLC) for storing 4 bits of data. In this case, the data stored in the cell CU corresponds to four pages of data. The number of bits of data that can be stored in a memory cell (MC) can be any positive integer. For example, a memory cell (MC) can be a multi-level cell (MLC) for storing 2 bits of data, a triple-level cell (TLC) for storing 3 bits of data, or a penta-level cell (PLC) for storing 5 bits of data. Note that the circuit configuration of the memory cell array 31 is not limited to the configuration described above. For example, the number of string cells SU provided in each block BLK and the number of memory cells MC and select transistors ST1 and ST2 provided in each inverse and string NS can be any number. The critical voltage distribution of the memory cells... The threshold voltage distribution of memory cells (MCs) will be illustrated with reference to Figure 4. Figure 4 is a diagram illustrating an example of the relationship between the threshold voltage distribution of memory cells (MCs) and the data stored in the memory cells (MCs). The horizontal axis of Figure 4 represents the threshold voltage of the memory cells (MCs). The vertical axis of Figure 4 represents the number of memory cells (MCs). As shown in Figure 4, when the memory cell MC stores 4 bits of data, the distribution of the threshold voltage is divided into 16 distributions. The 16 threshold voltage distributions are named sequentially from the lowest threshold voltage as "St0" state, "St1" state, ..., "St14" state and "St15" state. In addition, voltages V1, V2, ..., and V15 are used during write operations (e.g., applied to the gate of memory cell MC via the selected word line WL) to verify the "St1", "St2", ..., "St15" states (hereinafter referred to as "verification voltages"). Voltage VREAD is applied to the unselected word line WL during read operations. When voltage VREAD is applied to the gate of memory cell MC, memory cell MC is turned on regardless of the data stored in it. The relationship between these voltage values ​​is V1 < V2 < V3 < V4 < V5 < V6 < V7 < V8 < V9 < V10 < V11 < V12 < V13 < V14 < V15 < VREAD. The "St0" state corresponds to the erase state of the memory cell MC. The "St1", "St2", ..., and "St15" states correspond to states where charge is injected into the charge storage layer of the memory cell MC and data is stored in the charge storage layer of the memory cell MC. The threshold voltage of the memory cell MC in the "St0" state is lower than voltage V1. The threshold voltages of the memory cells MC in the "St1" through "St14" states are equal to or higher than voltages V1 through V14, and lower than voltages V2 through V15, respectively. The threshold voltage of the memory cell MC in the "St15" state is equal to or higher than voltage V15 and lower than voltage VREAD. The verification voltage and read voltage (corresponding to each state) applied to the gate of the memory cell MC via the selected word line WL during write and read operations may be the same or different. For simplicity, the case where the verification voltage and read voltage have the same set value will be described below. In the following text, each of the read operations using voltages V1, V2, ..., V15 is referred to as read operation R1, R2, ..., R15. Read operation R1 determines whether the threshold voltage of memory cell MC is lower than voltage V1. Read operation R2 determines whether the threshold voltage of memory cell MC is lower than voltage V2. Read operation R3 determines whether the threshold voltage of memory cell MC is lower than voltage V3. This also applies to other read operations. As described above, by making the threshold voltage fall within any of the 16 threshold voltage distributions, each memory cell MC can be in 16 different states. By assigning these states to the binary notation "0000", ..., and "1111", each memory cell MC can store 4 bits of data. Hereinafter, the 4 bits of data are referred to sequentially from the bottommost bit as the bottom bit, middle bit, top bit, and top bit. Furthermore, the set of bottom bits in the memory cells MC provided within the same cell unit CU is called the bottom page, the set of middle bits is called the middle page, the set of top bits is called the top page, and the set of top bits is called the top page. In the example of Figure 4, data is assigned to the "lower part / middle part / upper part / top part" of the memory cell MC provided in each state, as shown below. "St0" state: "1111" data "St1" state: "1110" data "St2" state: "1100" data "St3" state: "1101" data "St4" state: "1001" data "St5" state: "1011" data "St6" state: "0011" data "St7" state: "0010" data "St8" state: "1010" data "St9" state: "1000" data "St10" state: "0000" data "St11" state: "0001" data "St12" state: "0101" data "St13" state: "0111" data "St14" state: "0110" data "St15" state: "0100" data The data assigned to each state is not limited to this instance. When reading data assigned in this manner, the lower part is determined by read operations R6, R8, and R10. The middle part is determined by read operations R4 and R12. The upper part is determined by read operations R2, R5, R9, R13, and R15. The top part is determined by read operations R1, R3, R7, R11, and R14. In the memory system 1 of this disclosed embodiment, four pages of data are written to the reverse memory 30 by a first write operation (hereinafter also referred to as MLC programming) that writes data to the lower page and the middle page, and a second write operation (hereinafter also referred to as fine programming) that writes data to the lower page and the middle page and data to the upper page and the top page after the first write operation. This will be described later. During the second write operation, the lower page data and middle page data used in the second write operation are prepared by loading data from inside or outside the reflex and memory 30. Data loading methods for lower / middle pages include internal data load (IDL) and external data load (EDL). IDL is a method for loading (providing) lower / middle page data for a second write operation onto the memory cell array 31 inside the reflexive memory 30. EDL is a method of reflexively loading (providing) lower / middle page data for a second write operation from outside the memory 30 (e.g., RAM 16 of the memory controller 10). In the memory system 1 of this disclosed embodiment, the data loading method for the lower page data and intermediate page data for the second write operation is determined based on a specific index, which is related to the reliability of the lower page data and intermediate page data written to the memory 30 by the first write operation. For example, the reliability of data written to the memory cell array 31 of the reverse memory 30 varies depending on the period during which the data is stored in the memory cell array 31 or the operating state of the reverse memory 30 (e.g., temperature and / or usage cycle). (a-1-4) Write management circuit Figure 5 is a block diagram illustrating a configuration example of the write management circuit 18 of the memory controller 10 in the memory system 1 of this disclosed embodiment. As shown in Figure 5, the write management circuit 18 includes a data loading selector 181 and a global clock 182. Data loading selector 181 selects a data loading method for either IDL or EDL based on a specific index related to the reliability of the lower page data and middle page data written by the first write operation. Global clock 182 is a timer. Global clock 182, for example, begins measuring time from the first power-on of memory system 1. When the power supply to memory system 1 is cut off, global clock 182 can temporarily stop measuring time. The time measured before the power was cut off can be stored in reverse memory 30. When power is restored to memory system 1 from the power-off state, global clock 182 can resume measuring time. Global clock 182 can resume measuring time from the time measured before the power was cut off. In the write management circuit 18, the data load selector 181 records the completion time of the first write operation, measured by the global clock 182, in the management table TBL1. The management table TBL1 is stored, for example, in RAM 16. The management table TBL1 may also be stored in a storage area (e.g., a temporary register) provided in the write management circuit 18. Figure 6 is a diagram of the management table TBL1 in the memory system 1 of this disclosed embodiment. The management table TBL1 is a log table used to record the corresponding values ​​of each of the following: the entry for the word line number (word line address) targeted by the first write operation; the entry for the string unit number targeted by the first write operation; and the entry for the completion time of the first write operation. For example, one management table TBL1 is prepared for one write destination block. This is because multiple write destination blocks can be used concurrently. In the following text, the management table TBL1 is also referred to as the MLC programmatic log table TBL1. The data loading selector 181 refers to the MLC staging log table TBL1 to select the data loading method for the lower page data and the middle page data during the second write operation. The data loading selector 181 determines the data loading method for the second write operation time based on the current time represented by the global clock 182 (i.e., the time immediately before the second write operation is performed, or the time when the data loading method is selected) and the completion time of the first write operation located at the corresponding address in the MLC staging log table TBL1. For example, data loading selector 181 compares the difference between the current time and the completion time of the first write operation with a threshold value used to determine the data loading method. When the difference is greater than the threshold value, data loading selector 181 selects EDL. Thus, EDL is used as the data loading method for bottom / middle page data in the second write operation. When the difference is equal to or less than the threshold value, data loading selector 181 selects IDL. Thus, IDL is used as the data loading method for bottom / middle page data in the second write operation. (b) Operation An operational example of the memory system 1 according to the present disclosure will be described with reference to Figures 7 to 20. (b-1) Overview of write operations An overview of the write operations of memory system 1 and memory 30 in the present disclosed embodiment will be provided. The write operation (write sequence) of memory 30 includes programming operations and verification operations (also known as programmed verification). By repeating the combination of programming and verification operations, the threshold voltage of the memory cell MC is increased to the target level. Programming is an operation that increases the threshold voltage of a memory cell MC by injecting electrons into the charge storage layer of the memory cell MC (or maintains the threshold voltage by suppressing injection). In the following text, the operation of increasing the threshold voltage of the memory cell MC is referred to as "0" programming. For example, the threshold voltage of a memory cell MC in the "St0" state is increased to include the "St1" state, and this is referred to as "0" programming. The voltage (e.g., voltage VSS) used for "0" programming is applied to the bit line BL, which is the target of "0" programming. Simultaneously, the operation of maintaining the threshold voltage of the memory cell MC is referred to as "1" programming or write suppression. The voltage (e.g., positive voltage) used for "1" programming is applied to the bit line BL, which is the target of "1" programming. The verification operation is performed by reading data from the memory cell (MC) after a programmed operation to determine whether the threshold voltage of the memory cell (MC) has reached the target level. Memory cells (MCs) whose threshold voltage reaches the target level are set to suppress writes. In this disclosed embodiment, the write operation is performed in two separate stages. Specifically, the write operation of the four pages of data corresponding to a specific cell unit CU is performed in the two stages of the first write operation (MLC programming) and the second write operation (fine programming). (b-1-1) First write operation The first write operation (MLC programming) of the memory system 1 of the present disclosure embodiment will be described with reference to FIG7. Figure 7 is a graph showing the change in the threshold voltage distribution of the memory cell MC caused by the first write operation. When the first write operation is performed, the threshold voltage of the memory cell MC increases based on the written data, and four threshold voltage distributions are formed. As shown in Figure 7, the first write operation forms states "M0", "M1", "M2", and "M3". In the first write operation, for example, the threshold voltage distribution of state "M0" is formed by multiple memory cells MC in which "11" data is written. Here, the notation "kh" data means that the lower bit is "k" data and the middle bit is "h" data. The threshold voltage distribution of state "M1" is formed by multiple memory cells MC in which "10" data is written. The threshold voltage distribution of state "M2" is formed by multiple memory cells MC in which "00" data is written. The threshold voltage distribution of state "M3" is formed by multiple memory cells MC in which "01" data is written. Sequencer 36 uses voltages VM1, VM2, and VM3 as verification voltages. Voltage VM1 is the verification voltage used when writing "10" data. Voltage VM1 is equal to or higher than voltage V1 and lower than voltage V4. Voltage VM2 is the verification voltage used when writing "00" data. Voltage VM2 is equal to or higher than voltage V4 and lower than voltage V6. Voltage VM3 is the verification voltage used when writing "01" data. Voltage VM3 is equal to or higher than voltage V6 and lower than voltage V12. The threshold voltage of a memory cell MC in state "M0" is lower than voltage V1. The threshold voltage of a memory cell MC in state "M1" is equal to or higher than voltage VM1 and lower than voltage V5. The threshold voltage of a memory cell MC in state "M2" is equal to or higher than voltage VM2 and lower than voltage V7. The threshold voltage of a memory cell MC in state "M3" is equal to or higher than voltage VM3 and lower than voltage V13. In the following text, the stage in which the first write operation is performed is referred to as the MLC stage. A memory cell (MC) that has undergone the first write operation but has not yet undergone the second write operation is referred to as a memory cell (MC) in the MLC state. (b-1-2) Second Write Operation The second write operation (fine programming) of the memory system 1 of the present disclosure embodiment will be described with reference to FIG8. Figure 8 is a graph showing the change in the threshold voltage distribution of the memory cell MC caused by the second write operation. When the second write operation is performed, the threshold voltage of the memory cell MC increases based on the written data, forming 16 threshold voltage distributions. As shown in Figure 8, in the second write operation, for example, the threshold voltage distribution from state "M0" forms the threshold voltage distributions for states "St0", "St1", "St2", and "St3". The threshold voltage distribution from state "M1" forms the threshold voltage distributions for states "St4", "St5", "St8", and "St9". The threshold voltage distribution from state "M2" forms the threshold voltage distributions for states "St6", "St7", "St10", and "St11". The threshold voltage distribution from state "M3" forms the threshold voltage distributions for states "St12", "St13", "St14", and "St15". For example, when the threshold voltage distribution of the "M0" state changes to the threshold voltage distribution of the "St3" state, the data stored in the memory cell MC changes from the data of the "M0" state ("11" data) to the data of the "St3" state ("1101" data). For example, when the threshold voltage distribution of the "M1" state changes to the threshold voltage distribution of the "St4" state, the data stored in the memory cell MC changes from the data of the "M1" state ("10" data) to the data of the "St4" state ("1001" data). For example, when the threshold voltage distribution of the "M2" state changes to the threshold voltage distribution of the "St7" state, the data stored in the memory cell MC changes from the data of the "M2" state ("00" data) to the data of the "St7" state ("0010" data). For example, when the threshold voltage distribution of the "M3" state changes to the threshold voltage distribution of the "St14" state, the data stored in the memory cell MC changes from the data of the "M3" state ("01" data) to the data of the "St14" state ("0110" data). In the following text, the stage in which the second write operation is performed is referred to as the fine-grained stage. (b-1-3) Execution order of write operations Figure 9 illustrates an example of the selection order of character lines WL and string units SU when writing data to a specific block BLK. The solid-lined quadrilateral corresponding to the intersection of each character line WL and each string unit SU represents a cell CU. The upper stage, separated by the dashed lines of the quadrilateral, represents the write operation in the MLC stage. The lower stage, separated by the dashed lines of the quadrilateral, represents the write operation in the fine-grained stage. The values ​​of the upper and lower stages of the quadrilateral represent the execution order (hereinafter referred to as the "write order") of the MLC programming and fine-grained programming of the plurality of memory cells MC in each cell CU of a specific block BLK. As shown in Figure 9, as the first to fifth operations, the sequencer 36 performs the first write operation by selecting character line WL0 and sequentially selecting string units SU0 to SU4. As a sixth operation, sequencer 36 performs a first write operation by selecting string unit SU0 and selecting character line WL1. As a seventh operation, sequencer 36 performs a second write operation by selecting string unit SU0 and selecting character line WL0. As the eighth to fifteenth operations, the sequencer 36 uses the same procedure as the sixth and seventh operations to alternately execute the first write operation of the selection character line WL1 and the second write operation of the selection character line WL0 while sequentially selecting the string units SU1, ..., and SU4. As the sixteenth to twenty-fifth operations, the sequencer 36 performs the first write operation of selection character line WL2 and the second write operation of selection character line WL1 alternately while sequentially selecting string units SU0, ..., and SU4, in the same manner as the sixth to fifteenth operations. Subsequently, in the same manner as operations (26+10p) to (35+10p), sequencer 36 alternately performs the first write operation of selection character line WL(3+p) and the second write operation of selection character line WL(2+p) while sequentially selecting string units SU0, ..., and SU4. Here, p is an integer of 0 or greater than 0. In the order described above, the first write operation and the second write operation are performed sequentially on the cell unit CU specified by the data writing target address (hereinafter also referred to as the selected address). Note that the reverse memory 30 performs a second write operation on the cell unit CU specified by the selected address, without performing an erase operation on the block BLK including the cell unit CU between the first write operation (MLC programming) and the second write operation (fine programming) performed on the cell unit CU. (b-2) Data loading method The data loading method in the write operation will be explained with reference to Figures 10 to 12. As described above, in the second write operation (fine-grained programming), the lower page data and the middle page data are prepared internally in reverse memory 30 using IDL, or externally in reverse memory 30 using EDL. (b-2-1) IDL The IDL when fine programming is performed in the memory system 1 of the present disclosure embodiment will be described with reference to FIG10. Figure 10 is a sequence diagram illustrating IDL in fine-grained programming. As shown in Figure 10, in this embodiment, the memory system 1 performs MLC programming (first write operation) before performing fine programming (second write operation). In MLC programming, the SoC 100 of the memory controller 10 loads lower page data and intermediate page data from RAM 16. RAM 16 stores the lower page data and intermediate page data received from the host 2. The SoC 100 sends the lower page data and middle page data loaded from RAM 16, along with commands and addresses for MLC programming, to the reverse memory 30. In this way, the sense amplifier module 39 of the reverse memory 30 receives the lower page data and middle page data (referred to as data in) via the data latch 40. The inverted memory 30 programs the lower page data and middle page data in the sense amplifier module 39 into the cell unit CU with the address specified by the inverted interface circuit 17. In this way, the memory cell array 31 stores the two pages of lower / middle page data. In the memory system 1 of this disclosed embodiment, MLC programming is performed as described above. In this embodiment, the memory system 1 performs fine programming on the cell unit CU specified by the address in which MLC programming is performed. SoC 100 loads top page data and top page data from RAM 16. RAM 16 stores the top page data and top page data received from host 2. When using IDL for fine-grained programming, SoC 100 sends the upper and top page data loaded from RAM 16 along with commands and addresses to inverted memory 30, without transferring the lower / middle page data to inverted memory 30. In this way, the sense amplifier module 39 receives the upper and top page data. When performing fine-grained programming using IDL, the lower / middle page data is loaded from the memory cell array 31 into the sense amplifier module 39 inside the memory 30. In this way, the sensing amplifier module 39 stores the upper / top page data from the SoC 100 and the lower / middle page data from the memory cell array 31. The reflex memory 30 programs the lower page data, middle page data, upper page data, and top page data from the sense amplifier module 39 into the cell unit CU with the address specified by the reflex interface circuit 17. In this way, the memory cell array 31 stores the four pages of lower / middle / upper / top page data. As shown in FIG10, the IDL prepares the lower page data and middle page data for fine programming by reading the lower page data and middle page data from the memory cell array 31 and loading the lower page data and middle page data into the sense amplifier module 39 inside the reverse memory 30. (b-2-2) EDL The EDL when fine programming is performed in the memory system 1 of the present disclosure embodiment will be described with reference to Figures 11 and 12. The EDL for finely programmed data prepares the bottom / intermediate page data from RAM 16. The EDL may further include ECC processing for the bottom / intermediate page data. As shown in Figure 11, the lower page data and middle page data are programmed into the memory cell array 31 in the same way as in the example of Figure 10 by MLC programming. When performing fine programming, SoC 100 loads top / top page data from host 2 from RAM 16. As described above, EDL prepares the lower page data and middle page data outside the memory 30. In the example of Figure 11, RAM 16 stores lower / intermediate page data provided by host 2. This lower / intermediate page data is the same as the lower / intermediate page data stored in the cell unit CU specified by the selected address in which fine-grained programming is to be performed. Interface circuitry 17 loads the lower / intermediate page data from RAM 16. SoC 100 sends the lower / middle / upper / top page data loaded from RAM 16 along with commands and addresses to inverted memory 30. The sense amplifier module 39 then receives the lower / middle / upper / top page data. The reflex memory 30 programs the lower / middle / upper / top page data from the sense amplifier module 39 into the cell CU with the address specified by the reflex interface circuit 17. In this way, the memory cell array 31 stores four pages of data for the lower / middle / upper / top pages. Figure 12 shows a different EDL data loading method than the example in Figure 11. As shown in Figure 12, the lower page data and middle page data are programmed into the memory cell array 31 in the same way as in the examples of Figures 10 and 11 by MLC programming. In the example of Figure 12, when a request for fine-grained programming is made, the memory controller 10 (SoC 100) reads the lower page data and intermediate page data from the cell CU specified at the corresponding address of the memory 30. The ECC circuit 14 of the SoC 100 performs ECC processing on the lower page data and intermediate page data. This generates ECC-processed lower page data and intermediate page data. SoC 100 sends the ECC-processed lower / middle page data to RAM 30. The sense amplifier module 39 receives the ECC-processed lower / middle page data. The ECC-processed lower / middle page data can be stored in RAM 16 before being sent to the sense amplifier module 39. The system chip 100 loads the top / top page data from RAM 16. The SoC 100 sends the top / top page data, along with commands and addresses, to the inverted memory 30. The sense amplifier module 39 receives the top / top page data. The reflex memory 30 programs the lower / middle / upper / top page data from the sense amplifier module 39 into the cell CU with the address specified by the reflex interface circuit 17. In this way, the memory cell array 31 stores four pages of data for the lower / middle / upper / top pages. The fine-grained programming of the EDL using either Figure 11 or Figure 12 can be applied to memory system 1. For example, when RAM 16 has a large storage capacity, memory system 1 executes the fine-grained programming of the instance in Figure 11. Memory system 1 can be configured such that the method of fine-grained programming to be executed can be switched to either the instance in Figure 11 or the instance in Figure 12, depending on a request from host 2 or the operating state of memory system 1. As shown in Figures 11 and 12, the EDL prepares finely programmed lower page data and intermediate page data for use outside of memory 30. (b-3) Command Sequence The command sequence of the memory system 1 according to the present disclosure embodiment will be described with reference to Figures 13 to 15B. (b-3-1) Command sequence of the first write operation Figure 13 is a diagram illustrating the command sequence of a first write operation (MLC programming) in the memory system 1 of this disclosed embodiment. As shown in Figure 13, when the memory controller 10 instructs the reverse memory 30 to perform MLC programming, the memory controller 10 sends multiple command sets 500 (500-1, 500-2) to the reverse memory 30 during the MLC programming stage (MLC stage). The memory controller 10 sends command set 500-1 to the reverse memory 30. Command set 500-1 is a signal group related to writing data to the next page. Command set 500-1 includes commands 501, 502-1, 503 and 507, addresses 504 (504-1 and 504-2) and 505 (505-1, 505-2, 505-3 and 505-4), and write data 506-1. Commands 501, 502-1, and 503 include command codes "A1h", "01h", and "80h", respectively. The reverse memory 30 receives commands 501, 502-1, and 503. Command 501 with command code "A1h" is a prefix command to be added when a command is given for a write operation in the MLC stage (or a read operation from a memory cell MC in the MLC state). Command 502-1 with command code "01h" is a command used to instruct the reverse memory 30 to perform an operation corresponding to the data on the first page (lower page). Command 503 with command code "80h" is a command indicating the start of inputting the write target address. Following command 503 with command code "80h", memory controller 10 sends addresses 504 and 505 to reverse memory 30. Address 504 includes addresses 504-1 and 504-2. Address 505 includes addresses 505-1, 505-2, 505-3, and 505-4. Reverse memory 30 receives addresses 504 and 505. Addresses 504-1 and 504-2 are row addresses. Addresses 505-1, 505-2, 505-3, and 505-4 are column addresses. Row address 504 is transmitted in two cycles. Column address 505 is transmitted in four cycles. The number of cycles used to transmit each address is appropriately varied depending on the size of memory cell array 31 (e.g., the number of blocks BLK, the number of word lines WL). After transmitting addresses 504 and 505, memory controller 10 sends the lower page data 506-1 as write data to reverse memory 30. Reverse memory 30 receives the lower page data 506-1. After transmitting the next page data 506-1, the memory controller 10 sends a command 507 with command code "1Ah" to the reverse memory 30. The reverse memory 30 receives the command 507. The command 507 with command code "1Ah" is a command used to transfer data from the data latch 40 in the reverse memory 30 to the sense amplifier module 39. After receiving command 507 with command code "1Ah", the reverse memory 30 enters a busy state. Therefore, the reverse memory 30 changes the signal level of the ready / busy signal RBn from the "H" level to the "L" level. During the period when the signal level of the ready / busy signal RBn is at the "L" level, the data 506-1 on the lower page is transmitted from the data latch 40 to the sense amplifier module 39. After the sense amplifier module 39 stores the lower page data 506-1, the reverse memory 30 enters the ready state. Therefore, the reverse memory 30 changes the signal level of the ready / busy signal RBn from the "L" level to the "H" level. After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends command set 500-2 to the ready memory 30. Command set 500-2 is a group of signals related to writing intermediate page data. Command set 500-2 includes commands 502-2, 503 and 508, addresses 504 and 505, and write data 506-2. Commands 502-2 and 503 include command codes "02h" and "80h" respectively. The reverse memory 30 receives commands 502-2 and 503. Command 502-2 with command code "02h" is a command used to instruct the reverse memory 30 to perform an operation corresponding to the data on the second page (middle page). Following command 503, which transmits command code "80h", memory controller 10 sends addresses 504 and 505 to reverse memory 30. Reverse memory 30 receives addresses 504 and 505. The values ​​of addresses 504 and 505 provided in command set 500-2 are the same as the values ​​of addresses 504 and 505 provided in command set 500-1. After transmitting addresses 504 and 505, memory controller 10 sends intermediate page data 506-2 as write data to reverse memory 30. Reverse memory 30 receives intermediate page data 506-2. After transmitting intermediate page data 506-2, the memory controller 10 sends command 508 with command code "10h" to the reverse memory 30. The reverse memory 30 receives command 508. Command 508 with command code "10h" is a command used to perform programmed operations. Based on the received command 508 with command code "10h", the reverse memory 30 performs the writing of lower / middle page data (MLC programming) in the sense amplifier module 39. The reverse memory 30 enters a busy state during the execution of MLC programming. During the MLC programming cycle tPROG, the reverse memory 30 changes the signal level of the ready / busy signal RBn from the "H" level to the "L" level. During the period tPROG in which the ready / busy signal RBn is at the "L" level, two pages of data are written to the cell CU specified by the write target address in the memory cell array 31. When the MLC programming is complete, the reverse memory 30 enters the ready state. Therefore, the reverse memory 30 changes the signal level of the ready / busy signal RBn from the "L" level to the "H" level. As described above, the memory system 1 of this disclosed embodiment can perform MLC programming based on the command sequence of FIG13. (b-3-2) Command sequence for the second write operation When a request is made to write top / middle page data to an address containing lower / middle page data, a second write operation (fine-grained programming) is performed on the address based on the command sequence in Figure 14, Figure 15A, or Figure 15B. (b-3-2-1) Command sequence for the second write operation using IDL Figure 14 is a diagram illustrating a finely programmed sequence of commands using IDL in the memory system 1 of this disclosed embodiment. When it is desired to write data to an address that has been programmed using the MLC method according to the command sequence in FIG13, the memory system 1 of this disclosed embodiment performs fine programming on the address. As shown in Figure 14, when the memory controller 10 instructs the reverse memory 30 to perform fine programming using IDL, the memory controller 10 sends multiple command sets 500 (500-3, 500-4) to the reverse memory 30 for performing fine programming during the fine programming stage (fine stage). In this disclosed embodiment, the memory controller 10 sends a signal 555 to the reverse memory 30 to notify that an IDL has been selected in fine-grained programming. The reverse memory 30 receives the signal 555. The signal 555 is a flag or prefix command indicating that the data loading method used for fine-grained programming is an IDL. The signal 555 is a one-bit or more signal. After transmitting signal 555, memory controller 10 sends command set 500-3 to reverse memory 30. Command set 500-3 is a signal group related to writing data to the upper page. Command set 500-3 includes commands 502-3, 503 and 507, addresses 504 (504-1 and 504-2) and 505 (505-1, 505-2, 505-3 and 505-4), and write data 506-3. Commands 502-3 and 503 include command codes "03h" and "80h" respectively. The reverse memory 30 receives commands 502-3 and 503. Command 502-3 with command code "03h" is a command used to instruct the reverse memory 30 to perform an operation corresponding to the data on the third page (top page). Following command 503, which transmits command code "80h", memory controller 10 sends addresses 504 and 505 to reverse memory 30. Reverse memory 30 receives addresses 504 and 505. For example, the values ​​of addresses 504 and 505 provided in command set 500-3 are the same as the values ​​of addresses 504 and 505 provided in command sets 500-1 and 500-2 used for MLC programming. After transmitting addresses 504 and 505, the memory controller 10 sends the upper page data 506-3 as write data to the reverse memory 30. The reverse memory 30 receives the upper page data 506-3. After transmitting the upper page data 506-3, the memory controller 10 sends a command 507 with command code "1Ah" to the reverse memory 30. The reverse memory 30 receives the command 507. After receiving command 507 with command code "1Ah", reverse memory 30 enters a busy state. During the period when the signal level of the ready / busy signal RBn is "L", the data latch 40 in the reflexive data 506-3 and memory 30 of the upper page is transmitted to the sense amplifier module 39. After the sensing amplifier module 39 stores the upper page data 506-3, the reverse memory 30 enters the ready state. After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends command set 500-4 to the ready memory 30. Command set 500-4 is a group of signals related to writing top page data. Command set 500-4 includes commands 502-4, 503 and 508, addresses 504 and 505, and write data 506-4. Commands 502-4 and 503 include command codes "04h" and "80h" respectively. The reverse memory 30 receives commands 502-4 and 503. Command 502-4 with command code "04h" is a command used to instruct the reverse memory 30 to perform an operation corresponding to the data on the fourth page (top page). Following command 503, which transmits command code "80h", memory controller 10 sends addresses 504 and 505 to reverse memory 30. Reverse memory 30 receives addresses 504 and 505. The values ​​of addresses 504 and 505 provided in command set 500-4 are the same as the values ​​of addresses 504 and 505 provided in command sets 500-1, 500-2, and 500-3. After transmitting addresses 504 and 505, memory controller 10 sends top page data 506-4 as write data to reverse memory 30. Reverse memory 30 receives top page data 506-4. After transmitting the top page data 506-4, the memory controller 10 sends command 508 with command code "10h" to the reverse memory 30. The reverse memory 30 receives command 508. For example, in the fine-grained stage of using IDL, after transmitting command sets 500-3 and 500-4 related to the upper / top page data, the lower / middle page data is loaded from the memory cell array 31 to the sense amplifier module 39. The reverse memory 30 performs the writing (fine programming) of lower / middle / upper / top page data in the sense amplifier module 39 based on the received command 508 with command code "10h". The reverse memory 30 enters a busy state based on the received command 508 with command code "10h". During the period tPROG in which the ready / busy signal RBn is at the "L" level, four pages of data are written to the cell CU specified by the write target address of the memory cell array 31. When the fine programming is complete, memory 30 enters the ready state. In the memory system 1 of this disclosed embodiment, fine programming using IDL is performed as described above. As described above, the memory system 1 of this disclosed embodiment can perform fine-grained programming using IDL based on the command sequence in FIG14. (b-3-2-2) Command sequence for the second write operation using EDL Figure 15A is a diagram illustrating a finely programmed command sequence using EDL in a memory system 1 according to an embodiment of this disclosure. In the case where the lower / middle page data prepared by EDL is generated by ECC processing (see Figure 12), memory system 1 performs reflexive operation and memory 30 reads the lower / middle page data. As shown in Figure 15A, during the fine-grained stage of using EDL, the memory controller 10 sends multiple command sets 700 (700-1, 700-2, 700-3, 700-4) to the reflex memory 30 for the reflex memory 30 to read the lower / middle page data. The memory controller 10 sends a command set 700-1 to the memory 30. The command set 700-1 is a group of signals related to reading the lower page data from the memory cell array 31 to the sense amplifier module 39. Command set 700-1 includes commands 501, 502-1, 701 and 702, and addresses 504 and 505. Commands 501, 502-1, and 701 include command codes "A1h", "01h", and "00h", respectively. The reverse memory 30 receives commands 501, 502-1, and 701. Command 701, with command code "00h", indicates the start of inputting and reading the target address. Following command 701, which transmits command code "00h", the memory controller 10 sends the target addresses 504 and 505 for reading the lower page data to the reverse memory 30. The reverse memory 30 receives addresses 504 and 505. After transmitting addresses 504 and 505, the memory controller 10 sends command 702 with command code "30h" to the reverse memory 30. The reverse memory 30 receives command 702. Command 702 with command code "30h" is a command used to instruct the reverse memory 30 to output the data read from the target address from the memory cell array 31 to the data latch 40 (sensor amplifier module 39). After receiving command 702 with command code "30h", the reverse memory 30 enters a busy state. During cycle tR, the reverse memory 30 reads the cell unit CU represented by the lower page data free addresses 504 and 505 into the sense amplifier module 39. After the sensor amplifier module 39 stores the data of the next page, the memory 30 enters the ready state. After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 700-2 to the inverter and memory 30. The command set 700-2 is a group of signals related to the transfer of data from the inverter and memory 30 to the memory controller 10. Command set 700-2 includes commands 703 and 704 and addresses 504 and 505. The memory controller 10 sends command 703 with command code "05h" to the reverse memory 30. Command 703 with command code "05h" is used to instruct the reverse memory 30 to perform an operation (cache read) to output data from the data latch 40 to the memory controller 10 starting from the specified row address 504. After transmitting command 703 with command code "05h", memory controller 10 sends addresses 504 and 505 to inverse memory 30. The values ​​of addresses 504 and 505 in command set 700-2 are the same as the values ​​of addresses 504 and 505 in command set 700-1. After transmitting addresses 504 and 505, the memory controller 10 sends command 704 with command code "E0h" to the reverse memory 30. Command 704 with command code "E0h" is a command used to instruct the reverse memory 30 to output data to the memory controller 10. The reverse memory 30 sequentially receives command 703, addresses 504 and 505, and command 704. Based on command codes "05h" and "E0h" of commands 703 and 704, the reverse memory 30 sends the lower page data 705-1 from the sense amplifier module 39 to the memory controller 10 via the data latch 40. The memory controller 10 receives the lower page data 705-1. After receiving the read lower page data 705-1, the memory controller 10 sends a command set 700-3 to the memory 30. The command set 700-3 is a group of signals related to reading intermediate page data from the memory cell array 31 to the sense amplifier module 39. Command set 700-3 includes commands 501, 502-2, 701 and 702, and addresses 504 and 505. Using the same method as reading the lower page data according to command set 700-1, after the sense amplifier module 39 stores the intermediate page data according to command set 700-3, the memory 30 enters the ready state. After the signal level of the ready / busy signal RBn changes to the "H" level, the memory controller 10 sends a set of commands 700-4 to the memory 30. The set of commands 700-4 includes commands 703 and 704 and addresses 504 and 505. Using the same method as reading the lower page data according to command set 700-2, memory 30 sends intermediate page data 705-2 to memory controller 10 according to command set 700-4. Memory controller 10 receives intermediate page data 705-2. The memory controller 10 performs ECC processing on each of the received lower page data 705-1 and middle page data 705-2. By performing ECC processing, lower page data and middle page data that have been processed by ECC are generated. After ECC processing, the memory controller 10 performs the writing of bottom / middle / top / top page data (fine programming). For example, in this disclosed embodiment, the memory controller 10 sends a signal 777 to the reverse memory 30 to notify that an EDL has been selected in fine-grained programming. The reverse memory 30 receives the signal 777. The signal 777 is a flag or prefix command indicating that the data loading method used for fine-grained programming is an EDL. The signal 777 is a one-bit or more signal. Therefore, in this disclosed embodiment, the memory controller 10 can notify the reverse memory 30 to perform fine programming using EDL. After transmitting signal 777, memory controller 10 sends command set 500-A related to the lower page data to reverse memory 30. Command set 500-A basically includes the same commands, addresses, and write data as command set 500-1 illustrated with reference to FIG13, but does not include command 501 with command code "A1h". Additionally, the write data 506-A provided in command set 500-A is the lower page data after ECC processing. Note that signal 777 can be any signal (command) provided in command set 500-A. Reverse memory 30 receives command set 500-A. Using the same method as described with reference to FIG13, after receiving the command 507 of the command code "1Ah" provided in the command set 500-A, the memory 30 stores the ECC-processed lower page data 506-A in the sense amplifier module 39. After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a command set 500-B related to intermediate page data to the reverse memory 30. Command set 500-B includes the same commands, addresses, and write data as command set 500-2 illustrated with reference to FIG13. The write data 506-B provided in command set 500-B is intermediate page data after ECC processing. The reverse memory 30 receives command set 500-B. Using the same method as described with reference to FIG13, after receiving the command 507 of the command code "1Ah" provided in the command set 500-B, the memory 30 stores the intermediate page data 506-B after ECC processing in the sense amplifier module 39. After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a set of commands 500-C related to the upper page data to the memory 30. The set of commands 500-C includes the same commands, addresses, and write data as the set of commands 500-3 illustrated with reference to FIG14. Using the same method as described with reference to FIG14, after receiving the command 507 of the command code "1Ah" provided in the command set 500-C, the memory 30 stores the upper page data 506-C in the sense amplifier module 39. After the signal level of the ready / busy signal RBn changes from the "L" level to the "H" level, the memory controller 10 sends a set of commands 500-D related to the top page data to the memory 30. The set of commands 500-D includes the same commands, addresses, and write data as the set of commands 500-4 illustrated with reference to FIG14. Using the same method as described with reference to FIG14, the memory 30 writes the lower / middle / upper / top page data in the sense amplifier module 39 to the memory cell array 31 by fine programming of command 508 based on command code "10h" provided in command set 500-D. In the memory system 1 of this disclosed embodiment, fine programming using EDL is performed as described above. Note that in the case where the memory controller 10 transfers lower page data and middle page data from RAM 16 to RAM 30, the memory system 1 of this disclosed embodiment performs fine programming using EDL based on command sets 500-A, 500-B, 500-C, and 500-D, but does not perform operations based on command sets 700-1, 700-2, 700-3, and 700-4. As described above, the memory system 1 of this disclosed embodiment can execute fine-grained programming using EDL based on the command sequence of FIG15A. Figure 15B shows a modified example of a finely programmed command sequence using EDL in the memory system 1 of this disclosed embodiment. As shown in Figure 15B, the lower page data 506-A after ECC processing can be sent from RAM 16 to the reverse memory 30 before reading the intermediate page data. After sending the lower page data 506-A after ECC processing to the reverse memory 30 via command set 500-A, the intermediate page data 705-2 is sent from the reverse memory 30 to the memory controller 10 via read operations according to command sets 700-3 and 700-4. The memory controller 10 performs ECC processing on the intermediate page data 705-2. The memory controller 10 sends the intermediate page data 506-B after ECC processing to the reverse memory 30 using command set 500-B. Subsequently, the memory controller 10 sends the upper page data 506-C and the top page data 506-D to the reverse memory 30. (b-4) Processing flow of write operation The write operation process in the memory system 1 of this disclosed embodiment will be described with reference to Figures 16 to 20. (b-4-1) Basic flow of write operation Figure 16 is a flowchart illustrating the write operation in the memory system 1 of the present disclosure embodiment. The memory controller 10 receives a write request from the host 2 (S1). For example, the memory controller 10 determines to write the requested data as lower page data and middle page data to the memory 30 according to the write order illustrated with reference to FIG9. The memory controller 10 sends a set of commands (S2) to the memory 30 to perform MLC programming (first write operation) based on the write request. The reverse memory 30 executes MLC programming (S3) according to the set of commands from the memory controller 10. Hereby, lower page data and middle page data are written to the memory cell array 31 of the reverse memory 30. The memory controller 10 receives a write request from the host 2 (S4). For example, the memory controller 10 determines to write the requested data as top page data and top page data to the inverse memory 30 (where the address where MLC programming is performed) according to the write order illustrated with reference to FIG9. The memory controller 10 prepares to perform fine programming (second write operation). Note that the writing of bottom page data, middle page data, top page data, and top page data is determined based on a single write request from the host 2. During fine-grained programming, the memory controller 10 determines which of the IDL or EDL to use as the data loading method based on an index related to the reliability of the lower page data and middle page data stored in the memory 30 (S5). The memory controller 10 selects either the IDL or the EDL based on the index (S6). For example, in this disclosed embodiment, either IDL or EDL is selected based on the cycle from the completion of MLC programming to the start of fine programming. When the memory controller 10 determines that IDL is used as the finely programmed data loading method (yes in S6), the memory controller 10 sends a set of commands to instruct the memory 30 to use IDL to perform fine programming (S7A). The reverse memory 30 performs fine-grained programming (S8A) using IDL based on the set of commands from the memory controller 10. When the memory controller 10 determines that EDL is used as a finely programmed data loading method (not in S6), the memory controller 10 sends a set of commands to instruct the memory 30 to use EDL to perform fine programming (S7B). The reverse memory 30 performs fine-grained programming (S8B) using EDL based on the set of commands from the memory controller 10. After performing the fine-grained programming of memory 30, memory system 1 terminates the operation. (b-4-2) Specific example of the first write operation As described above, the memory system 1 of this disclosed embodiment selects the data loading method during the execution of fine programming based on an index of the reliability of the lower / middle page data at the start point of fine programming. Figure 17 is a flowchart illustrating an operational example of the memory system 1 of this disclosed embodiment when MLC programming is executed. Figure 18 is a diagram illustrating an operational example of the memory system 1 of this disclosed embodiment when MLC programming is executed. As shown in Figure 17, during the execution of MLC programming, the memory system 1 of this disclosed embodiment begins to manage information about the index to be used to select the data loading method during the execution of fine programming. The memory controller 10 instructs the reverse memory 30 to perform MLC programming (S100). Herein, MLC programming is performed in the reverse memory 30. The processor 12 of the memory controller 10 detects the completion of MLC programming, for example, in response to a change in the level of the ready / busy signal RBn from the "L" level to the "H" level. The processor 12 notifies the data load selector 181 of the write management circuit 18 of the completion of MLC programming. For example, as shown in FIG18, the processor 12 sends a notification signal ACK1 indicating the completion of MLC programming to the data load selector 181. Data loading selector 181 receives notification signal ACK1 (S101 in Figure 17) indicating completion of MLC programming. Data loading selector 181 acquires the time assumed to be the completion time of MLC programming (MLC programming completion time) t from the global clock 182 of the write management circuit 18 based on the notification signal ACK1 indicating completion of MLC programming. MLC The current time (S102). As shown in Figure 18, the data load selector 181 records the character line number, string cell number, and acquired MLC programming completion time t in the management table (MLC programming log table) TBL1 related to MLC programming in RAM 16. MLC (S103 in Figure 17). Therefore, during the execution of MLC programming, the memory system 1 of this disclosed embodiment can obtain information (here, the MLC programming completion time t). MLC This is used to select the data loading method during the execution of fine-grained programming. As described above, the processing of each cell of the memory controller 10 ends at the time of MLC programming. (b-4-3) Specific example of the second write operation Figure 19 is a flowchart illustrating an operational example of the memory system 1 of this disclosed embodiment when fine programming is performed. Figure 20 is a diagram illustrating an operational example of the memory system 1 of this disclosed embodiment when fine programming is performed. As shown in FIG19, when performing fine programming, the memory system 1 of this disclosed embodiment begins to perform various processes for selecting a data loading method. Memory system 1 determines whether to perform fine programming on a specific address (S110). When it is determined that fine-grained programming will be performed in memory system 1, processor 12 notifies data load selector 181 of the execution of fine-grained programming. For example, as shown in FIG20, processor 12 sends a notification signal ACK2 indicating the execution of fine-grained programming to data load selector 181. Data load selector 181 receives notification signal ACK2. Data loading selector 181 obtains the current time (immediately preceding the start of fine-grained programming) from the global clock 182 based on notification signal ACK2. c (S111 in Figure 19). Data loading selector 181 searches from multiple entries in the MLC programming log table TBL1 for the MLC programming completion time t associated with the character line number and string cell number that are the target of fine programming. MLC Therefore, the data loading selector 181 obtains the MLC programming completion time t associated with the fine-grained programming target address. MLC (S112). Data loading selector 181 uses the current time t c and the obtained MLC programming completion time t MLC Perform calculations. For example, data loading selector 181 executes the current time t. c MLC programming completion time t MLC Subtraction processing (Dx = t) c - t MLC In this way, the data loading selector 181 obtains the elapsed time Dx from the completion of MLC programming to the present at the corresponding address as the result (difference) Dx of the calculation process (S113). When the difference (elapsed time) Dx is a relatively large value, a large difference Dx indicates that the time elapsed since the completion of MLC programming is relatively long. When the difference Dx is a relatively small value, a small difference Dx indicates that the time elapsed since the completion of MLC programming is relatively short. Note that, generally speaking, in reverse and flash memory, the reliability of data stored in memory cells decreases over time. The data loading selector 181 compares the elapsed time Dx with the threshold value Dth used to select the data loading method. For example, the data loading selector 181 determines whether the elapsed time Dx is longer than the threshold value Dth (S114). When the elapsed time Dx is longer than the threshold value Dth (yes in S114), the data loading selector 181 selects EDL as the data loading method for the lower / middle page data of fine programming (S115). When the elapsed time Dx is equal to or shorter than the threshold value Dth (not in S114), the data loading selector 181 selects IDL as the data loading method for the lower / middle page data of fine programming (S116). In step S117, the processor 12 (or write management circuit 18) notifies the reverse memory 30 of the selection result of the data load selector 181 by transmitting flag or prefix commands as the aforementioned signals 555 and 777. The processor 12 sends a plurality of command sets to the reverse memory 30 according to the selected data loading method. In this way, the memory controller 10 instructs the reverse memory 30 to perform fine-grained programming using a data loading method selected between IDL and EDL. The reverse memory 30 performs fine-grained programming using the lower / middle page data prepared by the selected data loading method. As described above, the processing of each unit of the memory controller 10 ends during the finely programmed time. As described above, the memory system 1 of this disclosed embodiment uses the elapsed time Dx since the completion of MLC programming as an index for data reliability to select either IDL or EDL. Therefore, the memory system 1 of this disclosed embodiment can achieve high write performance of the memory system and high reliability of the data stored in the memory system. (c) Modification Example A modification example of the memory system 1 of the present disclosure embodiment will be described with reference to Figures 21 to 23. (c-1) Modification Example 1 Figure 21 is a block diagram illustrating a modified example of the memory system 1 of the present disclosed embodiment. In the memory system 1 of the first modified embodiment of this disclosure, a data loading method is selected during the fine programming time, taking into account the temperature of the memory system 1. Errors may occur in the data when the temperature of memory system 1 is high or when there is a large temperature difference between write and read operations on memory system 1. In other words, the reliability of the data can vary depending on the temperature of memory system 1. As shown in Figure 21, the reverse memory 30 includes a temperature sensor 43. The MLC programming log table TBL1A further includes a chip temperature T for recording the time during MLC programming. MLCchip The field. For example, the write management circuit 18 is based on the acquired wafer temperature T MLCchip The index used to determine the reference value (e.g., the threshold value Dth for the elapsed time Dx) is used to adjust the reliability of the data. Data loading selector 181 obtains the MLC program completion time t MLC Simultaneously, the temperature sensor 43 acquires the chip temperature T of memory 30 during the execution of MLC programming. MLCchip . Data loading selector 181 will acquire the wafer temperature T MLCchip MLC programming completion time t MLC They are recorded together in the corresponding entry of the MLC programmatic log table TBL1A. Data loading selector 181 (or processor 12) is based on the acquired wafer temperature T MLCchip This is used to adjust the threshold value Dth when selecting the data loading method. For example, the following is an instance of adjusting the threshold value Dth. Data loading selector 181 will load the wafer temperature T MLCchip With two critical limits T H and T L Compare the threshold values ​​T. H This is the critical limit value related to the high-temperature side. Critical limit value T L This is a threshold value related to the low-temperature side. When the wafer temperature T... MLCchip Higher than the critical limit T H Or the wafer temperature T MLCchip Below the critical limit T L At this time, the data loading selector 181 sets the threshold value Dth for the elapsed time Dx to be less than the initial setting value. By reducing the threshold value Dth in this way, EDL is selected even for shorter elapsed times Dx. Another example of adjusting the threshold value Dth is as follows. When fine programming is performed, the data loading selector 181 acquires the wafer temperature immediately preceding the fine programming (hereinafter referred to as the current wafer temperature) T. x The data loading selector 181 uses the chip temperature T at the time the MLC programming is completed. MLCchip With the current wafer temperature T xThe temperature difference (here referred to as D1) is calculated by subtraction. The data loading selector 181 compares the temperature difference D1 with a specific reference value (here referred to as the threshold value D2). When the temperature difference D1 is greater than the threshold value D2, the data loading selector 181 sets the threshold value Dth with respect to the elapsed time Dx to be less than the initial setting. This ensures that EDL is selected even for shorter elapsed times Dx. Note that the temperature difference D1 is dependent on the wafer temperature T. MLCchip With the current wafer temperature T x The value can be positive or negative depending on the quantitative relationship between the temperature difference D1 and the temperature difference D1. The change in the threshold value Dth can be adjusted according to the positive or negative polarity of the temperature difference D1. Furthermore, the temperature difference D1 can be determined by the wafer temperature T. MLCchip With the current wafer temperature T x It is expressed as the absolute value of the difference between them. In this disclosed modification example, the following example is illustrated: In this example, the data loading method for the lower / middle page data in fine programming is selected by considering both the storage time of data in the memory cell MC and the temperature of the memory system 1 (more specifically, the temperature of the memory 30). However, in this disclosed embodiment, the memory system 1 may select the data loading method for the lower / middle page data in fine programming solely based on the temperature of the memory system 1. For example, when the temperature of the memory system 1 is higher than a threshold value, the data loading selector 181 selects EDL instead of selecting based on the MLC programming completion time t. MLC The elapsed time Dx is compared with the threshold value Dth. For example, when the temperature of memory system 1 is equal to or below the threshold value, the data loading selector 181 selects IDL instead of the MLC-programmed completion time t. MLC The elapsed time Dx is compared with the critical value Dth. As described above, considering the impact of the temperature of the memory 30 on the reliability of the data, the memory system 1 of this disclosed embodiment may select the more suitable one of IDL and EDL. (c-2) Modified Example 2 Figures 22A to 22C are diagrams illustrating a second modified example of the memory system 1 according to the present disclosure embodiment. The multiple chips provided in memory 30 may have varying characteristics. The multiple blocks provided in memory cell array 31 may also have varying characteristics. The memory cells MC connected to the multiple word lines WL provided in each block may also have varying characteristics. Therefore, the data error rate varies among the multiple chips, the multiple blocks, and the multiple word lines. Taking into account the variation in error rate among the plurality of chips, the plurality of blocks, and the plurality of word lines, the memory system 1 according to the second modified example of the present disclosure sets threshold values ​​for selecting a data loading method during fine programming on a chip-by-chip, block-by-block, or word-line-by-word-line basis. For example, as shown in Figure 22A, a threshold value Dth can be set for each block BLK. In this case, a threshold value Dth_BLK0 is set for block BLK0, and a threshold value Dth_BLKi is set for block BLKi. Here, i is an integer of 0 or greater than 0. The value of the threshold value Dth_BLK0 may be the same as or different from the value of the threshold value Dth_BLKi. As shown in Figure 22B, a threshold value Dth can be set for each character line WL. In this case, a threshold value Dth_WL0 is set for character line WL0, and a threshold value Dth_WLi is set for character line WLi. As shown in Figure 22C, a threshold value Dth can be set for each chip provided in the reverse memory 30. In this case, a threshold value Dth_Chip0 is set for one chip, and a threshold value Dth_Chipi is set for another chip. For example, the critical threshold value Dth of a certain cell is determined during the design of memory system 1 or during the screening process when manufacturing memory 30. When setting the threshold value Dth for selecting the data loading method on a block-by-block or character-line-by-character-line basis, the threshold value Dth can be set such that IDL or EDL is always selected for a specific block and a specific character-line. For example, when always selecting EDL for a specific block or a specific character-line, the threshold value Dth is set to zero. Conversely, when always selecting IDL for a specific block or a specific character-line, the threshold value Dth is set to the maximum value within the range of values ​​specified for the threshold value Dth. As described above, in the memory system 1 of this disclosed embodiment, the index used to select either IDL or EDL can be set on a chip-by-chip, block-by-block, or word-line-by-word basis. (c-3) Modification Example 3 Figure 23 is a diagram illustrating a third modified example of the memory system 1 according to the present disclosure embodiment. As a result of the use of memory system 1, the block BLK (and memory cell MC) of memory 30 is damaged. The memory system 1 of the third modified instance dynamically adjusts the threshold value Dth used to select either IDL or EDL based on the wear level (degree of wear) of the block BLK. As shown in FIG23, in this disclosed embodiment, the memory controller 10 includes a programming / erase counter (P / E counter) 44 in the write management circuitry 18. The memory controller 10 enables the programming / erase counter 44 in the memory 30 to be non-volatile when the power supply to the memory system 1 is cut off, and can load the programming / erase counter 44 into the write management circuitry 18 in response to the power supply to the memory system 1 being turned on. The loading destination of the programming / erase counter 44 may be RAM 16. The programming / erase counter 44 measures the number of times programming and erase operations are executed in each block BLK. For example, a combination of a write operation and an erase operation is measured as an operation cycle. The memory controller 10 includes a management table TBL2 associated with the programming / erase count in RAM 16. The management table TBL2 records the number of programming and erase operations performed in each block BLK. The error rate of data in a block BLK varies depending on the programming / erase count. For example, the data error rate increases as the programming / erase count increases. For example, in the memory system 1 of the modified example disclosed herein, the memory controller 10 (processor 12 or data load selector 181) obtains the programming / erase count of each block BLK by referring to the programming / erase count counter 44. The memory controller 10 records the acquired programming / erase count in the management table TBL2. The data loading selector 181 (or processor 12) adjusts the threshold value Dth corresponding to each block BLK based on the programming / erase count recorded in the management table TBL2. For example, when the programming / erase count of a block BLK is relatively large (when the block BLK has a high wear level), the threshold value Dth is adjusted to a value smaller than the initial setting. This makes it more likely that an EDL will be selected for block BLKs with high wear levels. As described above, the memory system 1 of this disclosed embodiment can select a more suitable data loading method between IDL and EDL depending on the wear level of the block BLK. (d) Summary In the memory system 1 of this disclosed embodiment, based on an index related to the reliability of the lower / middle page data written to the memory cell array 31 via MLC programming, it is selected whether the lower / middle page data used for fine programming is loaded inside the reverse memory 30 or outside the reverse memory 30. For example, in inverted and flash memory, the threshold voltage of the memory cell MC tends to change over time after data is programmed into the memory cell MC. Therefore, the reliability of data written to the memory cell MC can decrease over time. When the lower / middle page data in the memory cell array 31 contains errors, the following situation may occur: the correct four page data are not written to the cell unit CU specified by the selected address of the memory cell array 31 during fine programming. Meanwhile, when the memory controller 10 provides the lower / middle page data to the reverse memory 30 during fine programming, the following situation may occur: due to the ECC processing of the lower / middle page data and / or the transmission of the command set including the lower / middle page data from the memory controller 10 to the reverse memory 30, the time before the fine programming is completed may be long. In this disclosed embodiment, when performing fine programming for a specific address, the memory controller 10 is based on the time t when bottom / middle page data is written to the memory cell array 31. MLC The reliability of the lower / middle page data is assessed by comparing the elapsed time Dx until the start of the fine-grained programming with the threshold value Dth. Therefore, the memory system 1 of this disclosed embodiment can select a more suitable data loading method between IDL and EDL to load (prepare) the lower / middle page data for the finely programmed data to be executed. Therefore, the embodiments disclosed herein can provide a memory system with high performance and high reliability. (2) Second embodiment The memory system of the second embodiment will be described with reference to Figures 24 to 30. (a) Configuration example A configuration example of the memory system 1 of the present disclosure embodiment will be described with reference to FIG24. Figure 24 is a block diagram illustrating a configuration example of the memory system 1 according to an embodiment of the present disclosure. The memory system 1 of this disclosed embodiment selects a data loading method during fine programming based on the workload applied to the memory system 1. As shown in FIG24, in the memory controller 10 of the memory system 1 of the disclosed embodiment, the write management circuit 18 further includes a throughput monitor 183. The throughput monitor 183 measures the amount of data written from the host 2 to the memory system 1 within a specific time window (unit of time). Hereinafter, the amount of data written within the specific time window is referred to as host write throughput or simply write throughput. For example, the throughput monitor 183 obtains the average write throughput within the time window based on the measurement results of the amount of data written from the host 2. The data load selector 181 of the write management circuit 18 compares the measured write throughput with a preset threshold (TPth). When performing fine programming, the data load selector 181 selects either IDL or EDL based on the comparison result between the write throughput (TP) and the threshold (TPth). (b) Operational Example An operational example of the memory system 1 of the present disclosure embodiment will be described with reference to Figures 25 and 26. Figure 25 is a flowchart illustrating an operational example of the memory system 1 according to an embodiment of the present disclosure. Figure 26 shows an example of the relationship between write throughput and time in the memory system 1 according to an embodiment of the present disclosure. In Figure 26, the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to write throughput. As shown in FIG25, in the memory controller 10 of the memory system 1 of this disclosed embodiment, the throughput monitor 183 of the write management circuit 18 measures the write throughput TP within a specific time window (S200). For example, the throughput monitor 183 acquires the amount of write data supplied from the host 2 within the specific time window. The throughput monitor 183 stores the acquired measurement results in the write management circuit 18. Data loading selector 181 compares the write throughput TP with the threshold value TPth (S201). Based on the comparison result, data loading selector 181 selects a finely programmed data loading method that can be executed in the next time window of a specific time window. As shown in Figure 26, in time window TW0, when the write throughput TP is higher than the threshold value TPth, it is assumed that the period during which the memory cell MC is in the MLC state is short. Therefore, when the write throughput TP is higher than the threshold value TPth (as in time window TW0), the data loading selector 181 selects IDL as the finely programmed data loading method that can be executed in the next time window TW1 (S202 in Figure 25). As shown in Figure 26, in time window TW2, when the write throughput TP is equal to or lower than the threshold value TPth, it is assumed that the period in which the memory cell MC is in the MLC state is long. Therefore, when the write throughput TP is equal to or lower than the threshold value TPth (as in time window TW2), the data loading selector 181 selects EDL as the finely programmed data loading method that can be executed in the next time window TW3 (S203 in Figure 25). The data loading selector 181 notifies the processor 12 of the selection result of the data loading method (S204). Thereby, when performing fine programming, the processor 12 instructs the memory 30 to perform fine programming using the data loading method indicated in the selection result. The memory 30 then performs fine-grained programming using the selected data loading method. This writes four pages of data to the write target address of the memory cell array 31. As described above, the memory system 1 of this disclosed embodiment terminates operation. Note that the range of the time window can be changed and is not fixed. Furthermore, instead of the amount of data written within the time window, the amount of data written for each specific number of commands can be measured as the write throughput. Furthermore, within the same time window as the time window for measuring write throughput, a finely programmed data loading method can be selected based on the write throughput measurement results. (c) Modified Example A modified example of the memory system 1 of the second embodiment will be described with reference to Figures 27 to 30. (c-1) Modification Example 1 Figure 27 is a block diagram showing a configuration example of memory system 1 according to the first modified instance. By taking into account not only the write throughput from host 2 to memory system 1, but also the performance of background processing (e.g., garbage collection (compression)) performed in memory system 1, the memory system 1 of this disclosed embodiment can select IDL or EDL with higher accuracy. As shown in Figure 27, in the memory system 1 of the first modified example, the write management circuit 18 further includes a write amplification factor (WAF) monitor 184. The WAF monitor 184 calculates the write amplification factor (WAF) of the memory system 1. WAF is a value representing the ratio of the amount of data written to the reverse memory 30 to the amount of data written from the host 2 to the memory system 1. For example, the WAF is obtained based on "the amount of data written to the reverse memory 30 / the amount of data written from the host 2 to the memory system 1". The WAF monitor 184 multiplies the write throughput obtained by the throughput monitor 183 by the WAF. The result of the multiplication (product) represents the amount of data written to the reverse memory 30 in a specific time window (hereinafter referred to as reverse throughput). The data loading selector 181 selects a finely programmed data loading method that can be executed in the next time window based on the comparison between the inverse and flux and the threshold value TPthz. Figure 28 illustrates the relationship between throughput and time in the memory system 1 of this disclosed embodiment. In Figure 28, the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to throughput. The memory system 1 of the first modified instance performs the comparison between throughput and threshold value TPthz and selects the data loading method for fine programming based on the processing flow that is substantially the same as that described with reference to FIG25. As shown in Figure 28, when the inverse throughput in time window TW0 is higher than the threshold value TPthz, the data loading selector 181 selects IDL as the finely programmed data loading method that can be executed in the next time window TW1. When the inverse flux in time window TW2 is equal to or lower than the threshold value TPthz, data loading selector 181 selects EDL as the finely programmed data loading method that can be executed in the next time window TW3. As described above, by further considering the processing power of the background processing of memory system 1, the memory system 1 of the first modified instance can choose a data loading method that is more suitable for fine-grained programming. (c-2) Modified Instance 2 Figure 29 is a block diagram showing a configuration example of memory system 1 according to the second modified example. A finely programmed data loading method can be selected based on the size of the data to be written (hereinafter referred to as the command size) requested by the command (request) sent from host 2 and the contiguousness of the address. As shown in Figure 29, in the memory controller 10 of the memory system 1 in the second modified example, the write management circuit 18 further includes a command size monitor 185 and an access pattern analyzer 186. Command size monitor 185 measures the command size of each of a plurality of commands (requests) sent from host 2. For example, command size monitor 185 stores the command sizes of a plurality of recently sent commands and obtains the average of the plurality of command sizes. Command size monitor 185 notifies data loading selector 181 whether the average of the obtained command sizes is greater than a set threshold. Access pattern analyzer 186 analyzes patterns of logical addresses, for example, those associated with the target data to be written. Based on the analysis results of the logical address patterns, access pattern analyzer 186 detects the continuity of logical addresses associated with the target data to be written. When, for example, the range of logical addresses of data to be written requested by a first command is adjacent to the range of logical addresses of data to be written requested by a second command, access pattern analyzer 186 determines that the logical addresses associated with the target data to be written are adjacent, respectively. Access pattern analyzer 186 notifies data load selector 181 whether the logical addresses associated with the target data to be written are adjacent. When accesses occur to logical addresses with relatively large command sizes (e.g., 128 kilobytes) and adjacent logical addresses, the frequency of writing data to logical addresses within this range tends to be relatively high. Therefore, the impact of reduced reliability of data corresponding to these logical addresses is considered to be small. In the memory system 1 of the second modified instance, when the command size is greater than the set threshold value and is adjacent to the logical address associated with the data to be written, the data loading selector 181 selects IDL as the data loading method during fine programming. When the command size is equal to or less than the set threshold, or when the logical address associated with the target data to be written is not adjacent, the data load selector 181 selects either IDL or EDL based on the aforementioned elapsed time, write throughput, or similar factors since MLC programming. Figure 30 is a flowchart illustrating an operational example of a second modified example of the memory system 1 according to the present disclosure embodiment. The memory controller 10 determines to execute fine programming (S230). Command size monitor 185 monitors the command size provided in the write request from host 2. Access pattern analyzer 186 analyzes the pattern (address continuity) of the logical address of the write target (S231). The data loading selector 181 determines whether the command size is greater than a specific threshold value based on the monitoring results of the command size (S232). When the command size is greater than the threshold value (yes in S232), the data loading selector 181 determines whether the write target address is adjacent based on the analysis results of the access pattern (S233). When the command size is large and the write target address is adjacent, the data load selector 181 selects IDL as the data loading method for fine programming (S234). When the command size is equal to or less than the threshold value (no in S232) or when the write target address is not adjacent (no in S233), at step S235, the data loading selector 181 selects either IDL or EDL as the data loading method for fine programming based on the above index (e.g., the elapsed time since the completion of MLC programming). Data loading selector 181 notifies processor 12 of the selection result of the data loading method (S236). Thereby, when performing fine programming, processor 12 instructs memory 30 to perform fine programming using the data loading method indicated in the selection result. As described above, the memory system 1 of the modified example disclosed herein terminates its operation. (d) Summary As described above, the memory system 1 of this disclosed embodiment can select a data loading method for fine-programmability based on the write throughput in a time window. Therefore, the embodiments disclosed herein can provide a memory system with high performance and high reliability. (3) Third embodiment The memory system of the third embodiment will be described with reference to Figures 31 to 33. (a) Configuration example Figure 31 is a block diagram illustrating a configuration example of the memory system 1 according to an embodiment of the present disclosure. The memory system 1 of this disclosed embodiment controls the selection of IDL or EDL based on whether the write operation uses write data from host 2 or is a write operation processed in the background. Hereinafter, a write operation requested by host 2 is referred to as a host write. Furthermore, a write operation processed in the background is referred to as a background write. Host write is an operation mode that writes data transferred from host 2 to the reverse memory 30. Background write is an operation mode that writes data prepared inside memory system 1 (such as garbage collection (compression), wear leveling, or data renewal) to the reverse memory 30. As shown in FIG31, in the memory controller 10 of the memory system 1 of the disclosed embodiment, the write management circuit 18 further includes a command analyzer 187. Command analyzer 187 analyzes whether the command generated by reverse interface circuit 17 is a command for host writing or a command for background writing based on various information blocks (e.g., attribute information) provided in the command generated by reverse interface circuit 17. Command analyzer 187 sends the analysis results of the command to data loading selector 181. The data loading selector 181 selects a data loading method for fine-grained programming based on the analysis results of the command by the command analyzer 187. When the write operation to be performed is a background write, IDL is selected as the finely programmed data loading method for the write operation. For example, the progress of background writes can be adjusted by memory system 1. Therefore, for the memory cell MC that is the target of background writes, memory controller 10 can control the elapsed time Dx from the completion of MLC programming to the present to be relatively short. Furthermore, in IDL, the loading of lower / middle page data is performed within backplane memory 30, and therefore IDL occupies less backplane bus NBS compared to EDL. Therefore, specifically, in workloads with relatively short idle times (where the interval between host write requests is equal to or shorter than a certain threshold), using IDL for background writes can reduce the impact on host write performance. Note that when background writes are performed using fine-grained programming with IDL, ECC processing is expected to be performed on the data written via background writes. If error correction fails during ECC processing, the memory controller 10 can re-perform background writes using lower / middle page data stored in the source block that is the target of the background write. When the write operation to be performed is a host write, either IDL or EDL is selected as the fine-grained data loading method based on other indexes mentioned above (e.g., elapsed time since the completion of MLC programming or write throughput). (b) Operation Example Figure 32 is a flowchart illustrating an operational example of the memory system 1 according to an embodiment of the present disclosure. As shown in FIG32, in the memory system 1 of this disclosed embodiment, when the reverse interface circuit 17 generates a command, the command analyzer 187 analyzes the command (S300). The command analyzer 187 sends the analysis result of the command to the data loading selector 181. The data loading selector 181 determines whether the write operation to be performed is a background write based on the analysis results of the command (S301). When the write operation to be performed is a background write (yes in S301), the data load selector 181 selects IDL as the finely programmed data loading method (S302). When the write operation to be performed is a host write (no in S301), at step S303, the data loading selector 181 selects either IDL or EDL based on one or more of the above-mentioned indexes (e.g., the elapsed time since the completion of MLC programming). Data loading selector 181 notifies processor 12 of the selection result of data loading method (S304). When performing fine programming, processor 12 instructs memory 30 to perform fine programming using the data loading method indicated in the selection result. As described above, the memory system 1 of this disclosed embodiment terminates operation. (c) Modified Example Figure 33 is a flowchart illustrating an operational example in a modified example of the memory system 1 of the present disclosed embodiment. In workloads with relatively long idle times (where the interval between host write requests is longer than a certain threshold), from the host's perspective, the time spent loading data during fine-tuning can impact memory system performance. Therefore, in workloads with relatively long idle times, it is desirable to use IDL for fine-tuning host writes. Furthermore, in workloads with relatively long idle periods, from the host's perspective, background processing is unlikely to impact memory system performance. Therefore, in workloads with relatively long idle periods, it is desirable to use EDL for fine-grained programming of background writes. The memory system 1 of this modified example is configured the same as the third embodiment described with reference to FIG31. As shown in Figure 33, in the modified example disclosed herein, the data loading selector 181 determines whether the write operation to be performed is a background write (S300, S301). When the write operation to be performed is a background write (yes in S301), the data load selector 181 selects EDL (S302A). When the write operation to be performed is not a background write (no in S301), the data load selector 181 selects, for example, IDL (S303A). Data loading selector 181 notifies processor 12 of the selection result of data loading method (S304). When performing fine programming, processor 12 instructs memory 30 to perform fine programming using the data loading method indicated in the selection result. As described above, the operation to modify the instance's memory system 1 is complete. (d) Summary The memory system 1 of this disclosed embodiment selects IDL or EDL as the data loading method during fine-programming based on whether the write operation to be performed is a host write or a background write. Therefore, the memory system 1 of this disclosed embodiment can perform the requested write operation by means of a data loading method suitable for fine programming, based on the type of write operation to be performed. Therefore, the memory system 1 of this disclosed embodiment can provide a memory system with high performance and high reliability. (4) Fourth embodiment The memory system of the fourth embodiment will be described with reference to Figures 34 and 35. (a) Configuration Example Figure 34 is a block diagram illustrating a configuration example of the memory system 1 according to an embodiment of the present disclosure. The memory system 1 of this disclosed embodiment selects either IDL or EDL as a finely programmed data loading method based on prompt information from the host 2. Host 2 sends a start flag SF and an end flag EF to memory controller 10 as notification information. The start flag SF is used to notify host 2 that a mass write command will begin to be transmitted to memory system 1. The end flag EF is used to notify that the transmission of the mass write command has ended. As shown in FIG34, in the memory controller 10 of the memory system 1 of this disclosed embodiment, the write management circuit 18 further includes a flag post 188. Flag post 188 receives start flag SF and end flag EF as prompt information. Flag post 188 sends notification signal ACK3 to data loading selector 181, causing IDL to be selected based on the received start flag SF during the period from receiving the start flag SF to receiving the end flag EF. Data loading selector 181 selects an IDL based on the notification signal ACK3 from flag bar 188 during the period from receiving the start flag SF to receiving the end flag EF. (b) Operational Example Figure 35 is a schematic diagram illustrating an operational example of the memory system 1 according to an embodiment of the present disclosure. As shown in Figure 35, host 2 sends a start flag SF to memory system 1 at time t10a as a notification. The start flag SF notifies memory system 1 that it intends to issue a large number of write commands from this point. At time t10b, memory controller 10 receives start flag SF. Flag post 188 analyzes the start flag SF. Based on the analysis results of the start flag SF, flag post 188 sends a notification signal ACK3 to data loading selector 181. Data loading selector 181 identifies IDL selection when performing fine-grained programming based on notification signal ACK3. During the period from time t11a to time t12a, host 2 sends a large number of write commands WC to memory system 1. During the period from time t11b to time t12b, memory system 1 receives the bulk write command WC. Data loading selector 181 continues to select IDL as the finely programmed data loading method to be executed during the period from time t11b to time t12b. After all write commands WC have been transmitted, host 2 sends the end flag EF as a notification message to memory system 1 at time t13a. At time t13b, memory controller 10 receives the end flag EF. In memory controller 10, flag post 188 receives the end flag EF. Flag post 188 analyzes the end flag EF. Flag post 188 then stops supply notification signal ACK3 based on the analysis results of the end flag. The data load selector 181 recognizes the end of the write operation based on the cessation of the supply of the notification signal ACK3. Therefore, the data load selector 181 stops the continuous selection of IDL. Subsequently, before receiving a new notification signal ACK3 from flag post 188, data loading selector 181 selects either IDL or EDL based on the index used to select the data loading method (e.g., the elapsed time since the completion of MLC programming). Note that the memory system 1 in this disclosed embodiment can select EDL as the data loading method during fine-tuning based on prompt information from the host 2. (c) Summary As described above, the memory system 1 of this disclosed embodiment can select a data loading method suitable for the write operation to be performed from either the IDL or the EDL based on prompt information from the host 2. Therefore, the memory system 1 of this disclosed embodiment can provide a memory system with high performance and high reliability. (5) Fifth embodiment The memory system of the fifth embodiment will be described with reference to Figures 36 and 37. (a) Configuration Example Figure 36 is a block diagram illustrating a configuration example of the memory system 1 according to an embodiment of the present disclosure. The memory system 1 of this disclosed embodiment performs finely programmed time control to select IDL and EDL based on the state of power cut-off and power restoration. As shown in FIG36, in the memory controller 10 of the memory system 1 of the disclosed embodiment, the write management circuit 18 further includes a power monitor 189. When a power cut-off is detected in memory system 1, power monitor 189 sends a power cut-off signal PS to processor 12. Processor 12 generates management table TBL3 based on the power cut-off signal PS. Management table TBL3 represents the word lines WL and serial units SU connected to the memory cell MC in MLC state. In the following text, management table TBL3 representing the word lines WL and serial units SU connected to the memory cell MC in MLC state is referred to as MLC state list TBL3. The MLC status list TBL3 is temporarily stored, for example, in RAM 16. For instance, when power to memory system 1 is cut off, memory controller 10 writes the generated MLC status list TBL3 to the inverted memory 30 or transmits the MLC status list TBL3 to host 2. When memory system 1 is started by power restoration, memory controller 10 reads the MLC status list TBL3 from the inverted memory 30 or receives the MLC status list TBL3 from host 2. When the memory controller 10 receives a write command from the host 2 after power is restored, the data loading selector 181 refers to the MLC status list TBL3. For memory cells MC managed in MLC status list TBL3, the elapsed time Dx from the completion of MLC programming to the present is unknown. Therefore, when the write target address corresponding to the write command from host 2 corresponds to the character line number and string cell number managed in MLC status list TBL3, data load selector 181 selects EDL, which has higher data reliability than IDL, as the data loading method for fine programming. After power is restored, after performing fine programming using EDL on all cell units CU specified by the addresses corresponding to word lines WL and string units SU recorded in the MLC status list TBL3, the data loading selector 181 selects either IDL or EDL as the data loading method for fine programming based on the above index (e.g., the elapsed time since the completion of MLC programming). Note that there may be a situation where the processor 12 is unable to generate the MLC status list TBL3 due to an unexpected power outage (e.g., a power failure). In this case, the processor 12 first determines, for example, based on some log information blocks, the block BLK (hereinafter referred to as the last write block) that was last written before the power outage. Next, the processor 12 calculates for each cell CU the number of memory cells MC that are turned on by applying one or more read voltages to each word line WL included in the last write block. Then, based on the calculation results, the processor 12 determines the cell CU that last entered the MLC state before the power outage (hereinafter referred to as the last MLC cell). The processor 12 uses EDL to perform all the fine-tuning up to the last MLC cell for these cell CUs (these fine-tunings will be performed according to the write order illustrated with reference to FIG9). For example, in the case where the cell CU corresponding to the character line WL1 and the string unit SU0 is the last MLC cell of the sixth write operation illustrated with reference to FIG9, the processor 12 uses the EDL for all fine programming to be performed on these cell CUs (i.e., the seventh write operation, the ninth write operation, the eleventh write operation, the thirteenth write operation, the fifteenth write operation, and the seventeenth write operation) up to this last MLC cell (the seventeenth write operation). For cell CUs after this last MLC cell (e.g., the nineteenth write operation or subsequent write operations), the processor 12 selects either the IDL or the EDL based on the aforementioned index (e.g., the elapsed time since the completion of the MLC programming (e.g., the eighth write operation or subsequent write operations)). Note that when the number of string units SU included in a block BLK is N (N is an integer of 1 or greater than 1, and N is 5 in the example shown in Figure 9), and the number of word lines WL is M (M is an integer of 1 or greater than 1, and M is 2 in the example shown in Figure 9), in the case where the word lines WL include multiple cell units CU that are written to after MLC programming of a certain cell unit CU is performed before fine programming of that cell unit CU, the processor 12 uses EDL to perform all fine programming up to the last MLC cell unit on L cell units CU. Here, L is calculated by L = (M-1) x N + 1. In the case where the last MLC cell unit is located at either end of the word line WL, the number of cell units CU to which EDL is applied may be less than L. However, to simplify processing, processor 12 can apply EDL to L cell units CU, regardless of the position of the last MLC cell unit within the word line WL. Alternatively, processor 12 can apply EDL to all fine-grained programming to be executed on L' cell units CU up to the last MLC cell unit. Here, L' is calculated by L' = (M'-1) x N + 1 (where M' is an integer greater than M). Alternatively, processor 12 can apply EDL to all fine-grained programming to be executed on L'' cell units CU up to the last MLC cell unit. Here, L'' is an integer greater than L. To further simplify processing, processor 12 can apply EDL to all fine-grained programming to be executed on all cell units included in the last write block. Furthermore, even if the management table (e.g., the MLC status list) associated with the write target address is not updated each time a power outage is detected, a finely programmed data loading method can still be selected after power is restored based on the write operation history prior to the power outage, similar to the case of an unexpected power outage. (b) Operational Example Figure 37 is a flowchart illustrating an operational example of the memory system 1 according to an embodiment of the present disclosure. As shown in Figure 37, when the power monitor 189 detects a power cut-off, the processor 12 generates a management table TBL3 (MLC status list TBL3) in response to the power cut-off signal PS from the power monitor 189. The generated MLC status list TBL3 is then transmitted to the reverse memory 30 or the host 2 (S500). When memory system 1 is started by power restoration, the MLC status list TBL3 is stored in RAM 16 of memory system 1. After power is restored, when the memory controller 10 receives a write request from the host 2, the data load selector 181 refers to the MLC status list TBL3 (S501). Data loading selector 181 determines whether the write target address (word line number and serial unit number) exists in the MLC status list TBL3 (S502). When the character line number and string cell number as the write target exist in the MLC status list TBL3 (yes in S502), the data loading selector 181 selects EDL as the finely programmed data loading method to be executed (S503). Data loading selector 181 updates the MLC status list TBL3 (S504). For example, data loading selector 181 removes the character line number and string cell number from the MLC status list TBL3 as the write target for fine-programming of the selected EDL. When there is no character line number and string cell number as the write target in the MLC status list TBL3 (no in S502), the data loading selector 181 selects either IDL or EDL based on an index (e.g., the elapsed time since the completion of MLC programming or the write throughput) (S505). The data loading selector 181 notifies the processor 12 of the selection result of the data loading method (S506). Thereby, when performing fine programming, the processor 12 instructs the memory 30 to perform fine programming using the data loading method indicated in the selection result. As described above, the memory system 1 of this disclosed embodiment terminates operation. (c) Summary As described above, even when the power supply to the memory system 1 is cut off, the memory system 1 of this disclosed embodiment can still provide a memory system with high performance and high reliability. (6) Other In the memory system of the embodiment described above, the non-volatile memory is not limited to anti-flash memory, but can be another memory element. In the memory system of the embodiment described above, when data is written to a memory cell through multiple write stages (write operations), the data written to the memory cell can be 2 bits, 3 bits, 5 bits, or 6 bits. Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel embodiments described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications falling within the scope and spirit of this disclosure. 1: Memory System 2: Host 9: Information Processing System 10: Memory Controller 11: Host Interface (I / F) Circuit 12: Processor 13: Buffer Memory 14: Error Checking and Correction (ECC) Circuit 15: Read-Only Memory (ROM) 16: Random Access Memory (RAM) 17: I / O Interface (I / F) Circuit 18: Write Management Circuit 30: I / O Memory / Memory Element 31: Memory Cell Array 32: Input / Output Circuit 33: Logic Control Circuit 34: Ready / Busy Control Circuit 35: Register 35A: Command Register 35B: Address Register 35C: Status Register 36: Sequencer 37: Driver Module 38: Column Decoder Module 39: Sensor Amplifier Module 40: Data... 43: Data latch; 44: Temperature sensor; 100: Programmable / erase counter (P / E counter); 181: System-on-a-Chip (SoC); 182: Data load selector; 183: Global clock; 184: Throughput monitor; 185: Write amplification factor (WAF) monitor; 186: Command size monitor; 187: Access pattern analyzer; 188: Command analyzer; 189: Flag bar; 500-1, 500-2, 500-3, 500-4, 500-A, 500-B, 500-C, 500-D, 700-1, 700-2, 700-3, 700-4: Command sets; 501, 502-1, 502-2, 502-3, 502-4, 503... 507, 508, 701, 702, 703, 704, CMD: Commands 504-1, 504-2, 505-1, 505-2, 505-3, 505-4, ADD: Address 506-1, 506-A: Write data / Lower page data 506-2, 506-B: Write data / Middle page data 506-3: Write data / Top page data 506-4: Write data / Top page data 506-C: Top page data 506-D: Top page data 555, 777, DQ0~DQ7: Signals 705-1: Lower page data 705-2: Middle page data ACK1, ACK2, ACK3: Notification signals ALE: Address latch enable signal / Signal BAd: Area Block addresses BL0, BL1~BLm-1: Bit lines BLK, BLK0, BLK1~BLKk-1: Block CAd: Row address CEn: Chip enable signal CLE: Command latch enable signal / signal CU: Cell unit DAT: Data / Write data DQS: Data select signal / signal Dth, Dth_Chip0~Dth_Chipi, Dth_BLK0~Dth_BLKi, Dth_WL0~Dth_WLi, TPth, TPthz: Threshold value Dx: Difference / Elapsed time EF: End flag H, L: Level HBS: Host bus M0, M1, M2, M3, St0, St1, St2, St3, St4, St5, St6St7, St8, St9, St10, St11, St12, St13, St14, St15: Status; MC0, MC1, MC2~MCn-2, MCn-1: Memory Cell; NBS: Inverted Bus; NS: Inverted Serial Bus; PAd: Page Address; PS: Power Off Signal; R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R 15: Read operation RBn: Ready / Busy signal / signal REn: Read enable signal / signal S1, S2, S3, S4, S5, S6, S7A, S7B, S8A, S8B, S100, S101, S102, S103, S110, S111, S112, S113, S114, S115, S116, S117, S200, S201, S202, S203, S204, S230, S231, S232, S233, S234, S235, S236, S300, S301, S302, S302A, S303, S303A, S304, S500, S501, S502, S503, S504, S505, S506: Step SF: Start Flags SGD0, SGD1, SGD2, SGD3, SGD4, SGS: Select Gate Line SL: Source lines ST1, ST2: Select transistors STS: Status information SU, SU0, SU1, SU2, SU3, SU4: Serial cells t10a, t10b, t11a, t11b, t12a, t12b, t13a, t13b: Time TBL1: Management table / MLC programmable log table / Table TBL1A: MLC programmable log table TBL2: Management table TBL3: Management table / MLC status list t, c Current time t MLC MLC programming completion time / time T MLCchip : Chip temperature TP; Write throughput tPROG, tR; Period TW0, TW2; Time window TW1, TW3; Next time window T x :Wafer Temperature / Current Wafer Temperature V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, VM1, VM2, VM3, VREAD: Voltage WC: Write Command WEN: Signal / Write Enable Signal WL, WL0, WL1, WL2, WLn-2, ​​WLn-1: Word Lines Figure 1 is a block diagram showing a configuration example of a memory system according to the first embodiment. Figure 2 is a block diagram showing a configuration example of a non-volatile memory according to the first embodiment. Figure 3 is a circuit diagram of a memory cell array of a non-volatile memory according to the first embodiment. Figure 4 is a diagram showing an example of the relationship between the threshold voltage and data of a memory cell according to the first embodiment. Figure 5 is a block diagram showing a configuration example of a write management circuit in the memory system of the first embodiment. Figure 6 is a diagram showing a configuration example of a management table in the memory system according to the first embodiment. Figure 7 is a diagram showing an operational example of a first write operation in the memory system of the first embodiment. Figure 8 is a diagram showing an operational example of a second write operation in the memory system of the first embodiment. Figure 9 is a diagram showing an operational example of a write operation in the memory system of the first embodiment. Figure 10 is a sequence diagram showing operational examples of a write operation in the memory system of the first embodiment. Figure 11 is a sequence diagram showing another operational example of a write operation in the memory system of the first embodiment. Figure 12 is a sequence diagram showing yet another operational example of a write operation in the memory system according to the first embodiment. Figure 13 is a sequence diagram illustrating an example of a command sequence for a first write operation in the memory system of the first embodiment. Figure 14 is a sequence diagram illustrating an example of a command sequence for a second write operation in the memory system of the first embodiment. Figure 15A is a sequence diagram illustrating another example of a command sequence for a second write operation in the memory system of the first embodiment. Figure 15B is a sequence diagram illustrating yet another example of a command sequence for a second write operation in the memory system of the first embodiment. Figure 16 is a flowchart illustrating an example of a write operation in the memory system of the first embodiment. Figure 17 is a flowchart illustrating an example of a first write operation in the memory system of the first embodiment. Figure 18 is a diagram illustrating an example of a first write operation in the memory system of the first embodiment. Figure 19 is a flowchart illustrating an example of a second write operation in the memory system of the first embodiment. Figure 20 is a diagram illustrating an example of a second write operation in the memory system of the first embodiment. Figure 21 is a block diagram illustrating a configuration example of a first modification example of the memory system of the first embodiment. Figures 22A to 22C are diagrams illustrating configuration examples of a second modification example of the memory system of the first embodiment. Figure 23 is a block diagram illustrating a configuration example of a third modification example of the memory system of the first embodiment. Figure 24 is a block diagram illustrating a configuration example of a memory system according to the second embodiment. Figure 25 is a flowchart illustrating an operation example of a write operation in the memory system according to the second embodiment. Figure 26 is a diagram illustrating an operation example of a write operation in the memory system according to the second embodiment. Figure 27 is a block diagram illustrating a configuration example of a first modified instance of the memory system according to the second embodiment. Figure 28 is a diagram illustrating an operation example of a write operation in the first modified instance of the memory system according to the second embodiment.Figure 29 is a block diagram illustrating a configuration example of a second modified instance of the memory system according to the second embodiment. Figure 30 is a flowchart illustrating an operation example of a write operation in the second modified instance of the memory system according to the second embodiment. Figure 31 is a block diagram illustrating a configuration example of the memory system according to the third embodiment. Figure 32 is a flowchart illustrating an operation example of a write operation in the memory system according to the third embodiment. Figure 33 is a flowchart illustrating an operation example of a write operation in a modified instance of the memory system according to the third embodiment. Figure 34 is a block diagram illustrating a configuration example of the memory system according to the fourth embodiment. Figure 35 is a diagram illustrating an operation example of a write operation in the memory system according to the fourth embodiment. Figure 36 is a block diagram illustrating a configuration example of the memory system according to the fifth embodiment. Figure 37 is a flowchart illustrating an operation example of a write operation in the memory system according to the fifth embodiment. S1, S2, S3, S4, S5, S6, S7A, S7B, S8A, S8B: Steps

Claims

1. A method for controlling non-volatile memory, said non-volatile memory comprising memory cells configured to store data in a non-volatile manner, the method comprising: The process includes: issuing a first command sequence to the non-volatile memory to perform a first write operation, wherein n (n is a positive integer greater than 1) bits of first data are written to the memory cell; selecting one of a first method and a second method for preparing m bits (m is a positive integer greater than n) of second data for a second write operation based on an index related to the reliability of the first data stored in the memory cell, the second data comprising the n bits of the first data; and issuing a second command sequence to the non-volatile memory to perform the second write operation, wherein the second data is written to the memory cell, the second command sequence representing the selected method for preparing the second data, wherein, in the first method, the second data for the second write operation is prepared inside the non-volatile memory, and in the second method, the second data for the second write operation is prepared outside the non-volatile memory.

2. The method as described in claim 1, wherein the index is the elapsed time since the first write operation to the memory cell was completed, and the first method is selected when the elapsed time is equal to or less than a first threshold, and the second method is selected when the elapsed time is longer than the first threshold.

3. The method of claim 1, wherein the memory cell is one of a plurality of memory cells, and the method further comprises: A first management table is stored in a first memory, the first management table having multiple entries corresponding to the plurality of memory cells, each of the plurality of entries representing a memory cell address and a first time associated with a first write operation performed on the memory cell specified by the memory cell address; when the difference between a second time associated with a second write operation to be performed on a target memory cell among the plurality of memory cells and the first time stored in the entry of the target memory cell is equal to or less than a second threshold, the first method is selected to perform the second write operation on the target memory cell; and when the difference is greater than the second threshold, the second method is selected to perform the second write operation on the target memory cell.

4. The method as described in claim 3, further comprising: The temperature sensor is configured to measure the temperature of the non-volatile memory. And adjust the second threshold value based on the measurement results of the temperature sensor.

5. The method as described in claim 4, wherein the second threshold is reduced when the first temperature measured by the temperature sensor is higher than the third threshold during the execution of the first write operation, and the second threshold is reduced when the first temperature is lower than the fourth threshold, which is smaller than the third threshold.

6. The method as described in claim 4 further includes: The temperature difference between a first temperature measured by the temperature sensor and a second temperature measured by the temperature sensor during the execution of the first write operation is obtained in order to prepare to issue the second command sequence for the second write operation; and when the temperature difference is greater than a fifth threshold value, the second threshold value is decreased.

7. The method as described in claim 3 further includes: Track the number of times an erase operation is performed on the memory cell; And when the number of times the erase operation is performed on the memory cell exceeds the sixth threshold, the second threshold is reduced.

8. The method as described in claim 1, wherein the index is the throughput of data from the host in the first period, and the method further comprises: When the flux is higher than the seventh threshold, the first method is selected in the second period after the first period; when the flux is equal to or lower than the seventh threshold, the second method is selected in the second period.

9. The method of claim 1, wherein the index is the throughput of write data in the non-volatile memory during a first cycle, and the method further comprises: When the flux is higher than the eighth threshold, the first method is selected in the second cycle following the first cycle. And when the flux is equal to or lower than the eighth threshold, the second method is selected in the second cycle.

10. The method as described in claim 1, further comprising: The first method is selected when the data size of the first write data specified by the first command from the host is greater than the ninth threshold and the logical address associated with the second write data specified by the second command from the host is adjacent to the logical address associated with the first write data; and when the data size of the first write data is equal to or less than the ninth threshold or when the logical address associated with the second write data is not adjacent to the logical address associated with the first write data, one of the first method and the second method is selected based on the index.

11. The method as described in claim 1, further comprising: When the second write operation is initiated by background processing, the first method is selected; And when the second write operation is initiated in response to a command from the host, one of the first method and the second method is selected based on the index.

12. The method as described in claim 11, further comprising: Determine whether the interval between multiple write requests from the host is equal to or shorter than the tenth threshold value; And when the interval is equal to or shorter than the tenth threshold value, the first method is selected for the second write operation initiated by the background processing; and based on the index, one of the first method and the second method is selected for the second write operation initiated in response to the command from the host.

13. The method as described in claim 1, further comprising: When the second write operation is initiated in response to a command from the host, the first method is selected; And when the second write operation is initiated by background processing, the second method is selected.

14. The method as described in claim 13, further comprising: Determine whether the interval between multiple write requests from the host is longer than the eleventh threshold. And when the interval is longer than the eleventh threshold, the first method is selected for the second write operation initiated in response to the command from the host; and the second method is selected for the second write operation initiated by the background processing.

15. The method as described in claim 1, further comprising: When the host receives a first flag indicating a transmission of multiple commands, the first method is selected consecutively; And when the host receives a second flag indicating the end of the transmission of the plurality of commands, the continuous selection of the first method is interrupted.

16. The method of claim 1, wherein the memory cell is one of a plurality of memory cells, and the method further comprises: When it is desired to stop power supply to the non-volatile memory, the address of the memory cell that has been subjected to the first write operation but has not yet been subjected to the second write operation is recorded in the third management table; The second method is selected when the address of the target memory cell among the plurality of memory cells that is the target of the second write operation is recorded in the third management table after power is restored to the non-volatile memory; And when the address of the target memory cell is not recorded in the third management table, one of the first method and the second method is selected based on the index.

17. The method of claim 1, wherein the non-volatile memory does not undergo an erase operation on the memory cell between the first write operation and the second write operation.

18. The method of claim 1, wherein the non-volatile memory further includes a data latch, and the method further includes: In the first method, the non-volatile memory is instructed to read the first data from the memory cell and store the read first data in the data latch; The third data is transferred to the non-volatile memory; the non-volatile memory is instructed to prepare the second data in the data latch, the second data including the read first data and the transferred third data; and the non-volatile memory is instructed by issuing a second command sequence to write the second data to the memory cell, and in the second method, the second data is prepared after the first write operation of the first data is performed on the memory cell; The second data is transferred to the non-volatile memory; And by issuing the second command sequence, the non-volatile memory is instructed to write the second data into the memory cell.

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