Semiconductor devices and methods for manufacturing the same

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, fins covering the substrate and providing multiple active regions for at least two devices, and a fin insulating structure disposed to electrically isolate the active regions of the at least two devices, wherein the fin insulating structure extends through the fins and into the substrate, wherein the fin insulating structure includes a first dielectric material, and a pair of seam isolation structures adjacent to the fins on multiple opposing sides of the fins, wherein the pair of seam isolation structures define multiple boundaries of the fin insulating structure on the sides of the fins.

Description

Technical Field

[0001] none. Prior Technology

[0002] In recent years, the integrated circuit (IC) industry has experienced rapid and sustained growth. Technological advancements in IC materials and design have led to continuous improvements in ICs generation after generation. Each new generation of products features smaller and more complex circuits than its predecessor, achieving higher functional density (i.e., the number of interconnect devices per wafer area) and smaller geometries (i.e., the smallest components or lines that can be created using a single manufacturing process). This scaling down of processes improves production efficiency and reduces associated costs. However, as feature sizes continue to shrink, manufacturing processes become more challenging, making it increasingly difficult to ensure the reliability of semiconductor devices. Therefore, the industry faces the ongoing challenge of developing processes capable of manufacturing smaller, more reliable ICs. Summary of the Invention

[0003] none. Simple Explanation of the Diagram

[0004] The nature of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is a flowchart of an exemplary method for forming a semiconductor structure according to some embodiments. Figures 2 through 45 schematically illustrate a first method for forming a semiconductor structure according to some embodiments. Figures 46 through 85 schematically illustrate a second method for forming a semiconductor structure according to some embodiments. Figure 86 schematically shows a partial top view of a semiconductor device at one stage of an integrated circuit manufacturing process according to some embodiments. Figure 87 schematically shows a partial top view of a portion of a semiconductor device at one stage of an integrated circuit manufacturing process according to some embodiments. Figure 88 schematically shows a perspective view of a portion of a semiconductor device at one stage of an integrated circuit manufacturing process according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or instances of various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these examples are merely exemplary and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.

[0006] As used herein, terms such as "first" and "second" describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish elements, components, regions, layers, or sections from one another. Unless expressly indicated herein, the terms such as "first" and "second" as used herein do not imply a sequence or order.

[0007] For the sake of brevity, conventional techniques associated with the manufacture of conventional semiconductor devices are not described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into a more comprehensive set of steps or processes that have additional functionality not described in detail herein. In particular, the various processes used in the manufacture of semiconductor devices are well-known; therefore, for the sake of brevity, many conventional processes will be mentioned only briefly or omitted entirely without providing well-known process details. It will become apparent to those skilled in the art, upon a full reading of this disclosure, that the structures disclosed herein can employ various techniques and can be incorporated into a wide variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of elements, and a single element shown in a figure may represent multiple elements.

[0008] Furthermore, spatial relative terms, such as "below," "below," "lower," "above," "upper," and similar terms, may be used herein for ease of description to describe the relationship of one element or feature relative to another element or feature, as illustrated in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those described in the accompanying drawings. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be understood accordingly. When spatially related terms (such as those exemplified above) are used to describe a first element and an associated second element, the first element may be directly on the other element, or there may be an intermediate element or membrane layer present. When referring to an element or membrane layer "on" another element or membrane layer, it is directly on and in contact with the other element or membrane layer.

[0009] It should be noted that the use of terms such as "one embodiment," "embodiment," "exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing that feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the art.

[0010] Some embodiments of this disclosure will now be described with reference to the accompanying drawings, wherein the same reference numerals are generally used to refer to the same parts throughout the text. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. However, it will be apparent that the claimed subject matter can be practiced without these specific details. In other examples, structures and arrangements are illustrated in block diagram form to facilitate the description of the claimed subject matter.

[0011] Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or eliminated. Additional features may be added to the semiconductor device structure. For different embodiments, some features described below may be replaced or eliminated. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in another logical order.

[0012] As used in this article, a "layer" is a region, such as a region with arbitrary boundaries, and not necessarily with uniform thickness. For example, a layer can be a region that includes at least some variation in thickness.

[0013] In semiconductor manufacturing, self-aligning contact (SAC) processes are used to establish contacts between metal interconnects and underlying semiconductor devices (such as transistors). SAC processes often use sacrificial material to temporarily fill the gaps between metal interconnects before the final contact is formed. This sacrificial material is then removed, leaving the self-aligned contact. In advanced nodes with stringent scaling requirements, SAC processes are needed to prevent leakage between the metal gate and the metal contacts connecting the source or drain.

[0014] Continuous metal on diffusion edge (CMODE) processes can be used, where a metal gate extends along the edge of the diffusion region. These processes can improve device performance and reduce parasitic resistance and capacitance. For the purposes of this disclosure, "diffusion edge" can be equivalently referred to as an active edge, where, for example, an active edge adjoins an adjacent active region. Furthermore, active regions include areas forming transistor structures (e.g., including source / drain structures and gate / channel structures). In some examples, active regions can be positioned between insulating regions. CMODE processes can provide isolation regions between adjacent active regions by performing an etching process along the active edge (e.g., at the boundary of adjacent active regions) to form cut regions and filling the cut regions with a refill material, thereby providing isolation regions between adjacent transistors.

[0015] However, combining SAC and CMODE processes presents several challenges. For example, if the SAC sacrificial material includes seams extending through it, byproduct materials from the etching process and / or refill materials may flow or diffuse into the seams connected to the diced area, potentially leading to serious defects in the semiconductor device and increasing the risk of leakage.

[0016] This document presents embodiments of semiconductor devices and methods for forming semiconductor devices using a combination of SAC and CMODE processes. To reduce the likelihood of unwanted material entering the seams of the SAC sacrificial material, the exemplary semiconductor devices disclosed herein include seam isolation structures configured to seal multiple line ends of the semiconductor device. As used herein, a "line end" refers to the point where a metal gate line terminates or ends. Metal gates are conductive pathways made of metal (e.g., TiN, TiAl, or W) patterned on the surface of the semiconductor device. These metal gates are used to turn transistors on or off in integrated circuits. In some examples, the seam isolation structures are formed in the semiconductor device prior to performing the SAC and / or CMODE processes.

[0017] Referring to Figure 1, the flowchart provides an exemplary method 100 for forming a semiconductor device according to various paradigms. For example, at least some operations (or steps) of method 100 can be used to form a fin field-effect transistor (FinFET) device, a gate-all-around (GAA) FET device, a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, etc. It should be noted that method 100 is merely exemplary and is not intended to limit this disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 100 of Figure 1, and only a few other operations may be briefly described herein. For convenience, certain operations of method 100 are described with reference to various views of exemplary semiconductor devices at various manufacturing stages of the integrated circuit manufacturing process shown in Figures 2 through 88. However, it should be understood that the semiconductor devices and methods disclosed herein are not limited to method 100 or the paradigms shown in Figures 2 through 88. In Figures 2 through 85, even-numbered diagrams are cross-sectional views of the semiconductor structure from an x-cut perspective, while odd-numbered diagrams are cross-sectional views of the semiconductor structure from a y-cut perspective.

[0018] Method 100 may begin at step 110. In step 112, method 100 includes providing a semiconductor device at an intermediate stage of the manufacturing process. For convenience, semiconductor devices at various intermediate stages of the manufacturing process will be referred to herein as semiconductor structures. The semiconductor device can be any of the various types of semiconductor devices as described above. As an example, Figures 2 and 3 show cross-sectional views of the semiconductor structure at an intermediate stage of the manufacturing process of a FinFET device along the x and y directions, respectively (referred to as the x-section and y-section in Figure 88).

[0019] In the manufacturing stages shown in Figures 2 and 3, this semiconductor structure includes a fin structure (fin) 210 that extends from the substrate 270 (as shown in Figures 50 through 85 and 88) through a shallow trench isolation (STI) 216 above the substrate 270 and into a dummy sacrificial gate layer 212 above the STI 216. Optionally, a dummy fin 218 extends from the STI 216 and into the insulating layer 212. A hard mask layer 214 covers the insulating layer 212.

[0020] Substrate 270 can be one of many types of semiconductor substrates commonly used in semiconductor integrated circuit manufacturing, and integrated circuits can be formed therein and / or on it. Substrate 270 can be any construction including semiconductor materials, including but not limited to bulk silicon, semiconductor wafers, silicon-on-insulator (SOI) substrates, or silicon-germanium substrates. Other semiconductor materials can be used, including group III, group IV, and / or group V semiconductors.

[0021] Fin 210 may be formed from one or more materials commonly used for active fins in semiconductor devices. In some examples, fin 210 may include certain conductive materials, such as, but not limited to, silicon and silicon-based materials. In some examples, fin 210 may be formed through various combinations of lithography and etching processes.

[0022] The lithography and etching processes discussed herein may include, for example, forming a mask layer (which may include multiple layers, such as a pad oxide layer and a covering pad nitride layer) on top of the layer to be modified (e.g., substrate 270). The pad oxide layer may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer may serve as an adhesion layer between the layer to be modified and the covering pad nitride layer. In some embodiments, the pad nitride layer is formed from silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. For example, the pad nitride layer may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Lithography techniques may be used to pattern the mask layer. Generally, lithography techniques utilize the deposition, irradiation (exposure), and development of photoresist materials to remove a portion of the photoresist material. The remaining photoresist material protects the underlying materials (such as the mask layer in this example) from subsequent processing steps (such as etching). For example, a patterned mask is formed by using photoresist to pattern the pad oxide layer and the pad nitride layer. Once the patterned mask is formed, an etching process can be used to etch the layer to be modified.

[0023] The etching processes discussed in this article may include plasma etching processes, which may possess a certain degree of anisotropic characteristics. In such plasma etching processes (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources (such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), hydrogen fluoride (HF), ammonia (NH3), and other suitable gas sources and combinations thereof) may be used in conjunction with passivation gases (such as oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof). Furthermore, for plasma etching processes, the gas source and / or passivation gas can be diluted and controlled using gases such as argon (Ar), helium (He), neon (Ne), nitrogen (N2), and other suitable diluting gases and combinations thereof.

[0024] In another instance, the etching process discussed herein may include a wet etching process combined with a plasma etching process, which may possess a certain degree of isotropic characteristic. In such a wet etching process, the primary etching chemicals (e.g., hydrofluoric acid (HF), fluorine (F2), and other suitable primary etching chemicals and combinations thereof) may be used in conjunction with auxiliary etching chemicals (e.g., sulfuric acid (H2SO4), hydrogen chloride (HCl), hydrogen bromide (HBr), ammonia (NH3), phosphoric acid (H3PO4), and other suitable auxiliary etching chemicals and combinations thereof) and solvents (e.g., deionized water, alcohol, acetone, and other suitable solvents and combinations thereof) to control the aforementioned etching rate.

[0025] The dummy sacrificial gate layer 212 may include various insulating materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), certain high-k dielectric materials (e.g., hafnium oxide (HfO2) or aluminum oxide (Al2O3)), and polycrystalline silicon. In some examples, a thin layer of silicon oxide-based dielectric material may be disposed between the dummy sacrificial gate layer 212 and the fin 210, separating the dummy sacrificial gate layer 212 and the fin 210. The STI 216 may include one or more materials commonly used in STIs in semiconductor devices. In some examples, the STI 216 may include various insulating materials, such as silicon dioxide (SiO2). The dummy fin 218 may include one or more materials commonly used in dummy fins in semiconductor devices. In some examples, the dummy fin 218 may include the same or different materials as the fin 210. In some examples, the dummy fin 218 may include one or more layers of insulating material, such as, but not limited to, silicon nitride (Si3N4). The hard mask layer 214 may include one or more materials commonly used in hard masks in semiconductor devices. In some examples, the hard mask layer 214 may include various insulating materials, such as silicon nitride (Si3N4) or silicon monoxide (SiO).

[0026] In step 114, method 100 includes designating a region of the semiconductor device to form a fin insulation structure. This region may be designated to separate individual active regions of the semiconductor device. In Figure 3, region 211 is shown as typically designating the location of the fin insulation structure to be formed in a later stage of method 100.

[0027] As described above, a seam isolation structure is formed around region 211 before the fin insulating structure is formed. However, in some examples, other components of the semiconductor structure may be formed before the seam isolation structure is formed. For example, method 100 may include forming source / drain structures, ILDs, etc. Figures 4 through 7 illustrate exemplary processes for forming various components in a semiconductor structure before forming the seam isolation structure.

[0028] In Figures 4 and 5, a trench 236 is formed in the semiconductor structure by removing multiple portions of the dummy sacrificial gate layer 212 and the fin 210. In some examples, as previously described, multiple portions of the dummy sacrificial gate layer 212 and the fin 210 can be removed using lithography and etching processes. The cavity in the fin 210 at the bottom of the trench 236 is filled to form a source / drain structure 220.

[0029] The etch stop layer 222 may be formed on the walls of the trench 236 adjacent to the hard mask layer 214 and the dummy sacrificial gate layer 212. In some examples, the etch stop layer 222 may be formed by a deposition process, such as a chemical vapor deposition (CVD) process (e.g., plasma-enhanced chemical vapor deposition (PECVD), high aspect ratio process (HARP), or a combination thereof), an atomic layer deposition (ALD) process, another suitable process, or a combination thereof. The etch stop layer 222 may be formed of a material resistant to etchants used to remove other materials from the semiconductor structure in subsequent steps of method 100, which is discussed in more detail below. In some examples, the etch stop layer 222 may comprise or be formed of a silicon oxide (SiO)-based low-k material.

[0030] At the bottom of trench 236, a source / drain structure 220 can be formed on the exposed portion of fin 210 using, for example, an epitaxial layer growth process. In some examples, the epitaxial layer growth process may include depositing a thin layer of semiconductor material, such as, but not limited to, silicon-germanium (SiGe) or other materials with properties suitable for enhancing transistor performance. Chemical vapor deposition (CVD) processes can be used for epitaxial growth. CVD processes may include introducing a precursor gas containing the desired semiconductor element into a reaction chamber at a high temperature. These gases decompose and react on the surface, resulting in the deposition of a crystalline semiconductor layer. Depending on the specific transistor to be produced, dopant atoms may be introduced during epitaxial growth to achieve desired electrical properties in the source / drain regions. Dopants such as phosphorus, arsenic, or boron may be used to control the conductivity and carrier concentration in the epitaxial layer. After epitaxial growth, an annealing process may be performed to improve crystal quality and activate the dopants in the epitaxial layer.

[0031] In Figures 6 and 7, trench 236 may fill spacer layer 224, ILD layer 226, and hard mask layer 228. In some examples, spacer layer 224 may include one or more materials commonly used as spacers in semiconductor devices, or be formed of one or more materials, such as silicon oxide, silicon nitride, or silicon carbide-based materials. In some examples, ILD layer 226 may include one or more materials commonly used as ILD layers in semiconductor devices, or be formed of one or more materials commonly used as ILD layers in semiconductor devices. In some examples, ILD layer 226 may include various dielectric materials, including silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or combinations thereof. In some examples, hard mask layer 228 may include one or more materials commonly used as hard masks in semiconductor devices. In some examples, the hard mask layer 228 may comprise various insulating materials, such as silicon nitride (Si3N4) or silicon monoxide (SiO). The spacer layer 224, ILD layer 226, and hard mask layer 228 can all be formed through various processes, such as certain deposition processes. A chemical mechanical polishing (CMP) process can be performed to remove any remaining portion of the hard mask layer 228.

[0032] In step 116, method 100 may include forming a seam isolation structure around a region designated for the fin insulating structure (e.g., region 211). Various methods can be used to form the seam isolation structure. Figures 8 through 13 illustrate exemplary processes for forming a seam isolation structure in a semiconductor structure.

[0033] In Figures 8 and 9, a hard mask layer 230 is formed on the semiconductor structure. In some examples, the hard mask layer 230 may include various insulating materials, such as silicon nitride (Si3N4) or silicon monoxide (SiO). A patterning process (e.g., dicing polysilicon) is performed to form a trench 232 that extends through the hard mask layer 230, through the dummy sacrificial gate layer 212, and exposes multiple portions of the dummy fin 218 disposed on opposite sides of region 211, enabling simultaneous gate patterning and seam isolation structure formation for the CMODE process. In some examples, the dummy fin 218 may be omitted and the trench 232 may extend to STI 216.

[0034] In Figures 10 and 11, trench 232 is filled to form seam isolation structure 290. Seam isolation structure 290 may include or be formed of one or more dielectric materials, such as, but not limited to, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon carbide, etc., or combinations thereof. In some examples, seam isolation structure 290 may be formed of or comprise the same material as hard mask layer 230. In Figures 12 and 13, a CMP process has been performed to remove hard mask layer 230.

[0035] After the seam isolation structure 290 is formed and before the fin isolation feature is formed, other components of the semiconductor device, such as, but not limited to, gate structures, can be formed. Figures 14 through 19 illustrate exemplary fabrication processes for gate structures in semiconductor structures.

[0036] In Figures 14 and 15, trench 240 is formed by removing portions of the dummy sacrificial gate layer 212 to expose fins 210, STI 216, and dummy fins 218. In some examples, the removal of the insulating layer 212 can be performed using an etching process. In Figures 16 and 17, trench 240 has been filled with various layers forming gate structures within it, such as a first gate spacer 242, a second gate spacer 244, and a metallic gate layer 246. In some examples, the first gate spacer 242 and the second gate spacer 244 may comprise a single conformal layer or a combination of two or more conformal layers. In some examples, the first gate spacer 242 may comprise a dielectric material, such as, but not limited to, silicon-based dielectrics, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, etc. In some examples, the second gate spacer 244 may include a high-k dielectric material, such as, but not limited to, hafnium oxide, aluminum oxide, lanthanum oxide, zirconium oxide, etc. In some examples, a combination of a first gate spacer 242 and a second gate spacer 244 having an opposite or repeating order may be used.

[0037] In some examples, the metal gate layer 246 may be formed of one or more layers of metal material. For example, the metal gate layer 246 may be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. The work function layer may also be referred to as a work function metal. Exemplary p-type work function metals may include TiN, TAN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals may include Ti, Ag, TaAl, TaAIC, TiAlN, TAC, TACN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof.

[0038] The first gate spacer 242, the second gate spacer 244, and the metal gate layer 246 can be formed using various processes, such as certain deposition processes. CMP processes can be used between the formation processes as needed.

[0039] In Figures 18 and 19, trench 248 is formed by removing portions of the gate structure layers to achieve the desired gate structure dimensions. In some examples, removal can be performed using a metal gate etch-back process. Optionally, a metal layer 250 can be selectively formed on the exposed portions of the metal gate layer 246. Portions of the etch stop layer 222 and spacer layer 224 can be removed to expose a portion of the ILD layer 226 and the hard mask layer 228. A portion of the seam isolation structure 290 may also be exposed.

[0040] In step 118, method 100 includes forming a SAC sacrificial material layer. In Figures 20 and 21, trench 248 is filled with a SAC sacrificial material layer 252. The SAC sacrificial material layer 252 can be formed through various processes, such as certain deposition processes. The SAC sacrificial material layer 252 may include one or more materials commonly used in semiconductor devices as SAC sacrificial materials, or be formed from one or more materials commonly used in semiconductor devices as SAC sacrificial materials. In some examples, the SAC sacrificial material layer 252 may include or be formed from amorphous silicon. A hard mask layer 254 may be formed to cover the SAC sacrificial material layer 252 and the seam isolation structure 290. The hard mask layer 254 may include one or more materials commonly used in hard masks in semiconductor devices. In some examples, the hard mask layer 214 may include various insulating materials, such as silicon nitride (Si3N4), silicon oxide (SiO2), or silicon. As shown in Figure 20, the SAC sacrificial material layer 252 may include a seam extending through the semiconductor structure above the gate structure (e.g., seam 294 in Figures 86 and 87).

[0041] In step 120, method 100 includes forming a fin insulating structure between seam isolation structures 290. Figures 22 and 23 illustrate an exemplary process for forming a fin insulating structure in a semiconductor structure. In Figures 22 and 23, a photoresist layer 260, an intermediate layer 258, and a bottom layer 256 have been formed to cover a hard mask layer 254. A trench 262 has been formed in the photoresist layer 260, exposing the intermediate layer 258 and aligned with a region 211 designated for the fin insulating structure. Figure 88 is a perspective view of the semiconductor structure at the fabrication stage shown in Figures 22 and 23, where the ILD layer 226 is partially transparent to allow observation of the other layers.

[0042] In Figures 24 and 25, lithography and etching processes have been performed to extend trench 262 through a portion of intermediate layer 258, bottom layer 256, hard mask layer 254, and SAC sacrificial material layer 252 to define trench 264 and expose the metal layer 250 covering trench 264. Photoresist layer 260, intermediate layer 258, and bottom layer 256 are then removed. Specifically, at least some sidewalls of trench 264 are defined by seam isolation structures 290, preventing trench 264 from accessing seams within the SAC sacrificial material layer 252; that is, trench 264 is not in fluid communication with its adjacent seams.

[0043] In Figures 26 and 27, another etching process has been performed to remove the gate structure exposed by trench 264 and expose fin 210 and a portion of the underlying STI 216. In Figures 28 and 29, another etching process may be performed to remove fin 210 within the region 211 designated for the fin insulation structure, as well as portions of the adjacent STI 216 and substrate 270. The removal of fin 210 and adjacent material extends trench 264 to define additional trench 266.

[0044] In Figures 30 and 31, a CMODE refill process has been performed to fill trenches 264 and 266 to form fin insulating structure 268. Fin insulating structure 268 can be formed from a CMODE refill material, such as a low-k material or a dielectric material. It is noteworthy that the CMODE refill material does not flow or diffuse into the seams of the SAC sacrificial material layer 252 because the CMODE refill material is constrained by the seam isolation structure 290. In Figures 32 and 33, CMP is performed to remove excess portions of fin insulating structure 268, hard mask layer 254, and SAC sacrificial material layer 252 sufficient to expose the hard mask layer 228. Figure 86 is a top view schematically illustrating some layers of the semiconductor structure at the fabrication stages shown in Figures 32 and 33 (other layers and features are omitted for clarity). From this perspective, it is clear that the seam isolation structure 290 blocks the seam of the SAC sacrificial material layer 252, thereby preventing or reducing the possibility of CMODE refill material (or any other undesirable material) flowing or spreading into the seam.

[0045] In step 122, method 100 includes removing the SAC sacrificial material layer. In Figures 34 and 35, the SAC sacrificial material layer 252 has been removed to define trench 272 and expose the underlying gate structure as well as a portion of etch stop layer 222 and spacer layer 224.

[0046] In step 124, method 100 includes performing a SAC process to form source / drain contacts. Figures 36 through 45 illustrate exemplary processes for forming source / drain contacts in a semiconductor structure. In Figures 36 and 37, trench 272 is filled with a SAC insulating material layer 276 covering the gate structure, hard mask layer 228, seam isolation structure 290, and fin insulating structure 268. In some examples, the SAC insulating material layer 276 may include silicon nitride (SiN). In some examples, a metal contact layer 274 may be formed on the gate structure prior to forming the SAC insulating material layer 276. The metal contact layer 274 may include a conductive material of tungsten (W) or cobalt (Co).

[0047] In Figures 38 and 39, a CMP process has been performed to remove excess portions of the SAC insulating material layer 276 and the hard mask layer 228 to expose the ILD layer 226. In Figures 40 and 41, an etching process has been performed to remove the ILD layer 226, forming trenches 278 and exposing a portion of the source / drain structure 220.

[0048] In Figures 42 and 43, a dielectric layer 280 has been formed over the SAC insulating material layer 276, and trenches 278 have been filled with the conductive layer 282. In some embodiments, a silicon compound may be formed between the conductive layer 282 and the source / drain structure 220 to reduce the contact resistance between the metal and the source or drain. The dielectric layer 280 may include or be formed from various dielectric materials and may be formed through various deposition, lithography, and etching processes. Although represented as a single layer, the conductive layer 282 may include two or more layers to prevent metal migration to the dielectric layer. For example, the conductive layer 282 may include a filler material and a pad. In some embodiments, these layers may include a pad formed of a noble metal or an alloy thereof, such as, but not limited to, rhenium (Re), rhodium (Rh), ruthenium (Ru), or alloys thereof. In some embodiments, these layers may include a filler material formed of copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof. The conductive layer 282 may be formed through various deposition processes. In Figures 44 and 45, a CMP process has been performed to remove excess material from the conductive layer 282, thereby defining source / drain contacts above the source / drain structure 220.

[0049] Method 100 can end at step 126.

[0050] Figures 46 through 85 illustrate alternative processes for forming seam isolation structures in semiconductor structures. For convenience, consistent reference numerals are used throughout Figures 2 through 85 to identify identical or functionally related / equivalent elements. Given the similarity between the examples, the following discussion of Figures 46 through 85 will focus primarily on aspects of the examples that differ from the others in some significant or marked ways. Other aspects of the examples not discussed in detail, in terms of structure, function, materials, etc., can be substantially as described for one or more other examples (including those in Figures 2 through 45).

[0051] Initially, the semiconductor structure can have the same structure as shown in Figures 2 and 3. In Figure 47, region 211 is shown, which typically specifies the location of the fin insulating structure. Unlike the examples in Figures 2 through 45, in this example, a seam isolation structure can be formed before other components of the semiconductor structure. Therefore, in Figures 46 and 47, trench 233 is formed by removing a portion of the hard mask layer 214 and the dummy sacrificial gate layer 212 to expose a portion of the dummy fin 218. In some examples, a portion of the hard mask layer 214 can be removed using processes such as lithography and etching. In Figures 48 and 49, trench 233 is filled with an insulating material to extend the dummy fin 218 to define an extended dummy fin 292. In some examples, the insulating material can be the same material used to form the dummy fin 218. A CMP process can be performed to remove excess portions of the hard mask layer 214 and the extended dummy fin 292. In this example, the extended dummy fin 292 defines the seam isolation structure and can be considered as extending from or integrated with the dummy fin 218 and thus extending from the STI 216.

[0052] Figures 50 through 53 illustrate exemplary fabrication processes for forming the source / drain structure 220, spacer layer 224, ILD layer 226, and hard mask layer 228. In some examples, the source / drain structure 220, spacer layer 224, ILD layer 226, and hard mask layer 228 can be formed according to the description in Figures 4 through 7.

[0053] Figures 54 through 59 illustrate exemplary fabrication processes for forming gate structures in semiconductor structures. In some examples, the gate structure can be formed according to the description in Figures 14 through 19.

[0054] Figures 60 and 61 illustrate exemplary processes for forming a SAC sacrificial material layer 252 in a semiconductor structure. In some examples, the SAC sacrificial material layer 252 may be formed according to the description in Figures 20 and 21.

[0055] Figures 62 through 73 illustrate exemplary processes for forming fin insulating structures in semiconductor structures. In some examples, the fin insulating structures can be formed according to the descriptions in Figures 22 through 33. Figure 87 is a top view schematically representing some layers of the semiconductor structure at the fabrication stages shown in Figures 72 and 73 (other layers and features are omitted for clarity). From this perspective, it is clear that the extended dummy fins 292 block the seams of the SAC sacrificial material layer 252, thereby preventing or reducing the possibility of CMODE refill material (or any other undesirable material) flowing or diffusing into the seams.

[0056] In the examples of Figures 2 through 45, the semiconductor structure includes a seam isolation structure 290 formed to cover the dummy fin 218, and in the examples of Figures 46 through 73, the semiconductor structure includes an extended dummy fin 292 covering the dummy fin 218. However, in some examples, the dummy fin 218 may be omitted, and the methods shown and described in Figures 2 through 73 may be performed using either the seam isolation structure 290 or the extended dummy fin 292 formed to directly contact the STI 216.

[0057] Figures 74 and 75 illustrate exemplary processes for removing the SAC sacrificial material layer 252. In some instances, the SAC sacrificial material layer 252 may be removed according to the description in Figures 34 and 35.

[0058] Figures 76 through 85 illustrate exemplary processes for forming source / drain contacts in a semiconductor structure. In some instances, the source / drain contacts can be formed according to the description in Figures 36 through 45.

[0059] Therefore, this disclosure provides a semiconductor device and a method for manufacturing the same that can significantly reduce the likelihood of defects in a semiconductor device. In some embodiments, the semiconductor device includes a seam isolation structure configured to reduce the possibility of material flow or diffusion into the SAC sacrificial material during the CMODE process.

[0060] According to one embodiment, a semiconductor device is provided, including a substrate, fins covering the substrate and providing multiple active regions for at least two devices, and a fin insulating structure disposed to electrically isolate the active regions of at least two devices, wherein the fin insulating structure extends through the fins and into the substrate, wherein the fin insulating structure includes a dielectric material, and a butt joint isolation structure adjacent to the fins on multiple opposing sides of the fins, wherein the butt joint isolation structure defines multiple boundaries of the fin insulating structure on the sides of the fins.

[0061] According to another embodiment, a method for manufacturing a semiconductor device is provided. This method includes providing a substrate; forming a fin-covered substrate; forming a plurality of seam isolation structures adjacent to the fins on a plurality of oppositely disposed sides of the fins; forming a plurality of active regions of at least two devices on the fins; and forming a fin insulating structure disposed to electrically isolate the active regions of the at least two devices, wherein the fin insulating structure extends through the fins and into the substrate, wherein the fin insulating structure includes a first dielectric material, and wherein the seam isolation structures define a plurality of boundaries of the fin insulating structure on the sides of the fins.

[0062] According to yet another embodiment, a method for manufacturing a semiconductor device is provided. This method includes providing a substrate; forming a fin-covered substrate; forming a plurality of active regions for a plurality of devices on the fins; forming a plurality of seam isolation structures adjacent to the fins on a plurality of opposing sides of the fins, wherein the seam isolation structures extend from shallow trench isolation within a location adjacent to the fins, wherein the seam isolation structures are formed of a first dielectric material; forming a plurality of gate structures between the active regions of the devices; forming fin insulating structures disposed to electrically isolate at least two of the active regions of the devices, wherein the fin insulating structures extend through the fins and into the substrate, wherein the fin insulating structures include a second dielectric material, wherein the seam isolation structures define a plurality of boundaries of the fin insulating structures on the sides of the fins; and forming a plurality of contacts electrically coupled to the active regions of the devices.

[0063] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments may also be possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0064] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from its scope or spirit. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended claims.

[0065] 100: Method 110: Steps 112: Steps 114: Steps 116: Steps 118: Steps 120: Steps 122: Steps 124: Steps 126: Steps 210: Fins 211: Region 212: Dummy sacrificial gate layer or insulation layer 214: Hard mask layer 216: Shallow trench isolation 218: Fictitious fins 220: Source / Drain Structure 222: Etching Stop Layer 224: Spacer layer 226: ILD layer 228: Hard mask layer 230: Hard mask layer 232: Trench 233: Trench 236: Trench 240: Trench 242: First gate spacer 244: Second gate spacer 246: Metal gate layer 248: Trench 250: Metal layer 252: SAC Sacrificial Material Layer 254: Hard mask layer 256: Bottom layer 258: Intermediate Layer 260: Photoresist layer 262: Trench 264: Trench 266: Trench 268: Fin insulation structure 270:Substrate 272: Trench 274: Metal contact layer 276: SAC insulation material layer 278: Trench 280: Dielectric layer 282: Conductive layer 290: Joint isolation structure 292: Extended virtual fins 294: Seam x-cut: X-cut y-cut: Y-cut

[0066] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device, comprising: One substrate; A fin covering the substrate and providing multiple active regions for at least two devices; a fin insulating structure disposed to electrically isolate the active regions of the at least two devices, wherein the fin insulating structure extends through the fin and into the substrate, wherein the fin insulating structure includes a first dielectric material; and a butt joint isolation structure located adjacent to the fin on multiple opposing sides of the fin, wherein the butt joint isolation structure defines multiple boundaries of the fin insulating structure on the sides of the fin, wherein the fin insulating structure extends between two opposing sidewalls of the butt joint isolation structure, and the fin insulating structure and the butt joint isolation structure extend in different directions.

2. The semiconductor device as claimed in claim 1, wherein the butt joint isolation structure is located at multiple ends of a metal gate wire.

3. The semiconductor device as claimed in claim 1, wherein the fin insulating structure allows the butt joint isolation structure to directly contact the fin insulating structure.

4. A method for manufacturing a semiconductor device, comprising: Provide a substrate; A fin is formed to cover the substrate; Multiple seam isolation structures are formed on multiple oppositely arranged sides of the fin adjacent to the fin; Multiple active regions of at least two devices are formed on the fin; and a fin insulating structure is formed to electrically isolate the active regions of the at least two devices, wherein the fin insulating structure extends through the fin and into the substrate, wherein the fin insulating structure includes a first dielectric material, and wherein the seam isolation structures define multiple boundaries of the fin insulating structure on the sides of the fin.

5. The method for manufacturing a semiconductor device as described in claim 4 further includes: After the seam isolation structures are formed and before the fin insulation structure is formed, a plurality of self-aligned contact sacrificial material layers are formed, wherein the seam isolation structures are disposed between the self-aligned contact sacrificial material layers and the fin insulation structure; after the fin insulation structure is formed, the self-aligned contact sacrificial material layers are removed; and a self-aligned contact process is performed to form a plurality of contacts coupled to the active regions of the at least two devices.

6. A method of manufacturing a semiconductor device as claimed in claim 4, wherein forming the seam isolation structures includes positioning the seam isolation structures at a plurality of ends of a metal gate wire of the semiconductor device.

7. A method of manufacturing a semiconductor device as claimed in claim 4, wherein the fin insulating structure causes the seam isolation structures to be in direct contact with the fin insulating structure.

8. A method of manufacturing a semiconductor device as claimed in claim 4, wherein the fin insulating structure extends between two opposite sidewalls of the seam isolation structures, and the fin insulating structure and the seam isolation structures extend in different directions.

9. A method for manufacturing a semiconductor device, comprising: Provide a substrate; A fin is formed to cover the substrate; Multiple active regions for multiple devices are formed on the fin; multiple seam isolation structures are formed adjacent to the fin on multiple opposing sides of the fin, wherein the seam isolation structures extend from a shallow trench in a location adjacent to the fin, wherein the seam isolation structures are formed of a first dielectric material; multiple gate structures are formed between the active regions of the devices; a fin insulation structure is formed to electrically isolate at least two of the active regions of the devices, wherein the fin insulation structure extends through the fin and into the substrate, wherein the fin insulation structure includes a second dielectric material, wherein the seam isolation structures define multiple boundaries of the fin insulation structure on the sides of the fin; and multiple contacts are formed to electrically couple to the active regions of the devices.

10. The method of manufacturing a semiconductor device as described in claim 9 further includes: After the seam isolation structures are formed and before the fin insulation structure is formed, a plurality of self-aligned contact sacrificial material layers are formed, wherein the seam isolation structures are disposed between the self-aligned contact sacrificial material layers and the fin insulation structure; and after the fin insulation structure is formed, the self-aligned contact sacrificial material layers are removed, wherein forming the contacts includes performing a self-aligned contact process.

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