Semiconductor device and methods of formation

Abstract

Before forming the internal spacers and source / drain regions of the nanostructured transistors in the semiconductor device, a sacrificial semiconductor layer is removed from the layer stack of the semiconductor device. The sacrificial semiconductor layer can be removed together with a hybrid layer formed due to the mixing of materials between the sacrificial semiconductor layer and the semiconductor channel layer. The sacrificial semiconductor layer and the hybrid layer can be replaced with a sacrificial dielectric layer. The sacrificial dielectric layer can then be etched to form cavities in which internal spacers are formed.

Description

Technical Field

[0001] none Prior Technology

[0002] As semiconductor device manufacturing advances and technology node sizes shrink, transistors can be affected by short-channel effects (SCE), such as hot carrier degradation, barrier lowering, and quantum confinement. Furthermore, as gate lengths are reduced to achieve smaller technology nodes, source / drain (S / D) electron tunneling increases, thereby increasing the transistor's cutoff current (the current flowing through the transistor's channels when it is in off-configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors, such as those in nanowires, nanosheets, and gate-all-around (GAA) devices, are potential candidates for overcoming short-channel effects at smaller technology nodes. Nanostructure transistors are highly efficient structures that, compared to other types of transistors, can reduce SCE and enhance carrier mobility. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] When read in conjunction with the accompanying drawings, the following detailed description will provide the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figures 1A through 1C are schematic diagrams of exemplary embodiments of the fin definition process described herein. Figure 2 is a schematic diagram of the fabrication process of the example dummy gate structure described in this article. Figure 3 is a schematic diagram of an example implementation of the source / drain recess formation process described in this article. Figures 4A to 4C are schematic diagrams of exemplary embodiments of the sacrificial dielectric layer formation process described herein. Figure 5 is a schematic diagram of an example implementation of the internal spacer formation process described herein. Figures 6A and 6B are schematic diagrams of an example implementation of the source / drain region formation process described herein. Figures 7A and 7B are schematic diagrams of exemplary embodiments of the interlayer dielectric formation process described herein. Figures 8A to 8D are schematic diagrams of example implementations of the alternative gate process described herein. Figures 9A to 9D are schematic diagrams of exemplary embodiments of forming a semiconductor device as described herein. Figures 10A to 10D are schematic diagrams of exemplary embodiments of forming a semiconductor device as described herein. Figures 11A to 11D are schematic diagrams of exemplary embodiments of forming a semiconductor device as described herein. Figures 12A to 12C are schematic diagrams of exemplary embodiments of forming a semiconductor device as described herein. Figures 13A to 13C are schematic diagrams of exemplary embodiments of forming a semiconductor device as described herein. Figures 14A to 14F are schematic diagrams of exemplary embodiments of forming a semiconductor device as described herein. Figure 15 is a schematic diagram of an exemplary embodiment of the semiconductor device described herein. Figure 16 is a schematic diagram of an exemplary embodiment of the semiconductor device described herein. Figure 17 is a flowchart of an example process for forming a semiconductor device as described in this article. Figure 18 is a flowchart of an example process for forming a semiconductor device as described in this article. Figures 19A to 19F are schematic diagrams of an example embodiment of the semiconductor device 105 described herein. Figures 20A to 20F are schematic diagrams of an example embodiment of the semiconductor device 105 described herein. Implementation

[0005] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or words may be repeated in various examples. This repetition is for simplicity and clarity and is not, in itself, merely a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, the spatially related terms used herein, such as "below," "under," "below," "above," and "on," are for descriptive purposes to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations shown in the figures, these spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0007] In some cases, nanochannels of nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors) can be formed by creating a stack of alternating sacrificial and channel layers (sometimes called a superlattice), and the layer stack is etched to define the nanostructured channels. The sacrificial layers define the vertical spacing between the nanostructured channels and are subsequently removed and replaced with the gate structure of the nanostructured transistor. However, the inclusion of sacrificial layers can lead to the formation of various types of defects in the nanostructured transistor and / or may cause a reduction in the performance of the nanostructured transistor.

[0008] For example, nanostructured transistors may include internal spacers between the source / drain regions and the gate structure, and the mixing of the materials of the nanostructured channels and the sacrificial layer can lead to defects in the internal spacers, such as rounded corners. Rounded corners may occur when forming cavities for internal spacers in a nanostructured transistor, and may also occur due to reduced etch selectivity between the nanostructured channels and the sacrificial layer caused by mixing. Internal spacers can provide various process and / or performance benefits, such as electrical insulation between the source / drain regions and the gate structure, and / or protection of the source / drain regions from etching during gate replacement operations to replace the sacrificial nanostructure layer with the gate structure. However, when performing gate replacement operations, rounded corners may result in the internal spacers providing less etch buffering or etch stopping, and etching may occur through the internal spacers and into the source / drain regions. Etching of the source / drain regions may damage the crystal structure of the source / drain regions and / or may cause electrical shorting between the source / drain regions and the gate structure. This could lead to the failure of nanostructured transistors and potentially reduce the yield of nanostructured transistors on semiconductor devices.

[0009] As another example, a sacrificial layer can support nanostructured channels during the formation of the source / drain regions. While the support provided by the sacrificial layer reduces the likelihood of bending and / or thinning of the nanostructured channel, which might otherwise occur due to stresses applied to the channel during source / drain formation, the high stiffness of the sacrificial layer can effectively absorb most of the stresses applied to the channel, thus limiting the strain that may be induced within it. A quantitative amount of strain within the nanostructured channel can be beneficial because strain can alter the crystal structure of the channel, leading to higher charged carrier mobilities. Therefore, the limited strain that the high stiffness of the sacrificial layer can induce in the nanostructured channel may limit improvements in charged carrier mobility that can be achieved during the formation of the source / drain regions.

[0010] In some embodiments described herein, a sacrificial semiconductor layer is removed from the layer stack of the semiconductor device before forming the internal spacers and source / drain regions of the nanostructured transistors. The sacrificial semiconductor layer may be removed along with a hybrid layer that may be formed due to the mixing of materials between the sacrificial semiconductor layer and the semiconductor channel layer, and the sacrificial semiconductor layer and the hybrid layer may be replaced by a sacrificial dielectric layer. The sacrificial dielectric layer may then be etched to form a cavity in which the internal spacers are formed.

[0011] Compared to the selectivity between the sacrificial semiconductor layer and the semiconductor channel layer, the sacrificial dielectric layer provides greater etch selectivity between them, enabling increased control over over-etching of the cavity. This increased etch control, along with the removal of the mixed layer, allows the cavity to form sharp corners, resulting in near-square or right-angled cavities. The sharpness of these cavity angles, along with the subsequent formation of internal spacers within the cavity, provides greater protection against etching of the source / drain regions, reducing the likelihood of source / drain region damage. Furthermore, highly doped epitaxial regions can be formed on the internal spacers before the source / drain regions are formed, further protecting them from etching.

[0012] Additionally and / or alternatively, the dielectric material of the sacrificial dielectric layer may have less elasticity than the material of the sacrificial semiconductor layer. The less elasticity of the sacrificial dielectric layer allows it to deform rather than absorb the stress applied to the nanostructure channels of the transistor structure during the formation of the source / drain regions. This allows the stress to induce strain in the nanostructure channels, thereby enhancing the charged carrier mobility.

[0013] Figures 1A through 1C are schematic diagrams of an exemplary embodiment 100 of the fin definition process described herein. Exemplary embodiment 100 includes examples of forming a fin structure 155 for a semiconductor device 105 and relating to a shallow trench isolation (STI) region. The semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanocharged transistors, and / or other types of nanostructured transistors. Exemplary embodiment 100 includes examples of forming a fin structure 155 for a transistor in the semiconductor device 105 and relating to an STI region 175.

[0014] Figures 1A through 1C each show a perspective view of the semiconductor device 105 and a cross-sectional view along cross section AA in the perspective view. As shown in Figure 1A, the semiconductor device 105 is fabricated in conjunction with a semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates.

[0015] A layer stack 115 is formed over a semiconductor substrate 110. The layer stack 115 can be considered as a superlattice. The layer stack 115 includes alternating layers arranged in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes vertically alternating layers of sacrificial semiconductor layer 120 and semiconductor channel layer 125 over the semiconductor substrate 110. The number of sacrificial semiconductor layers 120 and semiconductor channel layers 125 shown in Figure 1A are examples, and other numbers of sacrificial semiconductor layers 120 and semiconductor channel layers 125 are within the scope of this disclosure.

[0016] The sacrificial semiconductor layer 120 and the semiconductor channel layer 125 can be "nanostructure" layers or "nanoscale" layers because they can each have a z-direction thickness on the order of nanometers. For example, they can each have a z-direction thickness of about 10 nanometers or less. However, other values ​​for the z-direction thickness of the sacrificial semiconductor layer 120 and the semiconductor channel layer 125 are within the scope of this disclosure.

[0017] The sacrificial semiconductor layer 120 allows for the definition of the vertical distance between adjacent nanostructure channels formed by the semiconductor channel layer 125, and the sacrificial semiconductor layer 120 serves as a placeholder layer for the gate structure subsequently formed for the transistors of the semiconductor device 105, the gate structure being formed around the nanostructure channels. The sacrificial semiconductor layer 120 includes a first material composition, and the semiconductor channel layer 125 includes a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the sacrificial semiconductor layer 120 may include silicon germanide (SiGe), and the semiconductor channel layer 125 may include silicon (Si). Depending on the type of etchant used, the sacrificial semiconductor layer 120 and / or the semiconductor channel layer 125 may be selectively etched (e.g., the sacrificial semiconductor layer 120 but not the semiconductor channel layer 125 may be etched, or the semiconductor channel layer 125 but not the sacrificial semiconductor layer 120 may be etched).

[0018] One or more types of deposition tools can be used to deposit and / or grow alternating layers of the layer stack 115 to include nanostructures (e.g., nanosheets) above the semiconductor substrate 110. For example, the deposition tools can be used to grow the sacrificial semiconductor layer 120 and / or the semiconductor channel layer 125 via epitaxial growth, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial techniques. Additionally and / or alternatively, the sacrificial semiconductor layer 120 and / or the semiconductor channel layer 125 can be deposited via chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition techniques.

[0019] As shown in the close-up view of the partial layer stack 115 in Figure 1A, mixing may occur between two or more nanostructure layers in the layer stack 115. For example, mixing may occur between the sacrificial semiconductor layer 120 and the vertically adjacent semiconductor channel layer 125. Mixing may result in cross-diffusion of silicon (Si) and / or germanium (Ge) between the sacrificial semiconductor layer 120 and the semiconductor channel layer 125. Therefore, a mixing layer 130 may be present between the sacrificial semiconductor layer 120 and the semiconductor channel layer 125. The mixing layer 130 may include a region of silicon germanide (SiGe) with a higher silicon (Si) concentration than the germanium (Ge) concentration in the mixing layer 130 (e.g., due to silicon diffusion from the semiconductor channel layer 125 to the sacrificial semiconductor layer 120). Cross-diffusion of silicon (Si) and / or germanium (Ge) between the sacrificial semiconductor layer 120 and the semiconductor channel layer 125 may occur due to the high-temperature process used to form the layer stack 115. The sacrificial semiconductor layer 120 and semiconductor channel layer 125 of the layer stack 115 can be formed by epitaxial growth, and in some embodiments, the process temperature can exceed 1000 degrees Celsius. Higher temperatures may result in increased crystalline quality. However, low-temperature processes are within the scope of this disclosure. During the formation of the layer stack 115, high process temperatures can cause the material in the sacrificial semiconductor layer 120 and / or the semiconductor channel layer 125 to migrate and mix between the sacrificial semiconductor layer 120 and the semiconductor channel layer 125, resulting in the formation of a mixed layer 130.

[0020] One or more mask layers may be formed (e.g., using one or more deposition tools) over the layer stack 115. The mask layers may include a hard mask (HM) layer 135, a capping layer 140, an oxide layer 145, and / or a nitride layer 150. The mask layers may be used to perform fin patterning operations to form a fin structure 155 in the semiconductor substrate 110.

[0021] As shown in Figure 1B, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This results in the formation of a fin structure 155 extending over the semiconductor substrate 110. The fin structure 155 may extend along the x-direction in the semiconductor device 105 and may be aligned along the y-direction in the semiconductor device 105. The fin structure 155 includes a portion 160 of the layer stack 115 above and / or on a fin portion 165 above the semiconductor substrate 110. The fin structure 155 may be formed by patterning one or more masking layers and etching the semiconductor substrate 110 based on the pattern formed in the one or more masking layers. The one or more masking layers may be patterned using photolithography techniques, including dual patterning or multi-patterning techniques. Etching tools may be used based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or a combination of the above.

[0022] As further shown in Figure 1B, some fin structures 155 can be formed with different widths for different types of nanostructured transistors. For example, a first subset of fin structures 155a can be formed for p-type nanostructured transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructured transistors), and a second subset of fin structures 155b can be formed for n-type nanostructured transistors (e.g., n-type metal oxide semiconductor (NMOS) nanostructured transistors). As another example, a first subset of fin structures 155a can be formed for nanostructured transistors configured to operate at lower volts, and a second subset of fin structures 155b can be formed for nanostructured transistors configured to operate at higher volts.

[0023] As shown in Figure 1C, the liner 170 and the STI region 175 are formed between adjacent fin portions 165 of the fin structure 155. The liner 170 and the STI region 175 may each comprise a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), undoped silicate glass (USG), low-k dielectric materials (e.g., dielectric materials having a dielectric constant of about 3.9 or less), and / or other suitable insulating materials.

[0024] A deposition tool can be used to conformally deposit the substrate 170 (e.g., using ALD or other conformal deposition techniques) and a dielectric layer can be deposited over the substrate 170 (e.g., using CVD, PVD, ALD, and other suitable deposition techniques) such that the dielectric layer completely fills the space between the fin structures 155 and extends above the top of the fin structures 155. A planarization tool can then be used to perform a planarization or polishing operation (e.g., chemical mechanical planarization, CMP) to planarize the dielectric layer such that the top surface of the dielectric layer and the top of the nitride layer 150 are approximately coplanar. The nitride layer 150 serves as a CMP stop layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form the STI region 175 such that the top surface of the STI region 175 and the bottommost sacrificial semiconductor layer 120 are approximately coplanar, or the top surface of the STI region 175 is below the bottommost sacrificial semiconductor layer 120.

[0025] In some embodiments, a hard masking layer (not shown) may be formed over the top of the STI region 175 between the fin structures 155 to protect the STI region 175 in subsequent processes. The hard masking layer may include nitrides such as silicon nitride (SixNy), silicon oxynitride, silicon carbide, silicon carbonitride (SiCN), and / or silicon oxycarbonitride (SiOCN), etc. The hard masking layer may be deposited using appropriate processes such as CVD, plasma-enhanced CVD (PECVD), ALD, etc. The material of the masking layer deposited over the sidewalls of the fin structure 155 may be removed by any suitable etching process, such as dry etching or wet etching.

[0026] As shown above, Figures 1A through 1C provide one example. Other examples may differ from those described in Figures 1A through 1C.

[0027] Figure 2 is a schematic diagram of an example embodiment 200 of the dummy gate formation process described herein. Example embodiment 200 includes an example of forming a dummy gate structure 205 for a nanostructured transistor for a semiconductor device 105. In some embodiments, the operations described in conjunction with example embodiment 200 are performed after the processes described in conjunction with Figures 1A to 1C.

[0028] Figure 2 shows a perspective view of a dummy gate structure 205 formed on semiconductor device 105. The dummy gate structure 205 (also called a dummy gate stack or temporary gate structure) is formed over a portion of fin structure 155 and a portion of STI region 175. The dummy gate structure 205 extends in the y-direction and is aligned in the x-direction such that the dummy gate structure 205 is approximately perpendicular to fin structure 155. The dummy gate structure 205 is a sacrificial structure, which is replaced by a substitute gate structure or substitute gate stack in subsequent process stages of semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) recess, where the source / drain regions of the nanostructured transistor are formed in fin structure 155.

[0029] The dummy gate structure 205 may include a gate electrode layer 210, a capping layer 215 above and / or on the gate electrode layer 210, a spacer layer 220 on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 below the gate electrode layer 210. The gate electrode layer 210 includes polycrystalline silicon (polysilicon, or PO) or other materials. The capping layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or other materials) and a nitride layer formed on the oxide layer (e.g., a pad nitride layer that may include silicon nitride such as Si3N4 or other materials). The spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 225 may include silicon oxide (e.g., SiOx such as SiO2), silicon nitride (e.g., SixNy such as Si3N4), high-k dielectric material (e.g., dielectric material having a dielectric constant greater than about 3.9) and / or other suitable materials.

[0030] The dummy gate structure 205 can be formed using a variety of semiconductor process technologies, such as depositing the dummy gate structure 205, patterning the dummy gate structure 205 to define the dummy gate structure 205, and / or other semiconductor process technologies.

[0031] Figure 2 further illustrates the reference cross sections used in the subsequent figures described herein. Cross section AA spans the fin structure 155 in the source / drain region of the semiconductor device 105 in the yz plane (considered an x-cut). Cross section BB is in the xz plane (considered a y-cut), which is perpendicular to cross section AA and spans the dummy gate structure 205 and along the fin structure 155 below. Cross section CC is in the xz plane, which is parallel to cross section AA and perpendicular to cross section BB, and along the dummy gate structure 205. For clarity, the subsequent figures refer to these reference cross sections. In some figures, some reference numerals for elements or features shown may be omitted to avoid obscuring other elements or features in order to facilitate the depiction of the figures.

[0032] As shown above, Figure 2 provides one example. Other examples may differ from those shown in Figure 2.

[0033] Figure 3 is a schematic diagram of an exemplary embodiment 300 of the source / drain recess formation process described herein. Exemplary embodiment 300 includes an example of forming a source / drain recess 305 for a source / drain region of a nanostructured transistor for a semiconductor device 105. Figure 3 is shown as a perspective view from Figure 2, including a perspective view of cross-section BB and cross-section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 300 are performed after the processes described in conjunction with Figures 1A to 2.

[0034] As shown in cross-sections BB and CC of Figure 3, the capping layer 215 of the dummy gate structure 205 may include a multilayer stack. The multilayer stack may include a capping layer 215a on the gate electrode layer 210 and a capping layer 215b on the capping layer 215a. Capping layers 215a and 215b may include different materials to provide etch selectivity and / or to protect the gate electrode layer 210 from removal while performing various planarization operations. In some embodiments, capping layer 215a includes a nitrogen-containing material such as silicon nitride (e.g., SixNy from Si3N4), and capping layer 215b includes an oxygen-containing material such as silicon oxide (e.g., SiOx from SiO2). However, other combinations of materials used for capping layers 215a and 215b are within the scope of this disclosure.

[0035] As further shown in cross sections BB and CC of Figure 3, spacer layer 220 may be located on the sidewall of dummy gate structure 205. Spacer layer 220 includes spacer layer 220a on the sidewall of dummy gate structure 205 and spacer layer 220b above spacer layer 220a. Spacer layers 220a and 220b may include different materials to provide etch selectivity to protect dummy gate structure 205 from etching during the formation of source / drain recess 305. In some embodiments, spacer layer 220a includes a low-dielectric-constant dielectric material, such as silicon oxide (SiOx, such as SiO2), and spacer layer 220b includes a high-dielectric-constant dielectric material, such as silicon nitride (SixNy, such as Si3N4). However, other combinations of materials used for spacer layers 220a and 220b are within the scope of this disclosure.

[0036] As further shown in cross-section BB of Figure 3, a source / drain recess 305 is formed through portion 160 of the fin structure 155 during the etching operation. The source / drain recess 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes the use of plasma etching technology, wet chemical etching technology, and / or other types of etching technology.

[0037] In some embodiments, the source / drain recess 305 also extends to a portion of the fin portion 165 of the fin structure 155. Specifically, the source / drain recess 305 may extend to the mesa region 310 within the fin structure 155. The sidewall of each portion of the source / drain recess 305 beneath the layer stack 115 corresponds to the sidewall of the mesa region 310. The mesa region 310 (also referred to as a pedestal or fin pedestal) refers to the region of the fin portion 165 of the fin structure 155 that extends above the top surface of the STI region 175.

[0038] Alternatively, in conjunction with Figures 9A through 9D, a source / drain recess 305 can be formed such that the bottom of the source / drain recess 305 does not extend downward (e.g., in the z-direction) to the mesa region 310 below the bottommost sacrificial semiconductor layer 120. In these embodiments, the bottom of the source / drain recess 305 may be approximately coplanar with the bottommost sacrificial semiconductor layer 120, or may be located at a higher vertical (z-direction) height in the semiconductor device 105 than the bottom surface of the bottommost sacrificial semiconductor layer 120. This can reduce the amount and / or likelihood of current leakage from the source / drain regions to be formed in the source / drain recess 305, which could otherwise occur through the mesa region 310.

[0039] The formation of source / drain recesses 305 defines nanostructure channels 315 (e.g., nanostructure channels 315 of nanostructure transistor structures) in semiconductor device 105. Nanostructure channels 315 extend between adjacent source / drain recesses 305 and are located below dummy gate structures 205 between adjacent source / drain recesses 305. Nanostructure channels 315 include silicon-based nanostructures (e.g., nanosheets or nanowires) as semiconductor channels for nanostructure transistors in semiconductor device 105. In some embodiments, nanostructure channels 315 may include silicon (Si), doped silicon, silicon-germanium (SiGe), and / or other silicon-based materials. Nanostructure channels 315 are arranged in a direction approximately perpendicular to semiconductor substrate 110 (e.g., the z-direction). In other words, nanostructure channels 315 are vertically arranged or stacked above semiconductor substrate 110.

[0040] As further shown in cross-section BB of Figure 3, the endpoints of the sacrificial semiconductor layer 120, the endpoints of the hybrid layer 130, and the endpoints of the nanostructure channel 315 are exposed in the source / drain recess 305.

[0041] As shown above, Figure 3 provides one example. Other examples may differ from those depicted in Figure 3.

[0042] Figures 4A through 4C are schematic diagrams of an exemplary embodiment 400 of the sacrificial dielectric layer formation process described herein. Example embodiment 400 includes an example where a sacrificial semiconductor layer 120 is replaced with a sacrificial dielectric layer 415. Figures 4A through 4C are each shown as perspective views from cross sections BB and CC of Figure 2. In some embodiments, the operations described in conjunction with example embodiment 400 are performed after the processes described in conjunction with Figures 1A through 3.

[0043] As shown in cross sections BB and CC of Figure 4A, the retained portions of the sacrificial semiconductor layer 120 can be removed between the nanostructure channels 315. In some embodiments, the retained portions of the sacrificial semiconductor layer 120 are etched and removed via source / drain recesses 305. As further shown in Figure 4A, the mixed layer 130 can also be removed from the semiconductor device 105 during the removal of the retained portions of the sacrificial semiconductor layer 120. Because the mixed layer 130 includes material that is also contained in the retained portions of the sacrificial semiconductor layer 120 (e.g., a portion of silicon germanium (SiGe)), the etchant used to etch the sacrificial semiconductor layer 120 also etches the mixed layer 130. Some etching of the nanostructure channels 315 may also occur during the removal of the retained portions of the sacrificial semiconductor layer 120. The removal of the retained portions of the sacrificial semiconductor layer 120 creates a space 405 between vertically adjacent nanostructure channels 315 that was previously occupied by the retained portions of the sacrificial semiconductor layer 120.

[0044] In some embodiments, the etchant may include a gas-based etchant, including a combination of a fluorine-based etchant (e.g., F2 gas) and a hydrofluoric acid etchant (e.g., HF gas). Other gases, such as purge gases, carrier gases, and / or other reactant gases, may also be supplied to the process chamber during the etching operation. These gases may include argon (Ar), ammonia (NH3), chlorine trifluoride (ClF3), and / or nitrogen (N2), etc. The etchant can be used to etch the sacrificial semiconductor layer 120 and the mixed layer 130 by removing silicon (Si) and germanium (Ge) from the sacrificial semiconductor layer 120 and the mixed layer 130. The removal of silicon (Si) from the sacrificial semiconductor layer 120 and from the mixed layer 130 can be caused by a reaction between a fluorine-based etchant (e.g., F2 gas) in the etchant and silicon-germanium (SiGe) in the sacrificial semiconductor layer 120 and the mixed layer 130. A fluorine-based etchant (e.g., F2 gas) in the etchant can attach to silicon (Si) and germanium (Ge) in the sacrificial semiconductor layer 120 and the mixed layer 130 to form germanium trifluoride (GeF3) and silicon trifluoride (SiF3), respectively. Fluorine migration may occur when fluorine (F) atoms migrate from germanium trifluoride molecules to silicon trifluoride molecules, resulting in the formation of germanium difluoride (GeF2) and silicon tetrafluoride (SiF4) gases. Silicon tetrafluoride is removed from the semiconductor device 105, causing silicon (Si) to be removed from the sacrificial semiconductor layer 120 and the mixed layer 130.

[0045] Removal of germanium (Ge) from the sacrificial semiconductor layer 120 and the mixed layer 130 can be caused by a combination of fluorine-based etchants (e.g., F2 gas) and hydrofluoric acid etchants (e.g., HF gas) in the etchant and a reaction between silicon-germanium (SiGe) in the sacrificial semiconductor layer 120 and the mixed layer 130. Fluorine (F) in fluorine-based etchants (e.g., F2 gas) and / or hydrofluoric acid etchants (e.g., HF gas) can attach to silicon (Si) and germanium (Ge) in the sacrificial semiconductor layer 120 and the mixed layer 130. Furthermore, hydrogen in the hydrofluoric acid etchant can attach to silicon (Si) and germanium (Ge) in the sacrificial semiconductor layer 120 and the mixed layer 130. Fluorine and hydrogen react with germanium to form GeH2F and SiHF2. Hydrogen migration may occur when hydrogen (H) atoms migrate from SiHF2 molecules to GeH2F molecules, resulting in the formation of GeH3F gas and silicon difluoride (SiF2). GeH3F gas is removed from the semiconductor device 105, causing germanium (Ge) to be removed from the sacrificial semiconductor layer 120 and the mixed layer 130.

[0046] As shown in cross sections BB and CC of Figures 4B and 4C, the sacrificial semiconductor layer 120 and the hybrid layer 130 are removed and replaced with a sacrificial dielectric layer 415. The sacrificial semiconductor layer 120 and the hybrid layer 130 can be replaced by the sacrificial dielectric layer 415 to achieve precise control over the size and shape of the cavity 420 in which the internal spacers of the semiconductor device 105 are formed. In particular, the etch selectivity between the dielectric material of the sacrificial dielectric layer 415 and the semiconductor material (e.g., silicon (Si)) of the nanostructure channel 315 can be greater than the etch selectivity between the semiconductor material (e.g., silicon-germanium (SiGe)) of the sacrificial semiconductor layer 120 and the semiconductor material (e.g., silicon (Si)) of the nanostructure channel 315. This greater etch selectivity allows the cavity 420 to be formed with sharper angles compared to retaining the sacrificial semiconductor layer 120 and the hybrid layer 130. The sharper angle of cavity 420 promotes the formation of internal spacers with sharper angles (instead of rounded corners for the internal spacers if the sacrificial semiconductor layer 120 and hybrid layer 130 were retained). This reduces the risk of etching through the nanostructure channel 315 at the corners of the internal spacers during the alternative gate process of replacing the dummy gate structure 205 with a high-dielectric-constant / metal gate structure. Therefore, replacing the sacrificial semiconductor layer 120 and hybrid layer 130 with the sacrificial dielectric layer 415 reduces the risk of etch damage to the source / drain regions formed in the source / drain recess 305.

[0047] Instead of forming the layer stack 115 with a sacrificial dielectric layer 415 instead of a sacrificial semiconductor layer 120, the sacrificial semiconductor layer 120 and the hybrid layer 130 can be removed and replaced with a sacrificial dielectric layer 415 to achieve higher process efficiency and higher quality nanostructure channels 315. Since the semiconductor channel layer 125 (formed by the nanostructure channel 315) is epitaxially grown, the sacrificial semiconductor layer 120 provides a semiconductor substrate with a lattice structure on which the semiconductor channel layer 125 can be grown. The sacrificial semiconductor layer 120 and the semiconductor channel layer 125 can have similar lattice constants, which provides high-quality epitaxial growth of the semiconductor channel layer 125. If the semiconductor channel layer 125 is grown on the sacrificial dielectric layer 415, lattice mismatch between the sacrificial dielectric layer 415 and the semiconductor channel layer 125 may lead to cracking and other defects in the semiconductor channel layer 125. Furthermore, because additional steps and etchants may be required to etch the semiconductor material of the semiconductor channel layer 125 and the dielectric material of the sacrificial dielectric layer 415 in separate steps, the time, complexity, and / or cost of forming the source / drain recess 305 may be greater (while the semiconductor channel layer 125 and the sacrificial semiconductor layer 120 can be etched in the same etching step using the same etchant to form the source / drain recess 305).

[0048] As shown in cross sections BB and CC of Figure 4B, dielectric layer 410 can be deposited along the bottom and sidewalls of source / drain recess 305. Dielectric layer 410 can be further deposited vertically in spaces (or regions) 405 between nanostructure channels 315, spaces 405 previously occupied by sacrificial semiconductor layer 120. In some embodiments, deposition tools are used to deposit dielectric layer 410 using CVD, PVD, ALD, and / or other deposition techniques. In some embodiments, deposition tools are used to deposit material of dielectric layer 410 using flowable deposition techniques. For example, material of dielectric layer 410 can be dispensed into source / drain recess 305 such that material can flow into spaces 405 perpendicular to adjacent nanostructure channels 315, and a curing process can be used to cure the material to form dielectric layer 410.

[0049] As shown in cross sections BB and CC of Figure 4C, excess material of the dielectric layer 410 on the sidewalls and bottom surface of the source / drain recess 305 is removed, leaving the dielectric layer 410 in the space 405 between the vertically adjacent nanostructure channels 315 as a sacrificial dielectric layer 415. Etching tools can be used to trim the dielectric layer 410 using wet etching, dry etching, and / or other suitable etching techniques.

[0050] The sacrificial dielectric layer 415 can be a "nanostructure" layer or a "nanoscale" layer, because each sacrificial dielectric layer 415 can have a z-direction thickness on the order of nanometers. For example, each sacrificial dielectric layer 415 can have a z-direction thickness of about 10 nanometers or less. However, other values ​​for the z-direction thickness of the sacrificial dielectric layer 415 are within the scope of this disclosure.

[0051] Flow deposition techniques (and / or other low-density deposition techniques) used to deposit dielectric layer 410 can result in a low material density for sacrificial dielectric layer 415, which in turn results in relatively low stiffness. For example, sacrificial dielectric layer 415 may comprise low-density silicon oxide, the Young's modulus of which is less than that of the semiconductor material of sacrificial semiconductor layer 120 and less than that of the semiconductor material of nanostructure channel 315. Therefore, the elasticity (e.g., elastic modulus) of sacrificial dielectric layer 415 is less than that of sacrificial semiconductor layer 120 and less than that of nanostructure channel 315. Consequently, compared to sacrificial semiconductor layer 120, sacrificial dielectric layer 415 absorbs a small amount of tensile and compressive stress applied to nanostructure channel 315. Therefore, the sacrificial dielectric layer 415 can support the nanostructure channel 315 during subsequent stress-inducing processes (e.g., source / drain formation) to prevent or reduce the risk of permanent deformation (e.g., bending, thinning) of the nanostructure channel 315, while still enabling the lattice of the nanostructure channel 315 to be strained to increase the carrier mobility in the nanostructure channel 315.

[0052] In some embodiments, the Young's modulus of the material of the sacrificial dielectric layer 415 is in the range of about 43 to about 92. In some embodiments, the Young's modulus of the material of the sacrificial semiconductor layer 120 is in the range of about 100 to about 190. In some embodiments, the Young's modulus of the material of the nanostructure channel 315 is in the range of about 130 to about 188. However, other values ​​and ranges of the Young's modulus of the materials of the sacrificial dielectric layer 415, the sacrificial semiconductor layer 120, and the nanostructure channel 315 are within the scope of this disclosure.

[0053] As further shown in cross section BB of Figure 4C, in one or more first etch operations, the endpoints of the sacrificial dielectric layer 415 exposed in the source / drain recess 305 are etched laterally (e.g., in the x-direction approximately parallel to the length of the sacrificial semiconductor layer 120), thus forming a cavity 420 between the endpoints of the nanostructure channel 315 exposed in the source / drain recess 305. Specifically, the etch tool can be used to laterally etch the endpoints of the sacrificial dielectric layer 415 beneath the dummy gate structure 205 through the source / drain recess 305 to form the cavity 420 between the endpoints of the nanostructure channel 315.

[0054] As shown in the close-up view of Figure 4C, cavity 420 may have sharp inner corners, and the sidewalls and inner surface of cavity 420 are approximately orthogonal. As shown above, the etch selectivity between the dielectric material of the sacrificial dielectric layer 415 and the semiconductor material of the nanostructure channel 315, combined with the removal of the mixed layer 130, enables the formation of sharp inner corners in cavity 420. In some embodiments, the angle of the inner corner of cavity 420 (shown as dimension D1 in Figure 4C) may be greater than 80 degrees and may be in the range of approximately 85 degrees to approximately 90 degrees. However, other angles of the inner corner are within the scope of this disclosure.

[0055] As shown above, Figures 4A through 4C provide one example. Other examples may differ from those described in Figures 4A through 4C.

[0056] Figure 5 is a schematic diagram of an exemplary embodiment 500 of the internal spacer formation process described herein. Exemplary embodiment 500 includes an example of forming internal spacers 505 between the endpoints of nanostructure channels 315 exposed in the source / drain recess 305. Figure 5 is shown as a perspective view from cross-section BB of Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 500 are performed after the processes described in conjunction with Figures 1A through 4C.

[0057] As shown in Figure 5, an internal spacer 505 is formed in the cavity 420 between the endpoints of the vertically adjacent nanostructure channels 315 in the source / drain recess 305. The internal spacer 505 reduces parasitic capacitance in the nanostructure transistor and protects the source / drain regions (subsequently formed in the source / drain recess 305) from being etched during nanosheet release operations to remove the sacrificial dielectric layer 415 between the nanostructure channels 315. The internal spacer 505 includes silicon nitride (SixNy), silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or other dielectric materials.

[0058] To form the internal spacers 505, deposition tools can be used to deposit a layer of dielectric material in the cavity 420 and along the sidewalls and bottom surface of the source / drain recess 305. CVD, PVD, ALD, and / or other deposition techniques can be used to deposit the dielectric material layer. Etching tools are used to subsequently remove excess material from the dielectric material layer in the source / drain recess 305, leaving a portion corresponding to the internal spacers 505 in the cavity 420.

[0059] As shown in the close-up view of Figure 5, the internal spacer 505 may have a sharp inner angle, approximately orthogonal between the sidewalls and inner surface of the internal spacer 505. The sharp inner angle may be achieved as a result of the techniques described above for replacing the sacrificial semiconductor layer 120 and the hybrid layer 130, forming a cavity 420 in the sacrificial dielectric layer 415. In some embodiments, the angle of the inner angle of the internal spacer 505 (shown as dimension D2 in Figure 5) may be greater than 80 degrees and may be in the range of about 85 degrees to about 90 degrees. However, other angles of the inner angle are within the scope of this disclosure.

[0060] As shown above, Figure 5 provides one example. Other examples may differ from those depicted in Figure 5.

[0061] Figures 6A and 6B are schematic diagrams of an exemplary embodiment 600 of the source / drain region formation process described herein. Exemplary embodiment 600 includes an example of forming a source / drain region 610 of a nanostructured transistor for a semiconductor device 105. Figures 6A and 6B are shown from multiple perspective views in Figure 2, including a perspective view of cross-section AA and cross-section BB in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 600 are performed after the processes described in Figures 1A through 5.

[0062] As shown in the cross-section BB of Figure 6A , a non-contiguous (non-contiguous) epitaxial region 605 is formed above the sidewall in the source / drain depression 305 . The epitaxial region 605 is discontinuous because the epitaxial region 605 is a discrete (discrete) region of materials that are not in contact with each other. However, in some embodiments, two or more epitaxial regions 605 may be in physical contact.

[0063] In the myopically illustrated example of Figure 6A , a non-continuous epitaxial region 605 is formed on the endpoint of the internal spacer 505 exposed in the source / drain depression 305 . The epitaxial region 605 may continuously span the endpoints of the internal spacer 505 and some of the endpoints of the nanostructure channel 315 on the vertical contralateral side of the internal spacer 505 . Thus, overlapping regions 615 occur at some endpoints of nanostructured channels 315 on the vertical contralateral side of epitaxial region 605 partially overlapping internal spacer 505 . The epitaxial region 605 in the overlap region 615 protects the interface between the internal spacer 505 and the nanostructured channel 315 from being etched during the alternative gate process of the semiconductor device 105 (otherwise it may lead to etching of the source / dip region 610 formed in the source / dip depression 305 ).

[0064] The position of the non-continuous epitaxial region 605 shown in Figure 6A is exemplary, the other positions of the non-continuous epitaxial region 605 are within the scope of the present disclosure. Additional examples of the location of the non-continuous epitaxial region 605 are illustrated in conjunction with Figures 12A through 12C and 13A through 13C .

[0065] To enable the non-continuous epitaxial region 605 to withstand etching during the alternative gate process of the semiconductor device 105 , the non-continuous epitaxial region 605 may include a semiconductor material (e.g., silicon (Si)) with a higher doping concentration than that in the source / drain region 610 .

[0066] For the p-type source / drain regions, the discontinuous epitaxial region 605 may be doped with p-type dopants such as boron (B) and / or gallium (Ga). P-type doping increases the energy required to remove electrons from the discontinuous epitaxial region 605 (e.g., from about 3.55 electron-volts to about 4.1 electron-volts), thus requiring greater energy to remove material from the discontinuous epitaxial region 605 compared to the source / drain region 610. The doping concentration of the p-type dopant in the discontinuous epitaxial region 605 can range from about 1 × 10¹⁹ atoms per cubic centimeter to about 1 × 10²² atoms per cubic centimeter to provide sufficient etch resistance to halogen-based etchants. However, other values ​​and ranges for the doping concentration of the p-type dopant in the discontinuous epitaxial region 605 are within the scope of this disclosure. Increasing the concentration of p-type doping can enhance the etch resistance of the discontinuous epitaxial region 605.

[0067] For the n-type source / drain regions, the discontinuous epitaxial region 605 may be doped with carbon (C) and / or other suitable dopants. Carbon doping increases the etch resistance of the discontinuous epitaxial region 605 without negatively impacting the n-type doping in the n-type source / drain regions. The carbon doping concentration in the discontinuous epitaxial region 605 can range from approximately 1 × 10¹⁹ atoms per cubic centimeter to approximately 1 × 10²² atoms per cubic centimeter in the discontinuous epitaxial region 605 to provide sufficient etch resistance to halogen-based etchants. However, other values ​​and ranges of carbon doping concentration in the discontinuous epitaxial region 605 are within the scope of this disclosure.

[0068] In some embodiments, the discontinuous epitaxial region 605 may be doped with a plurality of dopants, including carbon doping and n-type doping such as arsenic (As) and / or phosphorus (P). In some embodiments, the concentration of carbon doping may be increased and / or the concentration of n-type doping may be decreased to increase the etch resistance of the discontinuous epitaxial region 605.

[0069] As shown in cross sections AA and BB of Figure 6B, additional epitaxial material is deposited over the discontinuous epitaxial region 605 in the source / drain recess 305 to form the source / drain region 610 in the source / drain recess 305. The term "source / drain region" may be used individually or collectively as source region and / or drain region, depending on the context. The source / drain region 610 may be on the opposite side of the dummy gate structure 205, such that the nanostructure channel 315 below the dummy gate structure 205 extends between and electrically couples the source / drain regions 610.

[0070] The source / drain regions 610 may each comprise epitaxially grown silicon (Si) and / or other epitaxial growth materials. In some embodiments, the source / drain regions 610 comprise silicon doped with one or more doped types, such as p-type materials (e.g., boron (B) or germanium (Ge), other examples), n-type materials (e.g., phosphorus (P) or arsenic (As), other examples), and / or other types of doped materials. In these embodiments, the semiconductor device 105 may include a PMOS nanostructure transistor having a p-type source / drain region, an NMOS nanostructure transistor having an n-type source / drain region, and / or other types of nanostructure transistors.

[0071] The epitaxial technique used to form the source / drain region 610 can induce lateral stress in the nanostructure channel 315. For example, epitaxial growth (and the associated high process temperatures) can cause tensile and / or compressive stresses in the nanostructure channel 315. The sacrificial dielectric layer 415 supports the nanostructure channel 315 during the epitaxial growth of the source / drain region 610 (preventing or reducing the possibility of bending and / or thinning of the nanostructure channel 315), while allowing lateral stress to still induce stress in the nanostructure channel 315. Strain in the nanostructure channel 315 increases the charged carrier mobility in the nanostructure channel 315.

[0072] As shown in Figure 6B, in some embodiments, the epitaxial material of the source / drain region 610 fills the source / drain recess 305. In some embodiments, an isolation layer is formed at the bottom of the source / drain recess 305, and the epitaxial material of the source / drain region 610 is formed above the isolation layer. In some embodiments, the bottom surface of the source / drain region 610 may be approximately perpendicularly aligned with the bottom surface of the lowest layer of the internal spacer 505.

[0073] As shown above, Figures 6A and 6B provide one example. Other examples may differ from those described in Figures 6A and 6B.

[0074] Figures 7A and 7B are schematic diagrams of an exemplary embodiment 700 of the interlayer dielectric (ILD) formation process described herein. Figures 7A and 7B are shown from multiple perspective views in Figure 2, including a perspective view of cross-section BB and a perspective view of cross-section CC in Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 700 are performed after the processes in conjunction with Figures 1A through 6B.

[0075] As shown in cross-section BB of Figure 7A, a dielectric layer 705 is formed over the source / drain region 610. The dielectric layer 705 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 705 may be formed during alternative gate processes to replace the dummy gate structures 205 to reduce the likelihood of damage to the source / drain region 610 and / or prevent damage to the source / drain region 610. The dielectric layer 705 may be referred to as an ILD zero (ILD 0) layer or other ILD layers. The dielectric layer 705 may include silicon oxide (SiOx), USG, FSG, and / or other suitable low dielectric constant materials. Deposition tools may be used to deposit the dielectric layer 705 using PVD, ALD, CVD, and / or other suitable deposition techniques. In some implementations, a contact etch stop layer (CESL) (not shown) is conformally deposited (e.g., through a deposition tool) over the source / drain region 610 prior to the formation of the dielectric layer 705.

[0076] As shown in cross sections BB and CC of Figure 7B, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. The planarization operation can cause the capping layers 215a and 215b to be removed from the dummy gate structure 205, exposing the top of the gate electrode layer 210 of the dummy gate structure 205.

[0077] As further shown in Figure 7B, during subsequent operations such as alternative gate processes, a capping layer 710 may be formed over the dielectric layer 705 to protect the dielectric layer 705. The capping layer 710 may include examples such as silicon nitride (SixNy), silicon carbonitride (SiCN), silicon oxynitride (SiON), or combinations thereof.

[0078] As shown above, Figures 7A and 7B provide one example. Other examples may differ from those described in Figures 7A and 7B.

[0079] Figures 8A through 8D are schematic diagrams of an exemplary embodiment 800 of the alternative gate process described herein. For the nanostructure transistor of semiconductor device 105, the alternative gate process is a process of removing the remaining portions of the dummy gate structure 205 and the sacrificial dielectric layer 415 from semiconductor device 105 and replacing them with a high-dielectric-constant / metal gate structure (e.g., an alternative gate structure). Figures 8A through 8D are perspective views, respectively, taken from cross-section BB and cross-section CC of Figure 2. In some embodiments, the operations described in conjunction with exemplary embodiment 800 are performed after the processes described in conjunction with Figures 1A through 7B.

[0080] As shown in cross sections BB and CC of Figure 8A, a dummy gate removal operation can be performed. The dummy gate removal operation includes removing a dummy gate structure 205 (e.g., the gate electrode layer 210 of the dummy gate structure 205) from the semiconductor device 105. Removal of the dummy gate structure 205 leaves an opening (or recess) between the capping layers 710. The dummy gate structure 205 can be removed in one or more etching operations. This etching operation can include plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques.

[0081] As shown in cross sections BB and CC of Figure 8B, the gate dielectric layer 225 can be removed from the semiconductor device 105. The removal of the dummy gate structure 205 and the gate dielectric layer 225 provides access to the underlying sacrificial dielectric layer 415 in subsequent nanosheet removal processes. The gate dielectric layer 225 can be removed in one or more etching operations. These etching operations can include plasma etching techniques, wet chemical etching techniques, and / or other types of etching techniques.

[0082] As shown in cross sections BB and CC of Figure 8C, the nanosheet release operation may include performing an etching operation to laterally etch the sacrificial dielectric layer 415 to remove the sacrificial dielectric layer 415 from between vertically adjacent nanostructure channels 315. The removal of the sacrificial dielectric layer 415 leaves a space 805 between vertically adjacent nanostructure channels 315.

[0083] As shown in a close-up view of Figure 8C, the epitaxial region 605 in the overlap region 615 protects the interface between the internal spacer 505 and the nanostructure channel 315 from etching during the wafer release process. Additionally and / or alternatively, the sharp inner corners of the internal spacer 505 (achieved at least in part by replacing the sacrificial semiconductor layer 120 and the hybrid layer 130 with a sacrificial dielectric layer 415) prevent and / or reduce the likelihood of etching of the interface between the internal spacer 505 and the nanostructure channel 315 during the wafer release process. Therefore, the etch resistance of the sharp inner corners of the internal spacer 505 and / or the epitaxial region 605 prevents and / or reduces the likelihood of etching into (e.g., damaging) the source / drain region 610 during wafer release operations that replace the gate process.

[0084] As shown in cross sections BB and CC of Figure 8D, the gate dielectric layer 810 may be formed around the nanostructure channel 315. In some embodiments, the gate dielectric layer 810 is also formed above the mesa region 310. Deposition tools may be used to deposit the gate dielectric layer 810 using PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, the gate dielectric layer 810 is a high-dielectric-constant gate dielectric layer comprising one or more high-dielectric-constant materials (e.g., dielectric materials having a dielectric constant greater than that of silicon dioxide (SiO2) (dielectric constant about 3.9). Examples include lanthanum oxide (LaxOy, e.g., La2O3), hafnium oxide (HfOx, e.g., HfO2), zirconium oxide (ZrOx, e.g., ZrO2), and / or aluminum oxide (AlxOy, e.g., Al2O3). Additionally and / or alternatively, silicon dioxide (SiO2) and / or other dielectric materials may be used instead of high dielectric constant dielectric materials. In some embodiments, the gate dielectric layer 810 may have a thickness ranging from about 0.5 nanometers to about 3 nanometers. However, other values ​​in the range are within the scope of this disclosure.

[0085] As further shown in Figure 8D, a gate structure 815 of the nanostructured transistor of the semiconductor device 105 can be formed above the gate dielectric layer 810. The gate structure 815 can be formed in the space 805 previously occupied by the sacrificial dielectric layer 415, such that the gate structure 815 surrounds the nanostructure channel 315 above one or more sides of the nanostructure channel 315. The material of the gate structure 815 can be deposited between vertically adjacent nanostructure channels 315.

[0086] Gate structure 815 includes one or more conductive metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo). Deposition tools can be used to deposit gate structure 815 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. Gate structure 815 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and gate structure 815 is deposited on top of the seed layer. In some embodiments, after depositing gate structure 815, planarization tools can be used to planarize gate structure 815.

[0087] In some embodiments, one or more work function metal layers (not shown) may be deposited over the gate dielectric layer 810, and a gate structure 815 may be deposited over the one or more work function metal layers. The work function metal layers may be used to adjust the work function of the gate structure 815.

[0088] In some embodiments, for a PMOS nanostructure transistor, the gate structure 815 is a p-type gate structure, and a p-type work function metal layer is formed as the gate structure 815. In some embodiments, the p-type work function metal layer may include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals having a work function greater than about 4.7 eV, to adjust the work function of the gate structure 815 such that the adjusted work function is close to the valence band (EV) of the material of the nanostructure channel 315.

[0089] In some embodiments, for NMOS nanostructure transistors, the gate structure 815 is an n-type gate structure, and an n-type work function metal layer is formed as the gate structure 815. In some embodiments, the n-type work function metal layer may include one or more n-type metals, such as titanium aluminum (TiAl) and / or titanium aluminum carbon (TiAlC), to adjust the work function of the gate structure 815 so that the work function is close to the conduction band (EC) of the material of the nanostructure channel 315.

[0090] As shown above, Figures 8A through 8D provide one example. Other examples may differ from those described in Figures 8A through 8D.

[0091] Figures 9A through 9D are schematic diagrams of an exemplary embodiment 900 of forming the semiconductor device 105 described herein. As shown in Figure 9A, the source / drain recess formation process in exemplary embodiment 900 may differ from the source / drain recess formation process shown and described in conjunction with Figure 3, because the source / drain recess 305 is formed at a z-direction depth in the semiconductor device 105 such that the bottom of the source / drain recess 305 does not extend downward (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as shown in Figure 9A, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height in the semiconductor device 105 higher than the bottom surface of the bottommost sacrificial semiconductor layer 120.

[0092] Etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0093] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0094] As shown in Figure 9B, the sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 and an internal spacer 505. The sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 in conjunction with a similar method described in Figures 4A to 4C, and the internal spacer 505 may be formed in conjunction with a similar method described in Figure 5.

[0095] As shown in Figure 9C, a source / drain region 610 is formed in the source / drain recess 305. The source / drain region 610 is formed using a similar method described in Figures 6A to 6B, except that the discontinuous epitaxial region 605 is omitted from the semiconductor device 105 in the example embodiment 900. Furthermore, the source / drain region 610 is formed such that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415 in the semiconductor device 105. This reduces the amount and / or likelihood of leakage current from the source / drain region 610, which could occur through the mesa region 310.

[0096] As shown in Figure 9D, dielectric layer 705 and capping layer 710 can be formed using a similar method as described in Figures 7A and 7B. Furthermore, the alternative gate process for semiconductor device 105 can be performed using a similar method as described in Figures 8A to 8D to replace the dummy gate structure 205 and sacrificial dielectric layer 415 with gate dielectric layer 810 and gate structure 815.

[0097] As shown above, Figures 9A through 9D provide one example. Other examples may differ from those described in Figures 9A through 9D.

[0098] Figures 10A to 10D are schematic diagrams of an exemplary embodiment 1000 of forming the semiconductor device 105 described herein. As shown in Figure 10A, the source / drain recess formation process in the exemplary embodiment 1000 may differ from the source / drain recess formation process shown and described in conjunction with Figure 3, because the source / drain recess 305 is formed at a z-direction depth in the semiconductor device 105 such that the bottom of the source / drain recess 305 does not extend downward (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as shown in Figure 10A, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height in the semiconductor device 105 higher than the bottom surface of the bottommost sacrificial semiconductor layer 120.

[0099] Etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0100] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0101] As shown in Figure 10B, the sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 and an internal spacer 505. The sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 in conjunction with a similar method described in Figures 4A to 4C, and the internal spacer 505 may be formed in conjunction with a similar method described in Figure 5.

[0102] As shown in Figure 10C, discontinuous epitaxial regions 605 and 610 are formed in the source / drain recess 305. The discontinuous epitaxial region 605 may be formed above the internal spacer 505, and the source / drain region 610 may be formed using a similar method as described in Figures 6A and 6B. However, the source / drain region 610 is formed such that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or in the semiconductor device 105, it may be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415. This reduces the amount and / or likelihood of leakage current from the source / drain region 610, which may occur through the mesa region 310.

[0103] As shown in Figure 10D, dielectric layer 705 and capping layer 710 can be formed using a similar method as described in Figures 7A and 7B. Furthermore, the alternative gate process for semiconductor device 105 can be performed using a similar method as described in Figures 8A to 8D to replace the dummy gate structure 205 and sacrificial dielectric layer 415 with gate dielectric layer 810 and gate structure 815.

[0104] As shown above, Figures 10A through 10D provide one example. Other examples may differ from those described in Figures 10A through 10D.

[0105] Figures 11A to 11D are schematic diagrams of an exemplary embodiment 1100 of forming the semiconductor device 105 described herein. In the exemplary embodiment 1100, an isolation spacer 1105 is formed at the bottom of the source / drain recess 305 to control the formation of the source / drain region 610 within the source / drain recess 305. In particular, the isolation spacer 1105 defines the position of the bottom surface of the source / drain region 610, which enables the source / drain region 610 to be formed such that the bottom of the source / drain region 610 and the bottom surface of the bottommost sacrificial semiconductor layer 120 are approximately coplanar, or can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415 in the semiconductor device 105.

[0106] As shown in Figure 11A, the source / drain recess formation process in Example Embodiment 1100 may differ from the source / drain recess formation process shown and described in conjunction with Figure 3, because the source / drain recess 305 is formed at a z-direction depth in the semiconductor device 105 such that the bottom of the source / drain recess 305 does not extend downward (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as shown in Figure 10A, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height in the semiconductor device 105 higher than the bottom surface of the bottommost sacrificial semiconductor layer 120.

[0107] Etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0108] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0109] As further shown in Figure 11A, the sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 and an internal spacer 505. The sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 in conjunction with a similar method described in Figures 4A to 4C, and the internal spacer 505 may be formed in conjunction with a similar method described in Figure 5.

[0110] As shown in Figure 11B, an isolation spacer 1105 is formed at the bottom of the source / drain recess 305. The isolation spacer 1105 may be formed such that the top surface of the isolation spacer 1105 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or may be located at a vertical (z-direction) height above the bottom surface of the bottommost sacrificial dielectric layer 415 in the semiconductor device 105.

[0111] In some embodiments, the spacer 1105 comprises a dielectric material, such as silicon oxide (SiOx) and / or silicon nitride (SixNy). In these embodiments, deposition tools can be used to deposit the spacer 1105 using PVD, ALD, CVD, and / or other suitable deposition techniques. In some embodiments, the spacer 1105 comprises a semiconductor material (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe)) or a doped semiconductor material (e.g., a p-type doped semiconductor material, an n-type doped semiconductor material, a carbon (C) doped semiconductor material). In these embodiments, deposition tools can be used to deposit the spacer 1105 using epitaxial growth techniques.

[0112] In some embodiments, the spacer 1105 has a z-direction thickness smaller than that of the inner spacer 505. In some embodiments, the z-direction thickness of the spacer 1105 is in the range of about 1 nanometer to about 3 nanometers. However, other values ​​and ranges of the z-direction thickness of the spacer 1105 are within the scope of this disclosure.

[0113] As shown in Figure 11C, discontinuous epitaxial regions 605 and 610 are formed in the source / drain recess 305. The discontinuous epitaxial region 605 may be formed over the internal spacer 505, and the source / drain region 610 is formed using a similar method as described in Figures 6A and 6B. However, the source / drain region 610 is formed over the isolation spacer 1105 in the source / drain recess 305. The isolation spacer 1105 ensures that the bottom surface of the source / drain region 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or may be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415 in the semiconductor device 105. This reduces the amount and / or likelihood of leakage current from the source / drain region 610, which may occur through the mesa region 310.

[0114] As shown in Figure 11D, dielectric layer 705 and capping layer 710 can be formed using a similar method as described in Figures 7A and 7B. Furthermore, the alternative gate process for semiconductor device 105 can be performed using a similar method as described in Figures 8A to 8D to replace the dummy gate structure 205 and sacrificial dielectric layer 415 with gate dielectric layer 810 and gate structure 815.

[0115] As shown above, Figures 11A through 11D provide one example. Other examples may differ from those described in Figures 11A through 11D.

[0116] Figures 12A to 12C are schematic diagrams of an exemplary embodiment 1200 of forming the semiconductor device 105 described herein. In exemplary embodiment 1200, discontinuous epitaxial regions 605 are primarily formed on the endpoints of nanostructure channels 315 exposed through source / drain recesses 305, which is the opposite of exemplary embodiment 600, as shown in Figures 6A and 6B, where they are primarily formed on internal spacers 505.

[0117] As shown in Figure 12A, the source / drain recess formation process in Example Embodiment 1200 may differ from the source / drain recess formation process shown and described in conjunction with Figure 3, because the source / drain recess 305 is formed at a z-direction depth in the semiconductor device 105 such that the bottom of the source / drain recess 305 does not extend downward (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as shown in Figure 12A, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height in the semiconductor device 105 higher than the bottom surface of the bottommost sacrificial semiconductor layer 120.

[0118] Etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0119] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0120] As further shown in Figure 12A, the sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 and an internal spacer 505. The sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 in conjunction with a similar method described in Figures 4A to 4C, and the internal spacer 505 may be formed in conjunction with a similar method described in Figure 5.

[0121] As shown in Figure 12C, discontinuous epitaxial regions 605 and 610 are formed in the source / drain recess 305. The discontinuous epitaxial regions 605 and 610 can be formed using a similar method described in Figures 6A and 6B. However, the source / drain regions 610 are formed such that the bottom of the source / drain regions 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415 in the semiconductor device 105. This reduces the amount and / or likelihood of leakage current from the source / drain regions 610, which may occur through the mesa region 310.

[0122] Furthermore, as shown in the close-up view of Figure 12B, the discontinuous epitaxial region 605 is primarily formed on the endpoints of the nanostructure channel 315 exposed through the source / drain recess 305, which is the opposite of the example embodiment 600 shown in Figures 6A and 6B, where it is primarily formed on the internal spacer 505. In example embodiment 1200, the epitaxial region 605 may continuously span across the endpoints of the nanostructure channel 315 and portions of the internal spacer 505 on the vertically opposite side of the nanostructure channel 315. Therefore, an overlap region 615 occurs where the vertical endpoint portion of the epitaxial region 605 overlaps with the portion of the internal spacer 505 on the vertically opposite side of the nanostructure channel 315.

[0123] Compared to the epitaxial process parameters used to achieve the formation of the discontinuous epitaxial region 605 in Example Embodiment 600 of Figures 6A and 6B, in Example Embodiment 1200, different epitaxial process parameters can be used to achieve the formation of the discontinuous epitaxial region 605. Examples include different chamber pressures, different deposition temperatures, different gas flow rates, different annealing temperatures, and / or different growth rates. These parameters can be used to achieve the formation of the discontinuous epitaxial region 605 in Example Embodiment 1200, compared to the formation of the discontinuous epitaxial region 605 in Example Embodiment 600 of Figures 6A and 6B.

[0124] As shown in Figure 12C, dielectric layer 705 and capping layer 710 can be formed using a similar method as described in Figures 7A and 7B. Furthermore, the alternative gate process for semiconductor device 105 can be performed using a similar method as described in Figures 8A to 8D, replacing the dummy gate structure 205 and sacrificial dielectric layer 415 with gate dielectric layer 810 and gate structure 815.

[0125] As shown above, Figures 12A through 12C provide one example. Other examples may differ from those described in Figures 12A through 12C.

[0126] Figures 13A to 13C are schematic diagrams of an exemplary embodiment 1300 of forming the semiconductor device 105 described herein. In the exemplary embodiment 1300, discontinuous epitaxial regions 605 are formed such that each epitaxial region 605 spans the entirety of a nanostructure channel 315 and the entirety of an adjacent internal spacer 505.

[0127] As shown in Figure 13A, the source / drain recess formation process in Example Embodiment 1300 may differ from the source / drain recess formation process shown and described in conjunction with Figure 3, because the source / drain recess 305 is formed at a z-direction depth in the semiconductor device 105 such that the bottom of the source / drain recess 305 does not extend downward (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as shown in Figure 13A, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height in the semiconductor device 105 higher than the bottom surface of the bottommost sacrificial semiconductor layer 120.

[0128] Etching of the source / drain recess 305 can stop at the bottom surface of the bottommost sacrificial semiconductor layer 120. In some embodiments, the bottom surface of the source / drain recess 305 may be non-uniform and / or may have a concave or convex cross-sectional profile.

[0129] In some embodiments, the source / drain recess 305 may be etched into the mesa region 310 below the bottom sacrificial semiconductor layer 120, and a portion of the source / drain recess 305 below the bottom sacrificial semiconductor layer 120 may be filled with a buffer layer (e.g., a silicon buffer layer, a boron-doped silicon buffer layer) such that the top surface of the buffer layer and the bottom surface of the bottom sacrificial semiconductor layer 120 are approximately coplanar, or located at a vertical (z-direction) height above the bottom surface of the bottom sacrificial semiconductor layer 120 in the semiconductor device 105. The buffer layer may be formed by epitaxial growth or deposited by CVD and / or other suitable deposition techniques.

[0130] As further shown in Figure 13A, the sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 and an internal spacer 505. The sacrificial semiconductor layer 120 may be replaced by a sacrificial dielectric layer 415 in conjunction with a similar method described in Figures 4A to 4C, and the internal spacer 505 may be formed in conjunction with a similar method described in Figure 5.

[0131] As shown in Figure 13C, discontinuous epitaxial regions 605 and 610 are formed in the source / drain recess 305. The discontinuous epitaxial regions 605 and 610 can be formed using a similar method described in Figures 6A and 6B. However, the source / drain regions 610 are formed such that the bottom of the source / drain regions 610 and the bottom surface of the bottommost sacrificial dielectric layer 415 are approximately coplanar, or can be located at a vertical (z-direction) height higher than the bottom surface of the bottommost sacrificial dielectric layer 415 in the semiconductor device 105. This reduces the amount and / or likelihood of leakage current from the source / drain regions 610, which may occur through the mesa region 310.

[0132] Furthermore, as shown in the close-up view of Figure 13B, the formation of discontinuous epitaxial regions 605 is such that each epitaxial region 605 spans both the entirety of the nanostructure channel 315 and the entirety of the adjacent internal spacer 505, which is the opposite of the case shown in Example Embodiment 600 of Figures 6A and 6B, where the regions are primarily formed on the internal spacers 505. In Example Embodiment 1300, the epitaxial regions 605 may continuously span only a portion of a single nanostructure channel 315 and only a portion of the adjacent internal spacer 505. Therefore, the epitaxial regions 605 are located above the interface between the adjacent nanostructure channel 315 and the internal spacer 505.

[0133] Compared to the epitaxial process parameters used to achieve the formation of the discontinuous epitaxial region 605 in Example Embodiment 600 of Figures 6A and 6B, in Example Embodiment 1300, different epitaxial process parameters can be used to achieve the formation of the discontinuous epitaxial region 605. Examples include different chamber pressures, different deposition temperatures, different gas flow rates, different annealing temperatures, and / or different growth rates. These parameters can be used to achieve the formation of the discontinuous epitaxial region 605 in Example Embodiment 1300, compared to the formation of the discontinuous epitaxial region 605 in Example Embodiment 600 of Figures 6A and 6B.

[0134] As shown in Figure 13C, dielectric layer 705 and capping layer 710 can be formed using a similar method as described in Figures 7A and 7B. Furthermore, the alternative gate process for semiconductor device 105 can be performed using a similar method as described in Figures 8A to 8D to replace the dummy gate structure 205 and sacrificial dielectric layer 415 with gate dielectric layer 810 and gate structure 815.

[0135] As shown above, Figures 13A through 13C provide one example. Other examples may differ from those described in Figures 13A through 13C.

[0136] Figures 14A to 14F are schematic diagrams of an exemplary embodiment 1400 of forming a semiconductor device 105 as described herein. Exemplary embodiment 1400 includes an example of forming a multilayer structure with a sacrificial dielectric layer 415.

[0137] As shown in Figure 14A, the source / drain recess formation process in Example Embodiment 1400 may differ from the source / drain recess formation process shown and described in conjunction with Figure 3, because the source / drain recess 305 is formed at a z-direction depth in the semiconductor device 105 such that the bottom of the source / drain recess 305 does not extend downward (e.g., in the z-direction) into the mesa region 310 below the bottommost sacrificial semiconductor layer 120. Instead, as shown in Figure 14A, the bottom of the source / drain recess 305 may be approximately coplanar with the bottom surface of the bottommost sacrificial semiconductor layer 120, or may be located at a vertical (z-direction) height in the semiconductor device 105 higher than the bottom surface of the bottommost sacrificial semiconductor layer 120.

[0138] As shown in Figure 14B, the sacrificial semiconductor layer 120 can be removed using a similar method as described in Figures 4A through 4C.

[0139] As shown in Figure 14C, in conjunction with a similar method described in Figures 4A to 4C, the sacrificial semiconductor layer 120 can be replaced by a sacrificial dielectric layer 415, except that the sacrificial dielectric layer 415 forms a multilayer structure. The multilayer structure includes a core 415b and a substrate 415a. The substrate 415a may surround the core 415b between the core 415b and the nanostructure channel 315. The substrate 415a may have a smaller thickness than the core 415b. For example, the substrate 415a may have a thickness of about 1 nanometer, while the core 415b may have a thickness greater than 1 nanometer. However, all other values ​​are within the scope of this disclosure.

[0140] The core 415b may comprise a low-elasticity material, such as low-density silicon oxide (SiOx), porous silicon oxide, other porous materials with extremely low dielectric constants, and / or other materials having a Young's modulus smaller than that of the nanostructure channel 315. The core 415b may be deposited as a flowable film (e.g., as described above in conjunction with Figures 4A to 4C) to achieve a low-density core 415b. The substrate 415a comprises a high-density dielectric material, such as silicon nitride (SixNy) or other high-dielectric-constant dielectric materials, high-density silicon oxide (SiOx), and / or other high-density materials. The substrate 415a may be deposited via ALD to achieve a high-density and nanometer-thickness substrate 415a.

[0141] The core 415b provides the sacrificial dielectric layer 415 with low elasticity, enabling it to resist and absorb stresses induced within the nanostructure channel 315. The liner 415a provides higher elasticity than the core 415b and reduces the likelihood of deformation of the nanostructure channel 315. The nanometer thickness of the liner 415a allows it to support the nanostructure channel 315 without reducing (or minimally reducing) the stress applied to it.

[0142] As further shown in Figure 14C, internal spacers 505 can be formed in cavities 420 at the endpoints of the sacrificial dielectric layer 415. The internal spacers 505 can be formed in conjunction with a similar method described in Figure 5, except that the internal spacers 505 formed above the core 415b and the liner 415a of the sacrificial dielectric layer 415 are formed on their inner surfaces.

[0143] As shown in Figure 14D, after forming the internal spacer 505, discontinuous epitaxial regions 605 and source / drain regions 610 can be formed in the source / drain recess 305. In some embodiments, the discontinuous epitaxial region 605 is formed above the internal spacer 505 using a method similar to that described in Figures 6A and 6B. In some embodiments, the discontinuous epitaxial region 605 is formed above the endpoints of the nanostructure channel 315 using a method similar to that described in Figures 12A to 12C. In some embodiments, the discontinuous epitaxial region 605 is formed above the endpoints of the nanostructure channel 315 and above the internal spacer 505 using a method similar to that described in Figures 13A to 13C. In some embodiments, the discontinuous epitaxial region 605 is omitted using a method similar to that described in Figures 9A to 9D. In some embodiments, the source / drain region 610 is formed using a method similar to that described in Figures 9A to 9D.

[0144] As shown in Figure 14E, dielectric layer 705 and capping layer 710 can be formed using a similar method described in Figures 7A and 7B. Further shown in Figure 14E, dummy gate structure 205 and sacrificial dielectric layer 415 can be removed using a similar method described in Figures 8A to 8D, except for the removal of core 415b and substrate 415a of sacrificial dielectric layer 415. In some embodiments, core 415b and substrate 415a of sacrificial dielectric layer 415 are removed together (e.g., in the same etch operation) from semiconductor device 105. In some embodiments, core 415b is removed in a first etch operation, and substrate 415a is removed in a second etch operation after core 415b is removed.

[0145] As shown in Figure 14F, the dummy gate structure 205 and the sacrificial dielectric layer 415 can be replaced by the gate dielectric layer 810 and the gate structure 815 in combination with a similar method described in Figures 8A to 8D.

[0146] As shown above, Figures 14A through 14F provide one example. Other examples may differ from those described in Figures 14A through 14F.

[0147] Figure 15 is a schematic diagram of an exemplary embodiment 1500 of the semiconductor device 105 described herein. In exemplary embodiment 1500, the semiconductor device 105 includes one or more PMOS nanostructure transistors 1505 and / or one or more NMOS nanostructure transistors 1510. In some embodiments, the semiconductor device 105 includes only PMOS nanostructure transistors 1505. In some embodiments, the semiconductor device 105 includes only NMOS nanostructure transistors 1510.

[0148] In some embodiments, the PMOS nanostructure transistor 1505 may include a p-type gate structure 815a, which includes one or more p-type work function metals. In some embodiments, the PMOS nanostructure transistor 1505 may include a p-type source / drain region 610a, which includes one or more p-type doped semiconductor materials (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe)) such as boron (B) and / or germanium (Ge). Doping of the p-type source / drain region 610a may increase the electrical performance of the p-type source / drain region 610a and / or induce compressive stress in the PMOS nanostructure transistor 1505.

[0149] The discontinuous epitaxial region 605a of the PMOS nanostructure transistor 1505 may include a higher p-type doping concentration (e.g., B) than the p-type doping concentration included in the p-type source / drain region 610a. The higher p-type doping concentration allows the discontinuous epitaxial region 605a to withstand etching during the replacement gate process of the PMOS nanostructure transistor 1505, thus protecting the p-type source / drain region 610a from etching during the replacement gate process. In some embodiments, the discontinuous epitaxial region 605a of the PMOS nanostructure transistor 1505 may include less Ge doping. The lower Ge doping concentration allows the discontinuous epitaxial region 605a to better withstand etching during the replacement gate process of the PMOS nanostructure transistor 1505, thus protecting the p-type source / drain region 610a from etching during the replacement gate process. In some implementations, Ge doping can be omitted from the discontinuous epitaxial region 605a of the PMOS nanostructure transistor 1505.

[0150] In some embodiments, the NMOS nanostructure transistor 1510 may include an n-type gate structure 815b, which includes one or more n-type work function metals. In some embodiments, the NMOS nanostructure transistor 1510 may include an n-type source / drain region 610b, which includes one or more n-type doped semiconductor materials (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe)) doped with examples such as arsenic (As) and / or phosphorus (P). Furthermore, the n-type source / drain region 610b may be doped with carbon (C). The n-type doping of the n-type source / drain region 610b can increase the electrical performance of the n-type source / drain region 610b and induce tensile stress in the nanostructure channel 315 of the NMOS nanostructure transistor 1510. Additionally and / or alternatively, the n-type source / drain region 610b may include semiconductor alloys such as silicon phosphide (SiP) and / or silicon arsenide (SiAs).

[0151] The discontinuous epitaxial region 605b of the NMOS nanostructure transistor 1510 may include a carbon doping concentration greater than that included in the n-type source / drain region 610b. This higher carbon doping concentration allows the discontinuous epitaxial region 605b to withstand etching during the replacement gate process of the NMOS nanostructure transistor 1510, thus protecting the n-type source / drain region 610b from etching during the replacement gate process. In some embodiments, carbon doping may be omitted from the discontinuous epitaxial region 605b of the NMOS nanostructure transistor 1510.

[0152] In some implementations, the discontinuous epitaxial region 605b of the NMOS nanostructure transistor 1510 may include less arsenic doping and / or less phosphorus doping. The lower doping concentration of arsenic and / or phosphorus allows the discontinuous epitaxial region 605b to better withstand etching during the replacement gate process of the NMOS nanostructure transistor 1510, thus protecting the n-type source / drain region 610b from etching during the replacement gate process.

[0153] As shown above, Figure 15 provides one example. Other examples may differ from those shown in Figure 15.

[0154] Figure 16 is a schematic diagram of an exemplary embodiment 1600 of the semiconductor device 105 described herein. As shown in Figure 16, the discontinuous epitaxial region 605 has an approximately triangular cross-sectional profile. The triangular cross-sectional profile of the discontinuous epitaxial region 605 can create a sidewall 1605 with an approximately zig-zag profile for the source / drain region 610. For example, the sidewall 1605 may include segments 1610 and 1615, which are arranged alternately along the sidewall 1605. Segment 1610 may be at an angle in a first direction, and segment 1615 may be at an angle in a second direction. In some embodiments, the first and second directions are opposite (or mirror) directions.

[0155] In other embodiments, the discontinuous epitaxial region 605 may have an approximately half-circle or semi-circle cross-sectional profile. In some embodiments, the discontinuous epitaxial region 605 may have an amorphous cross-sectional profile.

[0156] In some embodiments, in electron microscope images (e.g., in transmission electron microscopy (TEM) images), a higher doping concentration of the discontinuous epitaxial region 605 relative to the source / drain region 610 of the semiconductor device 105 can cause the discontinuous epitaxial region 605 to appear darker relative to the source / drain region 610 in the microscope image. Therefore, the interface between the discontinuous epitaxial region 605 and the source / drain region 610 can be seen in the microscope image.

[0157] As shown above, Figure 16 provides one example. Other examples may differ from those shown in Figure 16.

[0158] Figure 17 is a flowchart of an example process 1700 for forming a semiconductor device 105 as described herein. In some embodiments, one or more process blocks of Figure 17 are performed using one or more other types of semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or semiconductor process tools.

[0159] As shown in Figure 17, process 1700 may include forming a semiconductor channel layer and a sacrificial semiconductor layer, which are arranged alternately in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device (block 1710). For example, one or more semiconductor process tools may be used to form a semiconductor channel layer (e.g., semiconductor channel layer 125) and a sacrificial semiconductor layer (e.g., sacrificial semiconductor layer 120), which are arranged alternately in a direction approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0160] As further shown in Figure 17, process 1700 may include performing a first etch operation to etch the semiconductor channel layer and the sacrificial semiconductor layer to form a source / drain recess (block 1720). For example, one or more semiconductor process tools may be used to perform the first etch operation to etch the semiconductor channel layer and the sacrificial semiconductor layer to form a source / drain recess (e.g., source / drain recess 305), as described herein. In some embodiments, the source / drain recess defines a nanostructure channel (e.g., nanostructure channel 315) that is arranged in a direction approximately perpendicular to the semiconductor substrate. In some embodiments, the nanostructure channels and the sacrificial semiconductor layer are arranged alternately in a direction approximately perpendicular to the semiconductor substrate.

[0161] As further shown in Figure 17, process 1700 may include performing a second etch operation to remove the sacrificial semiconductor layer from the semiconductor device (block 1730). For example, one or more semiconductor process tools may be used to perform the second etch operation to remove the sacrificial semiconductor layer from the semiconductor device, as described herein.

[0162] As further shown in Figure 17, process 1700 may include forming a sacrificial dielectric layer (block 1740) in the space previously occupied by a sacrificial semiconductor layer between nanostructure channels. For example, one or more semiconductor process tools may be used to form a sacrificial dielectric layer (e.g., sacrificial dielectric layer 415) in the space previously occupied by a sacrificial semiconductor layer (e.g., space 405) between nanostructure channels, as described herein.

[0163] As further shown in Figure 17, process 1700 may include forming source / drain regions (block 1750) in the source / drain recess. For example, one or more semiconductor process tools may be used to form source / drain regions (e.g., source / drain region 610, p-type source / drain region 610a, n-type source / drain region 610b) in the source / drain recess, as described herein.

[0164] Process 1700 may include additional implementations, such as any single implementation or any combination of implementations described below and / or related to one or more other processes described elsewhere herein.

[0165] In the first embodiment, performing a second etching operation to remove the sacrificial semiconductor layer includes performing a second etching operation to remove the sacrificial semiconductor layer through a source / drain recess.

[0166] In the second embodiment, either alone or in combination with the first embodiment, forming a sacrificial dielectric layer includes forming a dielectric layer on the sidewalls of the source / drain recesses and in the space previously occupied by the sacrificial semiconductor layer between the nanostructure channels, and performing a third etching operation to trim the dielectric layer such that a portion of the dielectric layer remaining in the space previously occupied by the sacrificial semiconductor layer between the nanostructure channels serves as the sacrificial dielectric layer.

[0167] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the Young's modulus of the dielectric material of the sacrificial dielectric layer is less than the Young's modulus of the semiconductor material of the sacrificial semiconductor layer.

[0168] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the Young's modulus of the dielectric material of the sacrificial dielectric layer is smaller than the Young's modulus of the semiconductor material of the nanostructure channel.

[0169] In the fifth embodiment, the sacrificial dielectric layer comprises a porous silicon oxide (SiOx) material, either alone or in combination with one or more of the first to fourth embodiments.

[0170] In the sixth embodiment, the sacrificial dielectric layer is formed, either alone or in combination with one or more of the first to fifth embodiments, by including a liner (e.g., liner 415a) deposited through ALD, and a porous silicon oxide (SiOx) core (e.g., core 415b) deposited as a sacrificial dielectric layer as a flowable film.

[0171] Although Figure 17 shows example blocks of process 1700, in some embodiments, process 1700 includes additional blocks, fewer blocks, different blocks, or blocks arranged differently than those shown in Figure 17. Additionally or alternatively, two or more blocks of process 1700 may be executed in parallel.

[0172] Figure 18 is a flowchart of an example process 1800 for forming a semiconductor device as described herein. In some embodiments, one or more process blocks of Figure 18 are performed using one or more other types of semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or semiconductor process tools.

[0173] As shown in Figure 18, process 1800 may include forming a semiconductor channel layer and a sacrificial semiconductor layer, which are arranged alternately in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device (block 1810). For example, one or more semiconductor process tools may be used to form a semiconductor channel layer (e.g., semiconductor channel layer 125) and a sacrificial semiconductor layer (e.g., sacrificial semiconductor layer 120), which are arranged alternately in a direction approximately perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0174] As further shown in Figure 18, process 1800 may include forming a source / drain recess (block 1820) through a semiconductor channel layer and a sacrificial semiconductor layer. For example, one or more semiconductor process tools may be used to form a source / drain recess (e.g., source / drain recess 305) through a semiconductor channel layer and a sacrificial semiconductor layer, as described herein.

[0175] As further shown in Figure 18, process 1800 may include removing a sacrificial semiconductor layer from a semiconductor device via a source / drain recess (block 1830). For example, one or more semiconductor process tools may be used to remove the sacrificial semiconductor layer from a semiconductor device via a source / drain recess, as described herein.

[0176] As further shown in Figure 18, process 1800 may include forming a sacrificial dielectric layer (block 1840) in a space previously occupied by a sacrificial semiconductor layer between semiconductor channel layers. For example, one or more semiconductor process tools may be used to form a sacrificial dielectric layer (e.g., sacrificial dielectric layer 415) in a space previously occupied by a sacrificial semiconductor layer (e.g., space 405) between semiconductor channel layers, as described herein.

[0177] As further shown in Figure 18, process 1800 may include forming an internal spacer (block 1850) over the endpoints of the sacrificial dielectric layer exposed through the source / drain recess. For example, one or more semiconductor process tools may be used to form an internal spacer (e.g., internal spacer 505) over the endpoints of the sacrificial dielectric layer exposed through the source / drain recess, as described herein.

[0178] As further shown in Figure 18, process 1800 may include forming a discontinuous epitaxial region (block 1860) above the sidewalls of the source / drain recess. For example, one or more semiconductor process tools may be used to form a discontinuous epitaxial region (e.g., discontinuous epitaxial region 605) above the sidewalls of the source / drain recess, as described herein.

[0179] As further shown in Figure 18, process 1800 may include forming a source / drain region (block 1870) over a discontinuous epitaxial region in the source / drain recess. For example, one or more semiconductor process tools may be used to form a source / drain region (e.g., source / drain region 610, p-type source / drain region 610a, n-type source / drain region 610b) over a discontinuous epitaxial region in the source / drain recess, as described herein.

[0180] Process 1800 may include additional implementations, such as any single implementation or any combination of implementations described below and / or related to one or more other processes described elsewhere herein.

[0181] In the first embodiment, forming a discontinuous epitaxial region includes forming a discontinuous epitaxial region above the internal spacer.

[0182] In the second embodiment, either alone or in combination with the first embodiment, forming a discontinuous epitaxial region includes forming a discontinuous epitaxial region above the endpoints of the semiconductor channel layer exposed by the source / drain recess.

[0183] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 1800 includes forming a bottom isolation spacer (e.g., isolation spacer 1105) at the bottom of the source / drain recess and forming a source / drain region above the bottom isolation spacer in the source / drain recess.

[0184] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the top surface of the bottom spacer in the semiconductor device is higher than the bottommost inner spacer of the inner spacer in the source / drain recess.

[0185] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the p-type transistor structure of the semiconductor device (e.g., PMOS nanostructure transistor 1505) includes a source / drain region, and the discontinuous epitaxial region includes a p-type doped semiconductor material such as B.

[0186] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the n-type transistor structure of the semiconductor device (e.g., NMOS nanostructure transistor 1510) includes a source / drain region, and the discontinuous epitaxial region includes a carbon (C) doped semiconductor material.

[0187] Although Figure 18 shows example blocks of process 1800, in some embodiments, process 1800 includes additional blocks, fewer blocks, different blocks, or blocks arranged differently than those shown in Figure 18. Additionally or alternatively, two or more blocks of process 1800 may be executed in parallel.

[0188] Figures 19A to 19F are schematic diagrams of an exemplary embodiment 1900 of forming the semiconductor device 105 described herein. Exemplary embodiment 1900 includes an example of forming a multilayer structure of a sacrificial dielectric layer 415. Exemplary embodiment 1900 is similar to exemplary embodiment 1400 shown in Figures 14A to 14F, except that the core 415b of the sacrificial dielectric layer 415 is implemented as air spacers. Therefore, the dielectric constant of the core 415b of the sacrificial dielectric layer 415 can have a dielectric constant of approximately 1.0.

[0189] As shown above, Figures 19A through 19F provide one example. Other examples may differ from those described in Figures 19A through 19F.

[0190] Figures 20A to 20F are schematic diagrams of an exemplary embodiment 2000 of forming the semiconductor device 105 described herein. Exemplary embodiment 2000 is similar to exemplary embodiment 900 shown in Figures 10A to 10D, except that a sacrificial dielectric layer 415 is implemented as an air spacer. Therefore, the dielectric constant of the sacrificial dielectric layer 415 can have a dielectric constant of approximately 1.0.

[0191] As shown above, Figures 20A through 20F provide one example. Other examples may differ from those described in Figures 20A through 20F.

[0192] Thus, a sacrificial semiconductor layer is removed from the semiconductor device's layer stack before the formation of the internal spacers and source / drain regions of the nanostructured transistors. The sacrificial semiconductor layer can be removed together with a hybrid layer, formed by mixing the materials of the sacrificial semiconductor layer and the semiconductor channel layer, and both the sacrificial semiconductor layer and the hybrid layer can be replaced by a sacrificial dielectric layer. The sacrificial dielectric layer can then be etched to form cavities, within which internal spacers are formed. Compared to the selectivity between the sacrificial semiconductor layer and the semiconductor channel layer, the sacrificial dielectric layer provides greater etch selectivity between them, enabling increased control over over-etching of the cavities. Additionally and / or alternatively, the dielectric material of the sacrificial dielectric layer can have lower elasticity than the material of the sacrificial semiconductor layer.

[0193] As described in more detail above, some embodiments described herein provide a method. The method includes forming a semiconductor channel layer and a sacrificial semiconductor layer, such that the semiconductor channel layer and the sacrificial semiconductor layer are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device. The method includes performing a first etch operation to etch the semiconductor channel layer and the sacrificial semiconductor layer to form a source / drain recess, the source / drain recess defining a nanostructure channel, the nanostructure channel being arranged in a direction approximately perpendicular to the semiconductor substrate, the nanostructure channel and the sacrificial semiconductor layer being arranged alternately in a direction approximately perpendicular to the semiconductor substrate. The method includes performing a second etch operation to remove the sacrificial semiconductor layer from the semiconductor device. The method includes forming a sacrificial dielectric layer in the space between the nanostructure channels previously occupied by the sacrificial semiconductor layer. The method includes forming source / drain regions in the source / drain recess.

[0194] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes nanostructure channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure surrounding the nanostructure channels. The semiconductor device includes source / drain regions on one side of an adjacent gate structure and at the endpoints of adjacent nanostructure channels. The semiconductor device includes an internal spacer between the source / drain regions and the gate structure. The semiconductor device includes a discontinuous region between the source / drain regions and at least one nanostructure channel or internal spacer.

[0195] As described in more detail above, some embodiments described herein provide a method. The method includes forming a semiconductor channel layer and a sacrificial semiconductor layer, such that the semiconductor channel layer and the sacrificial semiconductor layer are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device. The method includes forming a source / drain recess through the semiconductor channel layer and the sacrificial semiconductor layer. The method includes removing the sacrificial semiconductor layer from the semiconductor device through the source / drain recess. The method includes forming a sacrificial dielectric layer in a space previously occupied by the sacrificial semiconductor layer between semiconductor channel layers. The method includes forming an internal spacer over the endpoints of the sacrificial dielectric layer exposed by the source / drain recess. The method includes forming a discontinuous epitaxial region over the sidewalls of the source / drain recess. The method includes forming a source / drain region over the discontinuous epitaxial region in the source / drain recess.

[0196] The terms "approximately" and "substantially" can refer to a given quantity of value that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. The terms "approximately" and "substantially" can refer to a percentage of that value given the given quantity disclosed herein.

[0197] The features of many embodiments outlined above will enable those skilled in the art to better understand the viewpoints of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same benefits as the embodiments described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0198] 100: Example Implementation 105: Semiconductor Devices 110: Semiconductor substrate 115: Layer stacking 120: Sacrificial Semiconductor Layer 125: Semiconductor Channel Layer 130: Hybrid Layer 135: Hard Mask 140: Overlay 145: Oxide layer 150: Nitride layer 155: Fin Structure 155a: Fin structure 155b: Fin structure 160: Part 165: Fin section 170: Lining 175: STI region 200: Example Implementation 205: Virtual gate structure 210: Gate electrode layer 215: Covering layer 215a: Covering layer 215b: Covering layer 220: Spacer layer 220a: Spacer layer 220b: Spacer layer 225: Gate dielectric layer 300: Example Implementation 305: Source / Drain Depression 310: Countertop area 315: Nanostructured Channel 400: Example Implementation 405: Space 410: Dielectric layer 415: Sacrificial Dielectric Layer 415a: Lining 415b: Core 420: Cavity 500: Example Implementation 505: Internal spacers 600: Example Implementation 605: Epitaxial region 605a: Epitaxial region 605b: Epitaxial region 610: Source / Drain Region 610a: p-type source / drain region 610b: n-type source / drain region 615: Overlapping area 700: Example Implementation 705: Dielectric layer 710: Covering layer 800: Example Implementation 805: Space 810: Gate dielectric layer 815: Gate Structure 815a: P-type gate structure 815b: n-type gate structure 900: Example Implementation 1000: Example Implementation 1100: Example Implementation 1105: Isolation spacers 1200: Example Implementation 1300: Example Implementation 1400: Example Implementation 1500: Example Implementation 1505: PMOS nanostructure transistor 1510: NMOS nanostructure transistor 1600: Example Implementation 1605: Sidewall 1610: Section 1615: Section 1700: Process 1710: Square 1720: Square 1730: Square 1740: Square 1750: Square 1800: Process 1810: Square 1820: Square 1830: Square 1840: Square 1860: Square 1900: Example Implementation 2000: Example Implementation AA: Cross-section BB: Cross-section CC: Cross section D1: Dimensions D2: Dimensions x: direction y: direction z: Direction

[0199] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: A plurality of semiconductor channel layers and a plurality of sacrificial semiconductor layers are formed such that the semiconductor channel layers and the sacrificial semiconductor layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; a first etching operation is performed to etch the semiconductor channel layers and the sacrificial semiconductor layers to form a source / drain recess, wherein the source / drain recess defines a plurality of nanostructure channels arranged in the direction approximately perpendicular to the semiconductor substrate, wherein the nanostructure channels and the sacrificial semiconductor layers are arranged alternately in the direction approximately perpendicular to the semiconductor substrate; a second etching operation is performed to remove the sacrificial semiconductor layers from the semiconductor device; a plurality of sacrificial dielectric layers are formed in a plurality of spaces between the nanostructure channels, which were previously occupied by the sacrificial semiconductor layers, wherein the Young's modulus of the dielectric material of the sacrificial dielectric layers is [missing information]. The modulus is less than the Young's modulus of the semiconductor material of the sacrificial semiconductor layers; and a source / drain region is formed in the source / drain recess.

2. The method as described in claim 1, wherein forming the sacrificial dielectric layers comprises: A dielectric layer is formed on the plurality of sidewalls of the source / drain recesses and in the spaces between the nanostructure channels, which were previously occupied by the sacrificial semiconductor layers; and a third etching operation is performed to trim the dielectric layer such that a plurality of portions of the dielectric layer remain in the spaces between the nanostructure channels as the sacrificial dielectric layers, which were previously occupied by the sacrificial semiconductor layers.

3. The method as described in claim 1, wherein the sacrificial dielectric layers comprise a porous silicon oxide material.

4. The method as described in claim 1, wherein the Young's modulus of the dielectric material of the sacrificial dielectric layers is smaller than the Young's modulus of the semiconductor material of the nanostructure channels.

5. The method as described in claim 1, wherein forming the sacrificial dielectric layers comprises: A substrate for depositing the sacrificial dielectric layers by atomic layer deposition (ALD); and a porous silicon oxide core for depositing the sacrificial dielectric layers as a flowable membrane.

6. A semiconductor device, comprising: A plurality of nanostructured channels are arranged in one direction, which is approximately perpendicular to a semiconductor substrate of the semiconductor device; A gate structure surrounding the nanostructure channels; a source / drain region adjacent to one side of the gate structure and adjacent to a plurality of endpoints of the nanostructure channels; a plurality of internal spacers between the source / drain region and the gate structure; and a plurality of non-contiguous epitaxial regions between the source / drain region and at least one of the following: the nanostructure channels, or the internal spacers, wherein one epitaxial region of the non-contiguous epitaxial regions continuously spans: an internal spacer, a portion of an endpoint of a first nanostructure channel among the nanostructure channels, the portion of the endpoint of the first nanostructure channel being perpendicularly adjacent to the internal spacer, and a portion of an endpoint of a second nanostructure channel among the nanostructure channels, the portion of the endpoint of the second nanostructure channel being perpendicularly adjacent to the internal spacer.

7. The semiconductor device as claimed in claim 6, wherein the bottom surface of the source / drain region and a plurality of bottom surfaces of a subset of the internal spacers located at the bottom of the source / drain region are approximately coplanar.

8. A semiconductor device, comprising: A plurality of nanostructured channels are arranged in one direction, which is approximately perpendicular to a semiconductor substrate of the semiconductor device; A gate structure surrounding the nanostructure channels; a source / drain region adjacent to one side of the gate structure and adjacent to a plurality of endpoints of the nanostructure channels; a plurality of internal spacers between the source / drain region and the gate structure; and a plurality of non-contiguous epitaxial regions between the source / drain region and at least one of the following: the nanostructure channels, or the internal spacers, wherein one epitaxial region of the non-contiguous epitaxial regions continuously spans: an endpoint of a first nanostructure channel, a portion of a first internal spacer perpendicularly adjacent to the nanostructure channel, and a portion of a second internal spacer perpendicularly adjacent to the nanostructure channel.

9. A method of forming a semiconductor device, comprising: A plurality of semiconductor channel layers and a plurality of sacrificial semiconductor layers are formed such that the semiconductor channel layers and the sacrificial semiconductor layers are arranged alternately in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; a source / drain recess is formed through the semiconductor channel layers and the sacrificial semiconductor layers; the sacrificial semiconductor layers are removed from the semiconductor device through the source / drain recess; a plurality of sacrificial dielectric layers are formed in a plurality of spaces between the semiconductor channel layers, the spaces previously occupied by the sacrificial semiconductor layers, wherein the Young's modulus of the dielectric material of the sacrificial dielectric layers is less than the Young's modulus of the semiconductor material of the sacrificial semiconductor layers; a plurality of internal spacers are formed at a plurality of endpoints of the sacrificial dielectric layers exposed through the source / drain recess; a plurality of discontinuous epitaxial regions are formed on a plurality of sidewalls of the source / drain recess; and a source / drain region is formed on the discontinuous epitaxial regions in the source / drain recess.

10. The method as described in claim 9, further comprising: A bottom isolation spacer is formed at the bottom of the source / drain recess, wherein forming the source / drain region includes: forming the source / drain region on the bottom isolation spacer in the source / drain recess.

Images