Semiconductor device and manufacture method thereof

Abstract

A semiconductor device and a method for forming the same are provided. An exemplary method includes: forming a plurality of nanostructures over a substrate; forming a first source / drain feature coupled to a bottommost nanostructure among the nanostructures; forming a second source / drain feature coupled to a topmost nanostructure among the nanostructures; forming a first gate structure surrounding the bottommost nanostructure; and forming a second gate structure surrounding the topmost nanostructure, wherein the second gate structure includes an aluminum-containing n-type work function layer, and the first gate structure includes a first p-type work function layer, a second p-type work function layer, and a diffusion barrier layer disposed between the first p-type work function layer and the second p-type work function layer, wherein the aluminum concentration of the first p-type work function layer is less than the aluminum concentration of the second p-type work function layer.

Description

Technical Field

[0001] none Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with circuits that are smaller and more complex than the previous generation. In IC development, functional density (i.e., the number of interconnects per die area) typically increases, while geometry (i.e., the smallest components or lines that can be produced using manufacturing processes) decreases. This scaling down process usually yields benefits through increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of processing and manufacturing ICs. For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing the short-channel effect (SCE). Multi-gate devices generally refer to devices with a gate structure or a portion thereof located on more than one side of the channel region. Fin-like field-effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices and have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a raised channel surrounded by a gate on more than one side (e.g., the gate surrounds the top and sidewalls of a semiconductor material "fin" extending from the substrate). GAA transistors have a gate structure that may partially or completely surround the channel region to provide access to two or more sides of the channel region. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also provides alternative names for GAA transistors, such as nanosheet transistors or nanowire transistors.

[0004] As the semiconductor industry further advances to technology nodes below 10 nanometers (nm) in pursuit of higher device density, higher performance, and lower costs, the challenges posed by manufacturing and design issues have led to the emergence of stacked device structure configurations, such as complementary field-effect transistors (CFETs). In these CFETs, n-type multi-gate transistors and p-type multi-gate transistors are vertically stacked, with one transistor on top of the other. While existing CFET structures are generally sufficient, they are not satisfactory in all configurations. Summary of the Invention

[0005] none Simple Explanation of the Diagram

[0006] The contents of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 illustrates a perspective view of one or more types of semiconductor devices including a complementary field-effect transistor (C-FET) according to this disclosure. Figure 2 illustrates a flowchart of a method for forming a semiconductor device including a vertical C-FET, according to one or more of the present disclosure. Figures 3, 4, 5, 6, 7, 8, 9 and 12 illustrate cross-sectional views of semiconductor devices during various manufacturing stages in the method of Figure 2, according to various forms of this disclosure. Figure 10 illustrates the amplification portion of the semiconductor device shown in Figure 9, according to one or more versions of this disclosure. Figures 11A, 11B, and 11C illustrate fragment cross-sectional views of alternative configurations of the semiconductor device shown in Figure 10, according to one or more of the states disclosed herein. Implementation

[0007] The following disclosure provides different embodiments or instances for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not directly contact each other.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0009] Furthermore, when using terms such as "about" or "approximately" to describe a number or range of numbers, the terminology is intended to encompass a reasonable range of numbers that take into account variations inherent in manufacturing, as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with features having a number-related characteristic in manufacturing, a number or range of numbers encompasses a reasonable range including said number, such as within + / - 10% of said number. For instance, a material layer with a thickness of "about 5 nanometers" can encompass a size range from 4.25 nanometers to 5.75 nanometers, where the manufacturing tolerances associated with the deposited material layer are known by one of ordinary skill in the art to be + / - 15%.

[0010] A stacked multi-gate device refers to a semiconductor device, which includes a bottom multi-gate device and a top multi-gate device stacked on top of the bottom multi-gate device. When the bottom and top multi-gate devices have different conductivity types, the stacked multi-gate device can be a complementary field-effect transistor (C-FET). The multi-gate device in a C-FET can be a FinFET or a GAA transistor. The gate electrode of the functional gate structure can include one or more work function layers with appropriate work functions, thereby enhancing the device performance of the corresponding transistor. In some cases, the gate electrode of the bottom multi-gate device includes a p-type work function layer, while the gate electrode of the top multi-gate device includes an n-type work function layer. When the n-type work function layer is formed above the p-type work function layer, elements of the n-type work function layer (e.g., aluminum) may diffuse into the p-type work function layer below it, thereby adversely affecting the work function position of the p-type work function layer and thus affecting the threshold voltage of the bottom multi-gate device. Therefore, it is desirable to find a method that can reduce aluminum diffusion without adversely affecting other states of C-FET.

[0011] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. For this purpose, Figure 1 illustrates a perspective view of a semiconductor device including a vertical C-FET according to one or more aspects of this disclosure. Figure 2 illustrates a flowchart of a method 100 for forming a semiconductor device 200 including a vertical C-FET according to one or more aspects of this disclosure. Method 100 is described below with reference to Figures 3 through 12, which are partial cross-sectional views of the intermediate structure 200 at different manufacturing stages according to embodiments of method 100. Method 100 is merely an example and is not intended to limit this disclosure to what is explicitly described therein. Additional steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Since the intermediate structure 200 will be manufactured into the semiconductor device 200 after the manufacturing process is completed, the intermediate structure 200 may be referred to as the semiconductor device 200 as needed by the context. Furthermore, in this application and its various embodiments, unless otherwise stated, the same element symbols denote the same features having similar structures and compositions. For the avoidance of doubt, the X, Y, and Z directions in the figures are perpendicular to each other and are used consistently.

[0012] Figure 1 depicts an exemplary semiconductor device (e.g., a C-FET) 10. The semiconductor device 10 includes a lower device 10L (e.g., a p-type transistor) and an upper device 10U (e.g., an n-type transistor) located above the lower device 10L. The lower device 10L includes a channel layer 26'L surrounded by a bottom gate structure 72. The bottom gate structure 72 includes a gate dielectric layer 78 and a gate electrode 80L. The lower device 10L also includes a source / drain feature (e.g., a p-type epitaxial source / drain feature) 62L coupled to the channel layer 26'L and adjacent to the bottom gate structure 72.

[0013] The upper device 10U includes a channel layer 26'U surrounded by an upper gate structure 74. The upper gate structure 74 includes a gate dielectric layer 78 and a gate electrode 80U. The upper device 10U also includes a source / drain feature (e.g., an n-type epitaxial source / drain feature) 62U, coupled to the channel layer 26'U and adjacent to the upper gate structure 74. An isolation layer 90 is disposed between the upper device 10U and the lower device 10L to electrically insulate the upper gate structure 74 of the upper device 10U from the bottom gate structure 72 of the lower device 10L. The configuration of the components in the semiconductor device 10 described above is for illustrative purposes only and may be modified according to actual implementation. It should be understood that some features are omitted in this figure for simplicity.

[0014] Referring now to Figures 2, 3, and 4, method 100 includes block 102: receiving intermediate structure 200. Figure 3 depicts a cross-sectional view of intermediate structure 200, and Figure 4 depicts a cross-sectional view of intermediate structure 200 taken along line BB shown in Figure 3. Intermediate structure 200 includes substrate 202. In one embodiment, substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Although not explicitly shown in the figures, substrate 202 may include n-type well regions and p-type well regions for fabricating transistors of different conductivity types. When present, each of the n-type and p-type wells is formed in substrate 202 and includes a doping profile. The n-type well may include a doping profile of an n-type dopant (e.g., phosphorus (P) or arsenic (As)). The p-type well may include a doping profile of a p-type dopant (e.g., boron (B)). The doping in the n-type and p-type wells may be formed using ion implantation or thermal diffusion and may be considered part of substrate 202.

[0015] The intermediate structure 200 also includes a fin-shaped structure 210 protruding from the substrate 202. In these embodiments, the fin-shaped structure 210 is formed from a superlattice structure 204 and a portion of the substrate 202. The superlattice structure 204 can be deposited over the substrate 202 using an epitaxial process. Suitable epitaxial processes include vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The superlattice structure 204 includes a plurality of channel layers 208, which are interleaved with a plurality of sacrificial layers 206. The sacrificial layers 206 and the channel layers 208 are deposited alternately on each other to form the superlattice structure 204. The channel layers 208 and the sacrificial layers 206 may have different semiconductor compositions. In some implementations, the channel layer 208 is formed of silicon (Si), while the sacrificial layer 206 is formed of silicon-germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layer 206 allows for selective removal or recessing of the sacrificial layer 206 without causing substantial damage to the channel layer 208.

[0016] For ease of reference, the superlattice structure 204 can be vertically divided into a bottom portion 204B, an intermediate sacrificial layer 206M located on the bottom portion 204B, and a top portion 204T located on the intermediate sacrificial layer 206M. In the depicted example, the bottom portion 204B of the superlattice structure 204 includes channel layers 208L1, 208L2, and 208L3 interleaved with sacrificial layers 206L1, 206L2, and 206L3. The top portion 204T of the superlattice structure 204 includes channel layers 208U1, 208U2, and 208U3 interleaved with sacrificial layers 206U1 and 206U2. The channel layers 208L1, 208L2, 208L3, 208U1, 208U2, and 208U3 will provide a nanostructure for the C-FET. In some embodiments, channel layers 208U1 and 208U2 provide channel components for the top GAA transistor of the C-FET, while channel layers 208L2 and 208L3 provide channel components for the bottom GAA transistor in the C-FET. The term "channel component" is used herein to refer to any portion of material in a transistor having nanoscale dimensions and an elongated shape, regardless of the cross-sectional shape of that portion. The germanium content of the intermediate sacrificial layer 206M may differ from the germanium content of the other sacrificial layers (e.g., sacrificial layers 206U1, 206U2, and sacrificial layers 206L1-206L3) of the top portion 204T and the bottom portion 204B. In some embodiments, the germanium content of the intermediate sacrificial layer 206M is greater than the germanium content of the other sacrificial layers 206U1, 206U2, and 206L1-206L3, such that the entire intermediate sacrificial layer 206M can be selectively removed during the formation of the inner spacer recess.

[0017] It should be understood that the superlattice structure 204 in Figures 3 and 4 includes six (6) channel layers 208 interleaved with six (6) sacrificial layers 206, which is for illustrative purposes only and is not intended to limit the scope specifically described in the claims. It is understood that any number of channel layers 208 may be included in the superlattice structure 204 and distributed within the bottom portion 204B and the top portion 204T. The number of layers depends on the number of channel components required for the top GAA transistor and the bottom GAA transistor. In some embodiments, the number of channel layers 208 in the superlattice structure 204 may be between 4 and 10. The thickness of the channel layers 208 and the sacrificial layers 206 may be selected based on device performance considerations for the bottom GAA transistor, the top GAA transistor, and the overall C-FET.

[0018] After forming the superlattice structure 204, a portion of the superlattice structure 204 and the substrate 202 are then patterned to form fin structures 210. The patterned portion of the substrate 202 may be referred to as a protrusion 202t, a mesa 202t, or a base fin 202t. For patterning, a hard masking layer may be deposited over the superlattice structure 204. The hard masking layer may be a single layer or multiple layers. In one example, the hard masking layer includes a silicon oxide layer and a silicon nitride layer located above the silicon oxide layer. As shown in Figures 3 and 4, each fin structure 210 extends vertically from the substrate 202 along the Z direction and longitudinally along the X direction. The fin structures 210 may be patterned using appropriate processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrel can then be used as an etching mask to etch the superlattice structure 204 and the substrate 202 to form the fin structure 210.

[0019] The intermediate structure 200 also includes an isolation feature 212 (as shown in Figure 3) formed around the fin structure 210 to separate two adjacent fin structures 210. The isolation feature 212 may also be referred to as a shallow trench isolation (STI) feature 212. In an exemplary process, dielectric material for the isolation feature 212 is deposited over the intermediate structure 200 (including the fin structure 210) using CVD, subatmospheric CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized and recessed to form the isolation feature 212. As shown in Figure 3, the fin structure 210 is higher than the isolation feature 212. The dielectric material of the isolation feature 212 may include silicon oxide, silicon oxynitride, fluorosilicate glass (FSG), low-k dielectric materials and combinations thereof, and / or other suitable materials.

[0020] Referring to Figures 2 and 5, method 100 includes block 104: forming a dummy gate stack 214 over the channel region 210C of the fin structure 210. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 214 serves as a placeholder for the functional gate structure. Other processes and configurations are also possible. To form the dummy gate stack 214, a dummy dielectric layer 216, a dummy gate electrode layer 218, and a gate top hard mask layer 220 are deposited over the intermediate structure 200. The deposition of these layers may include using chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electron beam evaporation, other suitable deposition techniques, and / or combinations thereof. The dummy dielectric layer 216 may include silicon oxide, the dummy gate electrode layer 218 may include polysilicon, and the gate-top hard mask layer 220 may be a multilayer structure including silicon oxide and silicon nitride. The gate-top hard mask layer 220 is patterned using lithography and etching processes. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The etching process may include dry etching, wet etching, and / or other etching methods. Similar to the fin structure 210, the dummy gate stack 214 may also be patterned using dual patterning or multiple patterning techniques. Subsequently, using the patterned gate-top hard mask 220 as an etching mask, the dummy dielectric layer 216 and the dummy gate electrode layer 218 are etched to form the dummy gate stack 214. The dummy gate stack 214 extends longitudinally along the Y direction to surround the fin structure 210 and rests on the isolation feature 212. The portion of the fin structure 210 located below the dummy gate stack 214 defines a channel region 210C. The channel region 210C and the dummy gate stack 214 also define a source / drain region 210SD that does not vertically overlap with the dummy gate stack 214. The channel region 210C is disposed along the Y direction between the two source / drain regions 210SD. The source / drain region may refer to a source region used to form a source and / or a drain region used to form a drain, and may refer to them individually or jointly depending on the context.

[0021] Referring again to Figures 2 and 5, method 100 includes block 106: a source / drain region 210SD recess of fin structure 210 to form a source / drain groove 224. Operation at block 106 may include forming at least one gate spacer 222 above the sidewalls of the dummy gate stack 214 prior to the source / drain region 210SD recess. In some embodiments, the formation of at least one gate spacer 222 includes depositing one or more dielectric layers over intermediate structure 200. In exemplary processes, one or more dielectric layers are conformally deposited using CVD, SACVD, or ALD. The one or more dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or combinations thereof. After forming the gate spacer 222, an anisotropic etching process is performed on the intermediate structure 200 to form the source / drain groove 224. The etching process at block 106 can be a dry etching process or other suitable etching processes. An exemplary dry etching process may employ oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, NF3, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. As shown in Figure 5, the sidewalls of the sacrificial layer 206 and the channel layer 208 in the channel region 210C are exposed in the source / drain groove 224.

[0022] Referring to Figures 2 and 6, method 100 includes block 108: forming inner spacer features 226. At block 108, the sacrificial layer 206 exposed in the source / drain trench 224 is selectively and partially recessed to form the inner spacer trench, while the exposed channel layer 208 is substantially unetched. The intermediate sacrificial layer 206M, due to its high germanium content, can be substantially removed during the formation of the inner spacer trench. In some embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing of the sacrificial layer 206 is controlled by the duration of the etching process. Selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Selective wet etching processes may include the use of hydrogen fluoride (HF) or ammonium hydroxide (NH4OH).

[0023] After forming the inner spacer recess, an inner spacer material layer is deposited above the intermediate structure 200 (including within the inner spacer recess). Alternatively, as shown in Figure 6, the inner spacer material layer can also be deposited in the space left after selectively removing the intermediate sacrificial layer 206M. The inner spacer material layer may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess portions of the inner spacer material layer above the sidewalls of the dummy gate stack 214, gate spacer 222, and channel layer 208, thereby forming the inner spacer feature 226 and the intermediate dielectric layer 226M as shown in Figure 6. In these embodiments, the inner spacer feature 226 includes inner spacer features 226a and 226b disposed above the intermediate dielectric layer 226M and inner spacer features 226c, 226d, and 226e disposed below the intermediate dielectric layer 226M. Each inner spacer feature 226a-226e and the intermediate dielectric layer 226M are disposed between two vertically adjacent channel layers 208. In some embodiments, the etch-back process at block 108 may be a dry etching process, which includes the use of oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas (e.g., CF3I), other suitable gases and / or plasma and / or combinations thereof.

[0024] Referring again to Figures 2 and 6, method 100 includes block 110: forming a bottom source / drain feature 230 in a source / drain recess 224. In some embodiments, prior to depositing the bottom source / drain feature 230, a barrier layer (not shown) may be deposited over the intermediate structure 200 to cover the sidewalls of the top portion 204T of the superlattice structure 204. The barrier layer may also cover the sidewalls of the intermediate dielectric layer 226M and the channel layer 208L1. The barrier layer may include a dielectric material. After forming the barrier layer, the bottom source / drain feature 230 may be formed using epitaxial processes (such as VPE, UHV-CVD, MBE, and / or other suitable processes). The epitaxial growth process may use gaseous and / or liquid precursors that interact with the composition of the substrate 202 and the channel layer 208 not covered by the barrier layer. In these embodiments, the epitaxial growth of the bottom source / drain feature 230 can be performed from the top surface of the substrate 202 and the exposed sidewalls of the bottom channel layers 208L2 and 208L3. A barrier layer, due to its dielectric composition, blocks the formation of the bottom source / drain feature 230 on the sidewalls of the channel layers 208U1-208U3 and 208L1. As shown in Figure 6, the bottom source / drain feature 230 is in solid contact (or adjacent) to the channel layers 208L2 and 208L3. Depending on the design, the bottom source / drain feature 230 can be n-type or p-type. In the depicted embodiments, the bottom source / drain feature 230 is a p-type source / drain feature and may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials. It can be in-situ doped during the epitaxial process by introducing a p-type dopant (such as boron or gallium) or ex-situ doped using a junction implantation process.

[0025] Referring again to Figures 2 and 6, method 100 includes block 112: forming a bottom contact etch stop layer (CESL) 232 and a bottom interlayer dielectric (ILD) layer 234 above the bottom source / drain feature 230. The bottom CESL 232 may include silicon nitride, silicon oxynitride, and / or other materials, and may be formed by CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In an embodiment, the bottom CESL 232 includes silicon nitride, and the ratio of nitrogen concentration to silicon concentration (i.e., N / Si) of the bottom CESL 232 is in the range of about 1.1 to about 1.3. In some embodiments, a bottom CESL 232 is first conformally deposited on the intermediate structure 200, and then a bottom ILD layer 234 is deposited on top of the bottom CESL 232 by spin coating, flowable CVD (FCVD), CVD, or other suitable deposition techniques. The bottom ILD layer 234 may comprise materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silica, such as borophosphosilicate glass (BPSG), fluorosilicone glass (FSG), silicon phosphate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. The bottom CESL 232 and the bottom ILD layer 234 may be etched back to the exposed sidewalls of the channel layers 208U1 and 208U2. In the embodiment shown in Figure 6, after etchback, the bottom CESL 232 is in direct contact with the inner spacer features 226b, 226c, channel layers 208U3, 208L1, and intermediate dielectric layer 226M. The barrier layer can be removed during etchback of the bottom CESL 232 and the bottom ILD layer 234.

[0026] Referring to Figures 2 and 7, method 100 includes block 114: a top source / drain feature 248 is formed above the bottom CESL 232 and the bottom ILD layer 234. The top source / drain feature 248 can be formed using epitaxial processes such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can use gaseous and / or liquid precursors that interact with the composition of the channel layers (e.g., channel layers 208U1 and 208U2) of the top portion 204T of the superlattice structure 204. Epitaxial growth of the top source / drain feature 248 can be performed from the exposed sidewalls of the top channel layers 208U1 and 208U2. The deposited top source / drain feature 248 is in solid contact (or adjacent) to the channel layers of the top portion 204T of the superlattice structure 204. According to the design, the top source / drain feature 248 can be n-type or p-type. In the depicted embodiment, the top source / drain feature 248 is an n-type source / drain feature and may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials. It can be in-situ doped during the epitaxial process by introducing an n-type dopant (such as phosphorus, arsenic, or antimony) or ex-situ doped using a junction implantation process.

[0027] Referring again to Figures 2 and 7, method 100 includes block 116: a top CESL 250 and a top ILD layer 252 are deposited over the top source / drain feature 248. The top CESL 250 may include silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed by CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes and / or other suitable deposition or oxidation processes. In some embodiments, the top CESL 250 is first conformally deposited on the intermediate structure 200, and then the top ILD layer 252 is deposited over the top CESL 250 by spin coating, FCVD, CVD, or other suitable deposition techniques. The top ILD layer 252 may include materials such as tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped silica (such as borosilicate glass (BPSG), fluorosilicone glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials). In some embodiments, after forming the top ILD layer 252, the intermediate structure 200 may be annealed to improve the integrity of the top ILD layer 252. To remove excess material and expose the top surface of the dummy gate electrode layer 218, a planarization process, such as chemical mechanical polishing (CMP), may be performed.

[0028] Referring to Figures 2 and 8, method 100 includes block 118: selectively removing the dummy gate stack 214 and the sacrificial layer 206. Operations at block 118 may include removing the dummy gate stack 214, releasing the channel layer 208 as channel components (including top channel components 2080U1, 2080U2 and bottom channel components 2080L1 and 2080L2) and nanostructures (including nanostructures 2080N1 and 2080N2). Removal of the dummy gate stack 214 may include one or more etching processes selectively applied to the material in the dummy gate stack 214. For example, removal of the dummy gate stack 214 may be performed using selective wet etching, selective dry etching, or a combination thereof. After removal of the dummy gate stack 214, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 210C are exposed. Subsequently, the sacrificial layer 206 in the channel region 210C is selectively removed to release the channel layer 208 as channel components (including top channel components 2080U1, 2080U2, bottom channel components 2080L1 and 2080L2) and nanostructures (including nanostructures 2080N1 and 2080N2). The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes ammonia-peroxide mixture (APM) etching (e.g., an ammonia-peroxide-water mixture). In some other embodiments, selective removal includes SiGe oxidation followed by removal of silicon-germanium oxide. For example, oxidation can be provided by ozone cleaning, followed by removal of the silicon-germanium oxide by an etchant (such as NH4OH). In the embodiment shown in Figure 8, the top channel components 2080U1 and 2080U2 are in direct contact with the top source / drain feature 248; the bottom channel components 2080L1 and 2080L2 are in direct contact with the bottom source / drain feature 230; and the nanostructures 2080N1, 2080N2 and the intermediate dielectric layer 226M are in direct contact with the bottom CESL 232.

[0029] Referring to Figures 2 and 8 through 10, method 100 includes block 120: a bottom gate structure 254B is formed near the bottom source / drain feature 230, and a top gate structure 254T is formed near the top source / drain feature 248. The bottom gate structure 254B and the top gate structure 254T may be referred to individually or collectively as gate structure 254. Figure 9 depicts a cross-sectional view of the intermediate structure 200 taken along line AA shown in Figure 8. Figure 10 depicts an enlarged portion of the gate structure 254 shown in Figure 9.

[0030] After selectively removing the sacrificial layer 206, a bottom gate structure 254B is formed to surround each of the bottom channel members 2080L1 and 2080L2, thereby forming a bottom multi-gate transistor (e.g., the lower device 10L in Figure 1), and a top gate structure 254T is formed to surround each of the top channel members 2080U1 and 2080U2, thereby forming a top multi-gate transistor (e.g., 10U in Figure 1) located above the bottom multi-gate transistor. In the depicted embodiment, both the bottom multi-gate transistor and the top multi-gate transistor are GAA transistors. In the cross-sectional view shown in Figure 8, the bottom gate structure 254B and the top gate structure 254T are physically isolated from each other by an intermediate dielectric layer 226M, and in the cross-sectional view shown in Figure 9, the top gate structure 254T is formed above the bottom gate structure 254B.

[0031] The formation of the bottom gate structure 254B and the top gate structure 254T includes forming a bottom gate dielectric layer 254a surrounding the channel members 2080L1 and 2080L2 and a top gate dielectric layer 254b surrounding the channel members 2080U1 and 2080U2. In an embodiment, the bottom gate dielectric layer 254a and the top gate dielectric layer 254b are formed simultaneously and have the same composition. For example, each of the bottom gate dielectric layer 254a and the top gate dielectric layer 254b includes an interface layer (not separately labeled) and a high-k dielectric layer (not separately labeled) located above the interface layer. The interface layer may be formed above the channel members 2080U1, 2080U2, 2080L1, 2080L2 and the nanostructures 2080N1, 2080N2, and covers the top surface and sidewalls of the protrusion 202t. The interface layer can be formed by thermal oxidation, chemical oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), other suitable processes, or combinations thereof. In embodiments where the interface layer is formed by thermal oxidation, the interface layer is formed on a semiconductor surface (e.g., channel members 2080U1, 2080U2, 2080L1, 2080L2 and nanostructures 2080N1, 2080N2), but not on a dielectric surface (e.g., isolation feature 212). In some other embodiments, the interface layer can be conformally deposited over substrate 202, including deposition on isolation feature 212. The interface layer includes dielectric materials such as SiO2, SiGeOx, HfSiO, SiON, other dielectric materials, or combinations thereof. In some embodiments, the interface layer is a group IV-based oxide layer, generally referring to an oxide of a group IV-based material (i.e., a material including at least one group IV element, such as Si, Ge, C, etc.). In some embodiments, the interface layer is a group III-V based oxide layer, typically referring to oxides of group III-V materials (i.e., materials comprising at least one group III element, such as Al, Ga, In, B, etc., and at least one group V element, such as N, P, As, Sb, etc.). The high-k dielectric layer may include a dielectric material having a high dielectric constant, for example, greater than that of silicon oxide. Exemplary high-k dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, other suitable components, or combinations thereof. In some embodiments, the high-k dielectric layer may include high-k dielectric materials such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, TiO2, Ta2O5, other suitable high-k dielectric materials, or combinations thereof.

[0032] The formation of the bottom gate structure 254B and the top gate structure 254T also includes forming a bottom gate electrode 254c for the bottom gate structure 254B and a top gate electrode 254d for the top gate structure 254T. Each of the bottom gate electrode 254c and the top gate electrode 254d may include one or more work function layers with appropriate work functions, thereby enhancing the device performance of the respective transistor (e.g., reducing the threshold voltage). In an embodiment where the bottom multi-gate transistor is a p-type transistor and the top multi-gate transistor is an n-type transistor, the bottom gate electrode 254c includes a p-type work function structure 254WFP, and the top gate electrode 254d includes an n-type work function structure 254WFN.

[0033] In some prior art, the n-type work function layer of the n-type work function structure 254WFN is formed above the p-type work function layer. Some elements (e.g., aluminum) may diffuse from the n-type work function layer to the p-type work function layer, thereby affecting the work function position of the p-type work function layer and consequently affecting the threshold voltage of the bottom multi-gate transistor. In this embodiment, in addition to the p-type work function layer, the p-type work function structure 254WFP also includes at least one diffusion barrier layer (e.g., diffusion barrier layer 254m) to reduce cross-diffusion. In an exemplary process, after forming the gate dielectric layers 254a and 254b, the p-type work function structure 254WFP is formed above the gate dielectric layers 254a and 254b, and then etched back to expose the gate dielectric layer 254b. Then, the n-type work function structure 254WFN is formed above the p-type work function structure 254WFP and the gate dielectric layer 254b. Each of the bottom gate electrode 254c and the top gate electrode 254d may include a metal filler 254e located above the n-type work function structure 254WFN and the p-type work function structure 254WFP to reduce contact resistance. In some cases, the metal filler 254e includes tungsten (W). The gate structure 254 may also include a pad layer, a wetting layer, an adhesive layer, a metal alloy, or a metal silicate.

[0034] See Figures 9 and 10 for details of the p-type work function structure 254WFP and the n-type work function structure 254WFN, with Figure 10 depicting an amplified portion of the gate structure 254 shown in Figure 9. The n-type work function structure 254WFN may include single-layer or multi-layer structures, such as various combinations of metal layers and selected work functions to enhance device performance. For example, the n-type work function structure 254WFN may include an n-type work function material, typically referring to a conductive material tuned to have an n-type work function. In some embodiments, the n-type work function structure 254WFN may include titanium aluminum, titanium aluminum carbide, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. In the embodiments described herein, the n-type work function structure 254WFN is a single-layer structure and may include aluminum-containing materials, such as TiAl or TiAlC.

[0035] To ensure good adhesion between the p-type work function structure 254WFP and its surrounding layers (e.g., the high-k dielectric layer and the n-type work function structure 254WFN), the p-type work function structure 254WFP is formed from a titanium nitride (TiN)-based work function layer. However, titanium nitride has a columnar grain structure with both inter-pillar and intra-pillar voids, and aluminum in the n-type work function structure 254WFN can diffuse into the titanium nitride (TiN)-based work function layer through the grain boundaries, leading to a degraded performance of the titanium nitride (TiN)-based work function layer and causing unnecessary changes in the threshold voltage of the bottom metal gate transistor. To reduce aluminum diffusion, in the embodiments described herein, the p-type work function structure 254WFP includes: a first p-type work function layer 2541 located on the gate dielectric layer 254a; a second p-type work function layer 2542 located below the n-type work function structure 254WFN; and a diffusion barrier layer 254m disposed between the first p-type work function layer 2541 and the second p-type work function layer 2542. Each of the first p-type work function layer 2541 and the second p-type work function layer 2542 can be conformally deposited on the gate dielectric layer 254a by ALD, CVD, or other suitable processes. In the embodiments, to provide satisfactory film adhesion, the first p-type work function layer 2541 includes titanium nitride formed by ALD and is in direct contact with the high-k dielectric layer of the gate dielectric layer 254a, and the second p-type work function layer 2542 includes titanium nitride formed by ALD and is in direct contact with the n-type work function structure 254WFN. However, as mentioned above, the titanium nitride layer formed by ALD also has a columnar grain structure, containing both inter-column and intra-column voids. Without treatment, a large amount of aluminum in the n-type work function structure 254WFN may diffuse through the grain boundaries of titanium nitride (TiN) into the first p-type work function layer 2541 and the second p-type work function layer 2542. In this embodiment, a diffusion barrier layer 254m is formed between the first p-type work function layer 2541 and the second p-type work function layer 2542 via, for example, an ALD process. The diffusion barrier layer 254m can at least partially fill the inter-column and intra-column voids, thereby reducing or even disrupting the diffusion paths within the columnar titanium nitride (TiN) grains. That is, it reduces the amount of aluminum that may diffuse into the first p-type work function layer 2541. In other words, the aluminum concentration in the first p-type work function layer 2541 is less than the aluminum concentration in the second p-type work function layer 2542. Feature 2543a represents diffusion paths in the first p-type work function layer 2541 that are not completely filled by the diffusion barrier layer 254m, and feature 2543b represents diffusion paths in the first p-type work function layer that are completely filled by the diffusion barrier layer 254m.Feature 2543c represents diffusion paths in the second p-type work function layer 2542, which are not completely filled by aluminum in the n-type work function structure 254WFN, and feature 2543d represents diffusion paths in the second p-type work function layer 2542, which are completely filled by aluminum in the n-type work function structure 254WFN. In some embodiments, aluminum may diffuse into the diffusion barrier layer 254m and into the first p-type work function layer 2541. Due to the diffusion of aluminum, the diffusion barrier layer 254m may become an aluminum-containing titanium layer, and the first p-type work function layer 2541 and the second p-type work function layer 2542 may include aluminum-containing titanium nitride layers having the above-described aluminum concentration relationship.

[0036] In the embodiment shown in Figure 9, the lower portion of the n-type work function structure 254WFN is separated from the diffusion barrier layer 254m by the second p-type work function layer 2542, and the upper portion of the n-type work function structure 254WFN is formed on and in direct contact with the diffusion barrier layer 254m, the first p-type work function layer 2541, and the second p-type work function layer 2542. The interface between the n-type work function structure 254WFN and the diffusion barrier layer 254m is located below the top surface of the intermediate dielectric layer 226M and above the bottom surface of the intermediate dielectric layer 226M.

[0037] In the embodiment described herein, the deposition process for forming the first p-type work function layer 2541, the second p-type work function layer 2542, and the diffusion barrier layer 254m is performed in situ. For example, after forming the high-k dielectric layer, the intermediate structure 200 is placed into a processing chamber prepared for an ALD process to form the p-type work function structure 254WMP. During the ALD process, after the formation of the p-type work function structure 254WMP is completed, the intermediate structure 200 remains in the same processing chamber.

[0038] The first p-type work function layer 2541 has a thickness T1, the second p-type work function layer 2542 has a thickness T2, and the diffusion barrier layer 254m has a thickness Tm. To provide sufficient barrier without significantly affecting the work function positions of the first p-type work function layer 2541 and the second p-type work function layer 2542, the ratio of thickness Tm to the total thickness of the first p-type work function layer 2541 and the second p-type work function layer 2542 (i.e., T1+T2) is in the range of about 0.1 to about 0.2. If the ratio is less than 0.1, the diffusion barrier layer 254m may be too thin to reduce or block the diffusion path in the columnar titanium nitride (TiN) grains; if the ratio is greater than 0.2, the diffusion barrier layer 254m may consume too much inter-layer spacing (e.g., the spacing between channel members 2080L1 and 2080L2) to form the bottom gate electrode. To allow sufficient space for forming the n-type work function structure 254WFN, the total thickness of the first p-type work function layer 2541 and the second p-type work function layer 2542 may be reduced, which could adversely affect the threshold voltage of the bottom multi-gate transistor and the device performance. In one embodiment, thickness T1 is equal to thickness T2, and the ratio of aluminum concentration in the second p-type work function layer 2542 to that in the first p-type work function layer 2541 is greater than 1. In another embodiment, thickness T2 is less than thickness T1, so the first p-type work function layer 2541 may play a more significant role in the overall work function and threshold voltage of the p-type work function structure 254WMP. Most of the aluminum diffused from the n-type work function structure 254WFN will be trapped in the second p-type work function layer 2542 and the diffusion barrier layer 254m. Without changing the total thickness of the p-type work function structure 254WMP, the performance of the bottom multi-gate transistor can be further improved by increasing thickness T1 and decreasing thickness T2 (e.g., T2 / T1 < 1). For example, by reducing the impact of aluminum diffusion on the first p-type work function layer, the threshold voltage can be increased and the device performance enhanced. In another embodiment, the ratio of the aluminum concentration of the second p-type work function layer 2542 to the aluminum concentration of the first p-type work function layer 2541 can be greater than 1.5. In this embodiment, the total thickness (i.e., T1+T2) of the first p-type work function layer 2541 and the second p-type work function layer 2542 is between about 1 nanometer and about 3 nanometers, and the thickness of the diffusion barrier layer 254m can be between about 0.1 nanometers and about 0.3 nanometers.

[0039] In the embodiment described above with reference to Figure 10, the deposition process for forming the first p-type work function layer 2541, the diffusion barrier layer 254m, and the second p-type work function layer 2542 is performed in situ. In another embodiment shown in Figure 11A, the deposition process for forming the first p-type work function layer 2541, the diffusion barrier layer 254m, and the second p-type work function layer 2542 is performed out of situ. In the exemplary process, after forming the gate dielectric layers 254a and 254b, the intermediate structure 200 is loaded into a first processing chamber, wherein the first processing chamber is prepared to perform a first ALD process to form the first p-type work function layer 2541. After performing the first ALD process, the intermediate structure 200, now including the first p-type work function layer 2541, is transferred to a second processing chamber, wherein the second processing chamber is prepared to perform a second ALD process to form the diffusion barrier layer 254m. During the transfer process between the first and second processing chambers, the top surface of the first p-type work function layer 2541 may be partially oxidized to form a first oxide-containing layer 264a. The oxide-containing layer 264a may be an oxide-containing titanium nitride layer (e.g., TiON). After the second ALD process is completed, the intermediate structure 200 (now including the diffusion barrier layer 254m) is transferred to a third processing chamber, which is prepared for a third ALD process to form a second p-type work function layer 2542. During the transfer process between the second and third processing chambers, the top surface of the diffusion barrier layer 254m may be partially oxidized to form a second oxide-containing layer 264b. The second oxide-containing layer 264b may be an oxide-containing titanium layer (e.g., TiO). The formation of the first oxide-containing layer 264a and the second oxide-containing layer 264b increases the oxygen concentration in the p-type work function structure 254WFP. Introducing oxygen into the p-type work function structure 254WFP can further reduce aluminum diffusion from the aluminum-containing n-type work function layer of the n-type work function structure 254WFN to the first p-type work function layer 2541. In some cases, aluminum in the aluminum-containing n-type work function layer of the n-type work function structure 254WFN diffuses to the second p-type work function layer 2542, the second oxide-containing layer 264b, the diffusion barrier layer 254m, the first oxide-containing layer 264a, and the first p-type work function layer 2541, with the aluminum concentration in those layers decreasing sequentially from top to bottom. That is, the aluminum concentration in the first p-type work function layer 2541 is the lowest among those layers, while the aluminum concentration in the second p-type work function layer 2542 is the highest among those layers. In one embodiment, the aluminum concentration in the second oxide-containing layer 264b is higher than the aluminum concentration in the first oxide-containing layer 264a.

[0040] In the embodiment described above with reference to Figure 10, the p-type work function structure 254WFP includes a diffusion barrier layer 254m located between two p-type work function layers (e.g., 2541 and 2542). In another embodiment shown in Figure 11B, the p-type work function structure 254WFP may include a plurality of metal barrier layers (e.g., 254m1, 254m2, 254m3). The first p-type work function layer 2541 and the second p-type work function layer 2542 are alternately separated by those metal barrier layers 254m1 to 254m3. For example, the first p-type work function layer 2541 is divided into two parts 2541a and 2541b by the diffusion barrier layer 254m1, and the second p-type work function layer 2542 is divided into two parts 2542a and 2542b by the diffusion barrier layer 254m3, and parts 2541b and 2542a are separated by the diffusion barrier layer 254m2. It should be noted that the total thickness T of the p-type work function structure 254WFP remains constant. In the embodiment, the total thickness of different portions of the first p-type work function layer 2541 is T1, the total thickness of different portions of the second p-type work function layer 2542 is T2, and the total thickness of these metal barrier layers 254m1, 254m2, and 254m3 is Tm. Although Figure 11B illustrates three metal barrier layers (e.g., 254m1, 254m2, and 254m3), it is understood that the p-type work function structure 254WFP may include any suitable number of metal barrier layers.

[0041] In another embodiment, as described above with reference to Figure 11A, the deposition process for forming different layers in the p-type work function structure 254WFP can be performed in situ. This concept can also be applied to the formation of the p-type work function structure 254WFP described above with reference to Figure 11B. After the deposition process is completed, as shown in Figure 11C, each of the metal barrier layers 254m1, 254m2, and 254m3 is sandwiched between the top oxide layer and the bottom oxide layer. The bottom oxide layer can be similar to oxide layer 264a, except that its thickness is less than that of oxide layer 264a. The top oxide layer can be similar to oxide layer 264b, except that its thickness is less than that of oxide layer 264b. The aluminum concentration in each layer of the p-type work function structure 254WFP can gradually decrease from top to bottom.

[0042] In the above embodiments, the first p-type work function layer 2541 and the second p-type work function layer 2542 comprise titanium nitride (TiN). Besides titanium nitride (TiN), p-type work function materials also include tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), zirconium silicon (ZrSi2), molybdenum silicon (MoSi2), tantalum silicon (TaSi2), nickel silicon (NiSi2), or other p-type work function materials. The concepts of this disclosure also apply to other p-type work function materials having columnar grains. Furthermore, in some embodiments, the diffusion barrier layer 254m may comprise other materials capable of disrupting the columnar growth of the p-type work function layer to reduce aluminum diffusion. For example, the diffusion barrier layer 254m may comprise tungsten nitride, molybdenum nitride, or tantalum nitride.

[0043] Referring to Figures 2 and 12, method 100 includes block 122: performing further processes to complete the fabrication of semiconductor device 200. These further processes may include forming a dielectric capping layer 255 over a top gate structure 254T. These further processes may also include forming a silicon layer 256 over a top source / drain feature 248 and forming a multi-layer interconnect (MLI) structure 258 over an intermediate structure 200. MLI 258 may include various interconnect features, such as vias 258v and conductive lines 258m, disposed in dielectric layers 258d, such as etch-stop layers and ILD layers. In some embodiments, vias are vertical interconnect features used to interconnect device-level contacts, such as source / drain contacts 260 formed over the top source / drain feature 248. Other processes may be further performed.

[0044] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their fabrication. For example, this disclosure provides a C-FET device having a top multi-gate device and a bottom multi-gate device. An aluminum diffusion barrier layer is formed between the two p-type work function layers to reduce aluminum diffusion into the lower layers of the p-type work function layer, thereby reducing the threshold voltage variation of the bottom multi-gate device.

[0045] This disclosure provides many different embodiments. This document discloses semiconductor structures and methods for forming them. In one exemplary embodiment, this disclosure relates to a method. The method includes: forming a first semiconductor layer stack having a first upper semiconductor layer above a first lower semiconductor layer, and forming a second semiconductor layer stack having a second upper semiconductor layer above a second lower semiconductor layer; forming a high-k dielectric layer above the first upper semiconductor layer, the second upper semiconductor layer, the first lower semiconductor layer, and the second lower semiconductor layer; forming a p-type work function structure above the high-k dielectric layer, the first upper semiconductor layer, and the first lower semiconductor layer, wherein the p-type work function structure includes a first p-type work function layer, a metal layer on the first p-type work function layer, and a second p-type work function layer on the metal layer; and forming an n-type work function layer above the high-k dielectric layer, the second upper semiconductor layer, the second lower semiconductor layer, and the p-type work function structure.

[0046] In some embodiments, the first p-type work function layer and the second p-type work function layer may include titanium nitride. In some embodiments, the n-type work function layer may include an aluminum-containing material. In some embodiments, the aluminum concentration of the first p-type work function layer is less than the aluminum concentration of the second p-type work function layer, and the first p-type work function layer and the second p-type work function layer include titanium nitride. In some embodiments, the first p-type work function layer, the second p-type work function layer, and the metal layer may include the same metal element. In some embodiments, the metal layer may include titanium. In some embodiments, the ratio of the thickness of the metal layer to the total thickness of the first p-type work function layer and the second p-type work function layer is between about 0.1 and about 0.2. In some embodiments, the method may also include: forming a first source / drain feature coupled to a first upper semiconductor layer and a first lower semiconductor layer; forming a second source / drain feature coupled to a second upper semiconductor layer and a second lower semiconductor layer; and forming an isolation structure between the first source / drain feature and the second source / drain feature. In some embodiments, the p-type work function structure may include a first oxide layer disposed between the metal layer and the first p-type work function layer and a second oxide layer disposed between the metal layer and the second p-type work function layer.

[0047] In another exemplary embodiment, this disclosure relates to a method. The method includes: forming a plurality of nanostructures over a substrate; forming a first source / drain feature coupled to the bottommost nanostructure of the nanostructures; forming a second source / drain feature coupled to the topmost nanostructure of the nanostructures; forming a first gate structure surrounding the bottommost nanostructure; and forming a second gate structure surrounding the topmost nanostructure, wherein the second gate structure includes an aluminum-containing n-type work function layer, the first gate structure includes a first p-type work function layer, a second p-type work function layer, and a diffusion barrier layer disposed between the first p-type work function layer and the second p-type work function layer, wherein the aluminum concentration of the first p-type work function layer is less than the aluminum concentration of the second p-type work function layer.

[0048] In some embodiments, the first p-type work function layer and the second p-type work function layer may include titanium nitride. In some embodiments, the diffusion barrier layer may include a titanium layer. In some embodiments, the thickness of the diffusion barrier layer is between about 0.1 nanometers and about 0.3 nanometers. In some embodiments, the total thickness of the first p-type work function layer and the second p-type work function layer is between about 1 nanometer and about 3 nanometers. In some embodiments, the thickness of the second p-type work function layer is less than the thickness of the first p-type work function layer. In some embodiments, the step of forming the first gate structure includes performing an in-situ deposition process to form the first p-type work function layer, the second p-type work function layer, and the diffusion barrier layer.

[0049] In another exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate; a lower source / drain feature disposed above the substrate; a plurality of first nanostructures coupled to the lower source / drain feature; a first gate structure surrounding each of the first nanostructures; an upper source / drain feature located above the lower source / drain feature; a plurality of second nanostructures coupled to the upper source / drain feature; and a second gate structure surrounding each of the second nanostructures, wherein the first gate structure includes a gate dielectric layer, a first p-type work function layer located above the gate dielectric layer, a metal layer located above the first p-type work function layer, and a second p-type work function layer located above the metal layer.

[0050] In some embodiments, the second gate structure may include an n-type work function layer, and in a cross-section extending through the first and second nanostructures but not through the lower and upper source / drain features, a portion of the n-type work function layer is located on a metal layer. In some embodiments, in another cross-section extending through the first and second nanostructures and the lower and upper source / drain features, the first and second gate structures are perpendicularly spaced from each other by a dielectric layer. In some embodiments, the thickness of the second p-type work function layer is less than the thickness of the first p-type work function layer.

[0051] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

[0052] 10: Semiconductor devices 10L: Lower device 10U: Upper device 26'L: Channel layer 26'U: Channel layer 62L: Source / Drain Characteristics / p-type epitaxial source / drain characteristics 62U: Source / Drain Characteristics / n-type Epitaxial Source / Drain Characteristics 72: Bottom gate structure 74: Upper gate structure 78: Gate dielectric layer 80L, 80U: Gate electrode 90: Isolation layer 100: Method Blocks 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, and 122: 200: Intermediate Structure / Semiconductor Device 202:Substrate 202t: Protrusion / Platform / Base Fin 204: Superlattice structure 204B: Bottom part 204T: Top section 206, 206L1~206L3, 206U1~206U3: Sacrificial Layer 206M: Intermediate Sacrificial Layer 208, 208L1~208L3, 208U1~208U3: Channel Layer 210: Fin-shaped structure 210C: Channel Area 210SD: Source / Drain Region 212: Isolation Features 214: Dummy gate stack 216: Dummy Dielectric Layer 218: Virtual gate electrode layer 220: Gate top hard mask layer / hard mask 222: Gate spacer 224: Source / Drain Groove 226, 226a~226e: Characteristics of internal spacers 226M: Intermediate Dielectric Layer 230: Bottom source / drain characteristics 232: Bottom Contact Etching Termination Layer / Bottom CESL 234: Bottom Interlayer Dielectric Layer / Bottom ILD Layer 248: Top source / drain characteristics 250: Top Contact Etching Termination Layer / Top CESL 252: Top ILD layer / Top interlayer dielectric layer 254: Gate structure 254a: Bottom gate dielectric layer / gate dielectric layer 254B: Bottom gate structure 254b: Top gate dielectric layer / Gate dielectric layer 254c: Bottom gate electrode 254d: Top gate electrode 254e: Metal filler 254m: Diffusion barrier layer 254m1~254m3: Metallic barrier layer / diffusion barrier layer 254T: Top gate structure 254WFN: n-type work function structure 254WFP: p-type work function structure 255: Dielectric capping layer 256: Silicon layer 258m: Conductive wire 258V: Through-hole 260: Source / Drain Contact 264a: Oxide-containing / First oxide-containing layer 264b: Oxide-containing / Second oxide-containing layer 2080L1, 2080L2: Bottom channel component / surrounding channel component 2080N1, 2080N2: Nanostructure 2080U1, 2080U2: Top channel component / surround channel component 2541: First p-type work function layer 2541a, 2541b, 2542a, 2542b: Partial 2542: Second p-type work function layer 2543a~2543d: Characteristics AA, BB: lines T: Total thickness T1, T2, Tm: Thickness X, Y, Z: Direction IL+HK: High-K dielectric layer

[0053] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, comprising: forming a first semiconductor layer stack having a first upper semiconductor layer above a first lower semiconductor layer, and forming a second semiconductor layer stack having a second upper semiconductor layer above a second lower semiconductor layer; forming a high-k dielectric layer above the first upper semiconductor layer, the second upper semiconductor layer, the first lower semiconductor layer, and the second lower semiconductor layer; forming a p-type work function structure above the high-k dielectric layer, the first upper semiconductor layer, and the first lower semiconductor layer, wherein the p-type work function structure includes a first p-type work function layer, a metal layer on the first p-type work function layer, and a second p-type work function layer on the metal layer; and forming an n-type work function layer above the high-k dielectric layer, the second upper semiconductor layer, the second lower semiconductor layer, and the p-type work function structure.

2. The method as described in claim 1, wherein the aluminum concentration of the first p-type work function layer is less than the aluminum concentration of the second p-type work function layer, and the first p-type work function layer and the second p-type work function layer comprise titanium nitride.

3. The method of claim 1, wherein the ratio of a thickness of the metal layer to a total thickness of the first p-type work function layer and the second p-type work function layer is between about 0.1 and about 0.

2.

4. The method of claim 1, further comprising: forming a first source / drain feature coupled to the first upper semiconductor layer and the first lower semiconductor layer; forming a second source / drain feature coupled to the second upper semiconductor layer and the second lower semiconductor layer; and forming an isolation structure between the first source / drain feature and the second source / drain feature.

5. The method as described in claim 1, wherein the p-type work function structure further comprises: a first oxide layer disposed between the metal layer and the first p-type work function layer; and a second oxide layer disposed between the metal layer and the second p-type work function layer.

6. A method of forming a semiconductor device, comprising: forming a plurality of nanostructures on a substrate; forming a first source / drain feature coupled to a bottommost nanostructure of the nanostructures; forming a second source / drain feature coupled to a topmost nanostructure of the nanostructures; forming a first gate structure surrounding the bottommost nanostructure; and forming a second gate structure surrounding the topmost nanostructure, wherein the second gate structure includes an aluminum-containing n-type work function layer, the first gate structure includes a first p-type work function layer, a second p-type work function layer, and a diffusion barrier layer disposed between the first p-type work function layer and the second p-type work function layer, wherein the aluminum concentration of the first p-type work function layer is less than the aluminum concentration of the second p-type work function layer.

7. The method of claim 6, wherein forming the first gate structure comprises: performing an in-situ deposition process to form the first p-type work function layer, the second p-type work function layer and the diffusion barrier layer.

8. A semiconductor device comprising: a substrate; a lower source / drain feature disposed above the substrate; a plurality of first nanostructures coupled to the lower source / drain feature; a first gate structure surrounding each of the first nanostructures; an upper source / drain feature located above the lower source / drain feature; a plurality of second nanostructures coupled to the upper source / drain feature; and a second gate structure surrounding each of the second nanostructures, wherein the first gate structure includes a gate dielectric layer, a first p-type work function layer located above the gate dielectric layer, a metal layer located above the first p-type work function layer, and a second p-type work function layer located above the metal layer.

9. The semiconductor device of claim 8, wherein the second gate structure includes an n-type work function layer, and in a cross-section extending through the first nanostructures and the second nanostructures but not through the lower source / drain feature and the upper source / drain feature, a portion of the n-type work function layer is located on the metal layer.

10. The semiconductor device of claim 9, wherein in another cross-section extending through the first nanostructures and the second nanostructures and the lower source / drain feature and the upper source / drain feature, the first gate structure and the second gate structure are perpendicularly separated from each other by a dielectric layer.

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