Manufacturing method of semiconductor device

Abstract

One embodiment of this disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. One method includes: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers in a first device region and a second device region; forming a sacrificial gate over the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of slots; and depositing an interposer material over the bottom surface and in the slots; performing an anisotropic etching on the interposer material positioned over the bottom surface in the first device region; and performing an isotropic etching on the interposer material in both the first and second device regions to remove the interposer material positioned over the bottom surface and to laterally recess the interposer material in the slots.

Description

Technical Field

[0001] none Prior Technology

[0002] The electronics industry has experienced a growing demand for increasingly smaller and faster electronic devices capable of simultaneously supporting a larger number of increasingly complex and sophisticated functions. Consequently, there is a persistent trend in the semiconductor industry to manufacture low-cost, high-efficiency, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down semiconductor IC dimensions (e.g., minimizing feature size), thereby improving production efficiency and reducing associated costs. However, such scaling has also introduced increased complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] One embodiment of this disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a flowchart illustrating a method according to some embodiments. Figures 2 through 6 are perspective views of the structure of a semiconductor device during a continuous manufacturing phase, according to some embodiments. Figure 7 is a cross-sectional view of the structure of the semiconductor device in Figure 6 according to some embodiments. Figure 8 is a cross-sectional view of the structure of a semiconductor device according to some embodiments during a continuous manufacturing stage. Figures 9 through 11 are perspective views of the structure of a semiconductor device according to some embodiments during the continuous manufacturing stage. Figures 12 through 17 are cross-sectional views of the structure of a semiconductor device according to some embodiments during the continuous manufacturing stage. Figures 18 and 19 are perspective views of the structure of a semiconductor device according to some embodiments at a selected manufacturing stage. Figure 20 is a cross-sectional view of the structure of a semiconductor device according to some embodiments at a selected manufacturing stage. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the subject matter. Specific examples of components and configurations are described below to simplify one implementation of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, "directly over" refers to the vertical alignment of features such that when the overlying feature is directly over the underlying feature, the vertical axis passes through both features. Furthermore, reference numerals and / or letters may be repeated in various instances of one implementation of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, spatial relative terms such as "directly above," "above," "overlapping," "upper," "top," "lower," "subordinate," "below," "below," "under," "bottom," "side," "positive slope," and "negative slope," and similar terms, may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] All figures in this description indicating quantities, ratios of materials, physical properties of materials, and / or uses should be understood to be modified by the word "about," unless otherwise explicitly indicated. When modifying numerical values ​​in the specification or claims, "about" indicates a range of accuracy familiar and acceptable to those skilled in the art. Generally, this range of accuracy is ±10%. Therefore, "about ten" means nine to eleven.

[0008] In some embodiments herein, a "material layer" is a layer comprising at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, or at least 99 wt.% of the identified material; and a layer that is a "material" comprises at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, or at least 99 wt.% of the identified material. For example, certain embodiments of each of a titanium nitride layer and a layer that is titanium nitride are layers of at least 50 wt.%, at least 60 wt.%, at least 75 wt.% titanium nitride, or at least 90 wt.% titanium nitride, or at least 99 wt.% titanium nitride.

[0009] For the sake of brevity, well-known techniques for manufacturing semiconductor devices may not be described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more complex procedures or processes with additional functionality not described in detail herein. Specifically, the various processes in manufacturing semiconductor devices are well-known, and therefore, for the sake of brevity, many processes will be briefly mentioned or completely omitted without providing well-known process details. It will be readily apparent to those skilled in the art that, after a complete reading of one embodiment of this disclosure, the structures disclosed herein can be used with various techniques and incorporated into various semiconductor devices and products. Additionally, it should be noted that semiconductor device structures include a varying number of components, and a single component shown in the illustrations may represent multiple components.

[0010] Some embodiments described herein generally relate to multi-gate transistors. Multi-gate transistors include those transistors in which gate structures are formed on at least two sides of a channel region. These multi-gate devices may include p-type metal-oxide-semiconductor devices or n-type metal-oxide-semiconductor multi-gate devices. Specific examples may be shown and referred to herein as gate-all-around (GAA) devices. A GAA device includes any means in which a gate structure or a portion thereof is formed on all four sides of a channel region (e.g., surrounding a portion of the channel region).

[0011] Please note that although the figures and descriptions depict the structure of a gate-all-around (GAA) device, it is anticipated that the methods described herein can be used to facilitate other types of devices, and that the devices described herein may be of other types.

[0012] The structures presented herein also include embodiments having channel regions in the form of nanosheets. The term "nanosheet" refers to any material portion having a nanoscale or even micrometer-scale size and an elongated shape without regard to the cross-sectional shape of this portion. Thus, this term refers to elongated material portions with circular and substantially circular cross-sections, such as nanowires, and includes rods and rod-shaped material portions, such as those with cylindrical or substantially rectangular cross-sections.

[0013] In devices such as NSFET / GAAFET, achieving good top-to-bottom loading in the full-around gate (dummy gate replacement) is critical for device performance and yield. Controlling pattern loading in the full-around process is also important in systems-on-chip (SoC) with numerous devices. However, OD width (OD) loading issues can lead to residual discardable oxide in the full-around process. The oxide diffusion region, or OD region, or active region in a semiconductor device is the active region of each transistor. This is where the source, drain, and channel are formed below the transistor gate. OD is located between non-active regions, such as shallow trench isolation (STI) or field oxide (FOX) regions.

[0014] In an embodiment, a method is provided to remove residual disposable oxides in the source / drain region where source / drain features are formed, such as source / drain features.

[0015] Some embodiments provide the removal of more disposable oxide in the vertical direction compared to the lateral direction. For example, directional etching can be used to remove the bottom portion of the trench of disposable oxide or to make the bottom portion of the trench recessed, while the lateral surfaces of the nanosheet portion of the disposable oxide are not etched, or are etched only in a negligible amount in the lateral direction.

[0016] Some embodiments provide a mask in which the device has a large OD width, i.e., a semiconductor device region from 5 nm to 100 nm, while having a small OD width, i.e., a semiconductor device region from 2 nm to 30 nm, through directional etching to remove or recess the disposable oxide layer. In some embodiments, the large OD width is at least 2 nm larger than the small OD width.

[0017] Referring now to Figure 1, a method 900 for forming a structure such as a multi-gate device is illustrated in the flowchart according to one embodiment of this disclosure. As used herein, the term "multi-gate device" describes a device (e.g., a semiconductor transistor) having at least some gate materials disposed on multiple sides of at least one channel of the device. In some instances, a multi-gate device may be referred to as a GAA device, which has gate materials disposed on four sides of at least one channel component of the device. The channel component may be referred to as a "nanosheet".

[0018] Figure 1 is described in conjunction with Figures 2 through 17, which illustrate a semiconductor device 800 at various manufacturing stages according to some embodiments of this disclosure during method 900. Method 900 is merely an example and is not intended to limit one embodiment of this disclosure to anything beyond what is expressly described in the claims. Additional steps may be provided before, during, and after method 900, and some of the steps described above for additional embodiments of method 900 may be removed, replaced, or eliminated. Additional features may be added to the semiconductor device depicted in the figures, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device.

[0019] As with other method embodiments and exemplary devices discussed herein, it should be understood that portions of semiconductor device 800 can be manufactured using typical semiconductor technology process flows, and therefore some processes are described only briefly herein. Additionally, exemplary semiconductor devices may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but have been simplified for better understanding of the concepts of one embodiment of this disclosure. In some embodiments, exemplary devices include a plurality of semiconductor devices (e.g., transistors), including interconnectable PFETs, NFETs, etc. Furthermore, please note that, as with the remainder of the methods and exemplary figures provided in one embodiment of this disclosure, the process steps of method 900, including any descriptions given with reference to the figures, are merely illustrative and are not intended to limit the scope beyond what is specifically described in the following claims.

[0020] At operation S902, method 900 (Figure 1) provides a substrate 200, as illustrated in Figure 2. In some embodiments, substrate 200 may be a semiconductor substrate such as a silicon (Si) substrate. Substrate 200 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 200 may include various doping configurations according to design requirements known in the art. For example, different doping profiles (e.g., p-type wells, n-type wells) may be formed on substrate 200 in regions designed for different device types (e.g., n-type field-effect transistors (NFETs), p-type field-effect transistors (PFETs)). Suitable doping may include dopant ion implantation and / or diffusion processes, such as boron (B) for p-type wells and phosphorus (P) for n-type wells. In some embodiments, substrate 200 includes a single-crystal semiconductor layer at least on its surface portion. The substrate 200 may comprise a single-crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, the substrate 200 may comprise a compound semiconductor and / or an alloy semiconductor. In the illustrated embodiment, the substrate 200 is made of crystalline Si.

[0021] As illustrated in Figure 2, at operation S904, method 900 (Figure 1) forms one or more epitaxial layers over substrate 200. In some embodiments, an epitaxial stack 212 is formed over substrate 200. The epitaxial stack 212 includes an epitaxial layer 214 of a first composite material into which an epitaxial layer 216 of a second composite material is inserted. The first composite material and the second composite material may be different. Embodiments including those providing first and second composite materials with different oxidation rates and / or etch selectivity are possible. Thus, epitaxial layer 214 can be selectively removed to define semiconductor layer 216 as a nanosheet channel layer. In an embodiment, epitaxial layer 214 is SiGe, and epitaxial layer 216 is silicon. In embodiments where epitaxial layer 214 comprises SiGe and epitaxial layer 216 comprises silicon, the silicon oxidation rate is less than the SiGe oxidation rate. Please note that the three layers of epitaxial layer 214 and the three layers of epitaxial layer 216 are illustrated in Figure 2, which is for illustrative purposes only and is not intended to limit the scope of the claims. It is understood that any number of epitaxial layers can be formed in the epitaxial stack 212; the number of layers depends on the desired number of channel regions of the GAA device 800. In some embodiments, the number of epitaxial layers 216 is between two and ten, such as six or seven.

[0022] In some embodiments, epitaxial layer 214 has a thickness ranging from about 5 nm to about 15 nm. The thickness of epitaxial layer 214 may be substantially uniform. In some embodiments, epitaxial layer 216 has a thickness ranging from about 5 nm to about 15 nm. In some embodiments, the stacked epitaxial layers 216 have a substantially uniform thickness. As described in more detail below, epitaxial layer 216 may serve as a channel region of a subsequently formed multi-gate device and has a thickness selected based on device performance considerations. Epitaxial layer 214 may be used to define gaps between adjacent channel regions of a subsequently formed multi-gate device and has a thickness selected based on device performance considerations.

[0023] By way of example, the epitaxial growth of the epitaxial stack 212 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial layer 216 may comprise the same material as the substrate 200. In some embodiments, the epitaxial growth layers 214 and 216 comprise materials different from those of the substrate 200. As stated above, in at least some instances, epitaxial layer 214 comprises an epitaxially grown Si1-xGex layer (where x ranges from 0.10 to 0.55), and epitaxial layer 216 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either epitaxial layer 214 or 216 may comprise other materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. As discussed above, the materials of epitaxial layers 214 and 216 may be selected based on providing different oxidation and etch selectivity properties. In various embodiments, epitaxial layers 214 and 216 are substantially doped (i.e., having a dopant range of 0 cm⁻³ to 1 × 10¹⁷). (intrinsic dopant concentration in cm⁻³), wherein, for example, unintentional doping is not performed during the epitaxial growth process. In some embodiments, the bottom and top layers of the epitaxial stack 212 are SiGe layers (not shown). In an alternative embodiment, the bottom layer of the epitaxial stack 212 is a Si layer, and the top layer of the epitaxial stack 212 is a SiGe layer.

[0024] As illustrated in Figure 3, at operation S906, method 900 (Figure 1) patternes the epitaxial stack 212 to form a semiconductor fin 220. In some embodiments, operation S906 includes forming a mask 217 over the epitaxial stack 212, as illustrated in Figure 2. The mask 217 includes a first mask layer 218 and a second mask layer 219. The exemplary first mask layer 218 is a pad oxide layer made of silicon oxide, which may be formed by thermal oxidation. The exemplary second mask layer 219 is made of silicon nitride (SiN) and may be formed by chemical vapor deposition (CVD), including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD); physical vapor deposition (PVD); atomic layer deposition (ALD) or other suitable processes. Mask 217 is patterned into a mask pattern using patterning operations including optical lithography and etching.

[0025] As illustrated in Figure 3, operation S906 then patterns the epitaxial stack 212 in an etching process, such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes, via openings defined in the patterned mask 217. The stacked epitaxial layers 214 and 216 are thereby patterned into fins 220. Although Figure 3 illustrates the formation of one fin 220, any suitable number of fins may be formed. Trench etching is performed between adjacent fins 220.

[0026] In various embodiments, each fin 220 includes an upper portion of staggered epitaxial layers 214 and 216 and a bottom portion or mesa portion 210 formed from the etched substrate 200. Each fin 220 projects upward from the substrate 200 in the Z direction and extends longitudinally in the Y direction. The sidewalls of each fin 220 may be vertical or inclined (not shown). In Figure 3, additional fins are spaced apart along the X direction. The fins 220 may have the same width or different widths.

[0027] As illustrated in Figure 4, at operation S908, method 900 (Figure 1) forms an isolation feature (also indicated as a shallow trench isolation or STI feature) 221, wherein a dielectric layer is formed in a trench adjacent to each fin 220. The STI feature 221 can be formed by first filling the trench around each fin 220 with a dielectric material layer to cover the top surface and sidewalls (not shown) of the fin 220. The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin coating. The dielectric material layer is then planarized using, for example, chemical mechanical planarization (CMP) until the top surface of mask 217 is exposed, and the dielectric material layer is recessed to form a shallow trench isolation (STI) feature (also referred to as STI feature) 221, as illustrated in Figure 4. In the illustrated embodiment, STI feature 221 is formed on substrate 200. Any suitable etching technique, including dry etching, wet etching, RIE, and / or other etching methods, can be used to recess the isolation feature 221, and in an exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation feature 221 without etching the fins 220. Mask 217 (illustrated in Figure 3) can also be removed before, during, and / or after recessing the isolation feature 221. In some embodiments, mask 217 is removed by a CMP process performed before recessing the isolation feature 221. In some embodiments, the mask 217 is removed by an etchant used to make the isolation feature 221 recessed.

[0028] As illustrated in Figure 5, at operation S910, method 900 (Figure 1) forms a sacrificial (dummy) gate structure 222. The sacrificial gate structure 222 is formed above the portion of the fin 220 that will be the channel region. Specifically, the sacrificial gate structure 222 is located directly above and defines the channel region of the GAA device to be formed. The sacrificial gate structure 222 may extend above a plurality of adjacent fins (not shown). Each of the sacrificial gate structures 222 includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224 above the sacrificial gate dielectric 223. As illustrated, the gate structures 222 extend longitudinally in the X direction and are spaced apart in the Y direction.

[0029] The sacrificial gate structure 222 is formed by first depositing a sacrificial gate dielectric layer over the fin 220 using a blanket deposition method. A sacrificial gate electrode layer is then deposited over the sacrificial gate dielectric layer and over the fin 220 using a blanket deposition method. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. The thickness of the sacrificial gate electrode layer is in some embodiments ranging from about 100 to about 200 nm. The sacrificial gate electrode 224 comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate dielectric layer is in some embodiments ranging from about 1 to about 5 nm. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, PVD, ALD, or other suitable processes, including LPCVD and PECVD. A mask 225 is formed over the sacrificial gate electrode layer. Mask 225 may include a mask layer 226 such as silicon oxide and a mask layer 227 such as silicon nitride. Subsequently, a patterning operation is performed on mask 225, and the sacrificial gate electrode layer and the sacrificial gate dielectric layer are patterned into a sacrificial gate structure 222, including a sacrificial gate dielectric 223 and a sacrificial gate electrode 224.

[0030] As shown in the figure, the fin 220 is partially exposed, that is, between the opposite sides of the sacrificial gate structure 222 and not covered by the overlying structure, thereby defining the source / drain (S / D) region. As used herein, "source / drain region" or "source / drain feature" may refer individually or collectively to the source or drain, depending on the context.

[0031] Referring again to Figure 5, in operation S912, method 900 (Figure 1) forms spacers 230 on the sidewalls of the sacrificial gate structure 222 and the sidewalls of the fins 220 by depositing spacer material and then etching. The spacers 230 may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each of the spacers 230 includes multiple layers, such as a liner layer 231 and a primary spacer layer 232 above the liner layer 231.

[0032] By way of example, spacer 230 is formed over sacrificial gate structure 222 by depositing spacer layers, including lining material layers and dielectric material layers, using processes such as subatmospheric CVD (SACVD), flow CVD, ALD, PVD or other suitable processes.

[0033] As illustrated in Figures 6 and 7, the deposited liner material layer and dielectric material layer are followed by an etch-back (e.g., anisotropic) process at S914 to expose and remove the portion 220a (e.g., source / drain region) of the fin 220 adjacent to and not covered by the sacrificial gate structure 222. Specifically, method 900 (Figure 1) recesses the portion of the fin 220 not covered by the sacrificial gate structure 222 to form a slot, recess, or cavity 234 in the source / drain region. Note that Figure 6 illustrates only one sacrificial gate structure 222 and the adjacent portion of the fin 220, making the etching of the S / D region between the sacrificial gate structures 222 in Figure 5 more clearly visible. Figure 7 is a cross-sectional view taken along line 6-6 in Figure 6, but similar to Figure 5. Figure 7 shows two sacrificial gate structures 222 and fins 220 adjacent to the two sacrificial gate structures 222.

[0034] The lining material layer and dielectric material layer may remain on the sidewalls of the sacrificial gate structure 222 as sidewall spacers 230, and also remain on the sidewalls of the fins as fin sidewall spacers 230. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The spacers 230 may have a thickness ranging from about 5 nm to about 20 nm.

[0035] As most clearly illustrated in Figure 7, the upper portion of the stacked epitaxial layers 214 and 216 and the substrate 200 forming fins 220 is etched downwards in the S / D region. Therefore, a bottom cavity surface 233 is formed in the fins 220. In some embodiments, operation S914 forms the cavity 234 by a suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof. As a result of the etching process, fin segments 235 of the upper portion of the fins 220 are defined and separated from each other by the cavities 234.

[0036] Figure 8 provides the same cross-sectional view as Figure 7 during subsequent manufacturing stages. As illustrated in Figure 8, at operation S916, method 900 (Figure 1) removes the first epitaxial layer 214, such as the SiGe layer 214. Therefore, a temporary gap 213 is formed between the remaining second epitaxial layers 216. In an embodiment, layer 214 can be removed using a wet etching process that selectively removes the material of the first layer (e.g., silicon germanium (SiGe)) without significantly removing the material of the second layer 216 (e.g., silicon (Si)). However, any suitable removal process can be utilized.

[0037] Figure 9 provides a perspective view of the lower portion of device 800 in a subsequent manufacturing stage. The mask 225 covering the sacrificial gate electrode 224 is not shown. As illustrated in Figure 9, at operation S918, method 900 (Figure 1) forms a disposable or sacrificial intermediate layer material or layer 700 above the structure of device 800. As illustrated, the intermediate layer 700 is conformally deposited on the surface of the sidewall spacers 230, above the bottom cavity surface 233, and in the temporary gap 213. The intermediate layer 700 may fill the temporary gap 213. The intermediate layer 700 includes a sidewall portion 710, a bottom portion 720, and a nanosheet portion 730. Additionally, the intermediate layer 700 may be formed above the mask (not shown) to cover the sacrificial gate electrode 224.

[0038] In some embodiments, the interposer 700 is an oxide material. For example, the interposer 700 may be silicon oxide. In some embodiments, the interposer 700 is formed by a refill process. In some embodiments, the interposer 700 is formed by a flow chemical vapor deposition (FCVD) process. In some embodiments, the interposer 700 comprises multiple layers formed to control the loading and / or shape of the layer 700. Additionally, in some embodiments, the interposer 700 is formed by an initial deposition process followed by a refill process, such as atomic layer deposition (ALD).

[0039] Figure 10 provides the same perspective view as Figure 9 for subsequent manufacturing stages. As illustrated in Figure 10, at operation S920, method 900 (Figure 1) includes performing an etching process to recess the interposer 700.

[0040] In some embodiments, operation S920 includes performing anisotropic or directional etching processes, such as in the vertical direction, i.e., the Z-direction. For example, operation S920 may include performing a plasma etching process by using bias power for directional control. The anisotropic etching process may use a gaseous plasma, such as CF4+CHF3, C5F8, and / or C4F8 with added gases such as N2, Ar, and / or O2. The etching reactor used may be a parallel-plate type with or without commercially available magnetic field or electron cyclotron resonance (ECR) type enhancement. The process formulation may include a gas mixture of 400 watts RF power, 80 millitor pressure, and 10 sccm CF4 + 90 sccm CHF3 + 80 sccm Ar, wherein the etching time is approximately 15 seconds.

[0041] As illustrated in Figure 10, the directional etching process allows the sidewall portion 710 to be recessed to the recessed upper surface 711. As shown, the recessed upper surface 711 of the sidewall portion 710 can be located above the substrate 200, i.e., at a greater height than the uppermost nanosheet portion 730, such as being located above the substrate 200, i.e., at a greater height than the uppermost nanosheet 216.

[0042] As further illustrated in Figure 10, the directional etching process can completely remove the bottom portion 720, leaving an interposer-free layer 700 on the bottom cavity surface 233. In other embodiments, after the directional etching process is performed, a residual portion of the bottom portion 720 may remain on the bottom cavity surface 233.

[0043] As seen in the embodiment of Figure 10, the portion 730 between nanosheets is not etched by a directional etching process.

[0044] Figure 11 provides the same perspective view as Figure 10 for subsequent manufacturing stages. As illustrated in Figure 11, at operation S922, method 900 (Figure 1) includes performing an etching process to laterally recess the inter-nanometer portion 730 of the interlayer 700.

[0045] In some embodiments, operation S922 includes performing an isotropic etching or non-directional etching process. For example, operation S922 may include performing wet etching. In some embodiments, operation S922 includes performing a wet etching process using a diluted HF solution and / or an aqueous buffered HF solution. In some embodiments, the etchant is selected to exhibit high selectivity relative to removing the substrate 200, nanosheet 216, or sidewall spacers 230 to remove the interposer 700.

[0046] As shown in Figure 11, operation S922 can remove a portion of the sidewall portion 710. Additionally, if any remaining portion of the bottom portion 720 remains after operation S920, operation S922 can remove all remaining portions of the bottom portion 720.

[0047] In some embodiments, the vertical thickness of any residual portion of the bottom portion 720 remaining on the bottom cavity surface 233 after operation S922 is completed is less than 0.4 nm, such as less than 0.3 nm, less than 0.25 nm, less than 0.2 nm, less than 0.15 nm, less than 0.1 nm, or less than 0.5 nm.

[0048] As shown in the figure, operation S922 causes the inter-sheet portion 730 to be laterally recessed into the recessed surface 731. As shown in the figure, the recessed surface 731 is spaced apart in the X direction from the outer surface 2161 of the nanosheet 216. Therefore, the lateral recess 732 is formed below / above the nanosheet 216 and laterally adjacent to the recessed surface 731 of the inter-sheet portion 730.

[0049] Figure 12 provides a cross-sectional view of the device 800 taken at a subsequent manufacturing stage, such as along the same cross-section as in Figure 8. As illustrated in Figure 12, at operation S924, method 900 (Figure 1) includes the formation of internal spacers 400 in the lateral recesses 732 of the laterally recessed nanosheet portion 730 adjacent to the interlayer 700.

[0050] For example, operation S924 may include depositing an internal spacer material layer in the cavity 234 on the sidewall of the slot, including the recessed surface 731 of the inter-nanosheet portion 730, the end of the epitaxial layer 216, and on the top and bottom surfaces, and on the bottom cavity surface 233. The internal spacer material layer may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon carbonoxynitride, and / or other suitable dielectric materials. In some embodiments, the internal spacer material layer is deposited as a conformal layer. The internal spacer material layer may be formed by ALD or any other suitable method. The internal spacer material layer may have a thickness ranging from 1 to 5 nm, for example, 1 to 4 nm, 1 to 3 nm, or 1 to 2 nm.

[0051] Operation S924 may further include trimming the internal spacer material layer. The removal of the internal spacer material layer may be performed by an etching process, such as anisotropic etching, for example, a dry etching process. In some embodiments, the dry etching process uses an etchant including fluorine-containing gases (e.g., SF6, CF4, CHF3, CH2F2 and / or C2F6), chlorine-containing gases (e.g., Cl2), bromine-containing gases (e.g., HBr and / or CHBR3), oxygen-containing gases (e.g., O2), helium-containing gases (e.g., He), argon-containing gases (e.g., Ar), other suitable gases, or combinations thereof. In this etching, the internal spacer material layer remains substantially within the lateral recess 732.

[0052] Figure 13 provides the same cross-sectional view as Figure 12 for subsequent manufacturing stages. As illustrated in Figure 13, method 900 (Figure 1) can continue in operation S926, which forms source / drain features 500 in cavity 234.

[0053] For example, operation S926 may include growing epitaxial material in cavity 234 to form source / drain feature 500. Note that source / drain feature 500 may be formed from subsequently formed layers. In an exemplary embodiment, source / drain feature 500 is a strained source / drain feature 500. Furthermore, source / drain feature 500 may have layers selected for use in NFETs or PFETs. In an exemplary embodiment, source / drain feature 500 may include N-type epitaxial material source / drain features and P-type epitaxial material source / drain features. Epitaxial material may include one or more Si, SiP, SiC, and SiCP layers for N-type channel FETs, or one or more Si, SiGe, and Ge layers for P-type channel FETs. For P-type channel FETs, boron (B) may also be present in the source / drain. Source / drain epitaxial layers can be formed by epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy (MBE).

[0054] Figure 14 provides the same cross-sectional view as Figure 13 in subsequent manufacturing stages. As illustrated in Figure 14, method 900 (Figure 1) can continue with operation S928 of covering the source / drain feature 500 with a dielectric material.

[0055] Specifically, a dielectric liner 440 may be formed above the source / drain feature 500 and along the sidewall spacer 230. Additionally, a dielectric 450 may be formed above the dielectric liner 440 above the source / drain feature 500. Specifically, the cavity 234 is filled with the dielectric 450. In an exemplary embodiment, the dielectric 450 is a first interlayer dielectric layer (ILD). The dielectric 450 may be silicon oxide or other suitable dielectric materials. In some embodiments, the dielectric liner 440 is a dielectric, such as silicon nitride or another suitable material.

[0056] As illustrated in Figure 14, structure 800 can be planarized, for example, by a chemical-mechanical planarization (CMP) process. Planarization removes the mask 225 and exposes the sacrificial gate electrode 224.

[0057] Method 900 (Figure 1) can be initiated by operation S930, which is used to initiate the process of source / drain feature 500. In some embodiments, operation S930 may be a high-temperature annealing process. For example, a high-temperature annealing process may be performed at a temperature of at least 1000 degrees Celsius. In other embodiments, the process may be a low-temperature annealing process. For example, a low-temperature annealing process may be performed at a temperature of less than 1000 degrees Celsius. During the annealing process, the interposer 700 prevents interdiffusion in the nanosheet layer 216. Specifically, the interposer 700 forms a barrier layer that resists the diffusion of impurities such as SiGe or Ge through vacancies in the nanosheet layer 216.

[0058] Figure 15 provides the same cross-sectional view as Figure 14 during subsequent manufacturing stages. As illustrated in Figure 15, operation S932 of removing the sacrificial gate structure 222 in method 900 (Figure 1) continues. As illustrated, the sacrificial gate electrode 224 is removed to form a gate cavity 499 between the sidewall spacers 230.

[0059] Figure 16 provides the same cross-sectional view as Figure 15 in subsequent manufacturing stages. As illustrated in Figure 16, method 900 (Figure 1) can continue with operation S934 of removing the inter-nanosheet portion 730 of the interlayer 700 between the nanosheet channel layers 216.

[0060] Removing the inter-nanosheet portion 730 creates a cavity 215 around the semiconductor layer 216. In some embodiments, operation S934 may include a wire release process to form vertically spaced nanosheets. The wire release process step may also be referred to as a sheet release process step, a sheet formation process step, a nanosheet formation process step, or a wire formation process step. In embodiments, the inter-nanosheet portion 730 may be removed using a wet etching process that selectively removes material from the inter-nanosheet portion 730 without significantly removing material from the second layer 216 (e.g., silicon (Si)). However, any suitable removal process may be used.

[0061] Figure 17 provides the same cross-sectional view as Figure 16 in subsequent manufacturing stages. As illustrated in Figure 17, method 900 (Figure 1) can continue in operation S936, which forms the metal gate 380 in the gate cavity 499.

[0062] Specifically, method 900 may include lining the gate cavity 499 with a dielectric layer or liner 610. For example, a high-K gate dielectric liner 610 may be deposited on the sidewalls of the gate cavity 499 and around the nanosheet channel layer 216.

[0063] As used and described herein, high-k gate dielectrics include dielectric materials having a high dielectric constant, for example, greater than that of thermally heated silicon oxide (about 3.9). An exemplary high-k gate dielectric liner 610 may include a high-k dielectric material such as hafnium oxide (HfO2). Alternatively, the high-k gate dielectric liner 610 may comprise other high-k dielectric materials, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, SiON, combinations thereof, or other suitable materials. The high-k gate dielectric liner 610 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0064] The metal gate 600 is further filled with a filler material 620 to fill the gate cavity 499. The filler material 620 may comprise multiple layers of metal, metal alloy, or metal silicate. The filler material 620 may comprise a single layer or alternatively a multilayer structure, such as a metal layer having a selected work function to enhance device performance (work function metal layer), a liner layer, a wetting layer, an adhesive layer, or various combinations of metal alloys or metal silicates. By way of example, the filler material 620 may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the filler material 382 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Additionally, the filler material 382 may be formed separately for N-type and P-type transistors that may use different metal layers. Furthermore, the filler material 620 can provide an N-type or P-type work function, serving as a transistor gate electrode, and in at least some embodiments, the filler material 620 may include a polycrystalline silicon layer. In some instances, the filler material 620 may include selectively grown tungsten (W) and / or fluorine-free tungsten (FFW) layers.

[0065] As illustrated in Figure 17, a chemical mechanical planarization (CMP) process can be performed to remove the overloaded portions of the liner 610 and filler material 620 to define the metal gate 600 in the gate cavity 499.

[0066] As indicated in Figure 1, method 900 can proceed with further processing, such as performing middle end of line (MEOL) processing and back end of line (BEOL) processing operations S938.

[0067] Figures 1 and 2 through 17 illustrate method 900, which ensures that all of the interposer layer 700 is removed from the bottom cavity surface 233 before the source / drain feature 500 is formed on the bottom cavity surface 233, or at least minimizes the amount of interposer layer 700 remaining on the bottom cavity surface 233. Therefore, the epitaxial growth of the material forming the source / drain feature 500 is improved.

[0068] Figure 18 illustrates another embodiment of the execution method 900.

[0069] Figure 18 illustrates a first region 801 and a second region 802 of device 800. Regions 801 and 802 are formed in different regions of substrate 200. Although shown in a vertically aligned manner in the figures, regions 801 and 802 are separated from each other in the X direction of device 800. In the first region 801, device 800 has a small active region or OD width 811 in the Y direction, i.e., an OD width 811 from 2 nm to 30 nm. In the second region 802, device 800 has a large active region or OD width 822 in the Y direction, i.e., an OD width 822 from 5 nm to 100 nm. In some embodiments, the large OD width 822 is at least 2 nm larger than the small OD width 811.

[0070] Figure 18 illustrates the apparatus 800 after the formation of the intermediate layer 700 according to operation S918. Specifically, the deposition process is performed across apparatus 800, including apparatus regions 801 and 802. Due to the difference between OD widths 811 and 822, the bottom portion 720 is formed with different heights or vertical thicknesses. Specifically, the bottom portion 720 in region 801 has a first thickness 831, and the bottom portion 720 in region 802 has a second thickness 832. As illustrated, the first thickness 831 is greater than the second thickness 832. For example, the first thickness 831 may be at least 1 nm larger than the second thickness 832, such as at least 2 nm, at least 3 nm, at least 5 nm, at least 8 nm, or at least 10 nm larger than the second thickness 832.

[0071] Therefore, extensive etching is required to remove the bottom portion 720 in the first region 801.

[0072] During operation S920, directional etching is used to simultaneously recess the bottom portions 720 in regions 801 and 802. Using highly selective etching, such as by controlling the CxFy / O2 ratio, over-etching of the bottom portions in region 802 can be avoided. Subsequently, method 900 can continue as described above in operation S922.

[0073] Figure 19 illustrates another embodiment of the execution method 900.

[0074] Figure 19 illustrates a first region 801 and a second region 802 of device 800. Regions 801 and 802 are formed in different regions of substrate 200. Although shown in a vertically aligned manner in the figures, regions 801 and 802 are separated from each other in the X direction within device 800. In the first region 801, device 800 has a small active region or OD width 811, i.e., an OD width 811 from 2 nm to 30 nm. In the second region 802, device 800 has a large active region or OD width 822, i.e., an OD width 822 from 5 nm to 100 nm. In some embodiments, the large OD width 822 is at least 2 nm larger than the small OD width 821.

[0075] Figure 19 illustrates the apparatus 800 after the formation of the intermediate layer 700 according to operation S918. Specifically, the deposition process is performed across apparatus 800, including apparatus regions 801 and 802. Due to the difference between the OD widths 811 and 822, the bottom portion 720 is formed with different heights or vertical thicknesses. Specifically, the bottom portion 720 in region 801 has a first thickness 831, and the bottom portion 720 in region 802 has a second thickness 832. As illustrated, the first thickness 831 is greater than the second thickness 832.

[0076] Therefore, extensive etching is required to remove the bottom portion 720 in the first region 801.

[0077] In the embodiment of Figure 19, prior to performing operation S920, a mask 850 is formed over device region 802 in operation S919 of method 900 as illustrated. The mask 850 may be formed of photoresist. Therefore, operation S920 may be performed by directional etching, which recesses the bottom portion 720 in region 801 but does not etch the bottom portion in region 802. In some embodiments, the bottom portion 720 in region 801 is recessed, and the first thickness 831 is reduced until the difference between thicknesses 831 and 832 is no greater than 0.5 nm. Specifically, the absolute value operation S920 may be performed until the absolute value of the first thickness 831 minus the second thickness 832 is less than or equal to 0.5 nm.

[0078] After performing operation S920, the mask can be removed in operation S921. Thereafter, method 900 can continue as described above in operation S922. By reducing the difference between thicknesses 831 and 832, the load is reduced during the isotropic etching in operation S922, and operation S922 can remove all the interposer layer 700 from the bottom cavity surface 233 without laterally etching too much of the inter-nanometer sheet portion 730, i.e., forming a disk shape.

[0079] Figure 20 is a cross-sectional view of the device 800 after the sacrificial gate has been removed, similar to that in Figure 15. As shown, the source / drain feature 500 comprises three distinct layers: a first layer 501, a second layer 502, and a third layer 503. The first layer 501 is grown directly on the bottom cavity surface 233.

[0080] The first layer 501, the second layer 502, and the third layer 503 can be formed from different materials. For example, layers 510, 502, and 503 can be silicon, silicon phosphide (SiP), silicon carbide, or silicon arsenide (SiAs). In some other embodiments, another pentavalent material can be used to form a silicon compound, such as antimony (Sb), bismuth (Bi), molybdenum (Mc), other pentavalent silicon compounds, or combinations thereof. Each layer 501, 502, and 503 can be formed by an epitaxial growth process. The epitaxial growth process can be an LPCVD process with silicon precursors, a selective epitaxial growth (SEG) process, a cyclic deposition and etching (CDE) process, other suitable processes, or combinations thereof. For example, silicon phosphide crystals can be formed by a chemical gas (Si3H8, SiH3CH3, and / or PH3) deposition process combined with a selective chemical vapor deposition process. In another example, silicon crystals can be grown using LLPCVD with dichlorosilane (SiH2Cl2) as a precursor. The precursor can be doped in situ (during the epitaxial growth process) or externally (after the epitaxial growth process is complete) with n-type dopants, such as phosphorus (P) for the first layer 501 and the second layer 502, and arsenic (As) for the third layer 503, to form different epitaxial layers of the epitaxial S / D feature 500. In some embodiments, the different epitaxial layers of the epitaxial S / D feature 500 are doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the different layers of the epitaxial S / D feature 500 are doped by an ion implantation process after the deposition process. The implantation energy and dose during the ion implantation process can be configured, depending on the design of the device 800. For example, the first epitaxial layer 501 may be formed by ion implantation doping with a low concentration of P (e.g., a molar ratio of P less than about 2%) to a silicon precursor with a thickness of about 1 nm to about 10 nm; the second epitaxial layer 502 may be formed by ion implantation doping with a higher concentration of P (e.g., a molar ratio of P of about 2% to about 10%) to a silicon precursor with a thickness of about 10 nm to about 40 nm; and the third epitaxial layer 503 may be formed by ion implantation doping with As (e.g., about 1×1022 to 1×1023 atoms / cm3 of arsenic, in some embodiments about 2% to about 10% of As) to a silicon precursor with a thickness of about 0.1 nm to about 20 nm.

[0081] As shown in Figure 20, the first layer 501 has a maximum vertical thickness 511 from the lowest surface to the highest surface.

[0082] In this embodiment, where device 800 is simultaneously formed in device region 801 with a small OD width and device region 802 with a large OD width, and device region 802 is not masked (i.e., operation S919 is not performed), the maximum vertical thickness 511 of device 800 in region 801 ranges from 1 to 30 nm, and the maximum vertical thickness 511 of device 800 in region 802 also ranges from 1 to 30 nm. Furthermore, in this embodiment, due to the high amount of oxide etched in region 802, the maximum vertical thickness 511 in region 802 is at least 0.2 nm greater than the maximum vertical thickness 511 in region 801.

[0083] These dimensions are achieved through an etching process that removes more oxides in device region 802 compared to device region 801.

[0084] In this embodiment, where device 800 is simultaneously formed in device region 801 with a small OD width and device region 802 with a large OD width, and device region 802 is masked (i.e., operation S919 is performed), the maximum vertical thickness 511 of device 800 in region 801 is from 1 to 30 nm, and the maximum vertical thickness 511 of device 800 in region 802 is from 1 to 30 nm. Furthermore, in this embodiment, the difference in maximum vertical thickness 511 between regions 801 and 802 is attributed to a selective region of no more than 0.5 nm provided by the selective etching of the thicker bottom portion 720 in region 801 while region 802 is masked.

[0085] In one embodiment, a method includes: in a first device region and in a second device region: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a sacrificial gate above the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of slots; and depositing an interposer material above the bottom surface and in the slots; in the first device region: performing an anisotropic etching on the interposer material positioned above the bottom surface; and in the first device region and the second device region: performing an isotropic etching on the interposer material to remove the interposer material positioned above the bottom surface and to laterally recess the interposer material in the slots.

[0086] In some embodiments of the method, isotropic etching is performed to form a plurality of lateral recesses, and the method further includes: forming a plurality of internal spacers in the lateral recesses; forming a source / drain feature in the cavity; removing a sacrificial gate to form a gate cavity; and forming a metal gate in the gate cavity.

[0087] In some embodiments, the method further includes: masking the second device region with a mask before performing anisotropic etching; and removing the mask from the second device region before performing isotropic etching.

[0088] In some embodiments, the method further includes: forming a source / drain feature in the cavity, including a first epitaxial material layer formed on the bottom surface, wherein in a first device region, the first epitaxial material layer has a first thickness of 1 to 30 nm; in a second device region, the first epitaxial material layer has a second thickness of 1 to 30 nm; and a difference of at least 0.2 nm between the first thickness and the second thickness.

[0089] In some embodiments of the method, anisotropic etching of the interlayer material positioned above the bottom surface is performed in the second device region.

[0090] In some embodiments of the method, after depositing the interposer material, the interposer material above the bottom surface in the first device region has a first initial thickness, and the interposer material above the bottom surface in the second device region has a second initial thickness; the difference between the first initial thickness and the second initial thickness is at least 1 nm; after performing anisotropic etching on the interposer material positioned above the bottom surface, the interposer material above the bottom surface in the first device region has a first recessed thickness, and the interposer material above the bottom surface in the second device region has a second initial thickness; and the difference between the first recessed thickness and the second initial thickness is not greater than 0.5 nm.

[0091] In some embodiments, the method further includes: forming a source / drain feature in the cavity, including a first epitaxial material layer formed on the bottom surface, wherein in a first device region, the first epitaxial material layer has a first thickness of 1 to 30 nm; in a second device region, the first epitaxial material layer has a second thickness of 1 to 30 nm; and a difference between the first thickness and the second thickness is less than 0.5 nm.

[0092] In some embodiments of the method, depositing an intermediate layer material above the bottom surface and in the gap includes filling the gap with the intermediate layer material.

[0093] In some embodiments of the method, the interlayer material is silicon oxide.

[0094] In some embodiments of the method, a residual portion of one of the interposer materials remains on the bottom surface after isotropic etching is performed, and wherein the residual portion has a vertical thickness of less than 0.2 nm.

[0095] In another embodiment, a method includes: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of slots; depositing an interposer material above the bottom surface and in the slots; recessing the interposer material positioned above the bottom surface, wherein a remaining portion of one of the interposer materials remains above the bottom surface; and performing an isotropic etching on the interposer material to remove the remaining portion of the interposer material positioned above the bottom surface and to laterally recess the interposer material in the slots.

[0096] In some embodiments of the method, isotropic etching is performed to form a plurality of lateral recesses, and the method further includes: forming a plurality of internal spacers in the lateral recesses; forming a source / drain feature in the cavity; and forming a metal gate adjacent to the source / drain feature.

[0097] In some embodiments of the method, depositing an intermediate layer material above the bottom surface and in the gap includes filling the gap with the intermediate layer material.

[0098] In some embodiments of the method, the interlayer material is silicon oxide.

[0099] In some embodiments of the method, a residual portion of one of the interposer materials remains on the bottom surface after isotropic etching is performed, and wherein the residual portion has a vertical thickness of less than 0.2 nm.

[0100] In another embodiment, a method includes: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a plurality of sacrificial gates over the stack; etching the stack to form a plurality of cavities having a plurality of bottom surfaces; removing the first epitaxial layers to form a plurality of slots; depositing an interposer material over the bottom surfaces and in the slots; directionally etching the interposer material positioned over a plurality of selected bottom surfaces; and isotropically etching the interposer material to remove the interposer material positioned over the bottom surfaces and to laterally recess the interposer material in the slots.

[0101] In some embodiments, the method further includes masking a plurality of non-selected bottom surfaces before directional etching of an interposer material positioned above the selected bottom surfaces; and exposing the non-selected bottom surfaces before isotropically etching the interposer material.

[0102] In some embodiments of the method, the method includes directional etching of an interposer material positioned above a plurality of non-selected bottom surfaces, while simultaneously directional etching of an interposer material positioned above a selected bottom surface.

[0103] In some embodiments, the method further includes forming a source / drain feature in the cavity, including a first epitaxial material layer formed on a bottom surface, wherein: the first epitaxial material layer has a first thickness of 1 to 30 nm above a plurality of selected bottom surfaces; the first epitaxial material layer has a second thickness of 1 to 30 nm above a plurality of non-selected bottom surfaces; and a difference of at least 0.2 nm between the first thickness and the second thickness.

[0104] In some embodiments, the method further includes: forming a source / drain feature in the cavity, including a first epitaxial material layer formed on a bottom surface, wherein: the first epitaxial material layer has a first thickness of 1 to 30 nm above a plurality of selected bottom surfaces; the first epitaxial material layer has a second thickness of 1 to 30 nm above a plurality of non-selected bottom surfaces; and a difference between the first thickness and the second thickness is not greater than 0.5 nm.

[0105] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of one embodiment of this disclosure. Those skilled in the art should understand that one embodiment of this disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of one embodiment of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of one embodiment of this disclosure.

[0106] 200:Substrate 210: Bottom section / Countertop section 212: Epitaxial Stacking 213: Temporary gap 214: Epitaxial layer 215: Cavity 216: Semiconductor layer / epitaxy layer 217: Mask 218: First masking layer 219: Second masking layer 220: Fins 220a: Partial 221: Isolation Features 222: Sacrificial (dummy) gate structure 223: Sacrificial gate dielectric 224: Sacrificial gate electrode 225: Mask 226: Masking layer 227: Masking layer 230: Spacer 231: Lining layer 232: Main spacer layer 233: Bottom cavity surface 234: Cavity 235: Fin section 380: Metal gate 382: Filler material 400: Internal spacers 440: Dielectric liner 450: Dielectric 499: Gate cavity 500: Source / Drain Characteristics 501: First Floor 502: Second layer 503: Third Floor 511: Maximum vertical thickness 600: Metal gate 610: Dielectric layer or lining 620: Filler material 700: Intermediary Layer 710: Sidewall section 711: Recessed upper surface 720: Bottom section 730: Nanosheet Intersection 731: Through the recessed surface 732: Lateral concave portion 800: Semiconductor Devices / Structures 801: Zone 1 802: Second District 811: OD width 822: OD width 831: First Thickness 832: Second thickness 850: Mask 900: Method 2161: Outer surface S902: Operation S904: Operation S906: Operation S908: Operation S910: Operation S912: Operation S914: Operation S916: Operation S918: Operation S919: Operation S920: Operation S921: Operation S922: Operation S924: Operation S926: Operation S928: Operation S930: Operation S932: Operation S934: Operation S936: Operation S938: Operation

[0107] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a semiconductor structure, comprising the following steps: in a first device region and a second device region: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a sacrificial gate over the stack; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of gaps; and depositing an interposer material over the bottom surface and in the gaps; in the first device region: performing an anisotropic etching on the interposer material positioned over the bottom surface; and in the first device region and the second device region: performing an isotropic etching on the interposer material such that the interposer material positioned over the bottom surface is removed and a portion of the interposer material in the gaps is removed to form a laterally recessed surface, wherein the interposer material positioned over the bottom surface and the interposer material in the gaps are the same material.

2. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the isotropic etching step is performed to form a plurality of lateral recesses, and wherein the method further comprises the following steps: forming a plurality of internal spacers in the lateral recesses; forming a source / drain feature in the cavity; removing the sacrificial gate to form a gate cavity; and forming a metal gate in the gate cavity.

3. The method of manufacturing a semiconductor structure as claimed in claim 1 further comprises the following steps: shielding the second device region with a mask before performing the anisotropic etching; and removing the mask from the second device region before performing the isotropic etching.

4. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the anisotropic etching of the interposer material positioned above the bottom surface is performed in the second device region.

5. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the step of depositing the interposer material above the bottom surface and in the gaps comprises the step of filling the gaps with the interposer material.

6. A method for manufacturing a semiconductor structure, comprising the steps of: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; etching the stack to form a cavity having a bottom surface; removing the first epitaxial layers to form a plurality of gaps; depositing an interposer material above the bottom surface and in the gaps; recessing the interposer material positioned above the bottom surface, wherein a remaining portion of the interposer material remains above the bottom surface; and performing an isotropic etching on the interposer material such that the remaining portion of the interposer material positioned above the bottom surface is removed and a portion of the interposer material in the gaps is removed to form a laterally recessed surface, wherein the remaining portion of the interposer material positioned above the bottom surface is the same material as the interposer material in the gaps.

7. A method for manufacturing a semiconductor structure as claimed in claim 6, wherein the isotropic etching step is performed to form a plurality of lateral recesses, and wherein the method further comprises the steps of: forming a plurality of internal spacers in the lateral recesses; forming a source / drain feature in the cavity; and forming a metal gate adjacent to the source / drain feature.

8. A method of manufacturing a semiconductor structure, comprising the steps of: forming a stack of a plurality of first epitaxial layers and a plurality of second epitaxial layers; forming a plurality of sacrificial gates over the stack; etching the stack to form a plurality of cavities having a plurality of bottom surfaces; removing the first epitaxial layers to form a plurality of gaps; depositing an interposer material over the bottom surfaces and in the gaps; directionally etching the interposer material positioned over a plurality of selected bottom surfaces; and isotropically etching the interposer material such that the interposer material positioned over the bottom surfaces is removed and a portion of the interposer material in the gaps is removed to form laterally recessed surfaces, wherein the interposer material positioned over the bottom surfaces and the interposer material in the gaps are the same material.

9. The method of manufacturing a semiconductor structure as claimed in claim 8, further comprising the steps of: masking a plurality of non-selected bottom surfaces before directional etching of an interposer material positioned above the selected bottom surfaces; and exposing the non-selected bottom surfaces before isotropically etching the interposer material.

10. A method for manufacturing a semiconductor structure as claimed in claim 8, wherein the method comprises the steps of: directionally etching the interposer material positioned above a plurality of non-selected bottom surfaces, and simultaneously directionally etching the interposer material positioned above the selected bottom surfaces.

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