Read-only memory (ROM) device and method

Abstract

A read-only memory (ROM) device includes an active region extending along a first direction and a plurality of gates extending across and above the active region along a second direction intersecting the first direction. The plurality of gates, together with the active region, are correspondingly configured as a plurality of transistors. Each of the plurality of transistors is configured to store data. The active region extends continuously through and beneath more than four of the plurality of gates.

Description

Prior Technology

[0001] An integrated circuit (“IC”) device includes one or more semiconductor devices represented in an IC layout (also referred to as a “layout”, “IC layout”, or “layout”). A layout is hierarchical and includes modules that perform higher-order functions according to the IC device design specifications. Modules are typically constructed from combinations of cells, each representing one or more semiconductor structures configured to perform a specific function. Cells with pre-designed layouts (sometimes referred to as standard cells) are stored in a standard cell library (hereinafter referred to as a “library” or “cell library” for brevity) and are accessible by various tools (such as electronic design automation (EDA) tools) to generate, optimize, and verify IC designs. Examples of IC devices and cells accordingly include memory devices and memory cells. Simple Explanation of the Diagram

[0002] The best understanding of the present disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is a schematic block diagram of a memory device according to some embodiments. Figures 2A, 2B, 2C, 2D, 2E, 2F, and 2G are schematic circuit diagrams of various memory cells according to some embodiments. Figure 3A is a schematic circuit diagram of the circuit region of a memory device according to some embodiments. Figure 3B is a schematic view of the layout of the circuit regions of a memory device according to some embodiments. Figure 3C is a schematic cross-sectional view of the circuit region of a memory device according to some embodiments. Figure 4 is a schematic view of the layout of the circuit regions of a memory device according to some embodiments. Figures 5A, 5B, 5C, 5D, and 5E each include schematic circuit diagrams and layout schematic views of the circuit regions of a memory device according to some embodiments. Figures 6A, 6B, 6C, 6D, 6E, and 6F each include schematic circuit diagrams and layout schematic views of the circuit regions of a memory device according to some embodiments. Figures 7A, 7B, 7C, and 7D are flowcharts of various methods according to some embodiments. Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 9 is a block diagram of an IC device manufacturing system and an associated IC manufacturing process according to some embodiments. Implementation

[0003] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, or the like are also contemplated. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Depending on the context, a source / drain may be referred to individually or collectively as a source or drain.

[0004] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0005] In some embodiments, a read-only memory (ROM) device or its layout includes instances of a plurality of circuit regions or ROM cells arranged adjacent to each other. The ROM device or layout includes active regions that extend continuously through the plurality of adjacent circuit regions or ROM cell instances without being interrupted or discontinuous by one or more isolation structures within or between the plurality of instances.

[0006] Compared to other methods that incorporate and / or maintain such isolation structures within adjacent instances of circuit regions or ROM cells, the size of the ROM device in one or more embodiments is advantageously reduced. In a non-limiting example, a 4x4 ROM cell according to some embodiments has a width of 4 gate pitches (sometimes referred to as "CPPs"), while a 4x4 ROM cell according to other methods has a larger width of 5 CPPs or 6 CPPs. Thus, according to one or more embodiments, a ROM device comprising a 4x4 ROM cell with 4-CPPs can achieve an area reduction of approximately 16.7% compared to a ROM device comprising a 4x4 ROM cell with 5-CPPs, or an area reduction of approximately 33.3% compared to a ROM device comprising a 4x4 ROM cell with 6-CPPs according to other methods. In some embodiments, one or more further advantages can be achieved, including but not limited to reduced bit line length, reduced variable bit line leakage, reduced polyextension effect (PXE), or similar effects.

[0007] Figure 1 is a schematic block diagram of a memory device 100 according to some embodiments. A memory device is a type of IC device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is incorporated as part of a larger IC device that includes circuitry for other functions besides the memory device. In one or more embodiments, the memory device 100 is a read-only memory (ROM) device.

[0008] Memory device 100 includes a memory array 101 comprising a plurality of memory cells MC, and a memory controller 102 (sometimes referred to as "memory control circuitry") coupled to control the operation of the memory cells MC. In a ROM device according to some embodiments, each memory cell MC is configured to store one bit, sometimes referred to as a bit cell, and the memory array 101 is referred to as a ROM array. In memory array 101, memory cells MC are arranged in a plurality of rows and a plurality of columns. The number of rows and the number of columns in memory array 101 may be the same or different. Rows and columns in memory array are sometimes referred to as memory rows and memory columns. Memory rows extend along a row direction, designated as the C-axis in the figure. Memory columns extend along a column direction laterally to the row direction, designated as the R-axis in the figure.

[0009] The memory device 100 also includes a plurality of word lines WL0, WL1, ... WLn extending along columns of the memory array 101, and a plurality of bit lines BL0, BL1, ... BLm extending along rows of the memory array 101. Word lines are generally denoted herein by the label WL, and bit lines are generally denoted herein by the label BL. Word lines are configured to transmit the address of a memory cell MC to be read. Word lines are sometimes referred to as "address lines." Bit lines are configured to transmit data read from the memory cell MC indicated by the address on the corresponding word line. Bit lines are sometimes referred to as "data lines." Various numbers of word lines and / or bit lines in the memory device 100 are within the scope of various embodiments. Memory cells MC in each memory column are electrically coupled to the memory controller 102 via corresponding word lines, and memory cells MC in each memory row are electrically coupled to the memory controller 102 via corresponding bit lines. For example, memory cells 111 in memory array 101 are coupled to memory controller 102 via corresponding word lines WL1 and corresponding bit lines BL1.

[0010] In the example configuration of Figure 1, the memory controller 102 includes word line driver circuitry 103 (sometimes referred to as a column decoder or column decoder circuit), bit line driver circuitry 104 (sometimes referred to as a row decoder or row decoder circuit), and control circuitry 106. Various numbers of word line driver circuits and / or bit line driver circuits are available throughout the various embodiments.

[0011] The word line driver circuit 103 is configured to decode the column address of one or more memory cells MC selected for access during a read operation. For example, the word line driver circuit 103 includes a plurality of word line drivers or similar elements, each coupled to one or more word lines of the memory array 101. The word line driver circuit 103 is configured to provide a set of access voltages to the selected word line corresponding to the decoded column address via the corresponding word line driver or similar element, and to provide a different set of voltages (e.g., zero) to the other unselected word lines.

[0012] Bit line driver circuit 104 is configured to decode the row address of one or more memory cells MC selected for access during a read operation. In some embodiments, bit line driver circuit 104 includes one or more bit line multiplexers, each coupled to one or more bit lines of memory array 101. In some embodiments, bit line driver circuit 104 is configured to provide a set of voltages to selected bit lines corresponding to the selected memory cell MC to be accessed via the bit line multiplexers, and to provide a different set of voltages to other unselected bit lines. In at least one embodiment, unselected bit lines remain floating. For example, bit line driver circuit 104 includes one or more pre-charging circuits configured to pre-charge selected bit lines to a pre-charging voltage during a read operation. In some embodiments, selected bit lines are not pre-charged. Bit line driver circuit 104 is configured to couple selected bit lines corresponding to the selected memory cell MC to an output circuit (not shown), a sense amplifier (not shown), or a similar element in memory controller 102 to read data stored in the selected memory cell MC.

[0013] In the example read operation, memory cell 111 is selected for access. Therefore, the corresponding word line WL1 is the selected word line, and the corresponding bit line BL1 is the selected bit line. Word line driver circuit 103 is configured to provide an access voltage (e.g., VDD) to the selected word line WL1 and a different voltage (e.g., zero or VSS) to the other unselected word lines. Bit line driver circuit 104 is configured to provide a pre-charge voltage (e.g., VDD) to the selected bit line BL1 and couple the selected bit line BL1 to an output circuit or a sense amplifier. When an access voltage is applied to memory cell 111 through word line WL1, the pre-charge voltage on bit line BL1 either remains unchanged or is pulled to VSS, depending on the data or bits stored in memory cell 111. The voltage on bit line BL1 is provided to the output circuit or sense amplifier to read the data or bits stored in memory cell 111.

[0014] Control circuitry 106 is configured to control the operation of word line driver circuitry 103, bit line driver circuitry 104, output circuitry, sense amplifier, and / or other components in memory controller 102. In at least one embodiment, memory controller 102 further includes one or more clock generators for providing clock signals to various components of memory device 100, one or more input / output (I / O) circuits for exchanging data, clock signals, and / or control with external devices or circuits, and / or one or more sub-controllers for controlling various operations in memory device 100. The described memory device configuration is an example, and other memory device configurations are also within the scope of various embodiments.

[0015] Figures 2A-2G are schematic circuit diagrams of various memory cells 200A-200G according to some embodiments. In some embodiments, one or more of memory cells 200A-200G correspond to one or more of the memory cells MC described with respect to Figure 1. For simplicity, corresponding components in Figures 2A-2G are designated by the same reference numerals.

[0016] Memory cells 200A-200B are examples of memory cells configured to store a first logic value, and memory cells 200C-200G are examples of memory cells configured to store a second logic value different from the first logic value. In the specific example described herein, the first logic value is logic "1" and the second logic value is logic "0". Other configurations where the first logic value is logic "0" and the second logic value is logic "1" are also within the scope of various embodiments. Memory cells 200A-200G are sometimes referred to as NOR-type ROM bit cells, and ROM devices including one or more memory cells 200A-200G are sometimes referred to as NOR-type ROM devices.

[0017] In Figure 2A, memory cell 200A includes a transistor T having a gate 211, a first source / drain 212, and a second source / drain 213. The gate 211 is electrically coupled to a word line WL, the first source / drain 212 is electrically coupled to a power rail 215, and the second source / drain 213 is electrically coupled to a bit line BL. In at least one embodiment, the word line WL corresponds to one or more word lines, and the bit line BL corresponds to one or more bit lines described with respect to Figure 1. The power rail 215 is configured to carry a power supply voltage for read operations of memory cell 200A. In the example configurations of Figures 2A-2G, the transistor T is an N-type transistor, and the power supply voltage carried by the power rail 215 is ground voltage, or VSS. The power rail 215 configured to carry VSS is referred to herein as the VSS power rail. Other configurations are also within the scope of various embodiments. For example, when transistor T is a P-type transistor, power rail 215 is configured to carry a positive voltage, such as VDD or a similar voltage. Examples of transistor T include, but are not limited to, MOSFETs, CMOS transistors, P-channel MOSFETs, N-channel MOSFETs, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or similar devices. In one or more non-limiting embodiments particularly described herein, all transistors in the ROM array are N-type transistors, such as NMOS transistors.

[0018] In an example read operation of memory cell 200A according to some embodiments, an access voltage (e.g., VDD) is supplied to the gate 211 of transistor T via word line WL, and bit line BL is precharged to a precharge voltage (e.g., VDD). The access voltage turns on transistor T, and the turned-on transistor T is electrically coupled to bit line BL to the VSS power rail. As a result, the voltage on bit line BL is pulled down from the precharge voltage (e.g., VDD) to VSS. The voltage pulled down on bit line BL to VSS is output or detected by a sense amplifier to indicate that logic "1" is stored in memory cell 200A.

[0019] The configuration of memory cell 200A, configured to store logic "1", is referred to herein as the ON configuration. The ON configuration means that when transistor T is turned on, the conducting transistor T electrically couples bit line BL to the VSS power rail. Memory cell 200B is another example of a memory cell having an ON configuration and configured to store logic "1". Conversely, as described herein, memory cells 200C-200G are examples of memory cells having an OFF configuration and configured to store logic "0". The OFF configuration means that when transistor T is turned on, the conducting transistor T does not electrically couple bit line BL to the VSS power rail.

[0020] The ON configuration of memory cell 200A, wherein the first source / drain 212 is electrically coupled to the VSS power rail and the second source / drain 213 is electrically coupled to the bit line BL, is referred to herein as ON configuration 1g.

[0021] In Figure 2B, memory cell 200B is configured to store logic "1" and has an ON configuration. In memory cell 200B, a first source / drain 212 is electrically coupled to bit line BL and a second source / drain 213 is electrically coupled to the VSS power rail, and the ON configuration of memory cell 200B is referred to herein as ON configuration 1h. In some embodiments, the read operation of memory cell 200B is similar to that described with respect to memory cell 200A, i.e., when transistor T is turned on, the turned-on transistor T electrically couples bit line BL to the VSS power rail, and the voltage on bit line BL is pulled down from the precharge voltage to VSS to indicate that logic "1" is stored in memory cell 200B.

[0022] In Figure 2C, memory cell 200C is configured to store logic "0" and has an OFF configuration. In memory cell 200C, both the first source / drain 212 and the second source / drain 213 are electrically coupled to the VSS power rail, and the OFF configuration of memory cell 200C is referred to herein as OFF configuration OFF.

[0023] In an example read operation of memory cell 200C according to some embodiments, an access voltage (e.g., VDD) is supplied to the gate 211 of transistor T via word line WL, and bit line BL is precharged to a precharge voltage (e.g., VDD). The access voltage turns on transistor T. However, because both the first source / drain 212 and the second source / drain 213 are electrically coupled to the VSS power rail, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail. As a result, the voltage on bit line BL remains at the precharge voltage (e.g., VDD). The voltage maintained at the precharge voltage on bit line BL is output or detected by a sense amplifier to indicate that logic "0" is stored in memory cell 200C.

[0024] In Figure 2D, memory cell 200D is configured to store logic "0" and has an OFF configuration. In memory cell 200D, both the first source / drain 212 and the second source / drain 213 are electrically coupled to bit line BL, and the OFF configuration of memory cell 200D is referred to herein as OFF configuration 0i. In some embodiments, the read operation of memory cell 200D is similar to that described with respect to memory cell 200C, i.e., when transistor T is turned on, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail, and the voltage on bit line BL is maintained at a precharge voltage to indicate that logic "0" is stored in memory cell 200D.

[0025] In Figure 2E, memory cell 200E is configured to store logic "0" and has an OFF configuration. In memory cell 200E, the first source / drain 212 and the second source / drain 213 are not electrically coupled to either the bit line BL or the VSS power rail. In at least one embodiment, the first source / drain 212 and the second source / drain 213 are electrically floating. In some embodiments, the read operation of memory cell 200E is similar to that described with respect to memory cell 200C, i.e., when transistor T is turned on, the turned-on transistor T does not electrically couple the bit line BL to the VSS power rail, and the voltage on bit line BL is maintained at a pre-charge voltage to indicate that logic "0" is stored in memory cell 200E.

[0026] In Figure 2F, memory cell 200F is configured to store logic "0" and has an OFF configuration. In memory cell 200F, a first source / drain 212 is electrically coupled to the VSS power rail, but a second source / drain 213 is not electrically coupled to either bit line BL or the VSS power rail. In at least one embodiment, the second source / drain 213 is electrically floating. In some embodiments, the read operation of memory cell 200F is similar to that described with respect to memory cell 200C, i.e., when transistor T is turned on, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail, and the voltage on bit line BL is maintained at a precharge voltage to indicate that logic "0" is stored in memory cell 200F.

[0027] In Figure 2G, memory cell 200G is configured to store logic "0" and has an OFF configuration. In memory cell 200G, the second source / drain 213 is electrically coupled to bit line BL, but the first source / drain 212 is not electrically coupled to either bit line BL or the VSS power rail. In at least one embodiment, the first source / drain 212 is electrically floating. In some embodiments, the read operation of memory cell 200G is similar to that described with respect to memory cell 200C, i.e., when transistor T is turned on, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail, and the voltage on bit line BL is maintained at a precharge voltage to indicate that logic "0" is stored in memory cell 200G. The OFF configuration of memory cells 200E-200G is generally referred to herein as OFF configuration 0a.

[0028] In some embodiments, during the design phase, a blank or unprogrammed ROM array corresponding to memory array 101 is developed. In such an unprogrammed ROM array, each memory cell or bit unit has the configuration described with respect to FIG. 2E, wherein the electrical connections from the first source / drain 212 and the second source / drain 213 to the bit lines BL and VSS power rails have not yet been determined. In a subsequent programming phase, the unprogrammed ROM array is programmed according to data to be stored in the ROM array. For example, each bit unit in the unprogrammed ROM array is programmed by adding or not adding one or more electrical connections according to the data or bit or logic value to be stored in the bit unit, and according to one of the configurations described with respect to FIG. 2A-FIG.

[0029] In some embodiments, the unprogrammed ROM array is programmed using Code Pattern 1, using the configuration described with respect to Figures 2A-2D, instead of the configuration described with respect to Figures 2E-2G. Non-limiting examples of ROM programming using Code Pattern 1 are described with respect to Figures 5A-5E.

[0030] In some embodiments, the unprogrammed ROM array is programmed using code mode 2, using all the configurations described with respect to Figures 2A-2G. Non-limiting examples of ROM programming using code mode 2 are described with respect to Figures 6A-6F.

[0031] Figure 3A is a schematic circuit diagram of circuit region 301 of memory device 300A according to some embodiments. In at least one embodiment, memory device 300A corresponds to memory device 100 and / or circuit region 301 corresponds to a region in memory array 101. For simplicity, corresponding elements in Figures 1, 2A-2G, and 3A are designated with the same reference numerals.

[0032] In Figure 3A, circuit region 301 includes four consecutive bit cells, each corresponding to one of the memory cells MC described with respect to Figure 1 and / or the memory cells 200A-200G described with respect to Figures 2A-2G. These four bit cells correspondingly include transistors T0-T3. The gates of transistors T0-T3 are electrically coupled to word lines WL0-WL3, respectively. Transistors T0-T3 are series coupled such that a pair of directly adjacent transistors share a common source / drain. When there are no other transistors between two transistors, the two transistors are considered directly adjacent (or adjacent). In some embodiments, as described herein, two directly adjacent transistors have corresponding gates physically separated by a gate pitch (CPP). In the example configuration of Figure 3A, transistors T0 and T1 are directly adjacent and share a common source / drain (unnumbered) electrically coupled to electrical connector 311, transistors T1 and T2 are directly adjacent and share a common source / drain (unnumbered) electrically coupled to electrical connector 312, and transistors T2 and T3 are directly adjacent and share a common source / drain (unnumbered) electrically coupled to electrical connector 313.

[0033] Another transistor TK outside circuit region 301 is directly adjacent to transistor T0 and shares a common source / drain (not numbered). A further transistor TL outside circuit region 301 is directly adjacent to transistor T3 and shares a common source / drain (not numbered). In some embodiments, another instance of circuit region 301 is disposed below and adjacent to circuit region 301 (in FIG. 3A), and transistor TK corresponds to transistor T3 in this other instance of circuit region 301, having a gate electrically coupled to a word line (not shown). In some embodiments, a further instance of circuit region 301 is disposed above and adjacent to circuit region 301 (in FIG. 3A), and transistor TL corresponds to transistor T0 in this further instance of circuit region 301, having a gate electrically coupled to a word line (not shown). In some embodiments, one of transistors TK and TL is omitted, for example when circuit region 301 is located at the edge of a ROM array.

[0034] Each of transistors T0-T3 (or their corresponding bit units) is configured to store a predetermined data, bit, or logic value according to one of the configurations described in Figures 2A-2G. For example, transistor T0 is configured to store logic "0". Because one source / drain of transistor T0 is electrically coupled to bit line BL via electrical connector 311, the other source / drain of transistor T0 is either electrically coupled to bit line BL according to the OFF configuration 0i in Figure 2D, or electrically floated according to the OFF configuration 0a in Figure 2G. Transistor T1 is configured to store logic "1" and has one source / drain electrically coupled to bit line BL via electrical connector 311 according to one of the ON configuration 1g in Figure 2A and the ON configuration 1h in Figure 2B, and the other source / drain is electrically coupled to the VSS power rail via electrical connector 312. Transistor T2 is configured to store logic "1" and, according to ON configuration 1g in FIG2A or ON configuration 1h in FIG2B, has one source / drain electrically coupled to the VSS power rail via electrical connector 312, while the other source / drain is electrically coupled to bit line BL via electrical connector 313. Transistor T3 is configured to store logic "0". Because one source / drain of transistor T3 is electrically coupled to bit line BL via electrical connector 313, the other source / drain of transistor T3 is either electrically coupled to bit line BL according to OFF configuration 0i in FIG2D, or electrically floated according to OFF configuration 0a in FIG2G. In some embodiments, each of transistors TK and TL outside circuit region 301 is also configured to store a logic value according to one of the configurations described in FIG2A-FIG.

[0035] Figure 3B is a schematic layout diagram of circuit region 302 of memory device 300B according to some embodiments. In at least one embodiment, memory device 300B corresponds to memory device 300A and / or circuit region 302 corresponds to circuit region 301. For simplicity, corresponding components in Figures 1, 2A-2G, and 3A-3B are designated by the same reference numerals.

[0036] As shown in the layout of Figure 3B, the memory device 300B includes an active region OD extending along a first direction (e.g., the X-axis) and a plurality of gates GK, G0-G3, GL extending through and above the active region OD along a second direction (e.g., the Y-axis), which intersects with the first direction. The gates GK, G0-G3, GL, together with the active region OD, are correspondingly configured as transistors, each transistor configured to store data. In some embodiments, the gates GK, G0-G3, GL in Figure 3B correspond to the gates of transistors TK, T0-T3, TL in Figure 3A, and the transistors with gates GK, G0-G3, GL in Figure 3B correspond to transistors TK, T0-T3, TL in Figure 3A. The gates GK, G0-G3, GL are arranged along the X-axis with a gate pitch (CPP), which is the distance between the center lines of directly adjacent gates along the X-axis, for example, as shown by gates G2 and G3. When there are no other gates between two gates, the two gates are considered to be directly adjacent (or immediately adjacent).

[0037] The active region OD extends continuously along the X-axis, passing through and below four or more of the multiple gates GK, G0-G3, GL. In the example configuration of FIG3B, the active region OD continuously spans and lies below six gates GK, G0-G3, GL. In at least one embodiment, one of the gates GK, GL is omitted (e.g., when the circuit region 302 is located at the edge of the ROM array), and the active region OD continuously spans and lies below at least five gates. Other numbers (greater than 6) of gates continuously extending below the active region OD are also within the range of various embodiments. In some embodiments, the memory device 300B includes multiple instances of circuit regions 302 arranged adjacent to each other along the X-axis. For example, another instance of circuit region 302 is arranged below and adjacent to circuit region 302 (in FIG3B), and / or a further instance of circuit region 302 is arranged above and adjacent to circuit region 302 (in FIG3B). In at least one embodiment, the active region OD continuously passes through and lies beneath the gates of a plurality of instances of circuit regions 302 arranged adjacently along the X-axis. In some embodiments, all gates through which the active region OD continuously extends and lies beneath belong to transistors configured to store data, such as transistors TK, T0-T3, TL described with respect to FIG. 3A and / or transistor T described with respect to FIG. 2A-FIG.

[0038] The active region OD extends continuously along the X-axis and lies beneath four or more gates of a transistor configured to store data, without being interrupted or discontinuous by an isolation structure. In some embodiments, the memory device 300B does not have an isolation structure dividing the active region OD into electrically isolated portions. This differs from other methods that include isolation structures within and / or at the edges of circuit regions. For example, according to other methods, there is an isolation structure beneath gates GL and GK extending along the Y-axis to divide the active region OD into three electrically isolated portions. Alternatively, according to other methods, gates GL and GK will be dummy gates containing non-conductive material and / or not forming a transistor configured to store data. For example, according to other methods, gates GL and GK will be dummy gates not electrically coupled to word lines. Conversely, in one or more embodiments, each of a plurality of gates continuously spanned and located beneath the active region OD is electrically coupled to a word line, and the transistor formed by such gates and the active region OD is configured to store data. Compared to other methods that have isolation structures that divide the active region into electrically isolated portions, the size of the memory device 300B with the active region OD continuously extended is advantageously reduced.

[0039] The memory device 300B also includes contact structures MD0-MD4, which are respectively located above the source / drain of the transistor configured by gates GK, G0-G3, GL and active region OD. For simplicity, not all contact structures are shown in Figure 3B. Contact structures MD0-MD4 are arranged along the X-axis with gate pitch (CPP), which is the distance between the centerlines of directly adjacent contact structures along the X-axis, for example, as shown by contact structures MD1 and MD2. When there are no other contact structures between two contact structures, the two contact structures are considered to be directly adjacent (or adjacent). Contact structures MD0 and MD4 are arranged on the edge of circuit region 302 and shared with other instances of circuit region 302 adjacent to circuit region 302. This is a further distinction from other methods of setting isolation structures and / or dummy gates on the edge of circuit region.

[0040] The memory device 300B also includes bit lines BL and VSS power rails that overlap with the active region OD and extend continuously along the X-axis across multiple gates. In the example configuration of Figure 3B, the bit lines BL and VSS power rails are conductive patterns in a phase metal layer above the contact structures MD0-MD4 and the gates GK, G0-G3, GL. In some embodiments, the bit lines BL and VSS power rails extend continuously across the same number of gates as the active region OD.

[0041] The memory device 300B also includes vias VD1-VD3, each of which has a corresponding bit line BL or VSS power rail in its electrically coupled contact structure MD0-MD4, for programming or configuring the corresponding transistor to store predetermined data. In at least one embodiment, vias VD1-VD3 correspond to electrical connectors 311-313.

[0042] In at least one embodiment, the size of the memory device 300B, which extends continuously over the active region OD, is advantageously reduced, as is the length of the bit line BL along the X-axis, compared to other methods that have isolation structures that divide the active region into electrically isolated portions. In at least one embodiment, the reduced bit line BL length provides one or more further advantages, including, but not limited to, reduced parasitic capacitance, reduced drive strength and / or size requirements of the bit line drive circuitry, etc.

[0043] Figure 3C is a schematic cross-sectional view of a circuit region of a memory device 300C according to some embodiments. In at least one embodiment, the memory device 300C corresponds to one or more of memory devices 100, 300A, and 300B. For simplicity, corresponding elements in Figures 1, 2A-2G, and 3A-3C are designated by the same reference numerals.

[0044] The memory device 300C includes a substrate 320 and at least one transistor 321 on the substrate 320. In at least one embodiment, the transistor 321 corresponds to one or more memory cells MC, memory cells 200A-200G, transistors TK, T0-T3, TL, and transistors having gates GK, G0-G3, GL in the memory device 100.

[0045] In some embodiments, substrate 320 is a semiconductor substrate. N-type and P-type dopants are added to the substrate to form N-type wells 322, 323 and P-type wells (not shown), respectively. In some embodiments, isolation structures are formed between adjacent P-type and N-type wells. For simplicity, several features such as P-type wells and isolation structures are omitted in FIG3C.

[0046] Transistor 321 includes a gate stack and source / drain electrodes. N-type wells 322, 323 define the source / drain electrodes of transistor 321. A portion of substrate 320, or a P-type well (not shown) between source / drain electrodes 322, 323, corresponds to a channel of transistor 321. The channel and source / drain electrodes 322, 323 together correspond to an active region, such as the active region OD described with respect to FIG. 3B. The gate stack of transistor 321 includes a gate dielectric layer 324 and a gate 325. In at least one embodiment, transistor 321 includes multiple gate dielectric layers. Exemplary materials for the gate dielectric layers include HfO₂, ZrO₂, or the like. Exemplary materials for the gate 325 include polysilicon, metal, or the like. The described transistor 321 configuration is one example. Various other transistor configurations are within the scope of various embodiments.

[0047] The memory device 300C also includes conductive features configured to electrically couple transistor 321 to other circuitry within the memory device 300C. These conductive features include source / drain (metal-to-device, or MD) contact structures 326 and 327, respectively, located above and electrically contacting source / drain 322 and 323. The conductive features also include various vias. For example, a via-to-gate (VG) via 330 is located above and electrically contacts gate 325. Vias-to-device (VD) vias 328 and 329 are located above and electrically contacting MD contact structures 326 and 327, respectively. The VG via 330 and / or VD vias 328 and 329 are configured as various patterns, as described herein, to couple transistor 321 to the MO layer of the redistribution structure 350.

[0048] The redistribution structure 350 comprises multiple metal layers M0, M1, ... and multiple via layers V0, V1, ..., arranged alternately in the thickness direction (i.e., along the Z-axis) of the substrate 320. The redistribution structure 350 also includes various interlayer dielectric (ILD) layers (not shown), with the metal layers and via layers embedded therein. The M0 layer, or metal zero (M0) layer, is the bottommost metal layer, directly above and electrically contacting the VD and VG vias, and is schematically represented by the label "M0" in the figure. The M1 layer is the metal layer directly above the M0 layer, and is schematically represented by the label "M1" in the figure. The redistribution structure 350 also includes other metal layers sequentially stacked above the M1 layer. The redistribution structure 350 also includes via layers arranged between consecutive metal layers and electrically coupled to them. Via layers Vn are arranged between and electrically coupled to layers Mn and Mn+1, where n is an integer starting from zero. For example, the via zero (V0) layer is the bottommost via layer, arranged between and electrically coupled to layers M0 and M1, and is schematically represented by the label "V0" in the figure. The metal layers and via layers of the redistribution structure 350 are configured to form interconnects, electrically coupling various components or circuits of the memory device 300C to each other and to external circuits.

[0049] In the example configuration of Figure 3C, the M0 layer includes M0 conductive patterns 331, 332, and 333, which are located on and electrically contacted with VD vias 328, 329, and 330, respectively. In at least one embodiment, M0 conductive pattern 331 corresponds to one of the bit line BL and the VSS power rail, while M0 conductive pattern 332 corresponds to the other of the bit line BL and the VSS power rail. For example, M0 conductive pattern 331 corresponds to the bit line BL, while M0 conductive pattern 332 corresponds to the VSS power rail. As described with respect to Figure 3B, M0 conductive patterns 331 and 332 extend along the X-axis. M0 conductive pattern 333 corresponds to the word line pattern and is electrically coupled to M1 conductive pattern 335 in the M1 layer through V0 via 334. M1 conductive pattern 335 corresponds to the word line and extends along the Y-axis.

[0050] The configuration of MD contact structures 326 and 327 coupled to the bit line BL (M0 conductive pattern 331) and VSS power rail (M0 conductive pattern 332) in FIG3C is an example and corresponds to, for example, the ON configuration 1g in FIG2A.

[0051] When transistor 321 is configured with ON configuration 1h as shown in FIG2B, MD contact structures 326 and 327 are coupled to VSS power rail (M0 conductive pattern 332) and bit line BL (M0 conductive pattern 331), respectively.

[0052] When transistor 321 is configured with the OFF configuration 0f in FIG2C, MD contact structures 326 and 327 are both coupled to the VSS power rail (M0 conductive pattern 332).

[0053] When transistor 321 is configured with OFF configuration 0i as shown in FIG2D, MD contact structures 326 and 327 are both coupled to bit line BL (M0 conductive pattern 331).

[0054] When transistor 321 is configured with OFF configuration 0a in FIG2E, MD contact structures 326, 327 are not coupled to VSS power rail (M0 conductive pattern 332) and bit line BL (M0 conductive pattern 331). For example, VD vias 328, 329 are omitted.

[0055] When transistor 321 is configured with OFF configuration 0a as shown in FIG2F, MD contact structure 326 is not coupled to bit line BL (M0 conductive pattern 331). For example, VD via 328 is omitted.

[0056] When transistor 321 is configured with the OFF configuration 0a in FIG2G, MD contact structure 327 is not coupled to VSS power rail (MO conductive pattern 332). For example, VD via 329 is omitted. According to some embodiments, memory device 300C may achieve one or more of the advantages described herein.

[0057] Figure 4 is a schematic diagram of the circuit region layout of a memory device 400 according to some embodiments. In some embodiments, the memory device 400 corresponds to one or more of memory devices 100, 300A, 300B, and 300C. For simplicity, corresponding elements in Figures 1, 2A-2G, 3A-3C, and 4 are designated with the same reference numerals.

[0058] Memory device 400 includes multiple instances of circuit regions arranged adjacent to each other along the X and Y axes. Some instances of the circuit regions are shown in FIG. 4 as Cell_0, Cell_1, Cell_2, Cell_3, for example. For simplicity, other instances of the circuit regions are omitted in FIG. 4. As shown in FIG. 4, Cell_0, Cell_1, Cell_2, and Cell_3 are arranged adjacent to each other along their corresponding boundaries. Each of Cell_0, Cell_1, Cell_2, and Cell_3 corresponds to a ROM cell 405 having the layout shown in FIG. 4. In at least one embodiment, the ROM cell 405 is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. In the example configuration of FIG. 4, the ROM cell 405 is a 4x4 ROM cell comprising 16 bit cells arranged in four rows along the X axis and four columns along the Y axis. Other sizes and / or dimensions of ROM cells are within the scope of various embodiments.

[0059] ROM cell 405 includes a boundary 410 (i.e., a cell boundary) through which multiple instances of ROM cell 405 can be placed adjacent to each other, as described herein. For example, boundary 410 corresponds to the boundary of each of Cell_0, Cell_1, Cell_2, and Cell_3. Boundary 410 includes edges 411, 412, 413, and 414. Edges 411 and 412 extend along the X-axis, while edges 413 and 414 extend along the Y-axis. In some embodiments, the X-axis is an example of one of a first direction and a second direction, while the Y-axis is an example of the other of the first direction and the second direction. Edges 411, 412, 413, and 414 are interconnected to form a closed boundary 410. In the layout and routing operations described herein (also known as "Automatic Placement and Routing (APR)"), multiple instances of ROM cell 405 are placed adjacent to each other at their respective boundaries in the layout of memory device 400 or its ROM array. The rectangular or square shape of boundary 410 is merely an example.

[0060] ROM cell 405 includes active regions OD0-OD3 and gates G0-G3. Active regions OD0-OD3 are spaced apart from each other along the Y-axis. Active regions OD0-OD3 extend continuously along the X-axis within boundary 410 and also extend beyond boundary 410 into further instances of ROM cells 405 adjacent to each other along the X-axis. For example, when ROM cell 405 corresponds to Cell_0, active regions OD0-OD3 continuously pass through at least Cell_0 and Cell_1. There is no isolation structure in ROM cell 405 that divides any active regions OD0-OD3 into electrically isolated portions. Active regions are sometimes referred to as oxide-defined (OD) regions and are schematically shown in the figures with the label "OD". In the example configuration of FIG4, all active regions OD0-OD3 are N-type or NMOS active regions configured to form N-type or NMOS transistors. In at least one embodiment, each of the active regions OD0-OD3 corresponds to the active region OD described with respect to FIG3B.

[0061] Gates G0-G3 extend along the Y-axis across active regions OD0-OD3. Gates G0-G3 are spaced apart along the X-axis by the gate pitch (CPP) described herein. Each of gates G0-G3 is a conductive gate, comprising a conductive material such as polysilicon, and is schematically shown in the figure with the label "PO". Other conductive materials for the gates, such as metals, are also within the scope of various embodiments. Gates G0-G3, together with each active region OD0-OD3, are configured as a series-coupled transistor, as described with respect to FIG. 3B. All gates G0-G3 are functional gates, configured together with one of the active regions OD0-OD3 as a transistor for storing data. The transistors in ROM cell 405 correspond to transistors T1-T16 as described with respect to FIG. 5A. ROM cell 405 does not contain dummy gates that are non-conductive materials and / or do not form transistors for storing data.

[0062] ROM cell 405 also includes gate-cutting (or polysilicon-cutting) regions CPO11, CPO12, CPO21, CPO22, CPO31, and CPO32 extending along the X-axis through gates G0-G3. The gate-cutting regions are schematically shown in the figure under the label "CPO". The gate-cutting regions correspond to areas where no gate is formed.

[0063] For example, the lengths of gates G0 and G1 along the Y-axis are defined by the cut gate regions CPO11 and CPO31, which correspondingly define the opposite ends of gates G0 and G1. Cut gate regions CPO21 and CPO22 are aligned and spaced apart along the X-axis. Gates G0 and G1 extend continuously along the Y-axis through the space between cut gate regions CPO21 and CPO22.

[0064] The gate region CPO22 cuts or separates gate G2 into two physically disconnected gate portions 421 and 422, and also cuts or separates gate G3 into two physically disconnected gate portions 431 and 432. However, the physically disconnected gate portions 421 and 422 are electrically coupled to each other through, for example, word lines WL2 in layer M1, while the physically disconnected gate portions 431 and 432 are electrically coupled to each other through, for example, word lines WL3 in layer M1.

[0065] The cut gate regions CPO11 and CPO12 are aligned and spaced apart along the X-axis. In some embodiments, the centerline of the cut gate regions CPO11 and CPO12 coincides with the edge 412 of the boundary 410. The gate portions 421 and 431 of the corresponding gates G2 and G3 extend continuously along the Y-axis through the space between the cut gate regions CPO11 and CPO12, entering another ROM cell 405 instance adjacent to the ROM cell 405 along the edge 412. For example, when the ROM cell 405 corresponds to Cell_0, the gate portions 421 and 431 of the corresponding gates G2 and G3 extend continuously from Cell_0 to Cell_2. The lengths of the gate portions 421 and 431 of the corresponding gates G2 and G3 (including portions in Cell_0 and Cell_2) are the same as or substantially the same as the lengths of the gates G0 and G1.

[0066] The cut gate regions CPO31 and CPO32 are aligned and spaced apart along the X-axis. In some embodiments, the centerline of the cut gate regions CPO31 and CPO32 coincides with the edge 411 of the boundary 410. The gate portions 422 and 432 of the corresponding gates G2 and G3 extend continuously along the Y-axis through the space between the cut gate regions CPO31 and CPO32, entering another ROM cell 405 instance adjacent to the ROM cell 405 along the edge 411. For example, when the ROM cell 405 corresponds to Cell_2, the gate portions 422 and 432 of the corresponding gates G2 and G3 extend continuously from Cell_2 to Cell_0. The lengths of the gate portions 422 and 432 of the corresponding gates G2 and G3 (including portions in Cell_0 and Cell_2) are the same as or substantially the same as the lengths of the gates G0 and G1. In some embodiments, the described staggered arrangement of the cut gate regions results in gate portions having the same or substantially the same length, and / or reduces the polysilicon extension effect (PXE).

[0067] ROM cell 405 also includes MD contact structures. For simplicity, the MD contact structures on active region OD0 are designated as MD0-MD4 in FIG. 4, while the MD contact structures on active regions OD1-OD3 are not designated. In at least one embodiment, the MD contact structures on active regions OD0-OD3 correspond to the contact structures MD0-MD4 described with respect to FIG. 3B. The MD contact structures are spaced apart from each other along the X-axis by gate pitch (CPP) and alternate along the X-axis with gates G0-G3. The MD contact structures are schematically shown in the figures with the label "MD".

[0068] A first set of MD contact structures, including MD contact structure MD0 (and its underlying source / drain), is arranged along edge 413 of boundary 410 and configured to be shared with another ROM cell 405 instance adjacent to ROM cell 405 along edge 413. For example, when ROM cell 405 corresponds to Cell_0, the first set of MD contact structures along edge 413 is shared by Cell_0 and Cell_1. In other words, Cell_0 and Cell_1 are directly adjacent, with no gate or dummy gate between them. In at least one embodiment, the MD contact structures in the first set have a centerline coinciding with edge 413. A second set of MD contact structures, including MD contact structure MD4 (and its underlying source / drain), is arranged along edge 414 of boundary 410 and configured to be shared with another ROM cell 405 instance adjacent to ROM cell 405 along edge 414. In at least one embodiment, the MD contact structures in the second set have a centerline coinciding with edge 414.

[0069] In the example configuration of Figure 4, the ROM cell 405 has a width of 4 CPP along the X-axis. This width is advantageously reduced compared to 4x4 ROM cells of other methods, and can be achieved by configuring the active regions OD0-OD3 as continuous without being interrupted or broken by one or more isolation structures inside the ROM cell 405 and / or on the boundary 410. A 4x4 ROM cell according to another method includes isolation structures on the active regions extending along the Y-axis edge and has a width of 5 CPP along the X-axis. A 4x4 ROM cell according to yet another method includes isolation structures not only on the Y-axis edge but also on the active regions inside the ROM cell and has a width of 6 CPP along the X-axis. The 4-CPP 4x4 ROM cell according to one or more embodiments achieves an area reduction of approximately 16.7% compared to the described 5-CPP 4x4 ROM cell, or approximately 33.3% compared to the 6-CPP 4x4 ROM cell of other described methods. The reduced width of the ROM cell according to some embodiments further advantageously reduces the bit line length of various bit lines, as described herein.

[0070] ROM cell 405 also includes vias VG0-VG3 to the gates, which are located above and electrically connected to the corresponding gates G0-G3, respectively. The vias to the gates are schematically represented by the symbol "VG" in the figure.

[0071] ROM cell 405 also includes M0 conductive patterns 441-455 in the M0 layer. M0 conductive patterns 442, 447, 449, and 454 are configured as multiple bit lines BL0-BL3, while M0 conductive patterns 443, 446, 450, and 453 are configured as multiple VSS power rails. The bit lines BL0-BL3 and the VSS power rails extend continuously along the X-axis through multiple adjacent ROM cell 405 instances. Each pair of bit lines and the corresponding VSS power rail extends above the corresponding active region. For example, bit line BL0 and the corresponding VSS power rail (M0 conductive pattern 443) extend above the active region OD0.

[0072] M0 conductive patterns 452, 445, 451, and 444 are configured as character line patterns. Character line patterns 444 and 445 are aligned along the X-axis and arranged on the same M0 track. Character line patterns 451 and 452 are aligned along the X-axis and arranged on the same M0 track. Character line patterns 452, 445, 451, and 444 are located above and electrically contacted with VG vias VG0-VG3, respectively, thereby electrically coupling with gates G0-G3. Character line patterns 452, 445, 451, and 444 are electrically coupled to the corresponding character lines WL0-WL3 (not shown) in the M1 layer through the corresponding V0 vias (not shown), in a manner similar to that described with respect to Figure 3C. In the example of ROM cell 405 corresponding to Cell_0, the word line WL0 in layer M1 extends continuously along the Y-axis above the similar word line patterns in word line patterns 452 and Cell_2, and is electrically coupled to the similar word line patterns in word line patterns 452 and Cell_2 through the corresponding V0 vias. Therefore, all transistors configured by gate G0 in Cell_0 and Cell_2 are electrically coupled to the word line WL0.

[0073] In the example configuration of Figure 4, ROM cell 405 does not yet include via-to-device (VD) vias located above and electrically contacting one or more MD contact structures. This is because, according to some embodiments, ROM cell 405 is a blank or unprogrammed ROM cell. In some embodiments, during the design phase, a blank or unprogrammed ROM array corresponding to memory array 101 is developed by arranging (e.g., in APR operation) multiple mutually adjacent instances of ROM cell 405 (as shown in Figure 4, Cell_0, Cell_1, Cell_2, Cell_3). In a subsequent programming phase, the unprogrammed ROM array is programmed by creating a set of VD vias to configure each individual bit cell in the ROM array to store logic "0" or logic "1" according to predetermined data to be stored in the ROM array, as described with respect to Figures 2A-2G and 3A-3C. Specific, non-limiting examples of ROM programming are further described with respect to Figures 5A-5E and 6A-6F.

[0074] Figures 5A-5E each include schematic circuit diagrams and layout views of circuit regions of a memory device according to some embodiments. Figures 5A-5E show non-limiting examples of ROM programming using code mode 1, i.e., using the configuration described with respect to Figures 2A-2D, but not the configuration described with respect to Figures 2E-2G. For simplicity, corresponding components in Figures 1, 2A-2G, 3A-3C, 4, and 5A-5E are designated by the same reference numerals.

[0075] Figure 5A includes a schematic circuit diagram of circuit region 500A and a schematic layout view of ROM cell 505A corresponding to circuit region 500A. ROM cell 505A is a programmed example of unprogrammed ROM cell 405. ROM cell 505A includes transistors T1-T16, wherein transistors T1, T5, T9, and T13 are configured with gates G0-G3 and active region OD0, respectively; transistors T2, T6, T10, and T14 are configured with gates G0-G3 and active region OD1, respectively; transistors T3, T7, T11, and T15 are configured with gates G0-G3 and active region OD2, respectively; and transistors T4, T8, T12, and T16 are configured with gates G0-G3 and active region OD3, respectively.

[0076] ROM cell 505A is programmed to store data or program code 501 in transistors T1, T5, T9, and T13; data or program code 502 in transistors T2, T6, T10, and T14; data or program code 503 in transistors T3, T7, T11, and T15; and data or program code 504 in transistors T4, T8, T12, and T16. In each program code 501-504, "0" represents logic "0" and "1" represents logic "1". For example, program code 501 is "0000", corresponding to all transistors T1, T5, T9, and T13 storing logic "0". As another example, program code 503 is "0010", corresponding to transistor T3 storing logic "0", transistor T7 storing logic "0", transistor T11 storing logic "1", and transistor T15 storing logic "0". Compared to ROM cell 405, ROM cell 505A also includes VD vias, each of which electrically couples the source / drain of the active regions OD0-OD3 to the corresponding bit line or power rail above the active region according to the data of the program codes 501-504 to be stored. VD vias 550-554 are shown in Figure 5A, while other VD vias are not shown for simplicity. In some embodiments, each of the program codes 501-504 is programmed into ROM cell 505A independently of the other program codes. In one example of a ROM programming operation, one of the program codes 501-504 is programmed sequentially, for example, from left to right or from right to left. For example, program code 501 is programmed sequentially from right to left, starting with transistor T13.

[0077] Transistor T13 is programmed to store logic "0", corresponding to OFF configuration 0f in FIG2C or OFF configuration 0i in FIG2D, according to code mode 1. In at least one embodiment, the selection between OFF configuration 0f and OFF configuration 0i depends on another transistor (not shown) located on bit line BL0, which is directly adjacent to the right side of transistor T13 and shares a common source / drain with transistor T13 (below the MD contact structure MD4). This other transistor has been programmed prior to transistor T13. If the programmed other transistor is coupled to the common source / drain shared by transistor T13 to the VSS power rail, transistor T13 is selected as OFF configuration 0f. If the programmed other transistor is coupled to bit line BL0 with the common source / drain shared by transistor T13, transistor T13 is selected as OFF configuration 0i. In the example configuration of FIG5A, transistor T13 is programmed with OFF configuration 0f. For this purpose, vias 553 and 554 are created (e.g., by an EDA tool performing an APR operation) to correspondingly couple the two source / drain terminals of transistor T13 to the VSS power rail 443 in ROM cell 505A. In at least one embodiment, via 554 is created when another transistor to the right of transistor T13 is programmed, while via 553 is created when transistor T13 is programmed.

[0078] Next, transistor T9 is programmed to store logic "0". Since the common source / drain of transistors T9 and T13 (below the MD contact structure MD3) is already coupled to the VSS power rail 443 via VD via 553, the OFF configuration OFF is selected for programming transistor T9. For this purpose, VD via 552 is created to couple the other source / drain of transistor T9 (below the MD contact structure MD2) to the VSS power rail 443. Similarly, transistor T5 is programmed to store logic "0" by coupling the MD contact structure MD1 to the VSS power rail 443 via VD via 551, and transistor T1 is programmed to store logic "0" by coupling the MD contact structure MD0 to the VSS power rail 443 via VD via 550.

[0079] Programming code 502, i.e., "0000", is programmed into transistors T2, T6, T10, and T14, starting with transistor T14, which is programmed with OFF configuration 0i. As a result, both source / drain terminals of transistor T14 are coupled to bit line BL1. Because the common source / drain terminals of transistors T10 and T14 are coupled to bit line BL1 when transistor T14 is programmed, the other source / drain terminal of transistor T10 is also coupled to bit line BL1 to program logic "0" into transistor T10 according to OFF configuration 0i. Similarly, based on the programming configuration of transistor T10, transistor T6 is programmed with OFF configuration 0i, and then based on the programming configuration of transistor T6, transistor T2 is programmed with OFF configuration 0i. The APR tool is configured to generate a set of VD vias (unnumbered) corresponding to the OFF configuration 0i at all transistors T2, T6, T10, and T14, as shown in ROM cell 505A.

[0080] Programming code 503, i.e., "0010", is programmed into transistors T3, T7, T11, and T15, starting with transistor T15, which is programmed to have the OFF configuration 0i. As a result, both source / drain terminals of transistor T15 are coupled to bit line BL2. Because when transistor T15 is programmed, the common source / drain terminal of transistors T11 and T15 is coupled to bit line BL2, the other source / drain terminal of transistor T11 is coupled to the VSS power rail to program logic "1" into transistor T11 according to the ON configuration 1g in Figure 2A. Because when transistor T11 is programmed, the common source / drain terminal of transistors T7 and T11 is coupled to the VSS power rail, the other source / drain terminal of transistor T7 is also coupled to the VSS power rail to program logic "0" into transistor T7 according to the OFF configuration 0f. Similarly, based on the programming configuration of transistor T7, transistor T3 is programmed to have an OFF configuration 0f. The APR tool is configured to generate a set of VD vias (unnumbered) corresponding to the programming configurations of transistors T3, T7, T11, and T15, as shown in ROM cell 505A.

[0081] Programming code 504, i.e., "0010", is programmed into transistors T4, T8, T12, and T16, starting with transistor T16, which is programmed with the OFF configuration 0f. As a result, both source / drain terminals of transistor T16 are coupled to the VSS power rail. Because when transistor T16 is programmed, the common source / drain terminal of transistors T12 and T16 is coupled to the VSS power rail, the other source / drain terminal of transistor T12 is coupled to bit line BL3 to program logic "1" into transistor T12 according to the ON configuration 1h in Figure 2B. Because when transistor T12 is programmed, the common source / drain terminal of transistors T8 and T12 is coupled to bit line BL3, the other source / drain terminal of transistor T8 is also coupled to bit line BL3 to program logic "0" into transistor T8 according to the OFF configuration 0i. Similarly, based on the programming configuration of transistor T8, transistor T4 is programmed to have OFF configuration 0i. The APR tool is configured to generate a set of VD vias (unnumbered) corresponding to the programming configurations of transistors T4, T8, T12, and T16, as shown in ROM cell 505A.

[0082] In Figure 5A, the programming configurations of transistors T1, T5, T9, and T13 include an example of programming data "0000" by configuring all transistors T1, T5, T9, and T13 with OFF configuration OFF, while the programming configurations of transistors T2, T6, T10, and T14 include another example of programming the same data "0000" by configuring all transistors T2, T6, T10, and T14 with OFF configuration OFF 0i. In at least one embodiment, group programming is performed to program multiple transistors simultaneously, rather than programming one transistor at a time. For example, two configurations (e.g., two sets of VD vias) are pre-developed and stored, for example, in a library, for use with data "0000". One of the pre-developed configurations corresponds to the programming configuration of transistors T1, T5, T9, and T13 in Figure 5A (e.g., VD via groups 550-554), while the other pre-developed configuration corresponds to the programming configuration of transistors T2, T6, T10, and T14 in Figure 5A (e.g., the corresponding VD via groups). When the data "0000" is to be programmed into a group or a string of four transistors, one of the pre-developed configurations is selected and used to program the four transistor strings simultaneously. The selection of the pre-developed configuration to be used is based on the previously programmed directly adjacent transistors, in a manner similar to that described regarding the programming of transistor T13.

[0083] Similarly, the programming configurations for transistors T3, T7, T11, and T15 include an example of programming data "0010," while the programming configurations for transistors T4, T8, T12, and T16 include another example of programming the same data "0010." In at least one embodiment, for group programming, two configurations (e.g., two sets of VD vias), for example, in a library, are pre-developed and stored for data "0010." One of the pre-developed configurations corresponds to the programming configurations for transistors T3, T7, T11, and T15 in FIG. 5A, while the other pre-developed configuration corresponds to the programming configurations for transistors T4, T8, T12, and T16 in FIG. 5A. When data "0010" is to be programmed into a group or a string of four transistors, one of the pre-developed configurations is selected and used to program the four transistor strings simultaneously. The selection of the pre-developed configuration to be used is based on the previously programmed directly adjacent transistors, in a manner similar to that described with respect to the programming of transistor T13. The example of group programming with four transistors described is merely illustrative. According to some embodiments, any other number of transistors can be used for group programming.

[0084] Figure 5B includes a schematic circuit diagram of circuit region 500B and a layout diagram corresponding to circuit region 500B. This layout includes a portion of ROM cells 505A and 505B. Similar to ROM cell 505A, ROM cell 505B is a programmed instance of an unprogrammed ROM cell 405.

[0085] ROM cell 505B has a boundary 510 corresponding to boundary 410. ROM cell 505B is placed adjacent to ROM cell 505A along the common edge of boundary 510 and boundary 410. This common edge is edge 413 of boundary 410. ROM cells 505A and ROM cell 505B share a common set of MD contact structures, including MD contact structure MD0, disposed on edge 413. In other words, ROM cells 505A and ROM cell 505B share a common source / drain located below this set of common MD contact structures.

[0086] ROM cell 505B includes 16 transistors arranged in a 4x4 pattern. Transistors T17-T20 of ROM cell 505B are illustrated in FIG. 5B, while other transistors are omitted for simplicity. Transistors T17-T20 of ROM cell 505B correspond to transistors T13-T16 of ROM cell 505A. Transistors T17-T20 of ROM cell 505B and transistors T1-T4 of ROM cell 505A are directly adjacent to each other and share a common source / drain set on edge 413. Transistors T17-T20 are correspondingly configured by active regions OD0-OD3 with gate GK. In some embodiments, gate GK in FIG. 5B corresponds to gate GK described with respect to FIG. 3B. In an example embodiment, ROM cell 505A corresponds to Cell_0 in FIG. 4, while ROM cell 505B corresponds to Cell_1 in FIG. 4. The active regions OD0-OD3, bit lines BL0-BL3, and VSS power rails 443, 446, 450, and 453 continuously pass through ROM cells 505A and ROM cells 505B along the X-axis.

[0087] ROM cell 505B is programmed to store code 506-509. For simplicity, the data to be stored by transistors T17-T20 is shown in Figure 5B as code 506-509, while the data to be stored by other transistors in ROM cell 505B is omitted. The logic "0" in code 506 is programmed into transistor T17 based on the programming configuration of transistor T1, or based on the electrical connection of the common source / drain of transistor T1 and the directly adjacent transistor T17. Because when transistor T1 is programmed, the common source / drain of transistor T1 and transistor T17 is coupled to VSS power rail 443 through via VD 550, and the other source / drain of transistor T17 is also coupled to VSS power rail 443, the logic "0" is programmed into transistor T17 according to the OFF configuration OFF. For this purpose, the APR tool was configured to generate a VD via 55K to electrically couple the MD contact structure MDK located above another source / drain of transistor T17 to the VSS power rail 443.

[0088] Similarly, transistor T18 is programmed with OFF configuration 0i based on the programming configuration of transistor T2, while transistor T19 is programmed with OFF configuration 0f based on the programming configuration of transistor T3. The APR tool is configured to generate corresponding VD vias corresponding to the programming configurations of transistors T18 and T19, as shown in ROM cell 505B.

[0089] The logic "1" in code 509 is programmed into transistor T20 based on the programming configuration of transistor T4. Because when transistor T4 is programmed, the common source / drain of transistors T4 and T20 is coupled to bit line BL3, and the other source / drain of transistor T20 is coupled to VSS power rail 453, the logic "1" is programmed into transistor T20 according to ON configuration 1g. For this purpose, the APR tool is configured to generate a VD via 559, electrically connecting the MD contact structure 558 located above the other source / drain of transistor T20 to VSS power rail 453. In some embodiments, the group programming described with respect to FIG. 5A is performed for ROM cell 505B and / or other ROM cells in the ROM array.

[0090] Figure 5C includes a schematic circuit diagram of circuit region 500C and a schematic layout view of ROM cell 505C corresponding to circuit region 500C. ROM cell 505C is a programmed example of an unprogrammed ROM cell 405.

[0091] Program codes 581-584 are programmed into transistors T1-T16 of ROM cell 505C in a manner similar to that described with respect to Figures 5A-5B. For example, to store program code 581, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to correspondingly have OFF configuration 0i, OFF configuration 0i, ON configuration 1g, and OFF configuration 0f. The APR tool is configured to generate a set of VD vias 564, 563, 562, 551, and 550 to correspond to the programming configurations of transistors T13, T9, T5, and T1, as shown in ROM cell 505C.

[0092] In Figure 5C, the programming configurations of transistors T1, T5, T9, and T13 include an example of programming data "0100", while the programming configurations of transistors T2, T6, T10, and T14 include another example of programming the same data "0100". In at least one embodiment, the programming configurations of transistors T1, T5, T9, and T13 (or the set of VD vias 550, 551, 562, 563, and 564) and the programming configurations of transistors T2, T6, T10, and T14 (or the corresponding set of VD vias) are pre-developed and stored (e.g., in a library) for group programming of data "0100" as described herein.

[0093] Similarly, the programming configurations of transistors T3, T7, T11, and T15 include examples of programming data "0110", while the programming configurations of transistors T4, T8, T12, and T16 include another example of programming the same data "0110". In at least one embodiment, the programming configurations (or corresponding VD via sets) of transistors T3, T7, T11, and T15 and the programming configurations (or corresponding VD via sets) of transistors T4, T8, T12, and T16 are pre-developed and stored (e.g., in a library) for group programming of data "0110" as described herein.

[0094] Figure 5D includes a schematic circuit diagram of circuit region 500D and a schematic layout view of ROM cell 505D corresponding to circuit region 500D. ROM cell 505D is a programmed example of an unprogrammed ROM cell 405.

[0095] Program codes 586-589 are programmed into transistors T1-T16 of ROM cell 505D in a manner similar to that described with respect to Figures 5A-5B. For example, to store program code 586, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to correspondingly have OFF configuration 0i, OFF configuration 0i, OFF configuration 0i, and ON configuration 1g. The APR tool is configured to generate a set of VD vias 564, 563, 562, 571, and 550 corresponding to the programming configurations of transistors T13, T9, T5, and T1, as shown in ROM cell 505D.

[0096] In Figure 5D, the programming configurations of transistors T1, T5, T9, and T13 include an example of programming data "1000", while the programming configurations of transistors T2, T6, T10, and T14 include another example of programming the same data "1000". In at least one embodiment, the programming configurations of transistors T1, T5, T9, and T13 (or the set of VD vias 550, 571, 562, 563, and 564) and the programming configurations of transistors T2, T6, T10, and T14 (or the corresponding set of VD vias) are pre-developed and stored (e.g., in a library) for group programming of data "1000" as described herein.

[0097] Similarly, the programming configurations of transistors T3, T7, T11, and T15 include examples of programming data "1010", while the programming configurations of transistors T4, T8, T12, and T16 include another example of programming the same data "1010". In at least one embodiment, the programming configurations (or corresponding VD via sets) of transistors T3, T7, T11, and T15 and the programming configurations (or corresponding VD via sets) of transistors T4, T8, T12, and T16 are pre-developed and stored (e.g., in a library) for group programming of data "1010" as described herein.

[0098] Figure 5E includes a schematic circuit diagram of circuit region 500E and a schematic layout view of ROM cell 505E corresponding to circuit region 500E. ROM cell 505E is a programmed example of an unprogrammed ROM cell 405.

[0099] Program codes 591-594 are programmed into transistors T1-T16 of ROM cell 505E in a manner similar to that described with respect to Figures 5A-5B. For example, to store program code 591, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to correspondingly have OFF configuration OFF, OFF configuration OFF, ON configuration 1h, and ON configuration 1g. The APR tool is configured to generate a set of VD vias 554, 553, 552, 571, and 550 to correspond to the programming configurations of transistors T13, T9, T5, and T1, as shown in ROM cell 505E.

[0100] In Figure 5E, the programming configurations of transistors T1, T5, T9, and T13 include an example of programming data "1100", while the programming configurations of transistors T2, T6, T10, and T14 include another example of programming the same data "1100". In at least one embodiment, the programming configurations of transistors T1, T5, T9, and T13 (or the set of VD vias 550, 571, 552, 553, and 554) and the programming configurations of transistors T2, T6, T10, and T14 (or the corresponding set of VD vias) are pre-developed and stored (e.g., in a library) for group programming of data "1100" as described herein.

[0101] Similarly, the programming configurations of transistors T3, T7, T11, and T15 include examples of programming data "1110", while the programming configurations of transistors T4, T8, T12, and T16 include another example of programming the same data "1110". In at least one embodiment, the programming configurations (or corresponding VD via sets) of transistors T3, T7, T11, and T15 and the programming configurations (or corresponding VD via sets) of transistors T4, T8, T12, and T16 are pre-developed and stored (e.g., in a library) for group programming of data "1110" as described herein.

[0102] Figures 6A-6F each include schematic circuit diagrams and layout views of the circuit regions of a memory device according to some embodiments. Figures 6A-6F show a non-limiting example of ROM programming using code mode 2, i.e., using the configuration described with respect to Figures 2A-2G. For the sake of brevity, corresponding components in Figures 1, 2A-2G, 3A-3C, 4, 5A-5E, and 6A-6F are designated by the same reference numerals.

[0103] Figure 6A includes a schematic circuit diagram of circuit region 600A and a schematic layout view of ROM cell 605A corresponding to circuit region 600A. ROM cell 605A is a programmed example of an unprogrammed ROM cell 405.

[0104] Program codes 601-604 are programmed into transistors T1-T16 of ROM cell 605A in a manner similar to that described with respect to Figures 5A-5B. For example, to store program code 601, transistors T13, T9, T5, and T1 are programmed sequentially from right to left so that all have the OFF configuration 0a shown in Figure 2E. Because all sources / drains of transistors T1, T5, T9, and T13 are electrically floating, the APR tool is configured to generate a set of five "nil" VD vias (i.e., no VD vias) for the five corresponding MD contact structures MD0-MD4 according to the programming configuration of transistors T1, T5, T9, and T13, as shown in ROM cell 605A.

[0105] To store code 602, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2G, and OFF configuration 0i, respectively. The APR tool is configured to generate a set of VD vias for the three corresponding MD contact structures based on the programming configurations of transistors T2, T6, T10, and T14. These vias include VD vias 606 and 607 and three "zero" VD vias, i.e., no VD vias, as shown in ROM cell 605A.

[0106] To store code 603, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2F, OFF configuration 0a in Figure 2F, and OFF configuration 0f, respectively. The APR tool is configured to generate a set of VD vias for the three corresponding MD contact structures based on the programming configurations of transistors T3, T7, T11, and T15. These vias include VD vias 608 and 609 and three "zero" VD vias, i.e., no VD vias, as shown in ROM cell 605A.

[0107] Program code 604 is programmed into transistors T4, T8, T12, and T16 in the same manner as transistors T1, T5, T9, and T13.

[0108] In Figure 6A, the programming configurations of transistors T1, T5, T9, and T13 include a first example of programming data "0000"; the programming configurations of transistors T2, T6, T10, and T14 include a second example of programming the same data "0000"; and the programming configurations of transistors T3, T7, T11, and T15 include a third example of programming the same data "0000". Other examples of programming the same data "0000" are also within the scope of various embodiments, depending on the various OFF configurations described with respect to Figures 2C-2G and the configurations available according to code mode 2. In at least one embodiment, the programming configurations of transistors T1, T5, T9, and T13, the programming configurations of transistors T2, T6, T10, and T14, the programming configurations of transistors T3, T7, T11, and T15, and / or one or more further examples of programming data "0000" are pre-developed and stored (e.g., in a library) for group programming of data "0000" as described herein.

[0109] In some embodiments, code mode 2 provides more options for programming the same data or code compared to code mode 1, which advantageously increases the flexibility of circuit design. In at least one embodiment, code mode 2 sometimes requires fewer VD vias than code mode 1 to program the same data or code, which advantageously reduces the need for wiring resources and / or reduces parasitic capacitance, thereby improving performance.

[0110] Figure 6B includes a schematic circuit diagram of circuit region 600B and a schematic view of the layout of ROM cell 605B corresponding to circuit region 600B. ROM cell 605B is a programmed example of an unprogrammed ROM cell 405.

[0111] Program codes 611-614 are programmed into transistors T1-T16 of ROM cell 605B in a manner similar to that described with respect to Figures 5A-5B. For example, program code 611 is programmed into transistors T1, T5, T9, and T13 in the same manner as program code 601 described with respect to Figure 6A.

[0112] To store code 612, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1h, OFF configuration 0i, and OFF configuration 0i as shown in Figure 2F, respectively. The APR tool is configured to generate a set of VD vias, including four VD vias and one "zero" VD via, as shown in ROM cell 605B, based on the programming configurations of transistors T2, T6, T10, and T14.

[0113] To store code 613, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1g, OFF configuration 0f, and OFF configuration 0f as shown in Figure 2G, respectively. The APR tool is configured to generate a set of VD vias, including four VD vias and one "zero" VD via, as shown in ROM cell 605B, based on the programming configurations of transistors T3, T7, T11, and T15.

[0114] To store program code 614, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1g (Figure 2G), OFF configuration 0a (Figure 2F), and OFF configuration 0a (Figure 2E), respectively. The APR tool is configured to generate a set of VD vias based on the programming configurations of transistors T4, T8, T12, and T16, including two "zero" VD vias, two VD vias, and another "zero" VD via, as shown in ROM cell 605B.

[0115] In Figure 6B, the programming configurations of transistors T2, T6, T10, and T14 include a first example of programming data "0010," the programming configurations of transistors T3, T7, T11, and T15 include a second example of programming the same data "0010," and the programming configurations of transistors T4, T8, T12, and T16 include a third example of programming the same data "0010." Other examples of programming the same data "0010" are also within the scope of various embodiments. In at least one embodiment, the programming configurations of transistors T2, T6, T10, and T14, the programming configurations of transistors T3, T7, T11, and T15, the programming configurations of transistors T4, T8, T12, and T16, and / or further examples of one or more programming data "0010" are pre-developed and stored (e.g., in a library) for group programming of data "0010," as described herein.

[0116] Figure 6C includes a schematic circuit diagram of circuit region 600C and a schematic view of the layout of ROM cell 605C corresponding to circuit region 600C. ROM cell 605C is a programmed example of an unprogrammed ROM cell 405.

[0117] Program codes 621-624 are programmed into transistors T1-T16 of ROM cell 605C in a manner similar to that described in Figures 5A-5B. For example, program code 621 is programmed into transistors T1, T5, T9, and T13 in the same manner as program code 601 described with respect to Figure 6A.

[0118] To store code 622, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2F, ON configuration 1h, and OFF configuration 0i, respectively. The APR tool is configured to generate a set of VD vias, including three VD vias and two "zero" VD vias, as shown in ROM cell 605C, based on the programming configurations of transistors T2, T6, T10, and T14.

[0119] To store code 623, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2G, ON configuration 1g, and OFF configuration 0f, respectively. The APR tool is configured to generate a set of VD vias, including three VD vias and two "zero" VD vias, as shown in ROM cell 605C, based on the programming configurations of transistors T3, T7, T11, and T15.

[0120] To store code 624, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2G, ON configuration 1g, and OFF configuration 0a in Figure 2F, respectively. The APR tool is configured to generate a set of VD vias based on the programming configurations of transistors T4, T8, T12, and T16, including one "zero" VD via, two VD vias, and two further "zero" VD vias, as shown in ROM cell 605C.

[0121] In Figure 6C, the programming configurations of transistors T2, T6, T10, and T14 include a first example of programming data "0100"; the programming configurations of transistors T3, T7, T11, and T15 include a second example of programming the same data "0100"; and the programming configurations of transistors T4, T8, T12, and T16 include a third example of programming the same data "0100". Other examples of programming the same data "0100" are also within the scope of various embodiments. In at least one embodiment, the programming configurations of transistors T2, T6, T10, and T14, the programming configurations of transistors T3, T7, T11, and T15, the programming configurations of transistors T4, T8, T12, and T16, and / or one or more further examples of programming data "0100" are pre-developed and stored (e.g., in a library) for group programming of data "0100", as described herein.

[0122] Figure 6D includes a schematic circuit diagram of circuit region 600D and a schematic view of the layout of ROM cell 605D corresponding to circuit region 600D. ROM cell 605D is a programmed example of an unprogrammed ROM cell 405.

[0123] Program codes 631-634 are programmed into transistors T1-T16 of ROM cell 605D in a manner similar to that described in Figures 5A-5B. For example, program code 631 is programmed into transistors T1, T5, T9, and T13 in the same manner as program code 601 described with respect to Figure 6A.

[0124] To store code 632, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1g, ON configuration 1h, and OFF configuration 0i as shown in Figure 2G. The APR tool is configured to generate a set of VD vias, including four VD vias and one "zero" VD via, as shown in ROM cell 605D, based on the programming configurations of transistors T2, T6, T10, and T14.

[0125] To store code 633, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1h, ON configuration 1g, and OFF configuration 0f as shown in Figure 2F. The APR tool is configured to generate a set of VD vias, including four VD vias and one "zero" VD via, as shown in ROM cell 605D, based on the programming configurations of transistors T3, T7, T11, and T15.

[0126] To store code 634, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1h, ON configuration 1g, and OFF configuration 0a in Figure 2F, respectively. The APR tool is configured to generate a set of VD vias based on the programming configurations of transistors T4, T8, T12, and T16, including one "zero" VD via, three VD vias, and one further "zero" VD via, as shown in ROM cell 605D.

[0127] In Figure 6D, the programming configurations of transistors T2, T6, T10, and T14 include a first example of programming data "0110"; the programming configurations of transistors T3, T7, T11, and T15 include a second example of programming the same data "0110"; and the programming configurations of transistors T4, T8, T12, and T16 include a third example of programming the same data "0110". Other examples of programming the same data "0110" are also within the scope of various embodiments. In at least one embodiment, the programming configurations of transistors T2, T6, T10, and T14, the programming configurations of transistors T3, T7, T11, and T15, the programming configurations of transistors T4, T8, T12, and T16, and / or further examples of one or more programming data "0110" are pre-developed and stored (e.g., in a library) for group programming of the data "0110" described herein.

[0128] Figure 6E includes a schematic circuit diagram of circuit region 600E and a schematic view of the layout of ROM cell 605E corresponding to circuit region 600E. ROM cell 605E is a programmed example of an unprogrammed ROM cell 405.

[0129] Program codes 641-644 are programmed into transistors T1-T16 of ROM cell 605E in a manner similar to that described in Figures 5A-5B. For example, to store program code 641, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2G, and ON configuration 1g, respectively. The APR tool is configured to generate a set of VD vias, including two VD vias and three "zero" VD vias, as shown in ROM cell 605E, based on the programming configuration of transistors T1, T5, T9, and T13.

[0130] To store program code 642, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2F, and ON configuration 1h, respectively. The APR tool is configured to generate a set of VD vias, including two VD vias and three "zero" VD vias, as shown in ROM cell 605E, based on the programming configurations of transistors T2, T6, T10, and T14.

[0131] The programming configurations of transistors T1, T5, T9, and T13 include a first example of programming data "1000", while the programming configurations of transistors T2, T6, T10, and T14 include a second example of programming the same data "1000". Other examples of programming the same data "1000" are also within the scope of various embodiments. In at least one embodiment, the programming configurations of transistors T1, T5, T9, and T13, the programming configurations of transistors T2, T6, T10, and T14, and / or further examples of one or more programming data "1000" are pre-developed and stored (e.g., in a library) for group programming of the data "1000" described herein.

[0132] To store code 643, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1h, OFF configuration 0i, and ON configuration 1g as shown in Figure 2F, respectively. The APR tool is configured to generate a set of VD vias, including four VD vias and one "zero" VD via, as shown in ROM cell 605E, based on the programming configurations of transistors T3, T7, T11, and T15.

[0133] To store code 644, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1g, OFF configuration 0f, and ON configuration 1h as shown in Figure 2F. The APR tool is configured to generate a set of VD vias, including four VD vias and one "zero" VD via, as shown in ROM cell 605E, based on the programming configurations of transistors T4, T8, T12, and T16.

[0134] The programming configurations of transistors T3, T7, T11, and T15 include a first example of programming data "1010," while the programming configurations of transistors T4, T8, T12, and T16 include a second example of programming the same data "1010." Other examples of programming the same data "1010" are also within the scope of various embodiments. In at least one embodiment, the programming configurations of transistors T3, T7, T11, and T15, the programming configurations of transistors T4, T8, T12, and T16, and / or further examples of one or more programming data "1010" are pre-developed and stored (e.g., in a library) for group programming of the data "1010" described herein.

[0135] Figure 6F includes a schematic circuit diagram of circuit region 600F and a schematic view of the layout of ROM cell 605F corresponding to circuit region 600F. ROM cell 605F is a programmed example of an unprogrammed ROM cell 405.

[0136] Program codes 651-654 are programmed into transistors T1-T16 of ROM cell 605F in a manner similar to that described in Figures 5A-5B. For example, to store program code 651, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2F, ON configuration 1h, and ON configuration 1g, respectively. The APR tool is configured to generate a set of VD vias, including three VD vias and two "zero" VD vias, as shown in ROM cell 605F, based on the programming configuration of transistors T1, T5, T9, and T13.

[0137] To store program code 652, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have OFF configuration 0a in Figure 2E, OFF configuration 0a in Figure 2G, ON configuration 1g, and ON configuration 1h, respectively. The APR tool is configured to generate a set of VD vias, including three VD vias and two "zero" VD vias, as shown in ROM cell 605F, based on the programming configurations of transistors T2, T6, T10, and T14.

[0138] The programming configurations of transistors T1, T5, T9, and T13 include a first example of programming data "1100", while the programming configurations of transistors T2, T6, T10, and T14 include a second example of programming the same data "1100". Other examples of programming the same data "1100" are also within the scope of various embodiments. In at least one embodiment, the programming configurations of transistors T1, T5, T9, and T13, the programming configurations of transistors T2, T6, T10, and T14, and / or further examples of one or more programming data "1100" are pre-developed and stored (e.g., in a library) for group programming of the data "1100" described herein.

[0139] To store program code 653, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1g, ON configuration 1h, and ON configuration 1g, respectively, as shown in Figure 2G. The APR tool is configured to generate a set of VD vias, including four VD vias and one "zero" VD via, as shown in ROM cell 605F, based on the programming configurations of transistors T3, T7, T11, and T15.

[0140] To store code 654, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have OFF configuration 0a, ON configuration 1h, ON configuration 1g, and ON configuration 1h as shown in Figure 2F. The APR tool is configured to generate a set of VD vias, including four VD vias and one "zero" VD via, as shown in ROM cell 605F, based on the programming configurations of transistors T4, T8, T12, and T16.

[0141] The programming configurations of transistors T3, T7, T11, and T15 include a first example of programming data "1110", while the programming configurations of transistors T4, T8, T12, and T16 include a second example of programming the same data "1110". Other examples of programming the same data "1110" are also within the scope of various embodiments. In at least one embodiment, the programming configurations of transistors T3, T7, T11, and T15, the programming configurations of transistors T4, T8, T12, and T16, and / or further examples of one or more programming data "1110" are pre-developed and stored (e.g., in a library) for group programming of the data "1110" described herein.

[0142] Figure 7A is a flowchart of a method 700A for generating a layout and manufacturing an IC device using that layout, according to some embodiments. According to some embodiments, method 700A can be implemented, for example, using the EDA system and / or integrated circuit (IC) manufacturing system described herein. Examples of layouts for method 700A include the layouts disclosed herein, or similar layouts. Examples of IC devices manufactured according to method 700A include one or more memory devices, such as ROM devices, disclosed herein. Method 700A includes operations 702, 704.

[0143] In operation 702, a layout is generated, including at least one ROM cell having at least one active region continuously extending through the ROM cell, as described herein. An example of operation 702 is described with reference to Figures 7B-7C.

[0144] In operation 704, based on the layout, at least one of the following operations is performed: (A) performing one or more photolithography exposures; or (B) fabricating one or more semiconductor masks; or (C) fabricating one or more components in the IC device layer. An example of operation 704 is described with reference to FIG7D.

[0145] Figure 7B is a flowchart of a method 700B for generating a layout of a read-only memory (ROM) cell. Method 700B is executed at least in part by a processor. In some embodiments, method 700B is executed to generate a ROM cell corresponding to ROM cell 405. Method 700B includes operations 710, 712, 714, 716, 718, and 720.

[0146] In operation 710, multiple active regions and multiple gates are disposed within the boundary of the ROM cell, wherein the multiple active regions extend continuously from within the boundary through the boundary to outside the boundary. For example, as shown in FIG4, multiple active regions OD0-OD3 and multiple gates G0-G3 are disposed within the boundary 410 of the ROM cell 405. The active regions OD0-OD3 extend continuously from within the boundary 410 through the boundary 410 to outside the boundary 410.

[0147] In operation 712, multiple contact structures are disposed over multiple active regions, wherein the multiple contact structures include at least one set of contact structures located on the edge of a boundary. For example, as shown in FIG4, multiple MD contact structures are disposed over active regions OD0-OD3. The multiple MD contact structures include at least one set of MD contact structures located on the edge of boundary 410 (e.g., edge 413 or edge 414).

[0148] In operation 714, multiple first through holes are disposed on multiple gates. For example, as shown in Figure 4, multiple VG through holes VG0-VG3 are correspondingly disposed on multiple gates G0-G3.

[0149] In operation 716, a pair of bit lines and power rails are disposed in the metal layer and above each active region. For example, as shown in FIG4, in the M0 layer, a pair of bit lines BL0 and VSS power rails 443 are disposed above active region OD0, and a pair of bit lines BL1 and VSS power rails 446 are disposed above active region OD1, or similarly.

[0150] In operation 718, multiple character line patterns overlapping with multiple first vias are disposed in the metal layer and between adjacent active regions in the multiple active regions. For example, as shown in FIG4, in the M0 layer, character line patterns 444 and 445 are disposed between adjacent active regions OD0 and OD1 to overlap with VG vias VG3 and VG1 respectively, and character line patterns 451 and 452 are disposed between adjacent active regions OD2 and OD3 to overlap with VG vias VG2 and VG0 respectively.

[0151] In operation 720, the layout of the obtained ROM cells is stored in a library or on a non-transitory computer-readable recording medium, for example, for later retrieval and use in generating a ROM array, as shown in FIG7C. In some embodiments, the stored ROM cells 405 do not contain VD vias, which will be added later in the ROM programming operations described herein. According to some embodiments, the ROM cells generated by method 700B may achieve one or more of the advantages described herein.

[0152] Figure 7C is a flowchart of a method 700C for generating a layout of a read-only memory (ROM) device. Method 700C is executed at least in part by a processor. In some embodiments, method 700C is executed to generate a ROM device layout corresponding to one or more memory devices and / or ROM devices described herein. Method 700C includes operations 730, 732, and 734.

[0153] In operation 730, multiple instances of ROM cells are repeatedly placed adjacent to each other to obtain a layout of the ROM device. A ROM cell includes an active region that extends continuously from one edge of the ROM cell to the opposite edge of the ROM cell without being interrupted or discontinuous by an isolation structure. For example, as shown in FIG4, multiple instances of ROM cells 405 (e.g., Cell_0 to Cell_3) are repeatedly placed adjacent to each other to obtain a layout of the memory device 400. ROM cells 405 include active regions (e.g., any one of active regions OD0-OD3) that extend continuously from edge 413 of ROM cell 405 to the opposite edge 414 of ROM cell 405 without being interrupted or discontinuous by an isolation structure.

[0154] In operation 732, vias are created in multiple instances of the ROM cell according to the data to be stored in the ROM device. For example, as described in one or more of Figures 5A-5E and 6A-6F, VD vias are added in various bit cells in instances of ROM cell 405 according to the data to be stored. As described in Figures 2A and 2B, in order to program a bit cell to store logic "1", two VD vias are added to couple one source / drain of the transistor in the bit cell to bit line BL and the other source / drain of the transistor to the VSS power rail. As described in Figures 2C and 2D, in order to program a bit cell to store logic "0", two VD vias are added to couple two sources / drains of the transistor in the bit cell to bit line BL, or to couple two sources / drains of the transistor to the VSS power rail. Alternatively, as shown in Figure 2E, no VD via is added to program the bit cell to store logic "0", or as shown in Figures 2F and 2G, only one VD via is added to couple one source / drain of the transistor in the bit cell to the bit line BL or VSS power rail. In some embodiments, the bit cells are programmed sequentially along the bit line one by one, or group programming is performed to program multiple bit cells simultaneously.

[0155] In operation 734, the obtained layout of the programmable ROM device is stored on a non-transitory computer-readable recording medium, for example, for later retrieval and for manufacturing the ROM device, as shown in FIG7D. According to some embodiments, the ROM device layout produced by method 700C can achieve one or more of the advantages described herein.

[0156] Figure 7D is a flowchart of a method 700D for manufacturing a ROM device according to some embodiments. In some embodiments, method 700D is performed to manufacture a ROM device corresponding to one or more memory devices and / or ROM devices described herein. Method 700D includes operations 740, 742, and 744.

[0157] In operation 740, a plurality of active regions extending continuously along a first direction are formed on a substrate. For example, as shown in FIG3C, an example active region corresponding to source / drain electrodes 322, 323 and the channel therebetween is formed along the X-axis on substrate 320. In some embodiments, the active regions comprise one or more semiconductor materials, such as silicon (Si), silicon-germanium (SiGe), silicon carbide (SiC), or the like, doped materials, such as boron (B), phosphorus (P), arsenic (As), gallium (Ga), or other suitable materials. In some embodiments, the active regions comprise nanosheet structures, such as a continuous volume of one or more layers of one or more semiconductor materials. In various embodiments, individual nanosheet layers comprise a single monolayer or multiple monolayers of a given semiconductor material.

[0158] In operation 742, a plurality of gates are formed over a plurality of active regions along a second direction intersecting the first direction. The plurality of gates, together with the plurality of active regions, are configured as a plurality of transistors for storing data. For example, as shown in FIG3C, an example gate 325 extends along the Y-axis and is formed over the active regions to be configured as transistor 321 together with the active regions. In some embodiments, the gate is part of a gate structure comprising one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials. The gate structure also includes a gate dielectric layer comprising one or more insulating materials, such as silicon dioxide, silicon nitride (Si₃N₄), and / or one or more other suitable materials, such as low-k materials having a k value less than 3.8, or high-k materials having a k value greater than 3.8, such as aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), tantalum pentoxide (Ta₂O₅), or titanium oxide (TiO₂).

[0159] Multiple active regions, multiple gates, and multiple transistors are arranged in multiple instances of a circuit region, which includes at least four adjacent transistors in a first direction. For example, as shown in FIG4, various active regions, gates, and transistors are arranged in multiple instances of the circuit region Cell_0 to Cell_3, such as ROM cell 405. ROM cell 405 includes four transistors adjacent to each other along the X-axis (e.g., transistors T1, T5, T9, and T13 described with respect to FIG5A).

[0160] Forming at least one of a plurality of active regions includes the absence of an isolation structure in at least one active region between adjacent instances in the plurality of instances. For example, as shown in FIG5B, no isolation structure is formed in any active regions OD0-OD3 between adjacent instances 505A and 505B of ROM cell 405.

[0161] In operation 744, one or more vias are formed on one or more sources / drains in multiple active regions according to the data to be stored in the ROM device. For example, as shown in FIG3C, one or more VD vias 328, 329 are formed to couple the corresponding source / drain 322, 323 to bit lines BL or VSS power rails, for example in the MO layer. Various examples of VD vias formed according to the data to be stored are described in FIG5A-5E, FIG6A-6F. Thus, the ROM device is programmed. In at least one embodiment, the ROM device manufactured according to method 700D can achieve one or more of the advantages described herein.

[0162] The described methods include example operations, but they do not necessarily need to be performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated according to the spirit and scope of the embodiments disclosed herein. Embodiments combining different features and / or different embodiments are within the scope of this disclosure and will be apparent to those skilled in the art upon review of this disclosure.

[0163] In some embodiments, at least one of the methods described above is performed, in whole or in part, by at least one EDA system. In some embodiments, the EDA system may be used as part of the design room of the IC manufacturing system discussed below.

[0164] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0165] In some embodiments, the EDA system 800 includes an APR tool. According to some embodiments, the EDA system 800 can be used to implement a method for representing wire routing arrangements according to one or more embodiments described herein.

[0166] In some embodiments, the EDA system 800 is a general-purpose computing device including a hardware processor 802 and a non-transitory computer-readable recording medium 804. The recording medium 804, among other things, also encodes (i.e., stores) computer program code 806 (i.e., a set of executable instructions). The hardware processor 802 executes the instructions 806 to represent (at least partially) an EDA tool that implements part or all of the methods described herein according to one or more embodiments (the processes and / or methods mentioned below).

[0167] Processor 802 is electrically coupled to computer-readable recording medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, allowing processor 802 and computer-readable recording medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in computer-readable recording medium 804 to enable system 800 to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0168] In one or more embodiments, the computer-readable recording medium 804 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable recording medium 804 includes semiconductor or solid-state memory, magnetic tape, portable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disc. In one or more embodiments using optical discs, the computer-readable recording medium 804 includes compact disc read-only memory (CD-ROM), compact disc read / write (CD-R / W), and / or digital video disc (DVD).

[0169] In one or more embodiments, recording medium 804 stores computer program code 806 configured to enable system 800 (where the execution representation (at least partially) EDA tools) to perform some or all of the mentioned processes and / or methods. In one or more embodiments, recording medium 804 also stores information that facilitates the execution of some or all of the mentioned processes and / or methods. In one or more embodiments, recording medium 804 stores a standard cell library 807 including the standard cells disclosed herein.

[0170] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for exchanging information and commands with processor 802.

[0171] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows system 800 to communicate with network 814, to which one or more other computer systems are connected. Network interface 812 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 800.

[0172] System 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. EDA system 800 is configured to receive UI-related information via I / O interface 810. This information is stored as a user interface (UI) 842 on computer-readable recording media 804.

[0173] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application, which is part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one embodiment of the mentioned processes and / or methods is a software application, which is part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by an EDA system 800. In some embodiments, a layout including standard cells is generated using tools such as VIRTUOSO® provided by CADENCE DESIGN SYSTEMS or other suitable layout generation tools.

[0174] In some embodiments, these processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memory, such as ROM, RAM, memory cards; and the like.

[0175] Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on layout, the manufacturing system 900 manufactures at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of semiconductor integrated circuits.

[0176] In Figure 9, the IC manufacturing system 900 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services associated with manufacturing IC devices 960, such as design studio 920, enclosure room 930, and IC manufacturer / fab (“fab”) 950. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 920, enclosure room 930, and IC fabrication plant 950 are owned by a single, larger company. In some embodiments, two or more of the design studio 920, enclosure room 930, and IC fabrication plant 950 coexist in a shared facility and use shared resources.

[0177] Design studio (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 960 to be manufactured. The layers are combined to form various IC features. For example, a portion of IC design layout 922 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads. Design studio 920 implements appropriate design procedures to form IC design layout 922. Design procedures include one or more of logic design, physical design, or place-and-route operations. IC design layout 922 is presented in one or more data files containing geometric pattern information. For example, IC design layout 922 may be represented in GDSII file format or DFII file format.

[0178] Mask room 930 includes data preparation 932 and mask fabrication 944. Mask room 930 uses an IC design layout 922 to fabricate one or more masks 945 for fabricating layers of an IC device 960 according to the IC design layout 922. Mask room 930 performs mask data preparation 932, in which the IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF to mask fabrication 944. Mask fabrication 944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) 945 or a semiconductor wafer 953. The design layout 922 is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturing company 950. In FIG. 9, mask data preparation 932 and mask fabrication 944 are illustrated as separate elements. In some embodiments, mask data preparation 932 and mask fabrication 944 may be collectively referred to as mask data preparation.

[0179] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RETs), such as off-axis illumination, secondary resolution aids, phase-shift masking, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0180] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 922, which has already been processed in the OPC. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 922 to compensate for constraints during mask manufacturing 944, which may undo some modifications performed by the OPC to comply with the mask creation rules.

[0181] In some embodiments, mask data preparation 932 includes lithography process checking (LPC), a simulation of the process to be performed by IC manufacturer 950 to manufacture IC device 960. LPC simulates this process based on IC design layout 922 to create a simulated manufacturing apparatus, such as IC device 960. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after the simulated manufacturing apparatus is created by LPC, if the shape of the simulated apparatus is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0182] It should be understood that, for clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, data preparation 932 includes additional features, such as logic operations (LOPs), to modify the IC design layout 922 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0183] After mask data preparation 932 and during mask manufacturing 944, a mask 945 or a set of masks 945 is manufactured based on a modified IC design layout 922. In some embodiments, mask manufacturing 944 includes performing one or more lithography exposures based on the IC design layout 922. In some embodiments, a mechanism using one or more electron beams is used to form a pattern on the mask (photomask or mask plate) 945 based on the modified IC design layout 922. The mask 945 can be formed using various techniques. In some embodiments, the mask 945 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmits through the transparent areas. In one example, a binary mask version of the mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, the mask 945 is formed using a phase-shift technique. In the phase-shift mask (PSM) version of the mask 945, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shift mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 944 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 953, in etching processes to form various etched regions in semiconductor wafer 953, and / or in other suitable processes.

[0184] IC manufacturing plant 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC manufacturing plant 950 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (FEOL manufacturing) of multiple IC products, a second manufacturing facility that can provide back-end manufacturing (BEOL manufacturing) for interconnects and packaging of IC products, and a third manufacturing plant that can provide other services for foundry operations.

[0185] IC manufacturing plant 950 includes manufacturing tools 952 configured to perform various manufacturing operations on semiconductor wafers 953, such that IC devices 960 are manufactured according to a mask (e.g., mask 945). In various embodiments, manufacturing tools 952 include one or more wafer steppers, ion implanters, photoresist coaters, process chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as described herein.

[0186] IC fabrication plant 950 uses a mask 945, fabricated by mask room 930, to fabricate IC device 960. Therefore, IC fabrication plant 950 fabricates IC device 960 at least indirectly using IC design layout 922. In some embodiments, semiconductor wafer 953 is fabricated by IC fabrication plant 950 using mask 945 to form IC device 960. In some embodiments, IC fabrication includes performing one or more lithography exposures at least indirectly based on IC design layout 922. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate having a layer of material formed thereon. Semiconductor wafer 953 further includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0187] In some embodiments, a read-only memory (ROM) device includes an active region extending along a first direction and a plurality of gates extending across and above the active region along a second direction intersecting the first direction. The plurality of gates are configured as a plurality of transistors corresponding to the active region. Each of the plurality of transistors is configured to store data. The active region extends continuously through and below more than four of the plurality of gates.

[0188]

[0189] In some embodiments, a read-only memory (ROM) device includes multiple instances of circuit regions. The circuit regions include multiple active regions extending continuously along a first direction, and multiple gates extending along a second direction intersecting the first direction and spanning the multiple active regions. The multiple gates, together with the multiple active regions, are configured as multiple transistors configured to store data. The multiple instances of the circuit regions include a first instance and a second instance that are adjacent to each other and share a set of source / drain electrodes.

[0190]

[0191] According to some embodiments, a method of manufacturing a read-only memory (ROM) device includes: forming a plurality of active regions extending continuously along a first direction on a substrate; forming a plurality of gates extending along a second direction intersecting the first direction on the plurality of active regions; wherein the plurality of gates and the plurality of active regions are configured together as a plurality of transistors configured to store data; and forming one or more vias on one or more sources / drains of the plurality of active regions, depending on the data to be stored in the ROM device. The plurality of active regions, the plurality of gates, and the plurality of transistors are arranged in multiple instances of a circuit region, the circuit region including at least four adjacent transistors in the first direction. Forming at least one of the plurality of active regions includes not forming an isolation structure in at least one active region between adjacent instances in the plurality of instances.

[0192]

[0193] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0194] 100: Electronic devices 0a, 0f, 0i: OFF configuration 1g, 1h:ON configuration 100, 300A, 300B, 300C, 400: Memory devices 101: Memory Array 102: Memory controller 103: Character line drive circuit 104: Bit line drive circuit 106: Control Circuit 111, 200A-200G, MC: Memory Cell 211, 325, G0-G3, GK, GL: Gate 212: First source / drain 213: Second source / drain 215: Power rail 301, 302, 500A-500E, 600A-600F: Circuit Areas 311, 312, 313: Electrical connectors 320: Base 321, T0-T20, TK, TL: Transistors 322, 323: N-type wells (source / drain) 324: Gate dielectric layer 326, 327, 558, MD0-MD4: MD contact structure 328, 329, 550-554, 562, 563, 564, 571: VD through holes 350: Redistributed Structure 405, 505A-505E, 605A-605F:ROM cells 410, 510: Boundaries 411, 412, 413, 414: Edges 421, 422, 431, 432: Gate section 443, 446, 450, 453: M0 conductive pattern / VSS power rail 444, 445, 451, 452: M0 conductive pattern / character line pattern 501-504, 506-509: Code Codes 501-504, 506-509, 581-584, 586-589, 591-594, 601-604, 611-614, 621-624, 631-634, 641-644, 651-654: 606, 607, 608, 609: VD through holes 700A, 700B, 700C, 700D: Methods 702, 704, 710, 712, 714, 716, 718, 720, 730, 732, 734, 740, 742, 744: Operation 800, 900: System 802: Processor 808: Busbar 810:I / O interface 812: Network Interface 814: Internet 920: Design Studio 922: Design Layout 930: Covered Room 932: Data Preparation 944: Curtain Manufacturing 945: Curtain 950: IC manufacturing company / IC manufacturer / IC manufacturing plant 953: Semiconductor wafer 960: IC device BL, BL0, BL0-BL3: Bit lines CPO11, CPO12, CPO21, CPO22, CPO31, CPO32: Cutting the gate region CPP: Gate Spacing M0, M1: Metal layers MD0-MD4: MD contact structure OD, OD0-OD3: Active regions V0, V1: Through-hole layer VD1-VD3: Through holes VG, VG0-VG3: Through-hole / VG through-hole VDD, VSS: Voltage WL, WL0-WL3: Character lines

Claims

1. A read-only memory (ROM) device, comprising: The active region extends along the first direction; and a plurality of gates extending across and above the active region along a second direction intersecting the first direction, wherein the plurality of gates and the active region are correspondingly configured as a plurality of transistors, each of the plurality of transistors being configured to store data, and the active region extending continuously through and below more than four of the plurality of gates, wherein the plurality of transistors includes: a first transistor configured to store a first logic value, the first transistor having a first source / drain electrically coupled to a bit line and a second source / drain electrically coupled to a power rail; a second transistor configured to store a second logic value different from the first logic value, the second transistor having first and second sources / drains electrically coupled to the bit line; and a third transistor configured to store the second logic value, the third transistor having first and second sources / drains electrically coupled to the power rail.

2. The ROM device as claimed in claim 1, further comprising: Multiple character lines are electrically coupled to the multiple gates.

3. The ROM device of claim 1, wherein the plurality of transistors further comprises at least one of: a fourth transistor configured to store the second logic value, the fourth transistor having electrically floating first and second source / drain terminals; a fifth transistor configured to store the second logic value, the fifth transistor having a first source / drain terminal electrically coupled to the bit line and an electrically floating second source / drain terminal; or a sixth transistor configured to store the second logic value, the sixth transistor having a first source / drain terminal electrically coupled to the power rail and an electrically floating second source / drain terminal.

4. The ROM device as claimed in claim 1, wherein the bit lines and the power rails overlap with the active region and extend continuously across the plurality of gates along the first direction.

5. The ROM device as claimed in claim 1, wherein all gates through which the active region extends continuously and located below belong to transistors configured to store data.

6. The ROM device as claimed in claim 1, wherein the ROM device does not have an isolation structure that divides the active region into electrically isolated portions.

7. A read-only memory (ROM) device, comprising: Multiple instances of a circuit region, wherein the circuit region includes: multiple active regions extending continuously along a first direction; and multiple gates extending along a second direction intersecting the first direction and spanning the multiple active regions, the multiple gates and the multiple active regions being configured together as multiple transistors, the multiple transistors being configured to store data, the multiple instances of the circuit region including a first instance and a second instance, which are adjacent to each other and share a set of source / drain electrodes, wherein the multiple transistors include: a first transistor configured to store a first logic value, the first transistor having a first source / drain electrically coupled to a bit line and a second source / drain electrically coupled to a power rail; a second transistor configured to store a second logic value different from the first logic value, the second transistor having first and second sources / drains electrically coupled to the bit line; and a third transistor configured to store the second logic value, the third transistor having first and second sources / drains electrically coupled to the power rail.

8. The ROM device as claimed in claim 8, wherein the plurality of active regions extend continuously from the first instance to the second instance.

9. A method for manufacturing a read-only memory (ROM) device, the method comprising: Multiple active regions are formed on the substrate, extending continuously along the first direction; A plurality of gates are formed on the plurality of active regions, extending along a second direction intersecting the first direction. The plurality of gates and the plurality of active regions are configured together as a plurality of transistors, which are configured to store data. And, according to the data to be stored in the ROM device, one or more vias are formed over one or more sources / drains in the plurality of active regions, wherein the plurality of active regions, the plurality of gates, and the plurality of transistors are arranged in multiple instances of a circuit region, the circuit region including at least four adjacent transistors in the first direction, and forming at least one active region in the plurality of active regions including at least one active region between adjacent instances in the plurality of instances without forming an isolation structure, wherein the plurality of transistors includes: a first transistor configured to store a first logic value, the first transistor having a first source / drain electrically coupled to a bit line and a second source / drain electrically coupled to a power rail; a second transistor configured to store a second logic value different from the first logic value, the second transistor having first and second sources / drains electrically coupled to the bit line; and a third transistor configured to store the second logic value, the third transistor having first and second sources / drains electrically coupled to the power rail.

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