Integrated circuit and method of operating the same

Abstract

An integrated circuit includes a first power rail for supplying a first supply voltage, a second power rail for supplying a second supply voltage, a first memory circuit coupled to the first and second power rails and for receiving a first control signal, the first or the second supply voltage, and a first core circuit. The second supply voltage has a first value or a second value different from the first value. The first memory circuit includes a first header circuit and a first memory cell array. The first header circuit is coupled to the second power rail and for supplying the second supply voltage to a first node in response to the first control signal. The first memory cell array is coupled to the first header circuit via the first node and for storing a first set of data, and receives the second supply voltage from the first header circuit.

Description

Technical Field

[0001] none Prior Technology

[0002] The integrated circuit (IC) industry produces a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured for data storage. As ICs become smaller and more complex, the resistance of the wires within these digital devices changes, thus affecting the operating voltage of these devices and the overall performance of the IC. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a block diagram of a memory circuit according to some embodiments. Figure 2 is a circuit diagram of an integrated circuit according to some embodiments. Figure 3A is a block diagram of a circuit that can be used in at least Figure 2 or Figure 9 according to some embodiments. Figure 3B is a block diagram of a circuit that can be used in at least Figure 2 or Figure 9 according to some embodiments. Figure 4 is a block diagram of a circuit that can be used in at least Figure 2 or Figure 9 according to some embodiments. Figures 5A to 5B are corresponding circuit diagrams of the corresponding eFuse circuits according to some embodiments. Figure 6 is a block diagram of a circuit that can be used in at least Figure 2 or Figure 9 according to some embodiments. Figure 7 is a timing diagram of the waveforms of an integrated circuit according to some embodiments. Figure 8 is a flowchart of a method for operating circuits according to some embodiments. Figure 9 is a circuit diagram of an integrated circuit according to some embodiments. Figure 10 is a circuit diagram of a level shifter circuit according to some embodiments. Figure 11 is a timing diagram of the waveforms of an integrated circuit according to some embodiments. Figure 12 is a flowchart of a method of operating circuitry according to some embodiments. Figure 13 is a schematic diagram of a controller for generating one or more control signals or voltages according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific instances of components, materials, values, steps, configurations, or the like are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, configurations, or the like are also contemplated. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive symbols used herein may be interpreted similarly accordingly.

[0007] According to some embodiments, an integrated circuit includes a first power rail for supplying a first supply voltage.

[0008] In some embodiments, the integrated circuit further includes a second power rail for supplying a second supply voltage. In some embodiments, the second supply voltage is different from the first supply voltage.

[0009] In some embodiments, the integrated circuit further includes a first memory circuit coupled to a first power rail and a second power rail. In some embodiments, the first memory circuit is configured to receive at least one of a first control signal, a first supply voltage, or a second supply voltage.

[0010] In some embodiments, the integrated circuit further includes a first core circuit coupled to the first memory circuit. In some embodiments, the first core circuit is configured to receive a second supply voltage.

[0011] In some embodiments, the first memory circuit includes a first header circuit. In some embodiments, the first header circuit is coupled to a second power rail. In some embodiments, the first header circuit is configured to supply a second supply voltage to at least a first node in response to a first control signal.

[0012] In some embodiments, the first memory circuitry includes a first memory cell array. In some embodiments, the first memory cell array is coupled to a first header circuit via a first node. In some embodiments, the first memory cell array is used to store a first set of data and receive a second supply voltage from the first header circuit.

[0013] In some embodiments, the second supply voltage has a first value or a second value. In some embodiments, the second value is different from the first value.

[0014] In some embodiments, by adjusting the second supply voltage to or from the first value to the second value, the integrated circuit has a flexible design that allows it to operate in two different voltage ranges, thereby reducing the power consumption of the integrated circuit compared to other methods that have only a single operating voltage range.

[0015] Figure 1 is a block diagram of a memory circuit 100 according to some embodiments.

[0016] Figure 1 is simplified for illustrative purposes. In some embodiments, the memory circuit 100 includes various elements other than those depicted in Figure 1, or is configured to perform the following operations.

[0017] The memory circuit 100 is an IC that includes memory partitions 102A~102D, a global control circuit 100GC, and a global input / output (GIO) circuit 100BL.

[0018] Each memory partition 102A~102D includes memory banks 110U and 110L adjacent to the word line (WL) driver circuit 110AC and the region control circuit 110LC. Each memory bank 110U and 110L includes a memory cell array 110AR and a local input output (LIO) circuit 110BS.

[0019] Memory partitions, such as memory partitions 102A-102D, are part of memory circuitry 100 and include a subset of memory devices (not shown in Figure 1) and adjacent circuitry for selectively accessing the subset of memory devices during programming and read operations. In the embodiment shown in Figure 1, memory circuitry 100 includes a total of four partitions. In some embodiments, memory circuitry 100 includes a total of more than or less than four partitions.

[0020] GIO circuit 100BL is a circuit used, for example, to control access to one or more electrical paths (e.g., bit lines) to memory devices in corresponding memory banks 110U or 110L of memory partitions 102A-102D by generating one or more bit line signals. In some embodiments, GIO circuit 100BL includes global bit line driver circuitry. In some embodiments, GIO circuit 100BL is coupled to each memory bank 110U and 110L via corresponding global bit lines (not shown).

[0021] The global control circuit 100GC is used, for example, to control some or all of the programming and reading operations of each memory partition 102A~102D by generating and / or outputting one or more control and / or enable signals.

[0022] In some embodiments, the global control circuit 100GC includes one or more analog circuits for interfacing with memory partitions 102A-102D to program data in one or more memory devices and / or use data received from one or more memory devices in one or more circuit operations. In some embodiments, the global control circuit 100GC includes one or more global address decoder or pre-decoder circuits for outputting one or more address signals to the WL driver circuit 110AC of each memory partition 102A-102D.

[0023] Each WL driver circuit 110AC is used to generate a word line signal on the corresponding word line WL. In some embodiments, each WL driver circuit 110AC is used to output the word line signal on the corresponding word line WL to the adjacent memory banks 110U and 110L in the corresponding memory partitions 102A to 102D.

[0024] Each WL driver circuit 110AC includes one or more circuits 116. For ease of illustration, circuits 116 are not shown in the memory libraries 110U and 110L of memory partitions 102B, 102C, and 102D. In some embodiments, each circuit 116 includes at least one word line driver circuit or at least one tracking word line driver circuit. In some embodiments, at least one word line driver circuit is used to generate a word line signal WL1 (shown at least in Figure 2). In some embodiments, at least one tracking word line driver circuit is used to generate a tracking word line signal (not shown). In some embodiments, each circuit 116 in the WL driver circuit 110AC is coupled to a corresponding column of memory devices 112 in the memory cell array 110AR.

[0025] Each region control circuit 110LC is an electronic circuit used to receive one or more address signals. Each region control circuit 110LC is used to generate signals corresponding to adjacent subsets of the memory device identified by the one or more address signals. In some embodiments, the adjacent subsets of the memory device correspond to rows in the memory device. In some embodiments, each region control circuit 110LC is used to generate complementary signal pairs. In some embodiments, each region control circuit 110LC is used to output signals to corresponding word line driver circuits within adjacent WL driver circuits 110AC in corresponding memory partitions 102A-102D. In some embodiments, the region control circuit 110LC includes library decoder circuitry. Other types of control circuitry used for the region control circuit 110LC are also within the scope of this disclosure.

[0026] Each LIO circuit 110BS responds to the GIO circuit 100BL, for example, selectively accessing one or more bit lines (as shown in Figure 2) of an adjacent subset of memory devices coupled to the corresponding memory cell array 110AR based on one or more BL control signals. In some embodiments, the adjacent subset of memory devices corresponds to columns in the memory devices. In some embodiments, the LIO circuit 110BS includes bit line selection circuitry.

[0027] Each LIO circuit 110BS includes one or more circuits 114. For ease of illustration, circuits 114 are not shown in the memory libraries 110U and 110L of memory partitions 102B, 102C, and 102D. In some embodiments, each circuit 114 includes at least one bit line driver circuit. In some embodiments, at least one bit line driver circuit is used to generate a bit line signal BL1 (shown at least in Figure 2). In some embodiments, each circuit 114 is coupled to a corresponding row of memory devices 112 in the memory cell array 110AR.

[0028] In some embodiments, each circuit 114 further includes at least one sense amplifier circuit and a write latch circuit. According to some embodiments, during a write operation, the write latch circuit is used to write data to at least one memory cell 112 in a corresponding row of memory cells in the corresponding memory cell array 110AR. According to some embodiments, during a read operation, the sense amplifier circuit is used to read data from at least one memory cell 112 in a corresponding row of memory cells in the corresponding memory cell array 110AR. In some embodiments, each circuit 114 in the LIO circuit 110BS is coupled to a corresponding row of memory devices 112 in the memory cell array 110AR.

[0029] In some embodiments, one or more of the LIO circuit 110BS, the area control circuit 110LC, the WL driver circuit 110AC, the GIO circuit 100BL, or the global control circuit 100GC include a memory circuit 120.

[0030] In some embodiments, memory circuitry 120 is coupled to at least one of a power rail 232 (as shown in Figures 2 and 9) for supplying a supply voltage VQPS or a power rail 230 for supplying a supply voltage VDDSOC. In some embodiments, memory circuitry 120 is further coupled to a power rail 930 (as shown in Figure 9) for supplying a supply voltage VDDHV.

[0031] In some embodiments, the supply voltage VDDSOC is different from the supply voltage VQPS. In some embodiments, the supply voltage VDDHV is different from both the supply voltage VQPS and the supply voltage VDDSOC.

[0032] In some embodiments, memory circuit 120 is used to supply a supply voltage VQPS or a supply voltage VDDSOC to at least one of circuits 112, 114, or 116. In some embodiments, memory circuit 120 is further used to supply a supply voltage VDDHV to at least one of circuits 112, 114, or 116.

[0033] In some embodiments, the memory circuit 120 is also referred to as a power gate circuit.

[0034] In some embodiments, the memory circuit 120 includes at least one or more circuits 112, 114, or 116.

[0035] Each memory bank 110U and 110L includes a corresponding memory cell array 110AR, which includes memory cells or memory devices 112 for access by adjacent LIO circuits 110BS and adjacent WL driver circuits 110AC in programming and read operations.

[0036] Each memory cell array 110AR includes an array of memory devices 112 having N columns and M rows, where M and N are positive integers. Columns of cells in the memory cell array 102 are arranged in a first direction X. Rows of cells in the memory cell array 102 are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (not shown). In some embodiments, each row of memory devices 112 in the memory cell array 110AR is coupled to a corresponding circuit 114 in the LIO circuit 110BS.

[0037] Memory device 112 is displayed in memory banks 110U and 110L of memory partition 102A. For ease of explanation, memory device 112 is not displayed in memory banks 110U and 110L of memory partitions 102B, 102C, and 102D.

[0038] Memory device 112 is an electrical, electromechanical, electromagnetic, or other means for storing bit data represented by logical states. At least one logical state of memory device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, the logical state corresponds to the voltage level of a charge stored in a given memory device 112. In some embodiments, the logical state corresponds to the physical properties of a component of a given memory device 112, such as voltage, current, resistance, or magnetic orientation.

[0039] In some embodiments, memory device 112 includes one or more one-time programmable (OTP) memory devices. In some embodiments, memory device 112 includes one or more electronic fuse (eFuse) devices. In some embodiments, memory device 112 includes one or more antifuse devices. In some embodiments, memory device 112 is an OTP memory device including one or more OTP memory cells. Different types of memory cells in memory device 112 are also within the scope of this disclosure. In some embodiments, memory device 112 includes one or more flash memory devices, random access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, or the like. In some embodiments, the memory device 112 includes one or more single-port (SP) static random access memory (SRAM) cells. In some embodiments, the memory device 112 includes one or more dual-port (DP) SRAM cells. In some embodiments, the memory device 112 includes one or more multi-port SRAM cells. In some embodiments, the memory device 112 includes one or more dynamic random access memory (DRAM) cells.

[0040] Other configurations of the memory circuit 100 are also within the scope of this disclosure.

[0041] Figure 2 is a circuit diagram of an integrated circuit 200 according to some embodiments.

[0042] In some embodiments, integrated circuit 200 may be used in Figure 1. Integrated circuit 200 is an embodiment of circuit 120 in Figure 1, therefore a similar detailed description is omitted.

[0043] In some embodiments, the integrated circuit 200 is an embodiment of at least a portion of one or more of the memory partitions 102A, 102B, 102C, or 102D of Figure 1, and therefore similar detailed descriptions are omitted. In some embodiments, the integrated circuit 200 is an embodiment of the memory cell array 110AR of Figure 1, the LIO circuit 110BS of Figure 1, and the WL driver circuit 110AC of Figure 1, and therefore similar detailed descriptions are omitted.

[0044] The integrated circuit 200 includes a memory circuit 202 and a core device assembly 220.

[0045] The memory circuit 202 includes a header circuit 204, a power switch 206, a memory cell array 208, a bit line driver circuit 210, a word line driver circuit 212, a control circuit 214, a power rail 230, and a power rail 232.

[0046] In some embodiments, the memory cell array 208 is an embodiment of one or more memory cells MCBs in at least one of the memory cell array 110AR of Figure 1 or the memory device 112 of Figure 1, and therefore similar detailed descriptions are omitted.

[0047] In some embodiments, at least one of the bit line driver circuit 210, control circuit 214, or power switch 206 is an embodiment of one or more circuits 114 of at least one of the LIO circuits 110BS of Figure 1, and therefore similar detailed descriptions are omitted.

[0048] In some embodiments, the character line driver circuit 212 is an embodiment of one or more of the WL driver circuits 110AC of Figure 1, and therefore similar detailed descriptions are omitted.

[0049] The memory circuit 202 is coupled to the power rail 230, the power rail 232, and the core device assembly 220.

[0050] The memory circuit 202 is coupled to power rails 230 and 232.

[0051] The power rail 230 has a supply voltage VDDSOC.

[0052] Power rail 232 has a supply voltage VQPS. In some embodiments, the supply voltage VQPS is greater than the supply voltage VDDSOC. In some embodiments, the supply voltage VQPS ranges from about 1.5 volts to about 2.0 volts. In some embodiments, the supply voltage VDDSOC ranges from about 0.45 volts to about 1.0 volt. Other supply voltage values ​​for VQPS or VDDSOC are also within the scope of this disclosure.

[0053] The memory circuit 202 is used to receive the supply voltage VDDSOC from the power rail 230 and the supply voltage VQPS from the power rail 232.

[0054] The header circuit 204 is coupled to the power rail 230. The header circuit 204 is used to receive the supply voltage VDDSOC from the power rail 230. The header circuit 204 is used to supply the supply voltage VDDSOC to at least node ND1.

[0055] In some embodiments, header circuit 204 is configured to supply a supply voltage VDDSOC to at least one of memory cell array 208, bit line driver circuit 210, word line driver circuit 212, or control circuit 214 in response to control signal PD1 (e.g., Figure 3A) or control signal PD5 (e.g., Figure 3B). In some embodiments, header circuit 204 is also referred to as a power gate circuit.

[0056] In some embodiments, the supply voltage VDDSOC is adjusted from the supply voltage VDDA to the supply voltage VDDB, and vice versa. In some embodiments, the supply voltage VDDSOC is set and adjusted by a circuit (such as the controller 1300 in Figure 13). In some embodiments, the supply voltage VDDSOC is set and adjusted by a circuit, such as the circuit 400 in Figure 4. In some embodiments, the supply voltage VDDA is less than the supply voltage VDDB. In some embodiments, the supply voltage VDDA ranges from about 0.4 volts to about 0.6 volts. In some embodiments, the supply voltage VDDB ranges from about 0.6 volts to about 1.0 volts. Other supply voltage values ​​for VDDA or VDDB are also within the scope of this disclosure.

[0057] In some embodiments, when the supply voltage VDDSOC is set to be equal to the supply voltage VDDA, the integrated circuit 200 is configured to be in sleep mode or power-off mode, thereby reducing the power consumption of the integrated circuit 200 compared with other methods.

[0058] In some embodiments, when the supply voltage VDDSOC is set to be equal to the supply voltage VDDA, the header circuit 204 is disabled and configured to be in sleep mode or power-off mode, and one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, sense amplifier 214a of control circuit 214, or power switch 206 are disabled and / or configured to be in sleep mode or power-off mode, thereby reducing the power consumption of integrated circuit 200 compared with other methods.

[0059] In some embodiments, when the supply voltage VDDSOC is set to be equal to the supply voltage VDDB, the integrated circuit 200 is configured to be in read mode, programmable mode, or standby mode. In some embodiments, when the supply voltage VDDSOC is set to be equal to the supply voltage VDDB, the header circuit 204 is enabled, and one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, sense amplifier 214a of control circuit 214, or power switch 206 are enabled and / or configured to be in read mode, programmable mode, or standby mode.

[0060] In some embodiments, by adjusting the supply voltage VDDSOC from the supply voltage VDDA to the supply voltage VDDB, the memory circuit 202 has a flexible design that can be used to operate in two different voltage ranges (e.g., VDDA & VDDB), thereby reducing the power consumption of the integrated circuit 200 compared to other methods that only have a single operating voltage range (which are inflexible and consume more power).

[0061] In some embodiments, by adjusting the supply voltage VDDSOC from the supply voltage VDDA to the supply voltage VDDB, the memory circuit 202 has a flexible design that can be used to operate in two different voltage ranges (e.g., VDDA & VDDB), thereby reducing the leakage current from the power rail 230 to at least node ND1 in sleep mode or power-down mode, thus reducing the power consumption of the integrated circuit 200 compared to other methods that have only a single operating voltage range (which are inflexible and consume more power).

[0062] The header circuit 204 is further coupled via node ND1 to one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, or control circuit 214. In some embodiments, the header circuit 204 is used to supply a supply voltage VDDSOC to at least one of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, or control circuit 214 via node ND1.

[0063] In some embodiments, at least one of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, or control circuit 214 is used to operate on the supply voltage VDDSOC received from the header circuit 204.

[0064] Other configurations, components, or the number of components in header circuit 204 are also within the scope of this disclosure.

[0065] The memory cell array 208 is coupled to the header circuit 204 via node ND1. The memory cell array 208 receives the supply voltage VDDSOC from the header circuit 204 via node ND1. The memory cell array 208 is used to store the data set DIN1.

[0066] Other configurations, elements, or number of elements in the memory cell array 208 are also within the scope of this disclosure.

[0067] Bit line driver circuit 210 is coupled to header circuit 204 via node ND1. Bit line driver circuit 210 is used to receive supply voltage VDDSOC. Bit line driver circuit 210 is used to generate bit line signal BL. In some embodiments, bit line driver circuit 210 is used to receive bit line signal BL.

[0068] Other configurations, components, or number of components in the bit line driver circuit 210 are also within the scope of this disclosure.

[0069] The character line driver circuit 212 is coupled to the header circuit 204 via node ND1. The character line driver circuit 212 receives the supply voltage VDDSOC. The character line driver circuit 212 generates the character line signal WL. In some embodiments, the character line driver circuit 212 receives the character line signal WL.

[0070] Other configurations, components, or number of components in the character line driver circuit 212 are also within the scope of this disclosure.

[0071] Control circuit 214 is coupled to header circuit 204 via node ND1. Control circuit 214 is used to receive supply voltage VDDSOC. In some embodiments, control circuit 214 is used to perform one or more control operations on memory cell array 208. In some embodiments, control circuit 214 is used to perform one or more read operations on memory cell array 208 in response to one or more corresponding sense amplifier enable (SAE) signals.

[0072] In some embodiments, the control circuit 214 includes at least one sense amplifier circuit 214a.

[0073] In some embodiments, the sense amplifier circuit 214a is coupled to the header circuit 204 via node ND1. In some embodiments, the sense amplifier circuit 214a is configured to receive a supply voltage VDDSOC. In some embodiments, the sense amplifier circuit 214a is configured to perform one or more read operations on the memory cell array 208 in response to one or more corresponding sense amplifier enable (SAE) signals.

[0074] In some embodiments, control circuit 214 includes other types of circuitry. In some embodiments, control circuit 214 includes at least one level shifter circuit, similar to a set of level shifter circuits 910 or 920 of Figure 9, and therefore such detailed descriptions are omitted. In some embodiments, control circuit 214 includes at least a charge pump circuit, a low-dropout (LDO) circuit, a bandgap circuit, a detector circuit, or a voltage generator circuit.

[0075] Other configurations, components, or number of components in the control circuit 214 or the sensing amplifier circuit 214a are also within the scope of this disclosure.

[0076] Power switch 206 is coupled to power rail 232. Power switch 206 is used to receive supply voltage VQPS. In some embodiments, power switch 206 is used to supply supply voltage VQPS to memory cell array 208 in response to a write operation performed by write driver circuitry (such as circuitry 114 in Figure 1) on memory cell array 208.

[0077] In some embodiments, the power switch 206 includes one or more transistors, similar to transistor P1 in Figures 3A to 3B, and therefore such detailed descriptions are omitted. In some embodiments, the power switch 206 includes at least one level shifter circuit, similar to a set of level shifter circuits 910 or 920 in Figure 9, and therefore such detailed descriptions are omitted.

[0078] Other configurations, components, or the number of components in the power supply circuit 206 are also within the scope of this disclosure.

[0079] Other configurations, components, or the number of components in memory circuit 202 are also within the scope of this disclosure.

[0080] The core device assembly 220 is coupled to the power rail 230. In some embodiments, the core device assembly 220 is coupled to the memory circuit 202 and the power rail 230. The core device assembly 220 is used to receive a supply voltage VDDSOC from the power rail 230.

[0081] In some embodiments, at least one circuit element or at least one core device in the set of core devices 220 is configured to operate on a supply voltage VDDSOC. In some embodiments, at least one circuit element or at least one core device in the set of core devices 220 is configured to operate on a supply voltage VDDA.

[0082] In some embodiments, the set 220 of core devices includes at least one or more of core devices 220A, ..., 220N, where N is an integer corresponding to the number of core devices in the set 220 of core devices.

[0083] In some embodiments, at least one of the core devices in the set 220 includes one or more of a central processing unit (CPU) core, a graphics processing unit (GPU) core, or a memory controller core.

[0084] Other configurations, components, or number of components in the core device assembly 220 are also within the scope of this disclosure.

[0085] In some embodiments, at least one of the transistors in the header circuit 204 has a threshold voltage VT1. In some embodiments, at least one of the transistors in the memory cell array 208, the bit line driver circuit 210, the word line driver circuit 212, the sense amplifier 214a of the control circuit 214, or the power switch 206 has a threshold voltage VT2. In some embodiments, the threshold voltage VT2 is greater than the threshold voltage VT1.

[0086] In some embodiments, the threshold voltage of a transistor device is related to one or more of the following: the difference in work function between the transistor channel and the transistor gate electrode, the amount of p-type or n-type dopant in the transistor device, the thickness of the gate oxide of the corresponding gate in the transistor device, or the like.

[0087] For example, in some embodiments, increasing the work function difference between the channel and gate of an NMOS transistor leads to an increase in the threshold voltage of the NMOS transistor, and vice versa. For example, in some embodiments, increasing the work function difference between the channel and gate of a PMOS transistor leads to a decrease in the threshold voltage of the PMOS transistor, and vice versa.

[0088] For example, in some embodiments, reducing the thickness of the gate oxide of the transistor device can lead to a reduction in the threshold voltage of the transistor device.

[0089] For example, in some embodiments, increasing the P-type dopant concentration in the channels of an NMOS transistor leads to an increase in the threshold voltage. In some embodiments, increasing the N-type dopant concentration in the channels of an NMOS transistor leads to a decrease in the threshold voltage.

[0090] In some embodiments, configuring memory circuit 202 with different threshold voltages reduces leakage current in the path including node ND1, thereby reducing the power consumption of integrated circuit 200 compared to other methods with higher leakage current and greater power consumption.

[0091] In some embodiments, when one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, or power switch 206 are disabled or in sleep mode (e.g., power-off mode), configuring the memory circuit 202 with header circuit 204 reduces leakage current in the path including node ND1, thereby reducing the power consumption of the integrated circuit 200 compared to other methods with higher leakage current and greater power consumption.

[0092] Other configurations, components, or number of components in the integrated circuit 200 are also within the scope of this disclosure.

[0093] Figure 3A is a block diagram of a circuit 300A that can be used in at least Figure 2 or Figure 9 according to some embodiments.

[0094] In some embodiments, circuit 300A is an embodiment of header circuit 204 in Figure 2 or header circuit 204 in Figure 9, and therefore similar detailed descriptions are omitted.

[0095] Circuit 300A includes a power rail 230, an inverter assembly 302, and a transistor P1.

[0096] The power rail 230 is coupled to the inverter assembly 302 and the transistor P1.

[0097] The set of inverters 302 includes at least one of inverters I1 or I2.

[0098] Inverter I1 is coupled to power rail 230 and inverter I2.

[0099] Inverter I1 is used to receive control signal PD1. Inverter I1 is used to generate control signal PD2 in response to control signal PD1. In some embodiments, control signal PD1 and control signal PD2 are inverted.

[0100] In some embodiments, inverter I1 includes an input terminal, an output terminal, and a voltage supply node ND2. In some embodiments, the voltage supply node ND2 is coupled to a power rail 230. In some embodiments, the voltage supply node ND2 is used to receive a supply voltage VDDSOC from the power rail 230. In some embodiments, inverter I1 is used to operate on the supply voltage VDDSOC. In some embodiments, the input terminal of inverter I1 is used to receive a control signal PD1. In some embodiments, the output terminal of inverter I1 is used to output a second control signal PD2. In some embodiments, the output terminal of inverter I1 is coupled to the input terminal of inverter I2.

[0101] In some embodiments, the control signal PD1 is generated by a circuit, such as the controller 1300 of Figure 13. In some embodiments, the input terminal of the inverter I1 is coupled to the controller 1300 of Figure 13.

[0102] Inverter I2 is coupled to the first power rail (VDDSOC), inverter I1, and transistor P1.

[0103] Inverter I2 is used to receive control signal PD2. Inverter I2 is used to generate control signal PD3 in response to control signal PD2. In some embodiments, control signal PD3 is the inverse of control signal PD2.

[0104] In some embodiments, inverter I2 includes an input terminal, an output terminal, and a voltage supply node ND3. In some embodiments, the voltage supply node ND3 is coupled to a power rail 230. In some embodiments, the voltage supply node ND3 is used to receive a supply voltage VDDSOC from the power rail 230. In some embodiments, inverter I2 is used to operate on the supply voltage VDDSOC. In some embodiments, the input terminal of inverter I2 is used to receive a control signal PD2. In some embodiments, the output terminal of inverter I2 is used to output the control signal PD3 to the gate terminal of transistor P1.

[0105] Transistor P1 is coupled to power rail 230, the output terminal of inverter I2, and node ND1. In some embodiments, transistor P1 is a PMOS transistor. Other transistor types of transistor P1 are also within the scope of this disclosure. In some embodiments, transistor P1 is an NMOS transistor.

[0106] Transistor P1 includes a gate terminal for receiving control signal PD3. The gate terminal of transistor P1 is coupled to the output terminal of inverter I2.

[0107] Transistor P1 further includes a source terminal coupled to power rail 230. In some embodiments, the source terminal of transistor P1 is used to receive a supply voltage VDDSOC. Transistor P1 further includes a drain terminal coupled to node ND1.

[0108] In some embodiments, when transistor P1 is enabled or turned on, transistor P1 is used to supply the supply voltage VDDSOC to node ND1. In some embodiments, when transistor P1 is disabled or turned off, transistor P1 is not used to supply the supply voltage VDDSOC to node ND1.

[0109] Selecting different numbers of inverters in Figures 3A to 3B and Figure 10 is also within the scope of various embodiments. Selecting different numbers of transistors or different types of transistors in Figures 3A to 3B, Figure 4, Figures 5A to 5B, and Figure 10 is also within the scope of various embodiments.

[0110] Other configurations, components, or the number of inverters in the inverter set 302 of circuit 300A are also within the scope of this disclosure.

[0111] Other configurations, components, or the number of transistors in circuit 300A are also within the scope of this disclosure.

[0112] In some embodiments, by adjusting the supply voltage VDDSOC to the supply voltage VDDA or from the supply voltage VDDA to the supply voltage VDDB, circuits 300A-300B have a flexible design that can be used to operate in two different voltage ranges (e.g., VDDA & VDDB), thereby reducing the leakage current flowing from the power rail 230 through transistor P1 to at least node ND1 during sleep mode or power-off mode, thus reducing the power consumption of circuits 300A-300B compared to other methods that only have a single operating voltage range (which are inflexible and consume more power).

[0113] Other configurations, components, or the number of components in circuit 300A are also within the scope of this disclosure.

[0114] Figure 3B is a block diagram of a circuit 300B that can be used in at least Figure 2 or Figure 9 according to some embodiments.

[0115] In some embodiments, circuit 300B is an embodiment of header circuit 204 in Figure 2 or header circuit 204 in Figure 9, and therefore similar detailed descriptions are omitted.

[0116] Circuit 300B is a variant of circuit 300A in Figure 3A, therefore a similar detailed description is omitted. For example, circuit 300B is illustrated as a non-limiting example in which circuit 300B further includes a set 322 of inverters, therefore a similar detailed description is omitted.

[0117] Compared to circuit 300A in Figure 3A, circuit 300B further includes a set of inverters 322, therefore a similar detailed description is omitted.

[0118] Circuit 300B includes a power rail 230, an inverter assembly 302, an inverter assembly 322, and a transistor P1.

[0119] The power rail 230 is coupled to the inverter assembly 302 and 322 and the transistor P1.

[0120] The set of inverters 322 includes at least one of inverters I3 or I4.

[0121] Inverter I3 is coupled to power rail 230 and inverter I4.

[0122] Inverter I3 is used to receive control signal PD5. Inverter I3 is used to generate control signal PD4 in response to control signal PD5. In some embodiments, control signal PD5 is the inverse of control signal PD4.

[0123] In some embodiments, inverter I3 includes an input terminal, an output terminal, and a voltage supply node ND4. In some embodiments, the voltage supply node ND4 is coupled to a power rail 230. In some embodiments, the voltage supply node ND4 is used to receive a supply voltage VDDSOC from the power rail 230. In some embodiments, inverter I3 is used to operate on the supply voltage VDDSOC. In some embodiments, the input terminal of inverter I3 is used to receive a control signal PD5. In some embodiments, the output terminal of inverter I3 is used to output a second control signal PD4. In some embodiments, the output terminal of inverter I3 is coupled to the input terminal of inverter I4.

[0124] In some embodiments, the control signal PD5 is generated by a circuit, such as the controller 1300 of Figure 13. In some embodiments, the input terminal of the inverter I3 is coupled to the controller 1300 of Figure 13.

[0125] Inverter I4 is coupled to the first power rail (VDDSOC), inverter I3, and inverter I1.

[0126] Inverter I4 is used to receive control signal PD4. Inverter I4 is used to generate control signal PD1 in response to control signal PD4. In some embodiments, control signal PD1 is the inverse of control signal PD4.

[0127] In some embodiments, inverter I4 includes an input terminal, an output terminal, and a voltage supply node ND5. In some embodiments, the voltage supply node ND5 is coupled to a power rail 230. In some embodiments, the voltage supply node ND5 is used to receive a supply voltage VDDSOC from the power rail 230. In some embodiments, inverter I4 is used to operate on the supply voltage VDDSOC. In some embodiments, the input terminal of inverter I4 is used to receive a control signal PD4. In some embodiments, the output terminal of inverter I4 is used to output a control signal PD1 to the input terminal of inverter I1.

[0128] Compared to circuit 300A in Figure 3A, the input terminal of inverter I1 is coupled to the output terminal of inverter I4, therefore a similar detailed description is omitted. Compared to circuit 300A in Figure 3A, the input terminal of inverter I1 is used to receive control signal PD1 from the output terminal of inverter I4, therefore a similar detailed description is omitted.

[0129] Other configurations, components, or the number of inverters in the set of inverters 302 or 322 in circuit 300B are also within the scope of this disclosure.

[0130] Other configurations, components, or the number of transistors in circuit 300B, such as transistor P1, are also within the scope of this disclosure.

[0131] In some embodiments, circuit 300B achieves one or more of the advantages described herein.

[0132] Other configurations, components, or the number of components in circuit 300B are also within the scope of this disclosure.

[0133] Figure 4 is a block diagram of a circuit 400 that can be used in at least Figure 2 or Figure 9 according to some embodiments.

[0134] In some embodiments, circuit 400 may be used to supply supply voltage to power rail 230 of Figure 2, Figure 3A, Figure 3B, Figure 5A, Figure 5B, Figure 6, Figure 9, or Figure 10, and therefore similar detailed descriptions are omitted.

[0135] Circuit 400 includes circuit 402 and power rail 230.

[0136] Circuit 402 is coupled to power rail 230. In some embodiments, circuit 402 is used to supply a supply voltage VDDA or VDDB as a supply voltage VDDSOC to power rail 230. In some embodiments, circuit 402 is used to set and / or adjust the supply voltage VDDSOC to be equal to the supply voltage VDDA or the supply voltage VDDB.

[0137] Circuit 402 includes transistor P2 and transistor P3.

[0138] Transistor P2 is coupled to power rail 230. In some embodiments, transistor P2 is a PMOS transistor. Other transistor types of transistor P2 are also within the scope of this disclosure. In some embodiments, transistor P2 is an NMOS transistor.

[0139] Transistor P2 includes a gate terminal for receiving control signal PS1. In some embodiments, the gate terminal of transistor P2 is coupled to a source of control signal PS1.

[0140] In some embodiments, the control signal PS1 is generated by a circuit, such as the controller 1300 of Figure 13. In some embodiments, the gate terminal of transistor P2 is coupled to the controller 1300 of Figure 13.

[0141] Transistor P2 further includes a source terminal coupled to the voltage supply VDDA. In some embodiments, the source terminal of transistor P2 is used to receive the supply voltage VDDA. Transistor P2 further includes a drain terminal coupled to the power rail 230.

[0142] Transistor P3 is coupled to power rail 230. In some embodiments, transistor P3 is a PMOS transistor. Other transistor types of transistor P3 are also within the scope of this disclosure. In some embodiments, transistor P3 is an NMOS transistor.

[0143] Transistor P3 includes a gate terminal for receiving control signal PS1B. In some embodiments, the gate terminal of transistor P3 is coupled to the source of control signal PS1B.

[0144] In some embodiments, the control signal PS1B is the inverse of the control signal PS1, and vice versa. In some embodiments, the control signal PS1B is generated by a circuit, such as the controller 1300 of Figure 13. In some embodiments, the gate terminal of transistor P3 is coupled to the controller 1300 of Figure 13.

[0145] Transistor P3 further includes a source terminal coupled to the voltage supply VDDB. In some embodiments, the source terminal of transistor P3 is used to receive the supply voltage VDDB. Transistor P3 further includes a drain terminal coupled to the power rail 230.

[0146] In some embodiments, when transistor P2 is enabled or turned on, transistor P3 is disabled or turned off, and vice versa. In some embodiments, when transistor P3 is enabled or turned on, transistor P2 is disabled or turned off, and vice versa.

[0147] In some embodiments, when transistor P2 is enabled or switched on, transistor P2 supplies a supply voltage VDDA to the power rail 230. In some embodiments, when transistor P2 is enabled or switched on, transistor P2 sets and / or adjusts the supply voltage VDDSOC to be equal to the supply voltage VDDA.

[0148] In some embodiments, when transistor P3 is enabled or switched on, transistor P3 supplies a supply voltage VDDB to the power rail 230. In some embodiments, when transistor P3 is enabled or switched on, transistor P3 sets and / or adjusts the supply voltage VDDSOC to be equal to the supply voltage VDDB.

[0149] In some embodiments, when transistor P2 is disabled or turned off, transistor P2 is not required to supply the supply voltage VDDA to the power rail 230. In some embodiments, when transistor P2 is disabled or turned off, transistor P2 is not required to set and / or adjust the supply voltage VDDSOC to be equal to the supply voltage VDDA.

[0150] In some embodiments, when transistor P3 is disabled or turned off, transistor P3 is not required to supply the supply voltage VDDB to the power rail 230. In some embodiments, when transistor P3 is disabled or turned off, transistor P3 is not required to set and / or adjust the supply voltage VDDSOC to be equal to the supply voltage VDDB.

[0151] Selecting different numbers or different types of transistors in Figure 4 is also within the scope of various embodiments.

[0152] Other configurations, components, or the number of transistors in transistor P2 are within the scope of this disclosure. Other configurations, components, or the number of transistors in transistor P3 are also within the scope of this disclosure.

[0153] In some embodiments, circuit 400 achieves one or more of the benefits described herein.

[0154] Other configurations, components, or the number of components in circuit 400 are also within the scope of this disclosure.

[0155] Figures 5A to 5B are corresponding circuit diagrams of electronic fuse circuits 500A to 500B according to some embodiments.

[0156] In some embodiments, at least one of circuits 500A or 500B is an embodiment of memory device 112 of Figure 1, and therefore similar detailed descriptions are omitted. In some embodiments, at least one of circuits 500A or 500B is an embodiment of one or more memory cells MCBs in at least one of memory cell arrays 110AR of Figure 1, and therefore similar detailed descriptions are omitted.

[0157] In some embodiments, at least one of circuits 500A or 500B is used to store the data signal DIN1.

[0158] Circuit 500A includes an electronic fuse Rfuse coupled between the programmed node PN and the bit line BL0.

[0159] Circuit 500A further includes an n-type metal-oxide semiconductor (NMOS) transistor N0 coupled between the electronic fuse Rfuse and the programmed node PN.

[0160] The gate of NMOS transistor N0 is coupled to word line WL0. The gate of NMOS transistor N0 is used to receive word line signals from word line WL0.

[0161] Two or more circuit elements are considered to be coupled based on direct electrical connection, resistive or reactive electrical connection, or electrical connection including one or more additional circuit elements, so that they can be controlled by a transistor or other switching device, for example, to make them resistive or open circuit.

[0162] The source of the NMOS transistor N0 is coupled to the programmed node PN. In some embodiments, the programmed node PN is coupled to a reference voltage supply VSS. The voltage of the reference voltage supply VSS is the reference voltage VSS'.

[0163] The drain of the NMOS transistor N0 is coupled to the first end of the electronic fuse Rfuse. The second end of the electronic fuse Rfuse is coupled to the bit line BL0. In some embodiments, the bit line BL0 is coupled to a voltage supply VDDQ. The voltage of the voltage supply VDDQ is voltage VDDQ'. In some embodiments, the bit line BL0 is used to provide a current Ifuse.

[0164] In some embodiments, the voltage supply VDDQ includes one or more of power rails 230, 232, or 930. In some embodiments, the supply voltage VDDQ' includes one or more of the supply voltage VDDSOC, supply voltage VQPS, or supply voltage VDDHV (Figure 9).

[0165] Circuit 500B is a variant of circuit 500A. Compared to circuit 500A, a p-type metal-oxide semiconductor (PMOS) transistor P0 replaces the NMOS transistor N0, therefore a similar detailed description is omitted.

[0166] Circuit 500B includes a PMOS transistor P0 coupled between an electronic fuse Rfuse and a programmed node PN.

[0167] The gate of PMOS transistor P0 is coupled to the word line WL0. The gate of PMOS transistor P0 is used to receive the word line signal from the word line WL0.

[0168] The source of the PMOS transistor P0 is coupled to the programmable node PN. In some embodiments, the programmable node PN is coupled to the voltage supply VDDQ.

[0169] The drain of the PMOS transistor P0 is coupled to the first end of the electronic fuse Rfuse. The second end of the electronic fuse Rfuse is coupled to the bit line BL0. In some embodiments, the bit line BL0 is coupled to a reference voltage supply VSS. In some embodiments, the bit line BL0 is used to receive current Ifuse.

[0170] In some embodiments, circuits 500A-500B are some or all of the bit units of a plurality of bit units, wherein each bit unit is coupled to bit line BL0. In some embodiments, bit line BL0 is one of a plurality of bit lines. In some embodiments, circuits 500A-500B are some or all of the bit units of a plurality of bit units of a memory circuit (not shown).

[0171] In some embodiments, the word line WL0 is a word line of the memory circuit, and the word line signal is used to select the bit cell including circuits 500A to 500B in a programming or read operation. In some embodiments, the memory circuit includes one or more sense amplifiers (not shown) used to determine the programming state of circuits 500A to 500B in a read operation.

[0172] An electronic fuse Rfuse is a circuit device comprising a conductive element that can be continuously changed and thus programmed by a current Ifuse having an amplitude exceeding a predetermined current level. In some embodiments, the electronic fuse Rfuse has a smaller resistance in its non-programmed state compared to its resistance in its programmed state.

[0173] Both NMOS transistor N0 and PMOS transistor P0 are programming devices in an IC device, capable of switching between a conducting state and a resistive state in response to an input signal (e.g., a word line signal) received at word line WL0. In the conducting state, the programming device has a low-resistance current path between two current path terminals (unlabeled), and in the resistive state, the programming device has a high-resistance current path between the two current path terminals.

[0174] In a conductive state, the programmed device is capable of having a low-resistance current path only for current values ​​up to a predetermined current saturation level, and a significantly higher relative resistance path for current values ​​above the saturation level. In operation, the programmed device thus limits the value of the current flowing between the two current path terminals in response to an increased voltage difference between the two current path terminals.

[0175] Although Figure 5A shows the programmable device as an NMOS transistor N0 and Figure 5B shows the programmable device as a PMOS transistor P0, in various embodiments, the programmable device includes a transmission gate, a MOS transistor, a field-effect transistor (FET), a FinFET, a bipolar transistor, or other suitable IC device capable of responding to input signals switching between conductive and resistive states.

[0176] In the embodiment depicted in Figure 5A, the NMOS transistor NO is in a conducting state in response to a word line signal with a high logic level and in a resistive state in response to a word line signal with a low logic level.

[0177] In the embodiment depicted in Figure 5B, the PMOS transistor P0 is in a conducting state in response to a word line signal with a low logic level and in a resistive state in response to a word line signal with a high logic level.

[0178] Other configurations, numbers of other fuse elements, or numbers of other transistors in circuits 500A or 500B are also within the scope of this disclosure. For example, at least circuit 500A or 500B includes more than one fuse element (e.g., an electronic fuse Rfuse). For example, at least circuit 500A or 500B includes more than one programmable device (e.g., an NMOS transistor N0 or a PMOS transistor P0).

[0179] Figure 6 is a block diagram of a circuit 600 that can be used in at least Figure 2 or Figure 9 according to some embodiments.

[0180] In some embodiments, circuit 600 may be used as one of the power rail 230, header circuit 204, and bit line driver circuit 210 or word line driver circuit 212 of Figure 1, and therefore similar detailed descriptions are omitted.

[0181] Circuit 600 includes buffer circuit 602, header circuit 204, and power rail 230.

[0182] Buffer circuit 602 is coupled to header circuit 204 via node ND1. Buffer circuit 602 receives supply voltage VDDSOC or VDDHV from corresponding power rails 230 or 930 via header circuit 204. The voltage supply node of buffer circuit 602 is coupled to header circuit 204 via node ND1. In some embodiments, buffer circuit 602 operates at supply voltage VDDSOC or supply voltage VDDHV.

[0183] In some embodiments, buffer circuit 602 is used to receive signal LL1. Buffer circuit 602 is used to generate signal LL2 in response to signal LL1. In some embodiments, signal LL2 is a delayed version of LL1. In some embodiments, buffer circuit 602 is an inverter circuit, and signal LL2 is an inverted version of LL1.

[0184] In some embodiments, the buffer circuit 602 is the bit line driver circuit 210 of Figures 2 and 9, and the buffer circuit 602 is used to generate bit line signals BL (e.g., signal LL2).

[0185] In some embodiments, the buffer circuit 602 is the character line driver circuit 212 of Figures 2 and 9, and the buffer circuit 602 is used to generate character line signals WL (e.g., signal LL2).

[0186] In some embodiments, the buffer circuit 602 is the bit line driver circuit 210 of Figure 2 or Figure 9, and the signal LL2 is at least one of the bit line signal BL in Figure 2 or the bit line signal BL1 or BL2 in Figure 9, so similar detailed descriptions are omitted.

[0187] In some embodiments, the buffer circuit 602 is the character line driver circuit 212 of Figure 2 or Figure 9, and the signal LL2 is at least one of the character line signal WL of Figure 2 or the character line signal WL1 or WL2 of Figure 9, therefore similar detailed descriptions are omitted.

[0188] The selection of different numbers or types of circuit elements in Figure 6 is also within the scope of various embodiments.

[0189] In some embodiments, circuit 600 achieves one or more of the benefits described herein.

[0190] Other configurations, components, or the number of components in circuit 600 are also within the scope of this disclosure.

[0191] Figure 7 is a timing diagram 700 of the waveforms of an integrated circuit according to some embodiments.

[0192] In some embodiments, Figure 7 is a timing diagram 700 of the waveforms of the integrated circuit 200 in Figure 2.

[0193] In some embodiments, one or more power-down operations, standby operations, read operations, and write / programming operations are applied to memory cells in the memory cell array 208 of Figure 2 or at least one memory cell in a single row of the memory cell array 110AR of Figure 1, and timing diagram 700 corresponds to the waveforms during one or more power-down operations, standby operations, read operations, or write / programming operations of at least one memory cell in a single row of the memory cell array 208 of Figure 2 or the memory cell array 110AR of Figure 1.

[0194] In some embodiments, one or more power-down operations, standby operations, read operations, or write / programming operations of the memory bank in at least one memory circuit 100 of Figure 1 are applied to at least one of memory partitions 102A, 102B, 102C, or 102D, and timing diagram 700 corresponds to the waveforms during the power-down operation, standby operation, read operation, or write / programming operation of at least one of memory partitions 102A, 102B, 102C, and 102D.

[0195] Timing diagram 700 includes the waveforms of supply voltage VDDSOC, voltage VUT, or voltage VW.

[0196] In some embodiments, the supply voltage VDDSOC ranges from approximately the reference voltage VSS to approximately the voltage VUT.

[0197] In some embodiments, voltage VUT is greater than voltage VW. In some embodiments, voltage VUT is the maximum voltage of one or more circuit elements in integrated circuit 200, and therefore a similar detailed description is omitted. In some embodiments, voltage VW is the operating voltage of one or more circuit elements in integrated circuit 200, and therefore a similar detailed description is omitted. In some embodiments, voltage VW is the threshold voltage of one or more circuit elements in integrated circuit 200, and therefore a similar detailed description is omitted.

[0198] In some embodiments, the voltage VUT ranges from about 0.6 volts to about 2.0 volts. In some embodiments, the voltage VW ranges from about 0.4 volts to about 1.8 volts.

[0199] Before time T0, the supply voltage VDDSOC is substantially equal to the reference supply voltage VSS (e.g., 0 volts).

[0200] In some embodiments, if the first element and the second element differ from each other by an amount equal to +10% or -10%, then the first element is substantially equal to the second element.

[0201] At time T0, the supply voltage VDDSOC changes from the reference supply voltage VSS (e.g., 0 volts) to voltage VW.

[0202] At time T1a, the supply voltage VDDSOC is essentially equal to the voltage VW.

[0203] Between time T1a and T1b, the supply voltage VDDSOC is essentially equal to the voltage VW.

[0204] In some embodiments, between time T0 and T1b, one or more circuit elements in the integrated circuit 200 are configured in a power-off, shutdown, or sleep mode. In some embodiments, when the supply voltage VDDSOC of Figures 2 and 8 is substantially equal to the supply voltage VDDA (e.g., voltage VL in Figure 7), one or more circuit elements in the integrated circuit 200 are configured in a power-off, shutdown, or sleep mode.

[0205] At time T1b, the supply voltage VDDSOC changes from voltage VW to voltage VUT.

[0206] Between time T1b and T2, the supply voltage VDDSOC is essentially equal to the voltage VUT.

[0207] In some embodiments, between time T1b and T2, one or more circuit elements in integrated circuit 200 are configured in read mode. In some embodiments, when the supply voltage VDDSOC of Figures 2 and 8 is substantially equal to the supply voltage VDDB (e.g., the voltage VUT in Figure 7), one or more circuit elements in integrated circuit 200 are configured in read mode, standby mode, or programmed mode.

[0208] Between time T2 and T3, the supply voltage VDDSOC is essentially equal to the voltage VUT.

[0209] In some embodiments, between time T2 and T3, one or more circuit elements in the integrated circuit 200 are configured in a standby mode.

[0210] At time T3, the supply voltage VDDSOC changes from voltage VUT to voltage VL. In some embodiments, voltage VL is less than voltage VW and greater than the reference supply voltage VSS.

[0211] Between time T3 and T4, the supply voltage VDDSOC is essentially equal to the voltage VL.

[0212] At time T4, the supply voltage VDDSOC changes from voltage VL to voltage VUT.

[0213] In some embodiments, between time T3 and T4, one or more circuit elements in integrated circuit 200 are configured in a power-off, shutdown, or sleep mode. In some embodiments, when the supply voltage VDDSOC of Figures 2 and 8 is substantially equal to the supply voltage VDDA, one or more circuit elements in integrated circuit 200 are configured in a power-off, shutdown, or sleep mode.

[0214] Between time T4 and T5, the supply voltage VDDSOC is essentially equal to the voltage VUT.

[0215] In some embodiments, between time T4 and T5, one or more circuit elements in the integrated circuit 200 are configured in a programmed mode.

[0216] In some embodiments, waveform 700 is repeated after time T5, and is therefore similar to time T0, so a similar detailed description is omitted.

[0217] In some embodiments, timing diagram 700 enables integrated circuit 200 to achieve at least one or more of the benefits described herein.

[0218] In some embodiments, although timing diagram 700 is described for integrated circuit 200, timing diagram 700 is also applicable to circuits 300A-300B and circuit 400 in a similar manner, and will not be described further for the sake of brevity.

[0219] Other configurations of timing diagram 700 are also within the scope of this disclosure.

[0220] Figure 8 is a flowchart of a method 800 of an operating circuit according to some embodiments.

[0221] In some embodiments, Figure 8 is a flowchart of a method 800 for operating at least one of the memory circuit 100 of Figure 1, the integrated circuit 200 of Figure 2, the circuit 300A of Figure 3A, the circuit 300B of Figure 3B, the circuit 400 of Figure 4, or the circuit 600 of Figure 6. For the sake of brevity, similar detailed descriptions are omitted.

[0222] In some embodiments, Figure 8 is a flowchart of a method 800 for operating an integrated circuit, which includes one or more features of the timing diagram 700 in Figure 7. For the sake of brevity, similar detailed descriptions are omitted.

[0223] It should be understood that additional operations may be performed before, during, and / or after method 800 shown in Figure 8, and only a few of these additional operations may be briefly described herein. It should be understood that method 800 utilizes features of at least one of the memory circuit 100 of Figure 1, the integrated circuit 200 of Figure 2, the circuit 300 of Figure 3, the circuit 400 of Figure 4, the circuit 600 of Figure 6, or the timing diagram 700 of Figure 7, and similar detailed descriptions are omitted for brevity.

[0224] In some embodiments, other orders of operation of method 800 are also within the scope of this disclosure. Method 800 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, reordered, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more of the operations of method 800 are not performed.

[0225] In operation 802 of method 800, the first controller sets the first supply voltage.

[0226] In some embodiments, the first supply voltage of method 800 includes at least the supply voltage VDDSOC. In some embodiments, the first controller of method 800 includes the controller 1300 of Figure 13.

[0227] In some embodiments, the first controller sets the first supply voltage to a first voltage level or a second voltage level. In some embodiments, the first voltage level of method 800 includes voltage VDDA. In some embodiments, the second voltage level of method 800 includes voltage VDDB.

[0228] In some embodiments, operation 802 further includes setting a second supply voltage by means of a first controller. In some embodiments, the second supply voltage of method 800 includes at least a supply voltage VQPS.

[0229] In some embodiments, operation 802 further includes adjusting the first supply voltage from a first voltage level to a second voltage level, and vice versa.

[0230] In operation 804 of method 800, a first supply voltage is received by a first power supply gate circuit.

[0231] In some embodiments, the first power gate circuit of method 800 includes one or more of header circuit 204, circuit 300A, circuit 300B, or circuit 400. In some embodiments, the first power gate circuit of method 800 includes one or more of the memory circuit 202 elements.

[0232] In operation 806 of method 800, it is determined whether the first supply voltage is less than the first threshold value.

[0233] In some embodiments, if the determination of operation 806 is "yes", then method 800 proceeds to operation 808. In some embodiments, if the determination of operation 806 is "no", then method 800 proceeds to operation 814.

[0234] In some embodiments, the first threshold value of method 800 includes at least the voltage VW shown in Figure 7.

[0235] In some embodiments, if the first supply voltage is set to a first voltage level (e.g., voltage VDDA), and the first supply voltage is less than a first threshold value (e.g., voltage VW), then method 800 proceeds to operation 808.

[0236] In some embodiments, if the first supply voltage is set to a second voltage level (e.g., voltage VDDB), then the first supply voltage is greater than or equal to a first threshold value (e.g., voltage VW), and then method 800 proceeds to operation 814.

[0237] In some embodiments, operation 806 is performed automatically based on the value of the first supply voltage. In some embodiments, operation 806 is not performed.

[0238] In operation 808 of method 800, the control signal is set to the first logic state.

[0239] In some embodiments, operation 808 includes setting a control signal to a first logic state in response to a first supply voltage being less than a first threshold value.

[0240] In some embodiments, the control signals of method 800 include one or more of control signals PD1, PD2, PD3, PD4, or PD5. In some embodiments, the first logic state of method 800 is a high logic state or logic 1.

[0241] In some embodiments, a control signal is set or adjusted by a second controller. In some embodiments, the second controller of method 800 includes the controller 1300 of Figure 13.

[0242] In operation 810 of method 800, the first power supply gate circuit receives a control signal and responds to the control signal by turning off or disabling the first power supply gate circuit.

[0243] In some embodiments, operation 810 includes receiving a control signal via a first power gate circuit and turning off or disabling the first power gate circuit in response to a first logic state of the control signal.

[0244] In some embodiments, operation 810 includes the set of inverters 302 receiving a control signal PD1, and transistor P1 being turned off or disabled based on the logic state of at least one of the control signals PD1, PD2, PD3, PD4, or PD5.

[0245] In some embodiments, operation 810 includes the set of inverters 322 receiving control signal PD5, and transistor P1 being turned off or disabled based on the logic state of at least one of control signals PD1, PD2, PD3, PD4, or PD5.

[0246] In operation 812 of method 800, one or more components in memory circuit 202 enter a power-off mode.

[0247] In some embodiments, the power-off mode is also referred to as the shutdown mode or sleep mode.

[0248] In operation 814 of method 800, the control signal is set to the second logic state.

[0249] In some embodiments, operation 814 includes setting a control signal to a second logic state in response to a first supply voltage being greater than or equal to a first threshold value.

[0250] In some embodiments, the second logic state of method 800 is a low logic state or logic 0.

[0251] In operation 816 of method 800, the first power supply control circuit receives a control signal and responds to the control signal by turning on or enabling the first power supply control circuit.

[0252] In some embodiments, operation 816 includes receiving a control signal via a first power gate circuit and turning on or enabling the first power gate circuit in response to a second logic state of the control signal.

[0253] In some embodiments, operation 816 includes the set of inverters 302 receiving a control signal PD1, and transistor P1 being turned on or enabled based on the logic state of at least one of the control signals PD1, PD2, PD3, PD4, or PD5.

[0254] In some embodiments, operation 816 includes the set of inverters 322 receiving control signal PD5, and transistor P1 being turned on or enabled based on the logic state of at least one of control signals PD1, PD2, PD3, PD4, or PD5.

[0255] In operation 818 of method 800, one or more elements in memory circuit 202 enter programming mode, read mode, or standby mode.

[0256] The benefits described herein are achieved by operating at least one of the memory circuit 100 of Figure 1, the integrated circuit 200 of Figure 2, the circuit 300A of Figure 3A, the circuit 300B of Figure 3B, the circuit 400 of Figure 4, or the circuit 600 of Figure 6 through operation method 800.

[0257] Figure 9 is a circuit diagram of an integrated circuit 900 according to some embodiments.

[0258] In some embodiments, integrated circuit 900 may be used in Figure 1. Integrated circuit 900 is an embodiment of circuit 120 in Figure 1, therefore a similar detailed description is omitted.

[0259] In some embodiments, the integrated circuit 900 is an embodiment of at least a portion of one or more of the memory partitions 102A, 102B, 102C, or 102D of Figure 1, and therefore similar detailed descriptions are omitted. In some embodiments, the integrated circuit 900 is an embodiment of the memory cell array 110AR of Figure 1, the LIO circuit 110BS of Figure 1, and the WL driver circuit 110AC of Figure 1, and therefore similar detailed descriptions are omitted.

[0260] Integrated circuit 900 is a variant of integrated circuit 200 in Figure 2, therefore a similar detailed description is omitted. For example, integrated circuit 900 is illustrated in a non-limiting example, wherein integrated circuit 900 further includes a set of level shifter circuits 910 and a set of level shifter circuits 920, therefore a similar detailed description is omitted.

[0261] Compared to the integrated circuit 200 in Figure 2, the integrated circuit 900 further includes a set of level shifter circuits 910 and a set of level shifter circuits 920, therefore a similar detailed description is omitted.

[0262] Compared to the integrated circuit 200 in Figure 2, the memory circuit 902 of the integrated circuit 900 replaces the memory circuit 202 in Figure 2, therefore a similar detailed description is omitted.

[0263] The integrated circuit 900 includes a memory circuit 902 and a core device assembly 220.

[0264] The memory circuit 902 includes memory circuit 202, a set of level shifter circuits 910, a set of level shifter circuits 920, and a power rail 930. In some embodiments, memory circuit 202 is not part of memory circuit 902, and therefore similar detailed descriptions are omitted.

[0265] The memory circuit 202 includes a header circuit 204, a power switch 206, a memory cell array 208, a bit line driver circuit 210, a word line driver circuit 212, a control circuit 214, a power rail 230, and a power rail 232.

[0266] The power rail 930 has a supply voltage VDDHV. In some embodiments, the supply voltage VDDHV is greater than the supply voltage VDDSOC and less than the supply voltage VQPS. In some embodiments, the supply voltage VDDHV ranges from about 0.45 volts to about 1.0 volt. In some embodiments, the supply voltage VQPS ranges from about 1.5 volts to about 2.0 volts. In some embodiments, the supply voltage VQPS ranges from about 3.5 volts to about 4.5 volts. In some embodiments, the supply voltage VDDSOC ranges from about 0.45 volts to about 1.0 volt. Other supply voltage values ​​for VDDHV, VQPS, or VDDSOC are also within the scope of this disclosure.

[0267] The memory circuit 902 is coupled to the power rail 230 and the core device assembly 220.

[0268] Memory circuit 902 is used to receive supply voltage VDDSOC from power rail 230. In some embodiments, memory circuit 902 is used to supply supply voltage VDDSOC to level shifter circuit assembly 910 and level shifter circuit assembly 920.

[0269] In some embodiments, the memory circuit 902 is configured to operate on a supply voltage VDDSOC received from the power rail 230.

[0270] In some embodiments, the supply voltage VDDSOC is adjusted from the supply voltage VDDA to the supply voltage VDDB, and vice versa. In some embodiments, the supply voltage VDDSOC is set and adjusted by a circuit (such as controller 1300 in Figure 13). In some embodiments, the supply voltage VDDSOC is set and adjusted by a circuit (such as circuit 400 in Figure 4). Further details of adjusting the supply voltage VDDSOC are described at least in Figure 2, therefore similar detailed descriptions are omitted.

[0271] The level shifter circuit assembly 910 is coupled between memory circuit 902 and memory circuit 202. In some embodiments, the level shifter circuit assembly 910 is coupled between power rail 230 and power rail 930.

[0272] The level shifter circuit 910 is directly coupled to one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, or power switch 206.

[0273] In some embodiments, the set of level shifter circuits 910 includes at least one of level shifter circuits 910a, 910b, or 910c. Other numbers of level shifters in the set of level shifter circuits 910 are also within the scope of this disclosure.

[0274] In some embodiments, at least one level shifter in the set of level shifter circuits 910 is used to receive a set of signals S1. In some embodiments, at least one level shifter in the set of level shifter circuits 910 is used to receive a set of signals S1 from one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, or power switch 206.

[0275] In some embodiments, at least one level shifter in the set of level shifter circuits 910 is used to generate a set of signals S2 in response to a set of signals S1. In some embodiments, at least one level shifter in the set of level shifter circuits 910 is used to output the set of signals S2 to one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, or power switch 206.

[0276] In some embodiments, the signal set S1 includes one or more of the following: sense amplifier signal SAE1, bit line signal BL1, word line signal WL1, control signal CS1, or input data DIN1.

[0277] In some embodiments, the signal set S2 includes one or more of the following: sense amplifier signal SAE2, bit line signal BL2, word line signal WL2, control signal CS2, or input data DIN1.

[0278] In some embodiments, signal set S1 has a first voltage swing (VSS to VDDSOC), and signal set S2 has a second voltage swing (VSS to VDDHV). In some embodiments, the second voltage swing is different from the first voltage swing.

[0279] In some embodiments, the range of the first voltage swing is from the reference supply voltage VSS to the supply voltage VDDSOC, and the range of the second voltage swing is from the reference supply voltage VSS to the supply voltage VDDHV.

[0280] In some embodiments, the level shifter circuitry 910 is coupled to power rails 230 and 930. In some embodiments, the level shifter circuitry 910 is used to receive a supply voltage VDDSOC from power rail 230 and a supply voltage VDDHV from power rail 930.

[0281] The set of level shifter circuits 910 is used to shift the set of signals S1 from the VDDSOC voltage domain using the supply voltage VDDSOC to the VDDHV voltage domain using the supply voltage VDDHV (e.g., the set of signals S2). In some embodiments, the set of signals S2 is referred to as the level-shifted output signal.

[0282] Other configurations, elements, or number of elements in the assembly 910 of level shifter circuits are also within the scope of this disclosure. In some embodiments, at least one level shifter in the assembly 910 of level shifter circuits is replaced by one or more of a charge pump circuit or a boost circuit.

[0283] The level shifter circuit assembly 920 is coupled between memory circuit 202 and memory circuit 902. In some embodiments, the level shifter circuit assembly 920 is coupled between power rail 930 and power rail 230.

[0284] The level shifter circuit 920 is directly coupled to one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, or power switch 206.

[0285] In some embodiments, the set of level shifter circuits 920 includes at least one of level shifter circuits 920a, 920b, or 920c. Other numbers of level shifters in the set of level shifter circuits 920 are also within the scope of this disclosure.

[0286] In some embodiments, at least one level shifter in the set of level shifter circuits 920 is used to receive a set of signals C1. In some embodiments, at least one level shifter in the set of level shifter circuits 920 is used to receive a set of signals C1 from one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, or power switch 206.

[0287] In some embodiments, at least one level shifter in the set of level shifter circuits 920 is used to generate a set of signals C2 in response to a set of signals C1. In some embodiments, at least one level shifter in the set of level shifter circuits 920 is used to output the set of signals C2 to one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, or power switch 206.

[0288] In some embodiments, the set of signals C1 includes one or more of the following: sense amplifier signal SAE1, bit line signal BL1, word line signal WL1, control signal CC1, or input data DIN1.

[0289] In some embodiments, the signal set C2 includes one or more of the following: sense amplifier signal SAE2, bit line signal BL2, word line signal WL2, control signal CC2, or input data DIN1.

[0290] In some embodiments, the signal set C1 has a second voltage swing (VSS to VDDHV), and the signal set C2 has a first voltage swing (VSS to VDDSOC).

[0291] In some embodiments, the level shifter circuitry 920 is coupled to power rails 930 and 230. In some embodiments, the level shifter circuitry 920 is used to receive a supply voltage VDDSOC from power rail 230 and a supply voltage VDDHV from power rail 930.

[0292] The set of level shifter circuits 920 is used to shift the set of signals C1 from the VDDHV voltage domain using the supply voltage VDDHV to the VDDSOC voltage domain using the supply voltage VDDSOC (e.g., the set of signals C2). In some embodiments, the set of signals C2 is referred to as the level-shifted output signal.

[0293] Other configurations, components, or number of components in the assembly 920 of level shifter circuits are also within the scope of this disclosure. In some embodiments, at least one level shifter in the assembly 920 of level shifter circuits is replaced by one or more of a low-dropout (LDO) regulator circuit or a buck circuit.

[0294] As shown in Figure 9, memory circuit 202 is coupled to power rails 930 and 232, and to level shifter circuits 910 and 920.

[0295] As shown in Figure 9, memory circuit 202 is used to receive supply voltage VDDHV from power rail 930 and supply voltage VQPS from power rail 232.

[0296] In some embodiments, the memory circuit 202 of Figure 9 is used to operate on a supply voltage VDDHV received from power rail 930 or a supply voltage VQPS received from power rail 232.

[0297] As shown in Figure 9, header circuit 204 is coupled to power rail 930. As shown in Figure 9, header circuit 204 is used to receive supply voltage VDDHV from power rail 930. As shown in Figure 9, header circuit 204 is used to supply at least supply voltage VDDHV to node ND1.

[0298] In some embodiments, as shown in Figure 9, header circuit 204 supplies a supply voltage VDDHV to at least one of memory cell array 208, bit line driver circuit 210, word line driver circuit 212, or control circuit 214 in response to control signal PD1 (e.g., Figure 3A) or control signal PD5 (e.g., Figure 3B). In some embodiments, header circuit 204 is also referred to as a power gate circuit.

[0299] As shown in Figure 9, the header circuit 204 is further coupled to one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, or control circuit 214 via node ND1. In some embodiments, as shown in Figure 9, the header circuit 204 is used to supply a supply voltage VDDHV to at least one of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, or control circuit 214 via node ND1.

[0300] In some embodiments, as shown in Figure 9, at least one of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, or control circuit 214 is used to operate on the supply voltage VDDHV received from the header circuit 204.

[0301] Other configurations, components, or the number of components in header circuit 204 are also within the scope of this disclosure.

[0302] As shown in Figure 9, the memory cell array 208 is used to receive the supply voltage VDDHV from the header circuit 204 via node ND1.

[0303] Other configurations, elements, or number of elements in the memory cell array 208 are also within the scope of this disclosure.

[0304] As shown in Figure 9, the bit line driver circuit 210 is used to receive the supply voltage VDDHV.

[0305] Other configurations, components, or number of components in the bit line driver circuit 210 are also within the scope of this disclosure.

[0306] As shown in Figure 9, the character line driver circuit 212 is used to receive the supply voltage VDDHV.

[0307] Other configurations, components, or number of components in the character line driver circuit 212 are also within the scope of this disclosure.

[0308] As shown in Figure 9, the control circuit 214 is used to receive the supply voltage VDDHV.

[0309] In some embodiments, as shown in Figure 9, the sensing amplifier circuit 214a is used to receive the supply voltage VDDHV.

[0310] In some embodiments, control circuitry 214 includes other types of circuitry. In some embodiments, control circuitry 214 includes at least one level shifter similar to a set of level shifter circuits 910 or 920, therefore a similar detailed description is omitted.

[0311] Other configurations, components, or number of components in the control circuit 214 or the sensing amplifier circuit 214a are also within the scope of this disclosure.

[0312] Other configurations, components, or the number of components in memory circuit 202 are also within the scope of this disclosure.

[0313] In some embodiments, at least one transistor in at least one of the level shifter circuits 910 or 920 has a threshold voltage VT1. In some embodiments, at least one transistor in the header circuit 204, memory cell array 208, bit line driver circuit 210, word line driver circuit 212, sense amplifier 214a of control circuit 214, or power switch 206 has a threshold voltage VT2. In some embodiments, the threshold voltage VT2 is greater than the threshold voltage VT1.

[0314] In some embodiments, by configuring either the set of level shifter circuits 910 or the set of level shifter circuits 920 to have a different threshold voltage than the memory circuit 202, the set of core circuits 220 and the memory circuit 902 are allowed to operate in a voltage range lower than that of the memory circuit 202, thereby reducing the power consumption of the set of core circuits 220 at least compared to other methods.

[0315] In some embodiments, by configuring the memory circuit 202 with the header circuit 204, leakage current in the path including node ND1 is reduced when one or more of the memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, or power switch 206 is disabled or in sleep mode (e.g., power-off mode), thereby reducing the power consumption of the integrated circuit 900 compared to other methods with higher leakage current and greater power consumption.

[0316] In some embodiments, the integrated circuit 900 achieves one or more of the benefits described herein.

[0317] Other configurations, components, or number of components in the integrated circuit 900 are also within the scope of this disclosure.

[0318] Figure 10 is a circuit diagram of a level shifter circuit 1000 according to some embodiments.

[0319] Level shifter circuit 1000 is an embodiment of one or more level shifter circuits 910a, 910b, or 910c in the set of level shifter circuits 910, and similar detailed descriptions are omitted.

[0320] Level shifter circuit 1000 is an embodiment of one or more level shifter circuits 920a, 920b, or 920c in the set of level shifter circuits 920, and similar detailed descriptions are omitted.

[0321] The level shifter circuit 1000 is used to receive the signal LSin and generate the signal LSout. The level shifter circuit 1000 is a level shifter used to shift the signal from a first voltage domain VXX using a supply voltage VXX1 to a second voltage domain VYY using a supply voltage VYY1.

[0322] In some embodiments, the first voltage domain VXX is the voltage domain VDD, the supply voltage VXX1 is the supply voltage VDD1, the second voltage domain VYY is the voltage domain VDDM, the supply voltage VYY1 is the supply voltage VDDM1, and the level shifter circuit 1000 is used to shift the signal from the voltage domain VDD using the supply voltage VDD1 to the voltage domain VDDM using the supply voltage VDDM1. For example, in these embodiments, the level shifter circuit 1000 is an embodiment of one or more level shifter circuits 910a, 910b, or 910c in the set of level shifter circuits 910, and similar detailed descriptions are omitted. For example, in these embodiments, when the level shifter circuit 1000 is an embodiment of one or more level shifter circuits 910a, 910b, or 910c in the set of level shifter circuits 910, the signal LSin corresponds to one or more of the sense amplifier signal SAE1, bit line signal BL1, word line signal WL1, control signal CS1, or input data DIN1, and the signal LSout corresponds to one or more of the bit line signal BL2, word line signal WL2, control signal CS2, or input data DIN1.

[0323] In some embodiments, the voltage domain VDD includes the supply voltage VDDSOC, and the voltage domain VDDM includes the supply voltage VDDHV; therefore, a similar detailed description is omitted.

[0324] In some embodiments, the first voltage domain VXX is the voltage domain VDDM, the supply voltage VXX1 is the supply voltage VDDM1, the second voltage domain VYY is the voltage domain VDD, the supply voltage VYY1 is the supply voltage VDD1, and the level shifter circuit 1000 is used to shift the signal from the voltage domain VDDM using the supply voltage VDDM1 to the voltage domain VDD using the supply voltage VDD1. For example, in these embodiments, the level shifter circuit 1000 is an embodiment of one or more level shifter circuits 920a, 920b, or 920c in the set of level shifter circuits 920, and similar detailed descriptions are omitted. For example, in these embodiments, when the level shifter circuit 1000 is an embodiment of one or more level shifter circuits 920a, 920b, or 920c in the set of level shifter circuits 920, the signal LSin corresponds to one or more of the sense amplifier signal SAE2, bit line signal BL1, word line signal WL1, control signal CS1, or input data DIN1, and the signal LSout corresponds to one or more of the bit line signal BL2, word line signal WL2, control signal CS2, or input data DIN1.

[0325] The level shifter circuit 1000 receives the signal LSin at an input terminal (unlabeled) and outputs the signal LSout at an output terminal (unlabeled). The signal LSin corresponds to the input signal of the level shifter circuit 1000, and the signal LSout corresponds to the output signal of the level shifter circuit 1000. The level shifter circuit 1000 generates the signal LSout based on the signal LSin.

[0326] The signal LSout corresponds to a level-shifted version of the signal LSin. In some embodiments, the voltage level of the signal LSin in the level shifter circuit 1000 is lower than the voltage level of the signal LSout in the level shifter circuit 1000. In some embodiments, the voltage level of the signal LSin in the level shifter circuit 1000 is higher than the voltage level of the signal LSout in the level shifter circuit 1000.

[0327] The level shifter circuit 1000 includes an inverter 1002, an NMOS transistor 1004, a PMOS transistor 1006, a PMOS transistor 1008, a PMOS transistor 1010, a PMOS transistor 1012, an NMOS transistor 1014, and an inverter 1016.

[0328] The input terminal of inverter 1002 is used to receive the signal LSin. The input terminal of inverter 1002, the gate terminal of PMOS transistor 1006, and the gate terminal of NMOS transistor 1004 are each coupled to each other. The output terminal of inverter 1002 is used to output the signal LSBin. In some embodiments, the signal LSBin is an inverted version of the signal LSin. Inverter 1002 is used to generate the signal LSBin based on the signal CKPI. Inverter 1002 is coupled to a voltage supply VXX. In some embodiments, inverter 1002 is a CMOS inverter type coupled to both the voltage supply VXX and a reference voltage supply VSS.

[0329] The gate terminal of NMOS transistor 1004 is used to receive the signal LSin. The source terminal of NMOS transistor 1004 is coupled to the reference voltage supply VSS. The drain terminal of NMOS transistor 1004, the drain terminal of PMOS transistor 1006, the gate terminal of PMOS transistor 1010, and the input terminal of inverter 1016 are all coupled together at node 10-N1.

[0330] The gate terminal of PMOS transistor 1006 is used to receive the signal LSin. The source terminal of PMOS transistor 1006 is coupled to the drain terminal of PMOS transistor 1008.

[0331] The source terminal of PMOS transistor 1008 is coupled to a voltage supply VYY. The gate terminal of PMOS transistor 1008, the drain terminal of NMOS transistor 1014, and the drain terminal of PMOS transistor 1012 are each coupled to each other at node 10-N2. The gate terminal of PMOS transistor 1008 is used to receive voltage at node 10-N2. In some embodiments, PMOS transistor 1008 is turned on or off based on the voltage at node 10-N2.

[0332] NMOS transistors 1004, 1006, and 1008 are used to set the voltage of node 10-N1 corresponding to the signal LSBout. For example, in some embodiments, if NMOS transistor 1004 is turned on, it pulls node 10-N1 towards the reference voltage VSS. For example, in some embodiments, if PMOS transistors 1006 and 1008 are turned on, they pull node 10-N1 towards the supply voltage VYY1.

[0333] The source terminal of PMOS transistor 1010 is coupled to a voltage supply VYY. The drain terminal of PMOS transistor 1010 is coupled to the source terminal of PMOS transistor 1012. The gate terminal of PMOS transistor 1010 is coupled to at least node 10-N1. The voltage at node 10-N1 corresponds to the signal LSBout. The gate terminal of PMOS transistor 1010 is used to receive the signal LSBout. In some embodiments, PMOS transistor 1010 is turned on or off based on the voltage at node 10-N1 (corresponding to the signal LSBout).

[0334] The gate terminal of PMOS transistor 1012 is used to receive the signal LSBin from inverter 1002. The gate terminals of PMOS transistor 1012, NMOS transistor 1014, and inverter 1002 are all coupled to each other.

[0335] The gate terminal of NMOS transistor 1014 is used to receive the signal LSBin from inverter 1002. The source terminal of NMOS transistor 1014 is coupled to the reference voltage supply VSS.

[0336] NMOS transistors 1014, 1010, and 1012 are used to set the voltage at node 10-N1 corresponding to the signal LSBout. For example, in some embodiments, if NMOS transistor 1014 is turned on, it pulls node 10-N2 towards the reference voltage VSS. For example, in some embodiments, if PMOS transistors 1010 and 1012 are turned on, they pull node 10-N2 towards the supply voltage VYY1.

[0337] The input terminal of inverter 1016 is used to receive the signal LSBout from node 10-N1. The output terminal of inverter 1016 is used to output the signal LSout. In some embodiments, the signal LSout is an inverted version of the signal LSBout. Inverter 1016 is used to generate the signal LSout based on the signal LSBout. Inverter 1016 is coupled to a voltage supply VYY. In some embodiments, inverter 1016 is a CMOS inverter type coupled to the voltage supply VYY and a reference voltage VSS. The signal LSout corresponds to the output signal of the level shifter circuit 1000. The signal LSout is a level-shifted version of the signal LSin.

[0338] Other configurations and types of level shifters used in the level shifter circuit 1000 are also within the scope of this disclosure.

[0339] In some embodiments, the level shifter circuit 1000 achieves one or more of the benefits described herein.

[0340] Other configurations, components, or the number of components in the level shifter circuit 1000 are also within the scope of this disclosure.

[0341] Figure 11 is a timing diagram 1100 of the waveforms of an integrated circuit according to some embodiments.

[0342] In some embodiments, Figure 11 is a timing diagram 1100 of the waveforms of the integrated circuit 900 in Figure 9.

[0343] In some embodiments, one or more power-down operations, standby operations, read operations, and write / programming operations are applied to at least one memory cell in a single row of the memory cell array 208 of Figure 9 or the memory cell array 110AR of Figure 1, and timing diagram 1100 corresponds to the waveforms during one or more power-down operations, standby operations, read operations, or write / programming operations of at least one memory cell in a single row of the memory cell array 208 of Figure 9 or the memory cell array 110AR of Figure 1.

[0344] In some embodiments, one or more power-down operations, standby operations, read operations, or write / programming operations of the memory bank in at least memory circuit 100 of Figure 1 are applied to at least one of memory partitions 102A, 102B, 102C, or 102D, and timing diagram 1100 corresponds to the waveforms during the power-down operation, standby operation, read operation, or write / programming operation of at least one of memory partitions 102A, 102B, 102C, and 102D.

[0345] Timing diagram 1100 includes waveforms of supply voltage VDDSOC, supply voltage VDDHV, or supply voltage VDDRV. In some embodiments, the supply voltage VDDHV is substantially equal to a voltage level (e.g., voltage VUT). In some embodiments, the supply voltage VDDSOC ranges from approximately a reference voltage supplied to VSS to approximately a voltage VW.

[0346] In some embodiments, voltage VUT is greater than voltage VW. In some embodiments, voltage VUT is the voltage of one or more circuit elements in integrated circuit 900, and therefore a similar detailed description is omitted. In some embodiments, voltage VW is the operating voltage of one or more circuit elements in integrated circuit 900, and therefore a similar detailed description is omitted. In some embodiments, voltage VW is the threshold voltage of one or more circuit elements in integrated circuit 900, and therefore a similar detailed description is omitted.

[0347] In some embodiments, the voltage VUT ranges from about 0.6 volts to about 2.0 volts. In some embodiments, the voltage VW ranges from about 0.4 volts to about 1.8 volts.

[0348] From time T0 to time T5, the supply voltage VDDHV is substantially equal to the voltage VUT. In some embodiments, the supply voltage VDDHV is a level-shifted version of the supply voltage VDD SOC, denoted as "L / S" in Figure 11, and therefore a similar detailed description is omitted.

[0349] Before time T0, the supply voltage VDDSOC is substantially equal to the reference supply voltage VSS (e.g., 0 volts).

[0350] At time T0, the supply voltage VDDSOC changes from the reference supply voltage VSS (e.g., 0 volts) to voltage VL.

[0351] At time T1a, the supply voltage VDDSOC is essentially equal to the voltage VL.

[0352] Between time T1a and T1b, the supply voltage VDDSOC changes from voltage VL to voltage VW.

[0353] In some embodiments, between time T0 and T1b, one or more circuit elements in the integrated circuit 900 are configured in a power-off, shutdown, or sleep mode. In some embodiments, when the supply voltage VDDSOC of Figures 9 and 8 is substantially equal to the supply voltage VDDA (e.g., voltage VL in Figure 11), one or more circuit elements in the integrated circuit 900 are configured in a power-off, shutdown, or sleep mode.

[0354] At time T1b, the supply voltage VDDSOC is essentially equal to the voltage VW.

[0355] Between time T1b and T2, the supply voltage VDDSOC is essentially equal to the voltage VW.

[0356] In some embodiments, between time T1b and T2, one or more circuit elements in the integrated circuit 900 are configured in read mode. In some embodiments, when the supply voltage VDDSOC in Figures 9 and 8 is substantially equal to the supply voltage VDDB (e.g., the voltage VW in Figure 7), one or more circuit elements in the integrated circuit 900 are configured in read mode, standby mode, or programmed mode.

[0357] Between time T2 and T3, the supply voltage VDDSOC is essentially equal to the voltage VW.

[0358] In some embodiments, between time T2 and T3, one or more circuit elements in the integrated circuit 900 are configured in a standby mode.

[0359] At time T3, the supply voltage VDDSOC changes from voltage VW to voltage VL. In some embodiments, voltage VL is less than voltage VW and greater than the reference supply voltage VSS.

[0360] Between time T3 and T4, the supply voltage VDDSOC is essentially equal to the voltage VL.

[0361] At time T4, the supply voltage VDDSOC changes from voltage VL to voltage VP. In some embodiments, voltage VP is greater than voltage VL and less than voltage VW.

[0362] In some embodiments, between time T3 and T4, one or more circuit elements in the integrated circuit 900 are configured in a power-off, shutdown, or sleep mode. In some embodiments, when the supply voltage VDDSOC in Figures 9 and 8 is substantially equal to the supply voltage VDDA, one or more circuit elements in the integrated circuit 900 are configured in a power-off, shutdown, or sleep mode.

[0363] Between time T4 and T5, the supply voltage VDDSOC is substantially equal to the voltage VP. In some embodiments, between time T4 and T5, the supply voltage VDDSOC is substantially equal to the voltage VW.

[0364] In some embodiments, between time T4 and T5, one or more circuit elements in the integrated circuit 900 are configured in a programmed mode.

[0365] In some embodiments, waveform 1100 is repeated after time T5, and is therefore similar to time T0, so a similar detailed description is omitted.

[0366] In some embodiments, timing diagram 1100 enables integrated circuit 900 to achieve at least one or more of the benefits described herein.

[0367] In some embodiments, although timing diagram 1100 is described with respect to integrated circuit 900, timing diagram 1100 is also applied in a similar manner to circuits 300A-300B and circuit 400, which will not be described further for the sake of brevity.

[0368] Other configurations of timing diagram 1100 are also within the scope of this disclosure.

[0369] Figure 12 is a flowchart of a method 1200 of an operating circuit according to some embodiments.

[0370] In some embodiments, Figure 12 is a flowchart of a method 1200 for operating the integrated circuit 900 of Figure 9, and similar detailed descriptions are omitted for the sake of brevity.

[0371] In some embodiments, Figure 12 is a flowchart of a method 1200 for operating at least one of the memory circuit 100 of Figure 1, the circuit 300A of Figure 3A, the circuit 300B of Figure 3B, the circuit 400 of Figure 4, or the circuit 600 of Figure 6. For the sake of brevity, similar detailed descriptions are omitted.

[0372] In some embodiments, Figure 12 is a flowchart of a method 1200 for operating an integrated circuit, which includes one or more features in the timing diagram 1100 of Figure 11. For the sake of brevity, similar detailed descriptions are omitted.

[0373] It should be understood that additional operations may be performed before, during, and / or after method 1200 shown in Figure 12, and only a few of these additional operations may be briefly described herein. It should be understood that method 1200 utilizes one or more features of at least one of the following: memory circuit 100 of Figure 1, integrated circuit 900 of Figure 9, circuit 300A of Figure 3A, circuit 300B of Figure 3B, circuit 400 of Figure 4, circuit 600 of Figure 6, electronic fuse circuits 500A-500B of Figure 10, or level shifter circuit 1000; and for the sake of brevity, similar detailed descriptions are omitted.

[0374] In some embodiments, other orders of operation of method 1200 are also within the scope of this disclosure. Method 1200 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, reordered, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more of the operations of method 1200 are not performed.

[0375] In operation 1202 of method 1200, a first supply voltage is received from the first power rail.

[0376] In some embodiments, the first supply voltage of method 1200 includes at least a supply voltage VQPS. In some embodiments, the first power rail of method 1200 includes at least a power rail 232.

[0377] In some embodiments, the memory circuit 202 receives the first supply voltage of method 1200.

[0378] In operation 1204 of method 1200, the second supply voltage of the second power rail is set or adjusted by the first controller.

[0379] In some embodiments, the second supply voltage of method 1200 includes at least the supply voltage VDDSOC. In some embodiments, the second power rail of method 1200 includes at least the power rail 230. In some embodiments, the first controller of method 1200 includes the controller 1300 of Figure 13.

[0380] In some embodiments, the second supply voltage is set by the first controller to a first voltage level or a second voltage level. In some embodiments, the first voltage level of method 1200 includes voltage VDDA. In some embodiments, the second voltage level of method 1200 includes voltage VDDB.

[0381] In some embodiments, operation 1202 further includes adjusting the second supply voltage from the first voltage level to the second voltage level, and vice versa.

[0382] In operation 1206 of method 1200, the first set of signals is received by the set of level shifter circuits.

[0383] In some embodiments, the level shifter circuitry is coupled between a second power rail and a third power rail. In some embodiments, the third power rail has a third supply voltage.

[0384] In some embodiments, the third power rail of method 1200 includes at least power rail 930. In some embodiments, the third supply voltage of method 1200 includes at least supply voltage VDDHV.

[0385] In some embodiments, the first set of signals in method 1200 includes one or more of the following: sense amplifier signal SAE1, bit line signal BL1, word line signal WL1, control signal CS1, or input data DIN1.

[0386] In operation 1208 of method 1200, a second set of signals is generated by the set of level shifter circuits responding to the first set of signals.

[0387] In some embodiments, the second set of signals in method 1200 includes one or more of the following: sense amplifier signal SAE2, bit line signal BL2, word line signal WL2, control signal CS2, or input data DIN1.

[0388] In some embodiments, a first set of signals has a first voltage swing (VSS to VDDSOC), and a second set of signals has a second voltage swing (VSS to VDDHV). In some embodiments, the second voltage swing is different from the first voltage swing.

[0389] In some embodiments, the range of the first voltage swing is from the reference supply voltage VSS to the supply voltage VDDSOC, and the range of the second voltage swing is from the reference supply voltage VSS to the supply voltage VDDHV.

[0390] In some embodiments, the range of the second voltage swing is from the reference supply voltage VSS to the supply voltage VDDSOC, and the range of the first voltage swing is from the reference supply voltage VSS to the supply voltage VDDHV.

[0391] In operation 1210 of method 1200, the first control signal is set to a first logic state or a second logic state. In some embodiments, the second logic state is different from the first logic state.

[0392] In some embodiments, operation 1210 includes setting a first control signal to a first logic state in response to a first supply voltage being less than a first threshold value.

[0393] In some embodiments, operation 1210 includes setting the first control signal to a second logic state in response to a first supply voltage being greater than or equal to a first threshold value.

[0394] In some embodiments, the first threshold value of method 1200 includes at least the voltage VW shown in Figure 11.

[0395] In some embodiments, if the first supply voltage is set to a first voltage level (e.g., voltage VDDA), and the first supply voltage is less than a first threshold value (e.g., voltage VW), then operation 1210 includes setting the first control signal to a first logic state.

[0396] In some embodiments, if the first supply voltage is set to a second voltage level (e.g., voltage VDDB), and the first supply voltage is greater than or equal to a first threshold value (e.g., voltage VW), then operation 1210 includes setting the first control signal to a second logic state.

[0397] In some embodiments, the first control signal of method 1200 includes one or more of control signals PD1, PD2, PD3, PD4, or PD5. In some embodiments, the first logic state of method 1200 is a high logic state or logic 1. In some embodiments, the second logic state of method 1200 is a low logic state or logic 0.

[0398] In some embodiments, a first control signal is set or adjusted by a second controller. In some embodiments, the second controller of method 1200 includes the controller 1300 of Figure 13.

[0399] In operation 1212 of method 1200, a third supply voltage and a first control signal are received by a first power supply control circuit. In some embodiments, the first power supply control circuit is coupled between the third power rail and the first node.

[0400] In some embodiments, the first power gate circuit of method 1200 includes one or more of header circuit 204, circuit 300A, circuit 300B, or circuit 400. In some embodiments, the first power gate circuit of method 1200 includes one or more of memory circuits 902 or 202.

[0401] In some embodiments, the first node of method 1200 includes node ND1.

[0402] In some embodiments, if the first control signal is set to a first logic state, method 1200 proceeds to operation 1214. In some embodiments, if the first control signal is set to a second logic state, method 1200 proceeds to operation 1220.

[0403] In operation 1214 of method 1200, the first power supply gate circuit is turned off or disabled in response to the first control signal.

[0404] In some embodiments, operation 1214 includes receiving a first control signal via a first power gate circuit and turning off or disabling the first power gate circuit in response to a first logic state of the first control signal.

[0405] In some embodiments, operation 1214 includes the set of inverters 302 receiving a control signal PD1, and transistor P1 being turned off or disabled based on the logic state of at least one of the control signals PD1, PD2, PD3, PD4, or PD5.

[0406] In some embodiments, operation 1214 includes the set of inverters 322 receiving control signal PD5, and transistor P1 being turned off or disabled based on the logic state of at least one of control signals PD1, PD2, PD3, PD4, or PD5.

[0407] In operation 1216 of method 1200, a first set of circuits is turned off or disabled in response to the first power supply gate circuit being disabled or turned off.

[0408] In some embodiments, the first set of circuits of method 1200 includes one or more of header circuit 204, power switch 206, memory cell array 208, bit line driver circuit 210, word line driver circuit 212, control circuit 214, set of level shifter circuits 910, or set of level shifter circuits 920.

[0409] In some embodiments, the first set of circuits of method 1200 includes one or more of memory circuits 202 or 902.

[0410] In operation 1218 of method 1200, one or more components of memory circuit 202 or 902 enter a power-off mode.

[0411] In some embodiments, the power-off mode is also referred to as the shutdown mode or sleep mode.

[0412] In operation 1220 of method 1200, the first power supply gate circuit is turned on or enabled in response to the first control signal.

[0413] In some embodiments, operation 1220 includes receiving a first control signal via a first power gate circuit and turning on or enabling the first power gate circuit in response to a second logic state of the first control signal.

[0414] In some embodiments, operation 1220 includes the set of inverters 302 receiving a control signal PD1, and transistor P1 being turned on or enabled based on the logic state of at least one of the control signals PD1, PD2, PD3, PD4, or PD5.

[0415] In some embodiments, operation 1220 includes the set of inverters 322 receiving control signal PD5, and transistor P1 being turned on or enabled based on the logic state of at least one of control signals PD1, PD2, PD3, PD4, or PD5.

[0416] In operation 1222 of method 1200, a first set of circuits is turned on or turned on in response to the first power gate circuit being enabled or turned on.

[0417] In operation 1224 of method 1200, one or more elements of memory circuit 202 or 902 enter programming mode, read mode, or standby mode.

[0418] By operating method 1200, at least one of the memory circuit 100 in Figure 1, the integrated circuit 900 in Figure 9, the circuit 300A in Figure 3A, the circuit 300B in Figure 3B, the circuit 400 in Figure 4, or the circuit 600 in Figure 6 is operated to achieve the benefits discussed herein.

[0419] Figure 13 is a schematic diagram of a controller 1300 for generating one or more control signals or voltages according to some embodiments.

[0420] In some embodiments, the controller 1300 may be used in one or more of the memory circuit 100 of Figure 1, the integrated circuit 200 of Figure 2, the circuit 300A of Figure 3A, the circuit 300B of Figure 3B, the circuit 400 of Figure 4, the electronic fuse circuits 500A~500B of Figures 5A to 5B, the circuit 600 of Figure 6, the integrated circuit 900 of Figure 9, the timing diagram 700 of Figure 7, the timing diagram 1100 of Figure 11, the method 800 of Figure 8, and the method 1200 of Figure 12. For the sake of brevity, similar detailed descriptions are omitted.

[0421] In some embodiments, the controller 1300 may be used to generate or set one or more of the following: supply voltage VDDA, supply voltage VDDB, supply voltage VDDSOC, and voltage VL. For the sake of brevity, similar detailed descriptions are omitted.

[0422] In some embodiments, the controller 1300 may be used to generate or set one or more of control signals PD1, PD5, PS1, or PS1B. For the sake of brevity, similar detailed descriptions are omitted.

[0423] The controller 1300 includes a hardware processor 1302 and a non-transitory computer-readable storage medium 1304 encoded (i.e., stored) with computer program code 1306 (i.e., a set of executable instructions). The computer-readable storage medium 1304 is also encoded with instructions 1306 for interfacing with at least one of the memory circuit 100 of Figure 1, the integrated circuit 200 of Figure 2, the circuit 300A of Figure 3A, the circuit 300B of Figure 3B, the circuit 400 of Figure 4, the electronic fuse circuits 500A-500B of Figures 5A to 5B, the circuit 600 of Figure 6, or the integrated circuit 900 of Figure 9.

[0424] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically coupled to I / O interface 1310 via bus 1308. Network interface 1312 is also electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314, enabling processor 1302 and computer-readable storage medium 1304 to be connected to external components via network 1314. Processor 1302 is used to execute computer program code 1306 encoded in computer-readable storage medium 1304 so that controller 1300 can be used to perform part or all of the operations described in at least one of method 800 or 1200 or timing diagram 700 or 1100.

[0425] In some embodiments, the processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0426] In some embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disc. In some embodiments using optical discs, the computer-readable storage medium 1304 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0427] In some embodiments, storage medium 1304 stores computer program code 1306 for causing controller 1300 to perform at least one of method 800 or 1200 or timing diagram 700 or 1100. In some embodiments, storage medium 1304 also stores information required to perform at least one of method 800 or 1200 or timing diagram 700 or 1100, as well as information generated during the performance of method 800, 1200 or timing diagram 700 or 1100, such as control signal 1316 or voltage 1318, and / or a set of executable instructions to perform the operation of method 800 and 1200 or timing diagram 700 or 1100.

[0428] In some embodiments, storage medium 1304 stores instructions (e.g., computer program code 1306) for interfacing with one or more of the memory circuit 100 of Figure 1, integrated circuit 200 of Figure 2, circuit 300A of Figure 3A, circuit 300B of Figure 3B, circuit 400 of Figure 4, electronic fuse circuits 500A-500B of Figures 5A to 5B, circuit 600 of Figure 6, and integrated circuit 900 of Figure 9. Instructions (e.g., computer program code 1306) enable processor 1302 to generate instructions to control the memory circuit 100 of Figure 1, the integrated circuit 200 of Figure 2, the circuit 300A of Figure 3A, the circuit 300B of Figure 3B, the circuit 400 of Figure 4, the electronic fuse circuits 500A~500B of Figures 5A to 5B, the circuit 600 of Figure 6, and the integrated circuit 900 of Figure 9, so as to effectively achieve at least one of method 800 or 1200 or timing diagram 700 or 1100.

[0429] The controller 1300 includes an I / O interface 1310. The I / O interface 1310 is coupled to an external circuit system. In some embodiments, the I / O interface 1310 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, and / or cursor arrow keys for transmitting information and commands to the processor 1302.

[0430] The controller 1300 also includes a network interface 1312 coupled to the processor 1302. The network interface 1312 allows the controller 1300 to communicate with a network 1314 to which one or more other computer systems are connected. The network interface 1312 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-13104. In some embodiments, at least one of method 800 or 1200 or timing diagram 700 or 1100 is implemented in two or more systems 1300, and information such as reference signals, scrambling signals, clock output signals, duty cycle signals, comparator output signals, control signal sets, selection signals, or FSM signals is exchanged between different systems 1300 via network 1314.

[0431] The controller 1300 receives information related to the reference signal via the I / O interface 1310 or the network interface 1312. The information is transferred to the processor 1302 via the bus 1308 to generate control signals. Then, the reference signal is stored as a control signal 1316 in the computer-readable medium 1304.

[0432] The controller 1300 receives voltage-related information via I / O interface 1310 or network interface 1312. This information is stored as voltage 1318 in computer-readable medium 1304.

[0433] In some embodiments, control signal 1316 includes one or more of control signal PD1, control signal PD5, control signal PS1, or control signal PS1B. In some embodiments, control signal 1316 includes one or more of the signals described herein.

[0434] In some embodiments, voltage 1318 includes one or more of supply voltage VDDA, supply voltage VDDB, supply voltage VDDSOC, and voltage VL.

[0435] In some embodiments, voltage 1318 includes one or more of the supply voltages described herein.

[0436] In some embodiments, one or more of the operations of methods 800 or 1200 are not performed. Furthermore, the various PMOS or NMOS transistors shown in this disclosure have specific dopant types (e.g., N-type or P-type) for illustrative purposes. The embodiments of this disclosure are not limited to specific transistor types, and one or more of the PMOS or NMOS transistors shown in this disclosure can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are also for illustrative purposes. The embodiments of this disclosure are not limited to specific logic values ​​when the signal is enabled and / or disabled. Choosing different logic values ​​is within the scope of various embodiments. Choosing different numbers of inverters in this disclosure is also within the scope of various embodiments. Choosing different numbers of transistors in this disclosure is also within the scope of various embodiments.

[0437] Those skilled in the art will readily recognize that one or more of the disclosed embodiments satisfy one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to make various modifications, equivalent substitutions, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only to the definitions contained in the appended claims and their equivalents.

[0438] One aspect of this specification relates to an integrated circuit. In some embodiments, the integrated circuit includes a first power rail for supplying a first supply voltage. In some embodiments, the integrated circuit further includes a second power rail for supplying a second supply voltage different from the first supply voltage, the second supply voltage having a first value or a second value different from the first value. In some embodiments, the integrated circuit further includes a first memory circuit coupled to the first power rail and the second power rail, and for receiving at least one of a first control signal, the first supply voltage, or the second supply voltage. In some embodiments, the first memory circuit includes a first header circuit coupled to the second power rail, and for supplying the second supply voltage to at least a first node in response to the first control signal. In some embodiments, the first memory circuit further includes a first memory cell array coupled to the first header circuit via a first node, for storing a first set of data, and receiving the second supply voltage from the first header circuit. In some embodiments, the integrated circuit further includes a first core circuit coupled to the first memory circuit, and for receiving the second supply voltage.

[0439] Another aspect of this specification relates to an integrated circuit. In some embodiments, the integrated circuit includes a first power rail for supplying a first supply voltage. In some embodiments, the integrated circuit further includes a second power rail for supplying a second supply voltage different from the first supply voltage. In some embodiments, the integrated circuit further includes a third power rail for supplying a third supply voltage different from both the first and second supply voltages. In some embodiments, the integrated circuit further includes a first memory circuit coupled to the first and second power rails and for receiving at least one of a first control signal, the first supply voltage, or the second supply voltage. In some embodiments, the first memory circuit includes a first set of level shifter circuits coupled between the second and third power rails and for generating a first set of signals in response to a second set of signals, the first set of signals having a first voltage swing, and the second set of signals having a second voltage swing different from the first voltage swing. In some embodiments, the first memory circuit further includes a second memory circuit coupled to the first and third power rails and for receiving at least one of the first control signal, the first supply voltage, or the third supply voltage. In some embodiments, the integrated circuit further includes a first core circuit coupled to a first memory circuit and used to receive a first supply voltage.

[0440] This specification also relates to another aspect of a method for operating an integrated circuit. In some embodiments, the method includes receiving a first supply voltage from a first power rail. In some embodiments, the method further includes setting a second supply voltage of a second power rail by a first controller. In some embodiments, the method further includes receiving a first set of signals by a level shifter circuit coupled between a second power rail and a third power rail, the third power rail having a third supply voltage. In some embodiments, the method further includes generating a second set of signals by the level shifter circuit in response to the first set of signals, the first set of signals having a first voltage swing, and the second set of signals having a second voltage swing different from the first voltage swing. In some embodiments, the method further includes setting a first control signal to a first logic state or a second logic state by a second controller, the second logic state being different from the first logic state. In some embodiments, the method further includes receiving a third supply voltage and a first control signal by a first power gate circuit coupled between a third power rail and a first node. In some embodiments, the method further includes disabling the first power gate circuit in response to the first logic state of the first control signal. In some embodiments, the method further includes disabling a first set of circuits in response to a first power gate circuit being disabled. In some embodiments, the method further includes putting the memory circuitry into a power-down mode.

[0441] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0442] 100: Memory Circuit 100BL: GIO Circuit 100GC: Global Control Circuit 102A~102D: Memory partitions 110AC:WL driver circuit 110AR: Memory Cell Array 110BS: LIO circuit 110L: Memory Bank 110LC: Area Control Circuit 110U: Memory Bank 112: Memory device 114: Circuit 116: Circuit 120: Memory Circuit 200: Integrated Circuits 202: Memory Circuit 204: Header Circuit 206: Power switch 208: Memory Cell Array 210: Bit line driver circuit 212: Character line driver circuit 214: Control Circuit 214a: Sensing Amplifier 220: Collection of Core Devices 220A: Core Unit 220N: Core Device 230: Power rail 232: Power rail 300A~300B: Circuit 302: Collection of Inverters 322: Collection of Inverters 400: Circuit 402: Circuit 500A~500B: Power rail 600: Circuit 602: Buffer Circuit 700: Timing Diagram 800: Method 802~818: Operation 900: Integrated Circuits 902: Memory Circuit 910: A collection of level shifter circuits 910a~910c: Level shifter circuit 920: A collection of level shifter circuits 920a~920c: Level shifter circuit 930: Power Rail 1000: Level shifter circuit 1002: Inverter 1004: NMOS transistor 1006: PMOS transistor 1008: PMOS transistor 1010: PMOS transistor 1012: PMOS transistor 1014: NMOS transistor 1016: Inverter 1100: Timing Diagram 1200: Method 1202~1224: Operations 1300: Controller 1302: Hardware Processor 1304: Non-transitory computer-readable storage media 1306: Instruction 1308: Busbar 1310:I / O interface 1312: Network Interface 1314: Internet 1316: Control signal 1318: Voltage ND1: Node ND2~ND5: Voltage supply nodes ND6: Voltage supply node VDDHV: Supply voltage VDDSOC: Supply voltage

[0443] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An integrated circuit comprising: a first power rail for supplying a first supply voltage; a second power rail for supplying a second supply voltage different from the first supply voltage, the second supply voltage having a first value or a second value different from the first value; and a first memory circuit coupled to the first power rail and the second power rail, and for receiving at least one of a first control signal, the first supply voltage, or the second supply voltage, the first memory circuit comprising: A first header circuit coupled to the second power rail and used to supply the second supply voltage to at least one first node in response to the first control signal; a first memory cell array coupled to the first header circuit via the first node and used to store a first set of data and receive the second supply voltage from the first header circuit; a bit line driver circuit coupled to the first header circuit via the first node and used to receive the second supply voltage and generate a bit line signal; and a first core circuit coupled to the first memory circuit and used to receive the second supply voltage.

2. The integrated circuit as claimed in claim 1 further comprises: a second core circuit coupled to the first memory circuit and used to receive the second supply voltage.

3. The integrated circuit as claimed in claim 1, wherein the first memory circuit further comprises: a first word line driver circuit coupled to the first header circuit via the first node, and for receiving the second supply voltage and generating a word line signal.

4. The integrated circuit as claimed in claim 3, wherein the first memory circuit further comprises: a first sense amplifier coupled to the first header circuit via the first node, and for receiving the second supply voltage and performing a read operation of one of the first memory cell arrays in response to a sense amplifier enable signal.

5. The integrated circuit as claimed in claim 4, wherein the first memory circuit further comprises: a first power switch coupled to the second power rail and configured to receive the first supply voltage and supply the first supply voltage to the first memory cell array in response to a write driver circuit performing a write operation on one of the first memory cell arrays.

6. The integrated circuit as claimed in claim 5, wherein the first header circuit has a first threshold voltage, and at least one of the first memory cell array, the first bit line driver circuit, the first word line driver circuit, the first sense amplifier, or the first power switch has a second threshold voltage, and the second threshold voltage is greater than the first threshold voltage.

7. The integrated circuit as claimed in claim 1, wherein the first header circuit comprises: a first inverter coupled to the first power rail and configured to generate a second control signal in response to the first control signal, the first control signal being an inverse of the second control signal; and a second inverter coupled to the first power rail and the first inverter and configured to generate a third control signal in response to the second control signal, the second control signal being an inverse of the third control signal.

8. An integrated circuit comprising: a first power rail for supplying a first supply voltage; a second power rail for supplying a second supply voltage different from the first supply voltage; a third power rail for supplying a third supply voltage different from the first supply voltage and the second supply voltage; and a first memory circuit coupled to the first power rail and the second power rail, and configured to receive at least one of a first control signal, the first supply voltage, or the second supply voltage, the first memory circuit comprising: A first set of multiple level shifter circuits coupled between the second power rail and the third power rail, and used to generate a first set of multiple signals in response to a second set of multiple signals, the first set of multiple signals having a first voltage swing, and the second set of multiple signals having a second voltage swing different from the first voltage swing; a second memory circuit coupled to the first power rail and the third power rail, and used to receive at least one of the first control signal, the first supply voltage, or the third supply voltage; and a first core circuit coupled to the first memory circuit and used to receive the first supply voltage.

9. The integrated circuit as claimed in claim 8, wherein the second memory circuit includes: a first header circuit coupled to the third power rail and configured to supply the third supply voltage to at least one first node in response to the first control signal.

10. A method of operating an integrated circuit, the method comprising the steps of: receiving a first supply voltage from a first power rail; setting a second supply voltage on a second power rail by a first controller; receiving a first set of a plurality of signals by a quasi-shifter circuit coupled between the second power rail and a third power rail, the third power rail having a third supply voltage; generating a second set of a plurality of signals in response to the first set of signals by the quasi-shifter circuit, the first set of signals having a first voltage swing, the second set of signals having a second voltage swing different from the first voltage swing; setting a first control signal to a first logic state or a second logic state by a second controller, the second logic state being different from the first logic state; receiving the third supply voltage and the first control signal by a first power gate circuit coupled between the third power rail and a first node; disabling the first power gate circuit in response to the first logic state of the first control signal; In response to the first power gate circuit being disabled, one of the multiple circuits in a first set is disabled; and the integrated circuit is put into a power-off mode.

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