Apparatus and method for producing waveform

Abstract

This document discloses a bias supply, a plasma processing system, and related methods. A bias supply includes a first inductor coupled between a first node of a switch and an output node, wherein a first node of a second inductor is coupled to either the output node or the first node of the switch. A voltage source is coupled between a second node of the switch and a second node of the second inductor. A connection is provided between a return node and either the second node of the switch or the second node of the second inductor. The bias supply further includes a controller configured to repeatedly close the switch such that the current through the switch completes a full cycle, thereby applying a periodic voltage between the output node and the return node.

Description

Technical Field

[0001] The present invention relates generally to a power supply, and more specifically to a power supply for applying voltage to power plasma processing.

[0002] This patent application claims priority to U.S. Provisional Application No. 62 / 873,680, filed July 12, 2019, entitled “A SINGLE CONTROLLED SWITCH, SINGLE SUPPLY EV SOURCE WITH ION CURRENT COMPESATION,” which is assigned to the assignee of this application and is incorporated herein by reference in particular. Prior Technology

[0003] Many types of semiconductor devices are manufactured using plasma-based etching techniques. If the material being etched is a conductor, a negative voltage relative to ground can be applied to the conductive substrate to generate a substantially uniform negative voltage across the surface of the substrate conductor, which attracts positively charged ions toward the conductor, and as a result, the positive ions that collide with the conductor have substantially the same energy.

[0004] However, if the substrate is dielectric, a non-changing voltage cannot be applied across the substrate surface. But, alternating current (AC) voltage (e.g., high-frequency AC or radio frequency (RF)) can be applied to the conductive plate (or clamp), causing the AC field to result in a voltage on the substrate surface. During the positive spike of the AC cycle, the substrate attracts electrons, which are lighter than positive ions; therefore, many ions will be attracted to the substrate surface during the positive spike of the cycle. As a result, the substrate surface will be negatively charged, causing ions to be attracted toward the negatively charged surface for the remainder of the AC cycle. And when ions bombard the substrate surface, the impact removes material from the substrate surface—completing the etching.

[0005] In many cases, a narrow ion energy distribution is desired, but applying a sinusoidal waveform to the substrate results in a wide ion energy distribution, which limits the plasma processing's ability to achieve the desired etch profile. Known techniques for achieving a narrow ion energy distribution are expensive, inefficient, difficult to control, and can adversely affect plasma density. As a result, these known techniques have not been commercially adopted. Therefore, a system and method are needed to address the shortcomings of current techniques and provide other novel and innovative features. Summary of the Invention

[0006] One embodiment of some of the implementations disclosed in this paper addresses the aforementioned requirements by using a switching frequency as a control means, along with a single control switch in the resonant circuit, requiring only a single variable voltage supply so that an extremely simplified circuit can provide the desired narrow energy distribution.

[0007] According to another embodiment, a power supply includes an output node, a return node, a switch, a first inductor, a second inductor, and a voltage source. The first inductor is coupled between the first node of the switch and the output node, and the first node of the second inductor is coupled to either the output node or the first node of the switch. The voltage source is coupled between the second node of the switch and the second node of the second inductor, and has a connection between the return node and either the second node of the switch or the second node of the second inductor. The controller is configured to apply a periodic voltage between the output node and the return node by repeatedly closing the switch for a sufficiently long time to allow the current through the switch to complete a complete cycle from zero to peak, back to zero, to a reverse peak, and back to zero.

[0008] According to another embodiment, a power supply includes an output node, a return node, a switch, a transformer, and a voltage source. A first node of the primary winding of the transformer is coupled to a first node of the switch, a first node of the secondary winding of the transformer is coupled to the output node, and a second node of the secondary winding of the transformer is coupled to the return node. The voltage source is coupled between the second node of the switch and the second node of the primary winding of the transformer. The power supply also includes a controller configured to apply a periodic voltage between the output node and the return node by repeatedly closing the switch for a sufficiently long time to allow the current through the switch to complete a complete cycle from zero to peak, back to zero, to a reverse peak, and back to zero.

[0009] Another embodiment disclosed herein is a plasma processing system comprising a plasma chamber and a bias supply. The plasma chamber includes a volume for containing plasma, an input node, and a return node. The bias supply includes a switch, a first inductor, a second inductor, and a voltage source. The first inductor is coupled between a first node of the switch and the input node of the plasma chamber, and the first node of the second inductor is coupled to either the input node of the chamber or the first node of the switch. The voltage source is coupled between a second node of the switch and a second node of the second inductor. A connection is provided between the return node and either the second node of the switch or the second node of the second inductor. The plasma processing system further includes a control mechanism for controlling the switch and the voltage source to achieve a desired waveform of the plasma load voltage when the plasma is in the plasma chamber.

[0010] According to another embodiment, a plasma processing system includes a plasma chamber and a bias supply. The plasma chamber includes a volume for containing plasma, an input node, and a return node, and the bias supply includes a switch, a transformer, and a voltage source. A first node of the primary winding of the transformer is coupled to a first node of the switch, a first node of the secondary winding of the transformer is coupled to the input node of the plasma chamber, and a second node of the secondary winding of the transformer is coupled to the return node. The voltage source is coupled between the second node of the switch and the second node of the primary winding of the transformer. The plasma processing system further includes a control mechanism for controlling the switch and the voltage source to achieve a desired waveform of the voltage of the plasma load when the plasma is in the plasma chamber. Simple Explanation of the Diagram

[0011] [Figure 1] is a block diagram depicting an exemplary plasma processing environment that can utilize one of the bias supplies disclosed herein;

[0012] [Figure 2] is a schematic diagram depicting a model bias supply;

[0013] [Figure 3] is a schematic diagram representing a layer of a plasma processing chamber in an electrical manner;

[0014] [Figure 4] is a timing diagram depicting the timing at the electrical level of the bias supply in Figure 2 when operating together with the plasma processing chamber in Figure 3;

[0015] [Figure 5A] is a graphical representation of sheath voltage versus time and the resulting ion flux versus ion energy;

[0016] [Figure 5B] is a graph showing the periodic voltage waveform that can be generated from the sheath voltage plotted in Figure 5A;

[0017] [Figure 6A] illustrates another sheath voltage versus induced ion flux and ion energy;

[0018] [Figure 6B] is a graph showing the periodic voltage waveform that can be generated from the sheath voltage plotted in Figure 6A;

[0019] [Figure 7A] illustrates another sheath voltage versus induced ion flux and ion energy;

[0020] [Figure 7B] is a graph showing the periodic voltage waveform that can be generated from the sheath voltage plotted in Figure 7A;

[0021] [Figure 8] includes a graph depicting the waveform of the periodic voltage that can be applied by the bias supply in Figure 2 and the corresponding sheath voltage;

[0022] [Figure 9] includes a graph depicting another cycle voltage waveform that can be applied by the bias supply of Figure 2 and the corresponding sheath voltage;

[0023] [Figure 10] includes a graph depicting another cycle voltage waveform that can be applied by the bias supply of Figure 2 and the corresponding sheath voltage;

[0024] [Figure 11] is a schematic diagram depicting another exemplary bias supply;

[0025] [Figure 12] includes a graph depicting the waveform of the periodic voltage that can be applied by the bias supply of Figure 11 and the corresponding sheath voltage;

[0026] [Figure 13] includes a graph depicting another cycle voltage waveform that can be applied by the bias supply of Figure 11 and the corresponding sheath voltage;

[0027] [Figure 14] includes a graph depicting the waveform of another cycle of voltage that can be applied by the bias supply of Figure 11 and the corresponding sheath voltage;

[0028] [Figure 15A] is a flowchart depicting one of the methods that can be discussed in relation to several embodiments;

[0029] [Figure 15B] is a flowchart depicting another method that can be discussed in relation to several embodiments;

[0030] [Figure 16A] is a schematic diagram depicting a model bias supply;

[0031] [Figure 16B] is a schematic diagram depicting another exemplary bias supply;

[0032] [Figure 16C] is a schematic diagram depicting another exemplary bias supply;

[0033] [Figure 16D] is a schematic diagram depicting another exemplary bias supply;

[0034] [Figure 16E] is a schematic diagram depicting another exemplary bias supply;

[0035] [Figure 16F] is a schematic diagram depicting another exemplary bias supply;

[0036] [Figure 17] is a block diagram depicting the components that can be used to implement the control layer disclosed herein. Implementation

[0037] The word “demonstration” is used herein to mean “as an example, illustration, or illustration.” Any embodiment described herein as a “demonstration” is not necessarily to be construed as superior to, or more advantageous than, other embodiments.

[0038] Preliminary Notes: The flowcharts and block diagrams in the following figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, some blocks in these flowcharts or block diagrams may represent modules, segments, or portions of code containing one or more instructions for implementing specified logical functions. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the figures. For example, two blocks shown consecutively may actually be executed simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. It will also be noted that the individual blocks in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system, or a combination of dedicated hardware and computer instructions, to perform the specified functions or actions.

[0039] In terms of the disclosure, the source generator is those components whose energy is primarily directed to generate and sustain plasma, while the "bias supply" is those components whose energy is primarily directed to generate surface potential to attract ions and electrons from plasma.

[0040] This article describes several embodiments of novel bias supply that can be used to apply cyclic voltage functionality to a substrate support in a plasma processing chamber.

[0041] Referring first to Figure 1, an exemplary plasma processing environment (e.g., a deposition or etching system) utilizing a bias supply is shown. The plasma processing environment may include a number of devices directly and indirectly coupled to a plasma chamber 101, the volume of which housing the plasma 102 and the workpiece 103 (e.g., a wafer) is contained within the plasma chamber 101. The devices may include vacuum manipulation and gas delivery equipment (not shown), one or more bias supplies 108, one or more source generators 112, and one or more source matching networks 113. In many applications, power from a single source generator 112 is connected to one or more source electrodes 105. The source generator 112 may be a higher frequency RF generator (e.g., 13.56 MHz to 120 MHz). Electrode 105 generally represents an implementation that can be implemented using an inductively coupled plasma (ICP) source, a capacitively coupled plasma (CCP) source with an auxiliary top electrode biased at another RF frequency, a spiral cone plasma source, a microwave plasma source, a magnetron, or some other independently operating plasma energy source.

[0042] In a variation of the system illustrated in Figure 1, the source generator 112 and source matching network 113 may be replaced with or have a remote plasma source added. Other variations of the system may include a single bias supply 108.

[0043] Although the following disclosures generalize about plasma-based wafer processing, implementations may include processing of any substrate within a plasma processing chamber. In some instances, objects other than substrates may be processed using the systems, methods, and apparatus disclosed herein. In other words, this disclosure applies to plasma processing of any object within a plasma processing chamber at sub-atmospheric pressure to influence surface changes, subsurface changes, deposition, or removal by physical or chemical means.

[0044] Referring to Figure 2, an exemplary bias supply 208 for applying a periodic voltage function is shown. As shown, the bias supply 208 includes an output 210 (also referred to as output node 210), a switch 220, and a voltage source 230. Furthermore, a first inductor 240 is coupled between the switch and the output, and a second inductor 250 is coupled between the voltage source and the output. A controller 260 is also shown, configured to open and close the switch 220 to generate a voltage at the output as further described herein. For example, the controller 260 may be configured to apply a periodic voltage between the output 210 (also referred to as output node 210) and ground connection 270 (also referred to as return node 270) by repeatedly closing the switch for a sufficiently long time to allow the current through the switch to complete a complete cycle from zero to peak, back to zero, to reverse peak, and back to zero. The current delivered to the load through output 210 returns to the bias supply 208 through the common ground connection 270 shared by the output 210 and the load.

[0045] Briefly referring to Figure 3, a schematic diagram of the layers of plasma load within plasma chamber 101 is shown in an electrical manner. As shown, plasma chamber 101 can be represented by a clamp capacitor Cch (which includes the capacitance of the clamp and the workpiece 103), which is positioned between the input 310 (also referred to as input node 310) to plasma chamber 101 and its node representing the voltage VS (also referred to herein as sheath voltage) on the substrate surface. Furthermore, a return node 307 (which may be a connection to ground) is depicted. The plasma in the processing chamber is represented by a parallel combination of sheath capacitor CS, a diode, and a current source. The diode represents the nonlinear, diode-like properties of the plasma sheath, which rectify the applied AC field, causing a direct-current voltage drop to appear between workpiece 103 and plasma 102.

[0046] Referring again to Figure 2, switch 220 (like most field-effect switches) includes a body diode that accommodates reverse current even when the switch is not controlled to be on. The applicant has found that the use of a body diode has the advantage that switch 220 (due to the body diode) can be turned off at any time during the first reversal of current through the switch; thus, the timing criticality of control is reduced. While other types of switches may be used, the switch may be implemented using a silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET). It should be understood that the drive signal 211 from the controller may be electrical or optical. It should also be understood that switches depicted in other biased supplies disclosed herein (e.g., in Figures 11 and 16A-16F) may also include body diodes, and those switches in other biased supplies may be driven by drive signal 211.

[0047] Referring to Figure 4, the waveforms depicting the electrical aspects of the bias supply 208 and the plasma processing chamber 101 are shown. This occurs when the ion current Iion is properly compensated, and the current iL2 through the second inductor L2 equals the ion current Iion. This disclosure addresses the problem of how to adjust the current iL2 through L2 to be equal to the ion current Iion. As shown in Figure 4, switch 220 (also referred to herein as switch S) can be controlled such that the current through the first inductor 240 (and therefore switch 220) completes a full cycle from zero to peak, back to zero, to a reverse peak, and back to zero. It should be understood that the peak value of current iL2 in the first half of the current cycle may be different from the peak value of current iL2 in the second half of the current cycle. Controller 260 can be configured to adjust the voltage of voltage source 230 and the time between repeated switch closures to achieve the desired voltage at VO.

[0048] Briefly referring to Figures 5A to 7B, background material is depicted to help understand the ion current compensation effect of ion energy distribution in plasma chamber 101. First, refer to Figures 5A and 5B in the IL2=Iion operating mode. As shown in Figure 5A, when the sheath voltage is substantially fixed between pulses, the corresponding ion energy 570 dispersion is quite narrow, producing a substantially monoenergetic ion energy distribution function. Figure 5B shows an asymmetric periodic voltage function, which can be applied by the bias supply 108 to generate the sheath voltage shown in Figure 5A.

[0049] Referring to Figures 6A and 6B, the layers relating to the sheath voltage, ion flux, and periodic asymmetric voltage waveform (output from the bias supply) for undercompensated ion current are shown. As shown in Figure 6A, when the ion current Iion is undercompensated, the sheath voltage becomes less negative in a ramp manner, resulting in a wider distribution 672 of ion energy. Figure 6B shows a periodic voltage that can be applied to the substrate support to achieve the sheath voltage depicted in Figure 6A. As shown, the negative ramp portion of the periodic voltage waveform decreases with a lower slope than the ramp portion of the periodic voltage waveform in Figure 5B (shown as the dashed line in Figure 6B). Note that the aforementioned distribution 672 of ion energy can be carefully achieved.

[0050] Figures 7A and 7B depict the layers associated with the sheath voltage, ion flux, and periodic asymmetric voltage waveform (output from the bias supply) of the overcompensated ion current. As shown in Figure 7A, when the ion current is overcompensated, the sheath voltage becomes more negative in a ramp manner, which also produces a wider distribution 774 of ion energy. Figure 7B shows the periodic voltage waveform that can be applied to the substrate support to achieve the sheath voltage depicted in Figure 7A. As shown, the negative ramp portion of the periodic voltage waveform decreases with a larger slope than the ramp portion of the periodic voltage waveform for compensating the ion current (shown as dashed lines). The aforementioned distribution 774 of ion energy can be carefully achieved and is desirable.

[0051] Referring back to Figures 2, 3, and 4, the applicant has discovered that the current iL2 through L2 (and therefore the compensation current) can be controlled by controlling the pulse repetition rate of the periodic voltage VO applied to the output of the bias supply. Furthermore, the pulse repetition rate can be controlled by the timing of the switch's opening and closing. Each time the switch is turned on, the applicant checks what happened and adjusts the timing for the next turn-on. For example, if the time between VO and the switch's on-time is fixed, and the second turn-on occurs slightly earlier, the applicant considers what will happen to the applied voltage VO. In this case, the second turn-on begins with the same initial conditions, so the second pulse voltage of the applied voltage VO should be the same. Because the time between pulses is now shorter, the average applied voltage VO is higher; therefore, the current through L2 should increase. Increasing iL2 will increase the downward slope of the applied voltage VO, thereby increasing the size of the second pulse. Therefore, increasing the pulse repetition rate is a method to improve ion current compensation. This is confirmed by the simulation shown in Figures 8-10.

[0052] Referring to Figure 8, which is a graph depicting the output voltage VO of the bias supply versus the sheath voltage VS, for the circuit of Figure 2 connected to a load as shown in Figure 3, where L1 = 3 μH, L2 = 4 mH, Cch = 1.5 nF, CS = 1 nF, and Iion = 3 A, when voltage source 230 (Vb) provides a 5 kV DC voltage and the switch is opened and closed to provide a pulse repetition rate of VO at 300 kHz. Operating the circuit with these parameters causes the initial sheath voltage VS to rise from -5 kV to -2.6 kV because the ion current is undercompensated. As shown in Figure 2, the repetition rate of switch closure can be the same as the pulse repetition rate of VO. And the switch can be closed for a sufficiently long time for the current IL1 through the switch to complete a complete cycle from zero to peak, back to zero, to the reverse peak, and back to zero. It should also be understood that the current IL2 can be substantially fixed during the period of the VO periodic voltage.

[0053] Referring next to Figure 9, a graph depicting the output voltage VO of the bias supply versus the sheath voltage VS with the same parameters as in Figure 8, except that the voltage source 230 (Vb) provides a DC voltage of 4.5 kV and the switch is opened and closed to provide a pulse repetition rate of 650 kHz. Operating the bias supply with these parameters results in a fixed sheath voltage of -5 kV because the ion current is precisely compensated.

[0054] Referring to Figure 10, a graph depicting the output voltage VO of a bias supply with the same parameters as in Figure 8 is shown, versus the sheath voltage VS, except that the voltage source Vb provides a DC voltage equal to 4.25 kV and the switch is opened and closed to provide VO with a pulse repetition rate of 800 kHz. Operating the circuit with these parameters causes the initial sheath voltage VS of -5 kV to drop to -5.25 kV because the ion current is overcompensated.

[0055] Referring next to Figure 11, a circuit diagram of a bias supply including transformer 1160 is shown, which couples the periodic voltage function to output 1110 (also referred to as output node 1110). As shown, the bias supply includes a voltage source 1130 coupled to an inductor 1140 of switch 1120 and transformer 1160. Controller 1150 is coupled to the switch and configured to open and close the switch to generate an asymmetrical voltage at the output. Inductor 1140 may be a discrete inductor or a portion of the leakage inductance of transformer 1160. For simulation purposes, the transformer is modeled as two fully coupled inductors. The parasitic capacitance between the transformer windings is modeled by CW.

[0056] Figure 12 is a graph depicting the output voltage VO of the bias supply versus the sheath voltage VS for the circuit of Figure 11 connected to a load as shown in Figure 3, where L1 = 50 nH, LP = 56 μH, LS = 5.6 mH, CW = 1.26 nF, Cch = 1.5 nF, CS = 1 nF, and Iion = 3 A. When the voltage source of the bias supply in Figure 11 is applied at 422 VDC and the controller switches on and off to generate a periodic voltage with a pulse repetition rate of 300 kHz at the output, operating the bias supply with these parameters causes the initial sheath voltage of -5 kV to increase to -2.8 kV because the ion current is undercompensated.

[0057] Figure 13 is a graph depicting the output voltage VO of the bias supply versus the sheath voltage VS with the same parameters as in Figure 12, except that a voltage source of 281 VDC is applied to the bias supply of Figure 11 and the controller opens and closes the switch to generate a periodic voltage with a pulse repetition rate of 775 kHz at the output. Operating the circuit with these parameters results in a fixed sheath voltage of -5 kV because the ion current is precisely compensated.

[0058] Figure 14 is a graph depicting the output voltage VO of the bias supply versus the sheath voltage VS with the same parameters as in Figure 12, except that a voltage source of 212 VDC is applied to the bias supply of Figure 11 and the controller opens and closes the switch to generate a periodic voltage with a pulse repetition rate of 1 MHz at the output. Operating the circuit with these parameters causes the initial sheath voltage of -5 kV to drop to -5.24 kV because the ion current is overcompensated.

[0059] Referring next to Figure 15A, a flowchart depicting one method described in relation to the embodiments disclosed herein (e.g., in relation to Figures 16A-16D) is shown. As shown, a first node of a first inductor (also referred to herein as a small inductor element) is connected to a first node of a switch, and a second node of the small inductor element is connected to an output node, wherein a capacitively coupled plasma load is connected between the output node and the return node (block 1510). A first node of a first inductor (also referred to herein as a large inductor element) may be connected to either node of the small inductor element (block 1520). As shown, a voltage source is connected between a second node of the switch and a second node of the large inductor element, and either node of the voltage source is connected to the return node (block 1530). In operation, the switch is repeatedly closed for a sufficiently long time to allow the current through the switch to complete a complete cycle from zero to peak, back to zero, to the reverse peak, and back to zero (block 1540). Furthermore, the voltage of the voltage source and the time between repeated switch closures can be adjusted to achieve a desired waveform of the plasma load voltage (block 1550). For example, the desired waveform can be a sheath voltage to achieve a narrow distribution of ion energy (e.g., as shown in Figure 5A) or a wider distribution of ion energy (e.g., as shown in Figures 6A and 7A).

[0060] Figure 15B is another flowchart illustrating one method that can be discussed in relation to the embodiments disclosed herein (e.g., in relation to Figures 16E and 16F). As shown, a first node of the primary winding of the transformer is connected to a first node of a switch, and a first node of the secondary winding of the transformer is connected to an output node, wherein a capacitively coupled plasma load is connected between the output node and a second node of the secondary winding of the transformer (block 1511). Furthermore, a voltage source is connected between the second node of the switch and the second node of the primary winding of the transformer (block 1521). In operation, the switch is closed for a sufficiently long time to allow the current through the switch to complete a complete cycle from zero to peak, back to zero, to the reverse peak, and back to zero (block 1531). Furthermore, the voltage of the voltage source and the time between repeated switch closures can be adjusted to achieve a desired waveform for the plasma load voltage (block 1541). For example, as discussed above, the desired waveform can be a sheath voltage to achieve a narrow distribution of ion energy (e.g., as shown in Figure 5A) or a wider distribution of ion energy (e.g., as shown in Figures 6A and 7A).

[0061] Referring to Figure 16A, an exemplary bias supply 1601 is shown to apply a cyclic voltage function to a capacitively coupled plasma load 1602 (which exists together with, for example, a plasma chamber 101). The output node 1604 of the bias supply 1601 is connected to the input node 1605 of the plasma load 1602, and the return node 1606 of the bias supply 1601 is connected to the return node 1607 of the plasma chamber 101. Return nodes 1606 and 1607 are typically made through the chassis or housing of both the bias supply and the plasma load, and because these are typically held at ground potential, they are also typically referred to as ground, chassis ground, or ground. As shown, the bias supply 1601 utilizes a DC supply 1603 as a voltage source, with the positive output terminal of the DC supply connected to ground and a large inductor L2 connected to the load side of a small inductor L1.

[0062] As shown, the first inductor L1 is coupled between the first node 1670 and the output node 1604 of the switch S, and the first node 1672 of the second inductor L2 is coupled to the output node 1604. A voltage source is coupled between the second node 1674 of the switch S and the second node 1676 of the inductor L2. A connection is also present between the return node 1606 and the second node 1674 of the switch S.

[0063] Referring to Figure 16B, an exemplary bias supply 1611 is shown to apply a cyclic voltage function to a capacitively coupled plasma load 1612. As shown, the bias supply 1611 utilizes a DC supply 1613, wherein the negative output terminal of the DC supply 1613 is connected to ground and a large inductor L2 is connected to the load side of a small inductor L1. As shown, the first inductor L1 is coupled between the first node 1670 of switch S and the output node 1604, and the first node 1672 of the second inductor L2 is coupled to the output node 1604. A voltage source is coupled between the second node 1674 of switch S and the second node 1676 of inductor L2, and a connection is made between the return node 1606 and the second node 1676 of inductor L2.

[0064] Referring to Figure 16C, an exemplary bias supply 1621 is shown to apply a cyclic voltage function to a capacitively coupled plasma load 1622. As shown, the bias supply 1621 utilizes a DC supply 1623, wherein the positive output terminal of the DC supply 1623 is connected to ground and a large inductor L2 is connected to the load side of a small inductor L1. As shown, the first inductor L1 is coupled between the first node 1670 and the output node 1604 of the switch S. The first node 1672 of the second inductor L2 is coupled to the first node 1670 of the switch S. A voltage source is coupled between the second node 1674 of the switch S and the second node 1676 of the inductor L2, and a connection is made between the return node 1606 and the second node 1674 of the switch S.

[0065] Referring to Figure 16D, an exemplary bias supply 1631 is shown to apply a cyclic voltage function to a capacitively coupled plasma load 1632. As shown, the bias supply 1631 utilizes a DC supply 1633, wherein the negative output terminal of the DC supply 1633 is connected to ground and a large inductor L2 is connected to the load side of a small inductor L1. As shown, the first inductor L1 is coupled between the first node 1670 and the output node 1604 of the switch S. The first node 1672 of the second inductor L2 is coupled to the first node 1670 of the switch S. A voltage source is coupled between the second node 1674 of the switch S and the second node 1676 of the inductor L2. As shown, a connection is present between the return node 1606 and the second node 1676 of the inductor L2.

[0066] Referring to Figure 16E, an exemplary bias supply 1641 is shown to apply a cyclic voltage function to a capacitively coupled plasma load 1642. As shown, the bias supply 1641 utilizes a DC supply 1643 (as a voltage source), wherein the positive output terminal of the DC supply 1643 is connected to ground, and a transformer 1644 is used to connect to the plasma load 1642. The transformer includes a primary winding (represented by LLP and LP) and a secondary winding (represented by LS and LLS). The first node 1680 of the primary winding of the transformer is coupled to the first node 1670 of the switch S. The first node 1682 of the secondary winding of the transformer is coupled to the output node 1604. And the second node 1684 of the secondary winding of the transformer is coupled to the return node 1606. The DC supply 1643 (voltage source) is coupled between the second node 1674 of the switch S and the second node 1686 of the primary winding of the transformer.

[0067] Referring to Figure 16F, an exemplary bias supply 1651 is shown to apply a cyclic voltage function to a capacitively coupled plasma load 1652. As shown, the bias supply 1651 utilizes a DC supply 1653 as a voltage source, wherein the negative output terminal of the DC supply 1653 is connected to ground, and a transformer 1654 is used to connect to the load. The bias supplies 1641 and 1651 in Figures 16E and 16F include transformers. As shown, a first node of the primary winding of the transformer is coupled to a first node of a switch, a first node of the secondary winding of the transformer is coupled to an output node, and a second node of the secondary winding of the transformer is coupled to a return node. The transformer includes a primary winding (represented by LLP and LP) and a secondary winding (represented by LS and LLS). A first node 1680 of the primary winding of the transformer is coupled to a first node 1670 of the switch S. A first node 1682 of the secondary winding of the transformer is coupled to an output node 1604. Furthermore, the second node 1684 of the transformer's secondary winding is coupled to the return node 1606. The DC power supply 1643 (voltage source) is coupled between the second node 1674 of switch S and the second node 1686 of the transformer's primary winding. As shown, the second node 1686 of the transformer's primary winding is configured to be coupled to the return node 1607.

[0068] The methods described in connection with the embodiments disclosed herein can be implemented directly in hardware, as processor executable code encoded in a non-transitory tangible processor-readable storage medium, or a combination of both. Referring, for example, to FIG17, a block diagram depicting the actual components that can be used to implement the control layer disclosed herein is shown. As shown, in this embodiment, a display 1312 and non-volatile memory 1320 are coupled to bus 1322, which is also coupled to random access memory (RAM) 1324, a processing section (which includes N processing components) 1326, a field programmable gate array (FPGA) 1327, and a transceiver component 1328 including N transceivers. Although the components depicted in FIG17 represent actual components, FIG17 is not intended to be a detailed hardware diagram; therefore, many of the components depicted in FIG17 can be implemented by common components or distributed in other actual components. Furthermore, it is anticipated that other existing or yet-to-be-developed actual components and architectures can be utilized to implement the functional components described in Figure 17.

[0069] This display 1312 typically operates to provide a user interface for a user, and in several embodiments, the display is implemented as a touchscreen display. In general, non-volatile memory 1320 is non-transitory memory that functions to store (e.g., persistently store) data and processor executable code (including executable code associated with performing the methods described herein). In some embodiments, for example, non-volatile memory 1320 includes bootloader code, operating system code, file system code, and non-transitory processor executable code to facilitate the execution of a method of biasing a substrate using a single control switch.

[0070] In many implementations, the non-volatile memory 1320 is implemented using flash memory (e.g., NAND or ONENAND memory), but it is anticipated that other memory types can be utilized in the same way. Although code from the non-volatile memory 1320 may be executed, the executable code in the non-volatile memory is typically loaded into RAM 1324 and executed by one or more of the N processing units in the processing section 1326.

[0071] The N processing units associated with RAM 1324 typically operate to execute instructions stored in non-volatile memory 1320, thereby enabling the execution of the algorithms and functions disclosed herein. It should be understood that several algorithms are disclosed herein, but some of these algorithms are not shown in the flowcharts. Processor-executable code implementing the methods described herein may be persistently stored in non-volatile memory 1320 and executed by the N processing units associated with RAM 1324. As will be understood by those skilled in the art, processing unit 1326 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing units or combinations of hardware and software processing units (e.g., an FPGA or an FPGA including a digital logic processing unit).

[0072] Alternatively, non-transitory FPGA configuration instructions may be persistently stored in non-volatile memory 1320 and accessed (e.g., during startup) to configure a field-programmable gate array (FPGA) to implement the algorithms disclosed herein (e.g., including, but not limited to, the algorithms described with reference to Figures 15A and 15B).

[0073] Input component 1330 may receive signals (e.g., signals indicating the current and voltage obtained at the output of the disclosed bias supply). Furthermore, input component 1330 may receive phase information and / or synchronization signals between bias supply 108 and source generator 112, indicating one or more layers of the environment within plasma processing chamber 101 and / or synchronization control between the source generator and the single-switch bias supply. Signals received by the input component may include, for example, synchronization signals, power control signals for various generator and power supply units, or control signals from a user interface. It will be readily understood by those skilled in the art that sensors of any type, such as, but not limited to, directional couplers and voltage-current (VI) sensors, can be used to sample electrical parameters such as voltage and current, and signals indicating electrical parameters can be generated in the analog domain and converted to the digital domain.

[0074] Output components typically operate to provide one or more analog or digital signals to perform the opening and closing of switches and the control of the voltage sources described herein.

[0075] The described transceiver component 1328 includes N transceiver links, which can be used to communicate with external devices via wireless or wired networks. Each of the N transceiver links can represent a transceiver associated with a specific communication scheme (e.g., WiFi, Ethernet, Profibus, etc.).

[0076] As will be understood by those skilled in the art, the present disclosure can be embodied as a system, method, or computer program product. Therefore, the present disclosure can take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware layers, all of which are generally referred to herein as a "circuit," "module," or "system." Furthermore, the present disclosure can take the form of a computer program product implemented on one or more computer-readable media having computer-readable code implemented thereon.

[0077] As used herein, the phrase "at least one of A, B, or C" is intended to mean "A, B, C, or any combination of A, B, and C." The prior description of the disclosed embodiments is provided so that those skilled in the art can make or use the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the embodiments shown herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

[0078] The prior description of the disclosed embodiments is provided so that those skilled in the art can make or use the invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not intended to be limited to the embodiments shown herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

[0079] 101: Plasma Chamber 102: Plasma 103: Workpiece 104: Bias electrode 105: Source Electrode 108: Bias Supply 112: Source Generator 113: Source Matching Network 208: Bias Supply 210: Output / Output Node 211: Drive Signal 220: Switch 230: Voltage source 240: First Inductor 250: Second Inductor 260: Controller 270: Grounding Connection / Return Node 307: Return to node 310: Input / Input Node 570: Distribution of Ion Energy 672: Distribution of Ion Energy 774: Distribution of Ion Energy 1110: Output / Output Node 1120: Switch 1130: Voltage source 1140: Inductor 1150: Controller 1160: Transformer 1312: Monitor 1320: Non-volatile memory 1322: Busbar 1324: Random Access Memory (RAM) 1326: Processing Section 1327: Field Programmable Gate Array (FPGA) 1328: Transceiver component 1330: Input 1510, 1520, 1530, 1540, 1550: Steps (blocks) of the method in Figure 15A 1511, 1521, 1531, 1541: Steps (blocks) of the method in Figure 15B 1601, 1611, 1621, 1631, 1641, 1651: Bias supply 1602, 1612, 1622, 1632, 1642, 1652: Plasma load 1603, 1613, 1623, 1633, 1643, 1653: DC power supplies 1604: Output node 1605: Input node 1606, 1607: Return to node 1644, 1654: Transformers 1670: The first node of switch S 1672: First node of inductor L2 1674: The second node of switch S 1676: The second node of inductor L2 1680: The first node of the primary winding of a transformer 1682: The first node of the secondary winding of a transformer 1684: The second node of the secondary winding of a transformer 1686: The second node of the primary winding of a transformer

Claims

1. An apparatus for generating waveforms, the apparatus comprising: First node; A switching path that couples a second node to the first node and, in response to the closing of the switching path, generates a pulse at the first node; a power supply that is coupled to the first node and is configured to generate a ramp voltage at the first node after the switching path is opened. And a controller for: repeatedly closing and opening the switching path to generate pulses; and adjusting the current flowing to the first node by changing the repetition rate of closing and opening the switching path.

2. The device of claim 1, wherein the controller is configured to repeatedly close the switching path for a period of time so that the current through the switching path completes a complete cycle from zero to peak, back to zero, to reverse peak and back to zero.

3. The device of claim 1, wherein the controller is configured to regulate the current flowing to the first node by changing the voltage of the power supply and changing the repetition rate of the closing and opening of the switching path.

4. The device of claim 1, wherein when the switch path is closed, the second node is coupled to the first node via an inductor.

5. The device of claim 1, wherein the power supply is coupled to the first node when the switch path is closed.

6. The device as requested in item 1, wherein the second node is configured to be coupled to ground.

7. The device as claimed in claim 1, wherein the power supply is coupled to the first node via an inductor.

8. The device of claim 7, wherein the power supply controls the current supplied to the first node in a controllable manner, thereby controlling the ramp voltage at the first node.

9. A method for generating a waveform, the method comprising: The voltage is repeatedly coupled to a node and decoupled from that node to generate the pulse of the waveform; Current is supplied to the node to generate a ramp of the waveform between each of the pulses; and the current flowing to the node is adjusted by changing the repetition rate of coupling the voltage to the node and decoupling the voltage from the node.

10. The method of claim 9, further comprising: The current supplied to the node is controlled to control the ramp of the waveform.

11. The method of claim 9, wherein coupling the voltage to the node comprises coupling the voltage to the node via an inductive element.

12. The method of claim 9, wherein providing the current to the node comprises providing the current to the node via an inductive element.

13. An apparatus for generating waveforms, the apparatus comprising: First node; A switch, which is coupled to the first node and the second node; A controller configured to close and open the switch to generate pulses of the waveform; and a power supply coupled to the first node and the second node, the power supply being configured to generate a ramp of the waveform between the pulses; The controller is configured to adjust the repetition rate of the switch closure, thereby adjusting the ramp of the waveform.

14. The device of claim 13, wherein the controller is configured to adjust the voltage of the power supply and the repetition rate of the switch closure.

15. The device of claim 13, wherein the power supply is coupled to the first node via an inductor.

16. The device of claim 13, wherein the switch is coupled to the first node via an inductor.

17. The device of claim 13, wherein the controller includes at least one of a processor or a field-programmable gate array, and the controller includes a non-transitory computer-readable medium containing stored instructions for the processor to execute or to configure the field-programmable gate array to control the operation of the switch.

18. The device of claim 13, wherein the controller is configured to repeatedly close the switch for a period of time so that the current through the switch completes a full cycle from zero to peak, back to zero, to a reverse peak and back to zero.

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