Flat epitaxial wafer having minimal thickness variation

Abstract

This disclosure provides an epitaxial wafer comprising a silicon substrate having a top surface and an epitaxial layer on said top surface, wherein the epitaxial layer has a thickness ranging from 0.3 µm to 1.0 µm, with a thickness variation of 1% or less. A method for fabricating such an epitaxial wafer includes placing the silicon substrate on a pedestal in an epitaxial reactor; rotating the pedestal at a rotational rate (D); introducing a source gas into the epitaxial reactor; and growing an epitaxial layer of desired thickness (B) on the silicon substrate at a growth rate (A). The source gas is applied for a growth time (C) satisfying C = B / A, and the rotational rate (D) is selected from the range of 22 to 70 rpm, which allows the pedestal to rotate an exact integer number of revolutions (E) based on the relationship D = E / C.

Description

Technical Field

[0001] This disclosure relates to epitaxial wafers, and more particularly to a method for manufacturing epitaxial wafers. Prior Technology

[0002] FinFETs provide three-dimensional fins (102), each fin serving as a channel contacted by a gate (104) on three sides, as shown in Figure 1(a). This structure helps reduce leakage current in conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). However, as design rules mandate higher densities in semiconductor devices, channel lengths in transistors are shortened, and even the three-sided contact with the gate provided by the vertical fin channels of a finFET can become prone to leakage current. In a gate-all-around (GAA) FET, as shown in Figure 1(b), channels (106) are stacked on top of the surface of a silicon wafer (108), and the gate (110) surrounds all four sides of the channel. Because such channels are stacked above the silicon wafer, the surface (112) of the silicon wafer is required to have significantly improved flatness and uniformity. Summary of the Invention

[0003] This disclosure relates to epitaxial wafers useful for devices using fully wound gate field-effect transistors (GAA FETs). The extremely thin epitaxial layer of this disclosure provides a flat and smooth surface with very small or no thickness variation.

[0004] The first morphology disclosed herein includes: a silicon substrate having a top surface; and a thin epitaxial layer formed on the top surface, the epitaxial layer being substantially unaffected by surface irregularities caused by process-induced defects (PID) of the underlying silicon substrate.

[0005] The second aspect disclosed herein relates to improving the edge flatness of epitaxial wafers (i.e., the minimum squares / range of the edge site frontsurface referenced (ESFQR)) and thereby improving the overall flatness of the epitaxial wafer surface.

[0006] The third variant disclosed herein includes an improved maximum ESFQR with an edge exclusion region of 1 mm to 2 mm.

[0007] The fourth pattern disclosed herein includes chamfer widths ranging from 150µm to 450µm.

[0008] The fifth paradigm disclosed herein includes silicon substrates without dislocation clusters and COP defects.

[0009] The sixth profile disclosed herein includes silicon substrates without COP (crystal originated particles) defects with a maximum cross-sectional width of 110 nm or greater.

[0010] The seventh type disclosed herein includes a nitrogen-containing silicon substrate.

[0011] The eighth type disclosed herein includes a silicon substrate cut from a {110} planar crystal at a tilt angle of 0.1 to 1.2 degrees.

[0012] The ninth pattern disclosed herein includes an epitaxial layer with a haze level of 1.20 ppm or less.

[0013] The tenth pattern disclosed herein includes an epitaxial layer having both a thickness variation of 1.0% or less and thickness uniformity.

[0014] The eleventh variant disclosed herein includes a method for manufacturing an epitaxial wafer, the method comprising: placing a silicon substrate on a susceptor in an epitaxial reactor; rotating the susceptor at a rotational rate (D); and introducing a source gas into the epitaxial reactor to grow an epitaxial layer having a desired thickness (B) on the silicon substrate at a growth rate (A); wherein the source gas is applied for a growth time (C) satisfying C = B / A, and the rotational rate (D) is selected from the range of 22 to 70 rpm, and allows the susceptor to rotate an integer number of revolutions (E) based on the relationship D = E / C. Simple Explanation of the Diagram

[0015] Figure 1(A) is a general perspective view of a finned FET device; Figure 1(B) is a general perspective view of a GAA FET device; Figures 2(A) and 2(B) illustrate a method for determining the ESFQR of a wafer; Figure 3 illustrates a cubic crystal as defined by its Miller indices; Figure 4 illustrates the measurement principle used to calculate the thickness variation of the epitaxial layer; Figure 5 illustrates the measurement principle used to calculate the thickness uniformity of epitaxial layers; Figure 6(A) illustrates a method for producing a silicon substrate having a tilt angle according to an embodiment of the present disclosure; Figure 6(B) is a separate depiction of a silicon substrate cut from the inclined plane shown in Figure 6(A); Figures 7(A) and 7(B) illustrate the following: <110> Crystal orientation (i.e., along the Y-axis) or along <100> Reference notch along the crystal orientation (i.e., along the X-axis); Figure 8 illustrates a method for manufacturing an epitaxial wafer according to an embodiment of the present disclosure; Figure 9 illustrates a shorter chamfer width for a wafer relative to a longer chamfer width; Figures 10(A) and 10(B) illustrate preferred epitaxial wafers having thin epitaxial layers according to embodiments of the present disclosure; and Figure 10(C) illustrates a conventional epitaxial wafer with a thicker epitaxial layer. Implementation

[0016] The details shown herein are by way of example and are presented solely for the purpose of illustrative discussion of the exemplary components disclosed herein, and are intended to illustrate the most useful and readily understandable descriptions of the principles and conceptual forms of the exemplary components. In view of this, no attempt is made to show the structural details of these exemplary components in more detail than necessary for a basic understanding of the exemplary components; the description, taken in conjunction with the accompanying drawings, makes it apparent to those skilled in the art how the forms of the exemplary components can be implemented in practice.

[0017] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended to indicate that the associated numerical value includes a tolerance of ±10% around the stated value. Furthermore, when percentages are mentioned in this specification, it is intended to indicate that those percentages are based on weight, i.e., weight percentage. The expression “up to” includes quantities from zero to the expressed upper limit and all values ​​in between. When a range is specified, the range includes all values ​​in between, such as increments of 0.1%. Additionally, when the terms “generally” and “substantially” are used in conjunction with geometry, it is intended to indicate that precision of the geometry is not required, but the latitude of the shape is within the scope of this disclosure.

[0018] In the accompanying drawings, the dimensions of layers and areas may be enlarged for clarity of illustration. Throughout this document, similar element symbols refer to similar elements. Throughout the specification, the same element symbols indicate the same parts. For ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “up” may be used herein to describe the relationship or function of one element or part illustrated in the figures with other elements or parts. It should be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or parts will be oriented as “above” other elements or parts. Thus, the illustrative term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0019] The exemplary components described herein are illustrated with reference to cross-sectional examples, which are schematic examples of idealized components (and intermediate structures) of the example components. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the example components should not be construed as limited to the specific shapes of the regions illustrated herein, but will include, for example, deviations in shape due to manufacturing processes. The regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of material, nor are they intended to limit the scope of the example components.

[0020] This disclosure relates to epitaxial wafers for devices using fully wound gate field-effect transistors (GAA FETs). The extremely thin epitaxial layer of this disclosure provides a flat and smooth surface with very small or no thickness variation. The thin epitaxial layer formed on the top surface of the silicon substrate is substantially unaffected by surface irregularities caused by process-induced defects (PIDs) on the top surface of the underlying silicon substrate.

[0021] The preferred thickness of the epitaxial layer disclosed herein is in the range of 0.3 µm to 1.0 µm. Preferably, the thickness of the epitaxial layer of the epitaxial wafer disclosed herein is about 0.5 µm.

[0022] One of the key features of this disclosure relates to ESFQR (Site Frontside Least Squares Range) in relation to the overall flatness of a wafer. ESFQR is an analytical characterization of the area near the edge of the wafer, affecting the flatness of the entire wafer. Here, SFQR (Site Frontside Least Squares Range) is a measurement of flatness along the entire wafer surface in a small segment. ESFQR is an index representing the flatness found by measuring the SFQR within a fan-shaped region formed in the peripheral portion of the wafer. A smaller ESFQR indicates higher flatness. ESFQR and SFQR are indices used to measure wafer flatness according to SEMI standards (M1, M67, or M1530). ESFQR can be determined using a flatness measurement system such as the WAFERSIGHT 2 manufactured by KLA-Tencor Corporation.

[0023] The ESFQR of the wafer can be determined as shown in Figures 2(a) and 2(b). In Figure 2(a), the 300mm wafer (202) is divided into 72 sectors or regions (204), each region having a 5-degree arc, and each region having a 1mm edge exclusion region (206) and a region length of 15mm. The edge exclusion region is arbitrarily chosen here and can be from 1mm to 2mm. In this case, "maximum ESFQR" means the maximum ESFQR value determined among the 72 regions.

[0024] As illustrated in Figure 2(b), the maximum value α of the location (204) is determined to be the maximum height above the least square location reference plane (208), and the minimum value β is determined to be the minimum value below the least square location reference plane (208). Mathematically, ESFQR is the absolute value of the maximum range from the least square location reference plane (208) in the edge location, or ESFQR = |α| + |β|.

[0025] Preferably, the maximum ESFQR of the embodiments disclosed herein is no greater than 11.3 nm in the edge exclusion region (206) about 1 mm from the edge of the wafer.

[0026] As a review of the nomenclature of basic crystal planes and directions, Miller indices are three-dimensional coordinate systems for crystals based on the unit cell. These coordinate systems can indicate directions or planes and are often written as (hkl). Some examples of Miller indices on a cubic crystal (302), as illustrated in Figure 3, include

[0111] , the body diagonal (304);

[0110] , the face diagonal (306); and (100), the face plane (308). The brackets surrounding hkl have specific designations, where [hkl] indicates a direction; <hkl>The directional family is represented by (hkl); the plane is represented by (hkl); and the plane family is represented by {hkl}. A silicon crystal with a cubic silicon lattice can be defined according to its equivalent plane family determined by its seed crystal, i.e., a {hkl} plane silicon crystal. In this respect, crystals can be grown to form either the {100} or {110} planes by selecting different seed crystals at the beginning of the crystal extraction from molten silicon. For the {110} and {100} planes and... <110> and <100> The determination of crystal orientation and related wafer dicing techniques are known in the art, as illustrated in examples in U.S. Patent Nos. 8,152,919 and 5,904,136.

[0027] Tables 1 and 2 illustrate how the thickness of the epitaxial layer affects ESFQR. Table 1 presents measurements from epitaxial wafers using a {100} planar silicon substrate and epitaxial layer thicknesses ranging from 0.3 µm to 2.0 µm. Table 2 presents measurements from epitaxial wafers using a {110} planar silicon substrate and epitaxial layer thicknesses also ranging from 0.3 µm to 2.0 µm. Table 1 Epitaxial layer thickness (µm) Maximum ESFQR (nm) 0.3 10.0 0.5 10.0 1.0 11.0 2.0 18.0 Table 2 Epitaxial layer thickness (µm) Maximum ESFQR (nm) 0.3 10.7 0.5 10.4 1.0 11.1 2.0 15.1

[0028] Tables 1 and 2 show the preferred range of epitaxial layer thickness from 0.3 µm to 1.0 µm. As shown, for both {100} and {110} substrates, this range keeps the maximum ESFQR at 11.1 nm or less.

[0029] Another aspect disclosed herein relates to improving the thickness variation of epitaxial layers. Yet another aspect disclosed herein relates to the thickness uniformity of epitaxial layers. Figure 4 illustrates the measurement principle for the thickness variation of epitaxial layers.

[0030] As shown in Figure 4, the thickness variation of the epitaxial layer [%] can be calculated as follows: |(AB)| / (A+B)×100, where A and B are any two measured thicknesses of the epitaxial layer within 10 mm of the wafer edge. However, as shown in the figure, A and B are symmetrical with respect to the center.

[0031] The thickness variation of the epitaxial layer disclosed herein is preferably 1.0% or less.

[0032] Similarly, as shown in Figure 5, the thickness uniformity [%] of the epitaxial layer disclosed herein can be calculated as follows: (Max-Min) / (Max+Min)×100, where "Max" and "Min" are the maximum and minimum thicknesses of the epitaxial layer (502) at any four symmetrical points (i.e., two pairs of symmetrical points) within 10 mm from the wafer edge and at the center of the epitaxial layer, respectively. The thickness uniformity of the epitaxial layer disclosed herein is preferably 1.0% or less.

[0033] The thickness variation and uniformity of the epitaxial layer disclosed herein can be achieved through various manufacturing methods. Specifically, according to this disclosure, a preferred silicon substrate (on which the epitaxial layer is grown) is a silicon substrate cut from the {110} plane at a tilt angle of ±0.1 to 1.2 degrees. Preferably, this tilt angle can be achieved by rotating the {110} plane relative to the Y-axis (tilt direction) in the XY plane. This arrangement is shown in Figure 6(a) and further described below.

[0034] Figure 6(a) illustrates a single-crystal silicon ingot (602) pulled perpendicularly along the Z-axis (604). It will be understood that each axis shown in Figure 6(a) represents the following direction related to the crystal structure. The Z-axis (604) is aligned with the direction in which the crystal is pulled. <110> Direction. The Y-axis (606) is another plane perpendicular (orthogonal) to the Z-axis. <110> Direction. The X-axis (608) is in a plane orthogonal to the Z-axis. <100> direction.

[0035] If there are sites in the silicon substrate <110> If there is a notch in the direction of the notch, then the Y-axis is a line passing through the notch and reaching the center of the silicon substrate, as shown in Figure 7(a). If there is a notch in the silicon substrate located at... <100> For a notch in the direction of the notch, the Y-axis is a line orthogonal to another line passing through the notch and reaching the center of the silicon substrate, as shown in Figure 7(b).

[0036] The X' axis (610) is the X-axis that rotates around the Y-axis.

[0037] The tilt angle θ(612) is the angle between the X-axis and the X'-axis.

[0038] Both positive tilt angle and negative tilt angle refer to the same silicon substrate.

[0039] The {110} silicon substrate disclosed herein is cut along a certain direction at an angle (referred to herein as "tilt angle" (612) and "tilt direction" (614), respectively). As illustrated in Figure 6(a), consider, for example, a {110} silicon substrate from a crystal disposed in a three-dimensional axis (X, Y, Z axis), if the direction of crystal growth is set along the Z axis (along... <110> If the direction is specified, the silicon substrate cut from the crystal lies in the XY plane, which is orthogonal to the Z-axis. Here, the X-axis is along... <100> Orientation aligned, and Y-axis along <110> Orientation alignment. In this configuration, the tilt angle and tilt direction refer to a small angular displacement of this XY plane relative to the Y-axis (in either direction). This rotated plane is referred to herein as the "tilted plane" (616), and therefore, the silicon substrate cut at the tilt angle lies in this tilted plane. Preferably, the tilt angle is in the range of 0.1 to 1.2 degrees.

[0040] Figure 6(b) is a separate depiction of a silicon substrate cut from an inclined plane (616) as shown in Figure 6(a). Here, the normal vector (618) is orthogonal to this inclined plane (616) (i.e., orthogonal to the surface of the silicon substrate), and the inclination angle θ (612) is the sum of the normal vector (618) and the angle along the plane. <110> The angle between the first vectors of the direction, the first vector (620) being along the direction the crystal is pulled out. The first vector (620) is orthogonal to the first vector along the direction the crystal is pulled out. <110> A second vector (622) extends in the inclined plane (616) along the radial direction of the silicon substrate. Furthermore, along... <100> The third vector (624) is orthogonal to the second vector (622). Furthermore, as shown in Figure 6(b), the fourth vector (626) is orthogonal to the normal vector (618), and the angle between the third vector (624) and the fourth vector (626) also constitutes the tilt angle θ (612). Figure 6(b) further shows that the second vector (622) and the fourth vector (626) lie in the tilt plane (616). Note that, given a wafer (silicon substrate) with a {110} plane, these vectors, including the first vector and the normal vector (618), can be determined by X-ray diffraction, and thus the tilt angle θ (612) can be determined.

[0041] It should be noted that growing crystals in the {110} plane is not an exact science. For example, in the early stages of crystal growth, small deviations in crystal alignment may be necessary to prevent dislocation defects. Any such small deviations will be within tolerance if the resulting silicon substrate exhibits the electrical properties expected in the {110} plane. Furthermore, those skilled in the art will understand that if the resulting silicon substrate more or less exhibits the expected electrical properties of the {110} plane, then a crystal grown with any such small deviation is still a {110} crystal.

[0042] Compared to {100}-planar substrates, {110}-planar silicon substrates have shown improved hole mobility, but at the cost of increased haze levels and a rougher surface. Therefore, {110} wafers with enhanced hole mobility should be particularly useful in the aforementioned GAA FET applications. However, in terms of surface roughness and high haze levels, using a conventional {110} substrate alone would be unacceptable. In another embodiment disclosed herein, the silicon substrate is cut from a {110}-planar crystal at a tilt angle of ±0.1 to 1.2 degrees, wherein this tilt angle is achieved by rotating the {110}-planar substrate relative to the Y-axis in the XY plane.

[0043] This tilt angle, as disclosed, helps maintain desired haze levels and desired surface roughness levels, which are difficult to achieve from conventional {110} silicon substrates. Therefore, as in the preferred embodiment of this disclosure, providing the silicon substrate from the {110} plane at a tilt angle provides greater carrier mobility without compromising surface roughness or haze levels. Preferably, the haze level of the epitaxial layer of this disclosure is 1.2 ppm or less. The haze level can be measured using the DWO mode of a SURFSCAN SP2 manufactured by KLA-Tencor.

[0044] Figures 7(a) and 7(b) illustrate the method of forming a reference notch on a {110} wafer. Figure 7(a) illustrates the notch at the end of the Y-axis or along... <110> A notch (702) in the crystal orientation. Example 7(b) shows a notch at the end of the X-axis or along... <100> Notch (704) in the crystal orientation.

[0045] Table 3 shows the haze level measurements (ppm) for various epitaxial wafers with different epitaxial layer thicknesses and tilt angles, each of which has a {110} silicon substrate. Table 3 Tilt angle (degrees) Epitaxial layer thickness (µm) 0.3µm 0.5µm 1.0µm 2.0µm Haze level (ppm) 0 1.88 1.57 2.25 2.63 0.1 0.88 0.85 0.88 0.87 0.4 0.65 0.62 0.68 0.65 0.7 0.66 0.63 0.64 0.72 1 0.64 0.59 0.67 0.69 1.2 0.59 0.61 0.65 0.65

[0046] Table 3 illustrates that for thin epitaxial layer thicknesses, tilt angles between 0.1 and 1.2 degrees produce low haze levels of no more than 0.88 ppm.

[0047] A method for producing an epitaxial wafer according to an embodiment of this disclosure is as follows. As shown in Figure 8, a silicon substrate (802) is disposed on a pedestal (804) and rotated in a reaction chamber (not shown). A gas inlet (806) receives a silicon source gas (808) (such as SiHCl3) and a carrier gas (such as H2). A dopant gas (such as B2H6) may also be introduced through the gas inlet (806). The silicon substrate (802) is heated from above and below and exposed to the silicon source gas for the growth of the epitaxial layer. The dopant is included in the silicon source gas (808) and may be carried by the carrier gas. The pedestal (804) is rotated as the epitaxial layer grows on the silicon substrate (802).

[0048] The carrier gas flow rate is typically 30-100 standard liters per minute (SLM). The silicon source gas flow rate is typically 3-20 SLM. The growth temperature is typically fixed between 1100°C and 1175°C. The epitaxial layer growth time is in the range of 0.1 to 1.0 minutes. The substrate rotation rate is preferably 22-70 revolutions per minute (RPM). It has been found that if the substrate rotation rate is slower than the lower limit of the above-preferred range (22 RPM), the epitaxial layer thickness at or around the edges tends to become excessive. Conversely, if the substrate rotation rate is faster than the upper limit of the above-preferred range (70 RPM), the epitaxial layer thickness in the central portion of the wafer tends to become excessive. Therefore, it is important to set the substrate rotation rate between 22 and 70 RPM to achieve an overall epitaxial layer thickness uniformity of 1.0% or less.

[0049] Table 4 shows the results of how the substrate rotation rate affects the thickness uniformity of the epitaxial layer. In this example, a silicon substrate cut from the {100} plane was placed in the reaction chamber and rotated to grow an epitaxial layer of 0.5 µm. The substrate was rotated incrementally between 22 and 70 RPM. Table 4 Rotational speed (rpm) Epitaxial layer thickness uniformity (%) 20 1.3 twenty two 0.8 25 0.7 30 0.7 35 0.6 40 0.7 45 0.6 50 0.5 55 0.7 60 0.7 65 0.7 70 0.9 72 1.2

[0050] Table 5 also shows the results of how the substrate rotation rate affects the thickness uniformity of the epitaxial layer. In this example, a silicon substrate cut from the {110} plane at a tilt angle of 1.0 degrees was placed in the reaction chamber and rotated to grow an epitaxial layer of 0.5 µm. The substrate was rotated incrementally between 22 and 70 RPM. Table 5 Rotational speed (rpm) Epitaxial layer thickness uniformity (%) 20 1.2 twenty two 0.8 25 0.8 30 0.6 35 0.5 40 0.6 45 0.6 50 0.7 55 0.6 60 0.7 65 0.7 70 0.8 72 1.4

[0051] As shown in Tables 4 and 5, for epitaxial wafers of both {100} and {110} silicon substrates, the thickness uniformity of the epitaxial layer can be maintained at 1.0% or less by setting the pedestal rotation speed in the range of 22 to 70 RPM.

[0052] Traditionally, the growth of the epitaxial layer on an epitaxial wafer is controlled by the growth rate and reaction time to achieve a desired thickness, where the growth rate is influenced by the gas flow rate. In this disclosure, the number of pedestal turns is an integer value to ensure that a desired thickness variation is achieved in addition to the desired thickness of the epitaxial layer. In one embodiment, the integer number of turns can be determined at the desired level using the following assumptions: epitaxial thickness (B) = 0.5 µm; pedestal rate (D) = 25 rpm; epitaxial growth rate (A) = 2 µm / min; growth time (C) = to be determined; and integer number of turns (E) = to be determined. Thus, C = B / A or 0.25 min; and E can be calculated from D = E / C or E = D × C or 6.25, whereby E is the integer closest to 6.25, or 6 turns.

[0053] Table 6 shows the effect of rotating the substrate an integer number of times on the thickness variation of the epitaxial layer compared to non-integer rotations. For these examples, epitaxial wafers with silicon substrates cut from the {100} plane and epitaxial layers with a thickness of 0.5 µm were used. Temperature and gas flow rate were set to achieve an epitaxial growth rate of 2.0 µm / min. In each of Examples 1 and 2, the rotation number was adjusted to an integer value as described above. The thickness variation of the epitaxial layer was measured and recorded. In the comparative examples, the conditions were the same except that the rotation number of the substrate was a non-integer value. Table 6 Comparison Examples Example 1 Example 2 Number of laps 12.5 10 17 Rotational speed (rpm) 50 40 68 Epitaxial layer thickness variation (%) 1.4 0.6 0.7

[0054] Table 7 also shows the effect of rotating the substrate an integer number of times on the thickness variation of the epitaxial layer compared to non-integer rotations. For these examples, epitaxial wafers with silicon substrates cut from the {110} plane and epitaxial layers with a thickness of 0.5 µm were used. Temperature and gas flow rate were set to achieve an epitaxial growth rate of 2.0 µm / min. In each of Examples 1 and 2, the rotation number was adjusted to an integer value as described above. The thickness variation of the epitaxial layer was measured and recorded. In the comparative examples, the conditions were the same except that the rotation number of the substrate was a non-integer value. Table 7 Comparison Example 1 Example 1 Example 2 Number of laps 12.5 10 17 Rotational speed (rpm) 50 40 68 Epitaxial layer thickness variation (%) 1.5 0.6 0.6

[0055] The results in Tables 6 and 7 demonstrate that rotating the substrate an integer number of times is crucial for keeping the thickness variation of the epitaxial layer sufficiently low. They also show that both {100} and {110} epitaxial wafers benefit from implementing an integer number of substrate rotations during epitaxial growth.

[0056] Table 8 further illustrates how the number of integer rotations of the substrate affects the thickness variation of epitaxial layers of various thicknesses. Table 8 records the thickness variation data of {100} epitaxial wafers with epitaxial layers of three different thicknesses (0.3, 0.5, and 1.0 µm). Table 8 Epitaxial layer thickness (µm) Epitaxial layer thickness variation (%) Comparison Examples (Non-integer) This disclosure example (Integer) 0.3 1.8 0.8 0.5 1.5 0.7 1.0 1.1 0.8

[0057] Table 9 also shows how rotating the base an integer number of times affects the thickness variation of epitaxial layers of various thicknesses. Table 9 records the thickness variation data of {110} epitaxial wafers with epitaxial layers of three different thicknesses (0.3, 0.5, and 1.0 µm). Table 9 Epitaxial layer thickness (µm) Epitaxial layer thickness variation (%) Comparison Examples (Non-integer) This disclosure example (Integer) 0.3 1.9 0.9 0.5 1.7 0.8 1.0 1.2 0.8

[0058] The results in Tables 8 and 9 show that, for various wafer types and epitaxial layer thicknesses, rotating the substrate an integer number of times keeps the thickness variation at a significantly low value, regardless of the thickness of the epitaxial layer.

[0059] Another embodiment of the epitaxial wafer disclosed herein includes a preferred chamfer width on the top surface of the silicon substrate ranging from 150 µm to 450 µm. Conventionally, the chamfer width of epitaxial wafers tends to be wider than the preferred chamfer width disclosed herein, resulting in a smaller active area overall. As shown in Figure 9, the preferred epitaxial wafer (902) disclosed herein includes a thinner epitaxial layer thickness (904) and a shorter chamfer width (906) compared to the conventional chamfer width (908) of conventional epitaxial wafers.

[0060] Figure 9 depicts a conventional epitaxial layer (910) in the dashed section. Typically, the thickness of a conventional epitaxial layer is about 2 micrometers. In contrast, Figure 9 further shows the preferred thickness (904) of the epitaxial layer disclosed herein (below the dashed section), which ranges from 0.3 to 1.0 micrometers.

[0061] The shorter chamfer width disclosed in this paper further improves ESFQR.

[0062] Table 10 illustrates the effect of chamfer width on ESFQR. In this demonstration, {100} epitaxial wafers with epitaxial layer thicknesses ranging from 0.3 µm to 2.0 µm were used, and each wafer was tested for chamfer widths ranging from 150 µm to 550 µm. The maximum ESFQR was measured for each wafer at different chamfer widths. Table 10 Epitaxial layer thickness (µm) Chamfer width (µm) 150µm 250µm 350µm 450µm 550µm Maximum ESFQR (nm) 0.3 9.7 9.6 9.7 10.0 13.5 0.5 9.5 9.7 10.0 10.0 13.6 1.0 10.0 10.2 10.7 11.0 15.4 2.0 11.1 12.5 16.3 18.0 24.7

[0063] Table 11 also shows the effect of chamfer width on ESFQR. In this demonstration, {110} epitaxial wafers with epitaxial layer thicknesses ranging from 0.3µm to 2.0µm were used, and each wafer was tested for chamfer widths ranging from 150µm to 550µm. The maximum ESFQR was measured for each wafer at different chamfer widths. Table 11 Epitaxial layer thickness (µm) Chamfer width (µm) 150µm 250µm 350µm 450µm 550µm Maximum ESFQR (nm) 0.3 9.1 9.1 9.5 10.7 13.3 0.5 9.2 9.1 9.8 10.4 13.6 1.0 9.9 9.9 10.4 11.1 15.6 2.0 11.5 12.1 13.9 15.1 20.3

[0064] The results in Tables 10 and 11 show that chamfer widths in the range of 150 µm to 450 µm provide the maximum ESFQR with an expected value of less than 11.1 nm. More importantly, this range of chamfer widths provides an acceptable maximum ESFQR for wafers with epitaxial layers of varying thicknesses (i.e., in the range of 0.3 to 1.0 µm).

[0065] As previously described, the ultrathin epitaxial layer disclosed herein provides a flat and smooth surface with little or no thickness variation, and this thin epitaxial layer formed on the top surface of the silicon substrate is substantially unaffected by surface irregularities caused by process-induced defects (PIDs) on the top surface of the underlying silicon substrate. However, it is preferred that this disclosure includes a silicon substrate substantially free of COP defects with a maximum cross-sectional width of 110 nm or greater. Particularly preferred is that this disclosure includes a silicon substrate substantially free of dislocation clusters and COP defects.

[0066] Figures 10(a) and 10(b) illustrate preferred epitaxial wafers of this disclosure. Figure 10(a) illustrates an epitaxial wafer having a relatively thin epitaxial layer (1001) between 0.3 and 1.0 µm and substantially free of COP defects in the silicon substrate (1002). Figure 10(b) also illustrates a relatively thin epitaxial layer (1001) having COP defects (1005) with a cross-sectional width less than 110 nm in the silicon substrate (1002) and substantially free of COP defects of larger dimensions (e.g., cross-sectional widths of 110 nm or greater).

[0067] In contrast, example 10(c) illustrates a conventional epitaxial wafer with an undesirably thick epitaxial layer (1003) between 2 and 4 µm and COP defects (1006) with a cross-sectional width of 110 nm or greater.

[0068] This disclosure is not limited to the components described above, and various variations and modifications may be possible without departing from the scope of this disclosure.

[0069] 102: Three-dimensional fins 104: Gate 106: Channel 108: Silicon wafer 110: Gate 112: The surface of a silicon wafer 202: Wafer 204: Location 206: Edge Exclusion Area 208: Reference Plane 302: Cubic crystal 304: Body diagonal 306: Face diagonal 308: Plane 502: Epitaxial layer 602: Monocrystalline silicon ingot 604: Z-axis 606: Y-axis 608: X-axis 610:X' axis 612: Inclination angle θ 614: Inclination direction 616: Inclined plane 618: Normal vector 620: First Vector 622: Second Vector 624: Third Vector 626: Fourth Vector 702: Notch 704: Notch 802: Silicon substrate 804: Base 806: Gas Inlet 808: Silicon source gas 902: Epistar wafer 904: Thickness 906: Chamfer width 908: Chamfer width 910: Epitaxial layer 1001: Epitaxial layer 1002: Silicon substrate 1003: Epitaxial layer 1005: COP Defect 1006: COP Defect< / hkl>

Claims

1. An epitaxial wafer, comprising: A single-crystal silicon substrate having a top surface; And an epitaxial layer mainly composed of silicon on the top surface, wherein the epitaxial layer has a thickness in the range of 0.3µm to 1.0µm, and the thickness variation is defined as a percentage of the absolute value of the thickness difference between any two symmetrical points of the epitaxial layer within about 10mm of the outer edge of the epitaxial wafer divided by the sum of the thicknesses, which is 1% or less.

2. The epitaxial wafer of Request 1 further includes an Edge Site Frontsurface referenced least sQuares / Range (ESFQR) of 11.3 nm or smaller.

3. The epitaxial wafer of claim 2, wherein the maximum ESFQR is determined by an edge exclusion region having a diameter of 1 mm to 2 mm.

4. The epitaxial wafer of claim 1 further includes a chamfer width on the top surface in the range of 150µm to 450µm.

5. As in request item 1, the epitaxial wafer, wherein, The single-crystal silicon substrate is essentially free of dislocation clusters and COP defects.

6. As in request item 1, the epitaxial wafer, wherein, The single-crystal silicon substrate is substantially free of COP defects with a maximum cross-sectional width of 110 nm or greater.

7. As in request item 6, the epitaxial wafer, wherein, The single-crystal silicon substrate contains nitrogen.

8. As in request item 1, the epitaxial wafer, wherein, The single-crystal silicon substrate is cut from a crystal, which forms a {110} plane growing along a Z-axis. The single-crystal silicon substrate forms an XY plane orthogonal to the Z-axis, wherein the XY plane includes an X-axis in the <100> direction and a Y-axis in the <110> direction. Furthermore, the single-crystal silicon substrate is cut by rotating the XY plane relative to the Y-axis at an inclined angle.

9. The epitaxial wafer of claim 8, wherein the tilt angle is in the range of 0.1 to 1.2 degrees.

10. The epitaxial wafer of claim 9, wherein the haze level of the epitaxial layer is 1.20 ppm or less.

11. The epitaxial wafer of claim 1 further includes a chamfer width on the epitaxial layer in the range of 150µm to 450µm.

12. An epitaxial wafer, comprising: A single-crystal silicon substrate having a top surface; And an epitaxial layer, primarily composed of silicon, on the top surface, wherein the epitaxial layer has a thickness in the range of 0.3µm to 1.0µm, and a thickness uniformity defined as a percentage of the difference between the maximum and minimum thicknesses of any two pairs of symmetrical points and the center point of the epitaxial layer within approximately 10mm from the outer edge of the epitaxial wafer, divided by the sum of the maximum and minimum thicknesses, is 1% or less; a maximum ESFQR of 11.3nm or less is determined in an edge-exclusive region having a thickness of 1mm to 2mm; and a chamfer width on the top surface in the range of 250µm to 450µm.

13. The epitaxial wafer as described in request item 12, wherein, The single-crystal silicon substrate is essentially free of dislocation clusters and COP defects.

14. The epitaxial wafer as described in request item 12, wherein, The single-crystal silicon substrate is substantially free of COP defects with a maximum cross-sectional width of 110 nm or greater.

15. The epitaxial wafer as described in request item 14, wherein, The single-crystal silicon substrate contains nitrogen.

16. The epitaxial wafer as described in request item 12, wherein, The single-crystal silicon substrate is cut from a crystal, which forms a {110} plane growing along a Z-axis. The single-crystal silicon substrate forms an XY plane orthogonal to the Z-axis, wherein the XY plane includes an X-axis in the <100> direction and a Y-axis in the <110> direction. Furthermore, the single-crystal silicon substrate is cut by rotating the XY plane relative to the Y-axis at an inclined angle.

17. The epitaxial wafer of claim 16, wherein the tilt angle is in the range of 0.1 to 1.2 degrees.

18. The epitaxial wafer of claim 17, wherein the haze level of the epitaxial layer is 1.20 ppm or less.

19. The epitaxial wafer of claim 12 further includes a chamfer width on the epitaxial layer in the range of 150µm to 450µm.

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