Semiconductor devices

Abstract

This invention provides a semiconductor device capable of improving PRSM tolerance. The semiconductor device of the present invention includes: a semiconductor substrate; an insulating layer formed on the surface of the semiconductor substrate and having an opening that exposes the surface of the semiconductor substrate; and a surface electrode formed at least in a region overlapping the opening and connected to the semiconductor substrate at the opening, wherein the semiconductor substrate has: an n-type drift layer; a p-type impurity region formed on the surface portion of the drift layer and in contact with the surface electrode; and columnar regions disposed at predetermined intervals in the region where the p-type impurity region is formed, the impurity concentration being higher than that of the p-type impurity region and the location being deeper than that of the p-type impurity region, and adjacent columnar regions being formed at the vertices of a regular hexagon when viewed from the predetermined columnar regions.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Prior Technology

[0002] Previously, a semiconductor device having an n-type drift layer and a p-type impurity region formed on the surface portion of the drift layer and in contact with the surface electrode, constituting a pn diode, was known (for example, see Patent Document 1).

[0003] As shown in FIG5, a conventional semiconductor device 900 includes: a semiconductor substrate 910, an insulating layer 920 formed on the surface of the semiconductor substrate 910 and having an opening 922 exposed on the surface of the semiconductor substrate 910, and a surface electrode 930 formed at least in the region overlapping with the opening 922 and connected to the semiconductor substrate 910 at the opening 922.

[0004] The semiconductor substrate 910 has: an n+ type low-resistance semiconductor layer 911, an n type drift layer 912, a p- type p-type impurity region 913 formed on the surface of the drift layer 912, and a p-type peripheral impurity region 916 formed on the periphery of the p-type impurity region 913 in the surface of the drift layer 912, wherein the impurity concentration is higher than that of the p-type impurity region 913.

[0005] Furthermore, it is also known in the past that a semiconductor device 901 with a guard ring 918 is formed instead of the surrounding impurity region 916 (see Figure 6 for a prior art semiconductor device 901). Multiple guard rings 918 are formed on the outside of the p-type impurity region 913 in the surface portion of the drift layer 912 (3 rings).

[0006] Prior technology documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 10-335679

[0008] However, in the conventional semiconductor device 900 and the prior art semiconductor device 901, when reverse biased, the electric field is concentrated near the bottom of the outermost periphery of the surface portion of the drift layer 912. Specifically, it is concentrated near the bottom of the outermost periphery of the peripheral impurity region 916 in the conventional semiconductor device 900 (see the BD region in FIG5) and the bottom of the guard ring 918 in the prior art semiconductor device 901 (see the BD region in FIG6), which causes breakdown in this region, making it difficult to improve the PRSM tolerance (peak reverse power tolerance).

[0009] Generally, in order to improve PRSM tolerance (surge reverse power tolerance), a structure with concentrated electric field is formed by creating a peripheral impurity region and a guard ring on the outer periphery of the p-type impurity region. However, there are limits to this, and the industry generally requires semiconductor devices with higher PRSM tolerance.

[0010] The present invention was made in view of the above circumstances, and its object is to provide a semiconductor device capable of improving PRSM tolerance. Summary of the Invention

[0011] The semiconductor device of the present invention includes: a semiconductor substrate; an insulating layer formed on the surface of the semiconductor substrate and having an opening that exposes the surface of the semiconductor substrate; and a surface electrode formed at least in a region overlapping with the opening and connected to the semiconductor substrate at the opening, wherein the semiconductor substrate has: a drift layer of a first conductivity type; an impurity region of a second conductivity type formed on a surface portion of the drift layer and in contact with the surface electrode; and columnar regions of a second conductivity type, which, when viewed from above, are arranged at predetermined intervals in the region where the impurity regions of the second conductivity type are formed, have an impurity concentration higher than that of the impurity regions of the second conductivity type, and have a depth deeper than that of the impurity regions of the second conductivity type, wherein the columnar regions adjacent to a certain columnar region are formed at the vertices of a regular hexagon when viewed from above.

[0012] Invention Effects

[0013] According to the semiconductor device of the present invention, since the semiconductor substrate has impurity regions of a second conductivity type formed on the surface portion of the drift layer and in contact with the surface electrode; and columnar regions of a second conductivity type arranged at predetermined intervals in the region where the impurity regions of the second conductivity type are formed when viewed from above, having a higher impurity concentration and a deeper depth than the impurity regions of the second conductivity type, when reverse biased, the location where the electric field is applied can be extended from near the bottom of the outermost periphery of the drift layer to the entire region (cell region) where the impurity regions of the second conductivity type are formed. In other words, breakdown can be intentionally performed in a larger cell region before breakdown near the bottom of the outermost periphery of the second conductivity type semiconductor region. Therefore, compared with conventional semiconductor devices and prior art semiconductor devices, the area of ​​the breakdown region is larger, the breakdown current flows more easily, and thus the PRSM withstand capability can be improved. Furthermore, due to the above structure, the effects of reducing leakage current and improving recovery characteristics can also be obtained.

[0014] Furthermore, according to the semiconductor device of the present invention, since adjacent columnar regions are formed at the vertices of a regular hexagon when viewed from above, the area where the electric field is applied can be evenly extended to the entire region (cell region) where the impurity region of the second conductivity type is formed. As a result, the reverse current flows uniformly throughout the entire region (cell region) where the impurity region of the second conductivity type is formed, which can further increase the PRSM tolerance. Simple Explanation of the Diagram

[0015] Figure 1 is a schematic diagram illustrating the semiconductor device of Embodiment 1. Figure 1(a) is an enlarged cross-sectional view of the main part of the semiconductor device, Figure 1(b) is an enlarged plan view of the main part of the surface layer of the semiconductor substrate, and Figure 1(c) is an enlarged plan view of the main part of the configuration structure of the columnar regions. In addition, the channel blocking region 119 is omitted in Figure 1(b). Figure 2 is a probability distribution of PRSM tolerance levels for "conventional structures" and "invented structures". Figure 3 is an electric field distribution diagram of the semiconductor device in Embodiment 1 under reverse bias. Figure 4 is a cross-sectional view of the semiconductor device according to Embodiment 2. Figure 5 is a cross-sectional view of a prior art semiconductor device. Additionally, reference numeral 919 indicates the channel blocking region, reference numeral 940 indicates the back electrode, and reference numeral 950 indicates the surface protective film. Figure 6 is a diagram illustrating a prior art semiconductor device. Figure 6(a) is an enlarged cross-sectional view of the main part of the semiconductor device, and Figure 6(b) is a diagram illustrating the surface layer of the semiconductor substrate. Additionally, the symbol 932 indicates a field electrode. Implementation

[0016] The semiconductor device of the present invention will now be described based on embodiments shown in the accompanying drawings. The embodiments described below do not limit the scope of the invention as defined in the appended claims. Furthermore, not all elements and combinations thereof described in the embodiments are essential to the solutions of the present invention.

[0017] Implementation Method 1

[0018] 1. Structure of the semiconductor device 100 in Embodiment 1

[0019] As shown in FIG1, the semiconductor device 100 of Embodiment 1 is a diode, which includes: a semiconductor substrate 110; an insulating layer 120 formed on the surface of the semiconductor substrate 110 and having an opening 122 that exposes the surface of the semiconductor substrate; a surface electrode 130 formed at least in the region overlapping with the opening 122 and connected to the semiconductor substrate 110 at the opening 122; a second surface electrode 134 disposed on the insulating layer 120 at a position separate from the surface electrode 130 and electrically connected to a protective ring 118 (described later) via the opening 122 formed in the insulating layer 120; an EQR electrode (equi-potential ring electrode) 136 formed near the outermost periphery of the surface of the semiconductor substrate 110; a back electrode 140 formed on the back side of the semiconductor substrate 110; and a protective insulating film 150 having an opening in the center.

[0020] Furthermore, although the illustrations are omitted, the semiconductor device 100 according to Embodiment 1 has a generally rectangular shape when viewed from above. A device forming region A1 is formed in the central portion, and an outer peripheral region A2 is formed around the device forming region A1. In Embodiment 1, the region further inward than the inner peripheral end of the peripheral impurity region 116 (described later) is designated as the device forming region A1, and the region further outward than the inner peripheral end of the peripheral impurity region 116 is designated as the outer peripheral region A2.

[0021] The opening 122 of the insulating layer 120 is formed to expose a portion of the entire component forming region A1 and the outer peripheral region A2. The insulating layer 120 can be made of a suitable material.

[0022] The surface electrode 130 is formed to extend upwards, covering the inner peripheral end of the insulating layer 120, and the surface electrode on the insulating layer 120 constitutes the field plate electrode 132. When viewed from above, the surface electrode 130 extends to the outer side of the surrounding impurity region 116.

[0023] As shown in Figure 1(a), the semiconductor substrate 110 has: a low-resistance semiconductor layer 111, a drift layer 112, a p-type impurity region 113 (a second conductivity type impurity region), a columnar region 114, a first high-concentration region 115, a peripheral impurity region 116, a second high-concentration region 117, a protective ring 118, and a channel blocking region 119.

[0024] The low-resistance semiconductor layer 111 is an n+ type semiconductor layer formed on the back side of the semiconductor substrate 110.

[0025] A drift layer 112 is formed on the surface side of the low-resistance semiconductor layer 111, and is an n-type (first conductivity type) semiconductor layer with a lower concentration than the low-resistance semiconductor layer 111. The low-resistance semiconductor layer 111 and the drift layer 112 are formed on the entire surface of the device formation region A1 and the outer peripheral region A2. The impurity concentration of the drift layer 112 is, for example, in the range of 1.0 × 10¹³ cm⁻³ to 1.0 × 10¹⁵ cm⁻³.

[0026] The p-type impurity region 113 is a p-type semiconductor region formed on the surface portion of the drift layer 112. The p-type impurity region 113 is formed in a defined area between the device formation region A1 and the outer peripheral region A2, specifically extending to the outer side of the inner peripheral end of the insulating layer 120, and contacting the surface electrode 130. The outer peripheral end of the p-type impurity region 113 is closer to the inner peripheral side than the outer peripheral end of the peripheral impurity region 116. When viewed from above, the p-type impurity region 113 has a generally rectangular shape with arc-shaped corners, and possesses multiple corners C and multiple sides L. The impurity concentration of the p-type impurity region 113 is, for example, in the range of 5.0 × 10¹⁵ cm⁻³ to 4.4 × 10¹⁶ cm⁻³.

[0027] The columnar region 114 is a plurality of columnar regions arranged at a predetermined interval in the region where the p-type impurity region 113 is formed. The impurity concentration of the columnar region 114 is higher than that of the p-type impurity region 113, and the depth of the columnar region 114 is deeper than that of the p-type impurity region 113.

[0028] In the columnar region 114, when viewed from the defined columnar region 114, adjacent columnar regions 114 are formed at the vertices of a regular hexagon when viewed from above. That is, as shown in Figures 1(b) and 1(c), the columnar regions 114 are arranged in an alternating shape with the vertices of triangles in the region where the p-type impurity region 113 is formed, and the spacing between adjacent columnar regions 114 is equal.

[0029] In the columnar region 114, at corner C, the area per unit area where the columnar region 114 is formed is smaller than the area per unit area where the columnar region 114 is not formed (the area of ​​p-type impurity region 113). Specifically, at corner C, columnar regions 114 are not formed at the position in contact with the second high-concentration region 117, resulting in a state where the columnar regions 114 are so often removed at intervals. Therefore, at corner C, the area of ​​the p-type impurity region 113 becomes larger.

[0030] Furthermore, in the region other than the corner C of the p-type impurity region 113 (the region on the edge and the inner side), the area of ​​the region with columnar region 114 per unit area is equal to the area of ​​the region without columnar region 114 per unit area (the region of p-type impurity region 113).

[0031] The first high-concentration region 115 is the overlapping area of ​​the p-type impurity region 113 and the columnar region 114. The impurity concentration in the first high-concentration region 115 is higher than that in other regions of the p-type impurity region 113 (regions in the p-type impurity region 113 other than the first high-concentration region 115). Therefore, the impurity concentration increases in the order of p-type impurity region 113, columnar region 114, and first high-concentration region 115.

[0032] A peripheral impurity region 116 is formed at the periphery of the p-type impurity region 113 in the surface portion of the drift layer 112, having a portion overlapping with the p-type impurity region 113. The impurity concentration of the peripheral impurity region 116 is higher than that of the p-type impurity region 113. The peripheral impurity region 116 has the same depth as the columnar region 114, but is deeper than the p-type impurity region 113. The outermost periphery of the peripheral impurity region 116 is located outside the outermost periphery of the p-type impurity region 113 and inside the outermost periphery of the surface electrode 130 (field plate electrode 132). The peripheral impurity region 116 is connected to the surface electrode 130 through a second high-concentration region 117, described later.

[0033] The second high-concentration region 117 is formed in the overlapping portion of the p-type impurity region 113 and the surrounding impurity region 116. Its impurity concentration is higher than that of other regions of the p-type impurity region 113 (regions other than the second high-concentration region 117 within the p-type impurity region 113) and other regions of the surrounding impurity region 116 (regions other than the second high-concentration region 117 within the surrounding impurity region 116). The impurity concentration of the second high-concentration region 117 is in the range of 1.0 × 10¹⁶ cm⁻³ to 1.0 × 10²⁰ cm⁻³, more preferably in the range of 2.0 × 10¹⁷ cm⁻³ to 1.0 × 10²⁰ cm⁻³.

[0034] In the first embodiment, the second high-concentration region 117 is formed only in the region where the p-type impurity region 113 overlaps with the surrounding impurity region 116, but it can be formed not only in the overlapping region, but also on the inner periphery of the overlapping region.

[0035] The guard ring 118 is a p-type region formed on the outer side of the surface portion of the drift layer 112, relative to the surrounding impurity region 116. The impurity concentration in the guard ring 118 is higher than that in the p-type impurity region 113. The depth of the columnar region 114 is the same as the depth of the guard ring 118. Furthermore, the diameter of the guard ring 118 is the same as the diameter of the columnar region 114.

[0036] The channel blocking region 119 is connected to the outermost EQR electrode 136 located on the semiconductor substrate 110. The impurity concentration in the channel blocking region 119 is higher than that in the drift layer 112.

[0037] In Embodiment 1, although no recombination centers are formed within the semiconductor substrate 110, recombination centers can still be formed. Recombination centers can be formed by irradiating the semiconductor substrate 110 with electron beams (followed by annealing), or by coating the semiconductor substrate with a heavy metal (e.g., platinum or gold) and then heating it to allow diffusion.

[0038] 2. PRSM tolerance and potential distribution of the semiconductor device 100 in Embodiment 1

[0039] Next, it will be explained that the PRSM tolerance of the semiconductor device 100 of Embodiment 1 is better than that of the conventional semiconductor device 900. Here, semiconductor devices with the same structure as the semiconductor device 100 of Embodiment 1, namely the "inventive structure" and the "conventional structure", were actually manufactured, and their PRSM tolerance was evaluated.

[0040] Figure 2 is a graph showing the probability distribution of PRSM tolerance levels for "inventive structures" and "conventional structures". The horizontal axis of Figure 2 represents PRSM tolerance level, and the "percentage" on the vertical axis represents the cumulative probability of PRSM tolerance levels for "conventional structures" and "inventive structures".

[0041] First, semiconductor devices with the "inventive structure" and the "conventional structure" are fabricated. The semiconductor device with the "inventive structure" is a semiconductor device having the same structure as the semiconductor device 100 of Embodiment 1, except that the area ratio of the p-type impurity region 113 at the corner C of the p-type impurity region 113 to the columnar region 114 is 1:1. Although the figures are omitted, the semiconductor device with the "conventional structure" is a semiconductor device having the same structure as the semiconductor device 100 of Embodiment 1, except that it does not have the columnar region 114.

[0042] As described above, the PRSM tolerance of semiconductor devices with the "inventive structure" and the "conventional structure" was measured, and the cumulative probability of the measured PRSM tolerance was plotted.

[0043] As shown in Figure 2, in the "inventive structure," the cumulative probability is plotted as a value with high PRSM tolerance (peak reverse power tolerance). In contrast, in the "conventional structure," the cumulative probability is plotted as a low PRSM tolerance value. Therefore, it can be confirmed that the PRSM tolerance of the semiconductor device 100 according to Embodiment 1 is better than that of the semiconductor device of the conventional structure.

[0044] Next, the potential distribution of the semiconductor device 100 in Embodiment 1 will be described. FIG3 is a diagram of the electric field distribution of the semiconductor device 100 in this embodiment when reverse biased. In addition, the solid line in FIG3 represents the depletion layer.

[0045] As shown in Figure 3, in the semiconductor device 100 of Embodiment 1, under reverse bias, the region with high potential is not in the outer peripheral region A2, but rather in a relatively wide region of the device formation region A1 where the potential becomes higher. Therefore, it can be confirmed that the electric field is dispersed in the device formation region A1, and breakdown occurs in the device formation region A1. Thus, it can be confirmed that the area of ​​the breakdown region becomes larger, and the breakdown current becomes easier to flow, thereby increasing the PRSM withstand capability.

[0046] Furthermore, in the case of conventional semiconductor devices, it is believed that when reverse biased, the electric field is concentrated near the bottom of the outermost periphery of the surface portion of the drift layer 912. Specifically, in the area near the bottom of the outermost periphery of the peripheral region of the conventional semiconductor device 900 (see the BD region in Figure 5), breakdown occurs in this region, the breakdown current is difficult to flow, and the PRSM withstand value is difficult to reach the specified value.

[0047] 3. Effects of the semiconductor device 100 in Embodiment 1

[0048] According to the semiconductor device 100 of Embodiment 1, since the semiconductor substrate 110 has a p-type impurity region 113 formed on the surface portion of the drift layer 112 and in contact with the surface electrode 130; and columnar regions 114 arranged at predetermined intervals in the region where the p-type impurity region 113 is formed, with a higher impurity concentration and deeper than the p-type impurity region 113 when viewed from above, the area where the applied electric field is applied can extend from near the bottom of the outermost periphery of the drift layer 112 to the entire region where the p-type impurity region 113 is formed (element formation region A1) under reverse bias. That is, breakdown can be intentionally performed in the larger element formation region A1 before breakdown near the bottom of the outermost periphery of the p-type impurity region 113. Therefore, compared with conventional semiconductor devices and prior art semiconductor devices, the area of ​​the breakdown region is larger, the breakdown current flows more easily, and thus the PRSM withstand capability can be improved.

[0049] Furthermore, according to the semiconductor device 100 of Embodiment 1, since adjacent columnar regions 114 are formed at the vertices of regular hexagons when viewed from above, the area where the applied electric field is applied can be evenly extended to the entire region (element formation region A1) where the p-type impurity region 113 is formed. As a result, reverse current flows evenly in the entire region (element formation region A1) where the p-type impurity region 113 is formed, thus further increasing the PRSM tolerance.

[0050] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the surface electrode 130 extends further outward than the p-type impurity region 113 when viewed from above, and in the corner C, the area per unit area where the columnar region 114 is formed is larger than the area per unit area where the columnar region 114 is not formed, it is easier to induce electric field concentration in the device formation region A1 compared to the outer peripheral region A2. As a result, breakdown is more likely to be induced in the device formation region A1.

[0051] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the area of ​​the region with columnar regions 114 formed per unit area is equal to the area of ​​the region without columnar regions 114 (the region of p-type impurity region 113) per unit area in the region other than the corner C of the p-type impurity region 113, the area where the electric field is applied can be evenly extended to the entire region (element formation region A1) where the p-type impurity region 113 is formed. Therefore, local concentration of electric field at a specific location in the element formation region A1 can be prevented, and breakdown at a specific location can be prevented.

[0052] In the case where the region containing the p-type impurity region 113 has a plurality of columnar regions 114 arranged at predetermined intervals, holes that are recovered and moved to the surface electrode 130 via the columnar regions 114 during reverse recovery will pass through the region where the p-type impurity region 113 overlaps with the columnar regions 114. Therefore, the current density in this region may increase. However, according to the semiconductor device 100 of Embodiment 1, since a first high-concentration region 115 with a higher impurity concentration than other regions of the p-type impurity region 113 is formed in the region where the p-type impurity region 113 overlaps with the columnar regions 114, holes can easily flow, and the current density in this region can be reduced. As a result, a sharp increase in the recovery current in this region can be prevented, and good recovery characteristics can be achieved. Furthermore, since the current density in this region can be reduced, temperature rise can also be suppressed.

[0053] Furthermore, according to the semiconductor device 100 of Embodiment 1, since it has a p-type peripheral impurity region 116 formed on the periphery of the p-type impurity region 113 on the surface of the drift layer 112, and has a portion overlapping the p-type impurity region 113 with a higher impurity concentration than the p-type impurity region, the impurity concentration gradient at the outer peripheral end of the p-type impurity region 113 can be reduced, thus suppressing breakdown at the outer peripheral end of the p-type impurity region 113. As a result, the PRSM tolerance in the outer peripheral region A2 can be good.

[0054] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the depth of the columnar region 114 is the same as the depth of the peripheral impurity region 116, during reverse bias, it is possible to prevent the electric field from concentrating near the bottom of the outermost periphery of the peripheral impurity region 116. This allows the area of ​​electric field concentration to extend from near the bottom of the outermost periphery of the surface portion of the drift layer 112 to the entire region where the p-type impurity region 113 is formed (element formation region A1). As a result, while maintaining good PRSM tolerance in the peripheral region A2, the overall PRSM tolerance of the semiconductor device is even higher.

[0055] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the surface portion of the drift layer 112 includes a p-type guard ring 118 with a higher impurity concentration than the p-type impurity region 113 located further outward than the peripheral impurity region 116, the depletion layer can extend towards the outer peripheral region A2 before the electric field in the outermost peripheral region of the device formation region A1, where electric field concentration is prone to occur, exceeds the critical electric field. Therefore, the withstand voltage of the outer peripheral region A2 can be improved.

[0056] Furthermore, in the semiconductor device 100 according to Embodiment 1, since the depth of the columnar region 114 is the same as the depth of the guard ring 118, it is possible to prevent the electric field from concentrating near the bottom of the outermost periphery of the guard ring 118 during reverse bias. This allows the area of ​​electric field concentration to extend from near the bottom of the outermost periphery of the surface portion of the drift layer 112 to the region where the p-type impurity region 113 is formed (element formation region A1). As a result, while maintaining good PRSM tolerance in the outer peripheral region A2, the overall PRSM tolerance of the semiconductor device is even higher.

[0057] Furthermore, since the columnar region 114, the peripheral impurity region 116, and the protective ring 118 have the same depth, the depletion layer can be extended in the outer peripheral region A2 before the electric field in the outermost peripheral region of the component formation region A1, which is prone to electric field concentration, exceeds the critical electric field, thereby preventing local electric field concentration.

[0058] Furthermore, in the semiconductor device 100 according to Embodiment 1, the diameter of the columnar region 114 is the same as the diameter of the protective ring 118, so the columnar region 114 and the protective ring 118 can be formed together.

[0059] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the portion where the p-type impurity region 113 overlaps with the peripheral impurity region 116 has a second high-concentration region 117 with a higher impurity concentration than other regions of the p-type impurity region 113, it is possible to prevent holes in the peripheral region A2 from flowing to the surface of the device formation region A1 due to the impurity concentration difference between the p-type impurity region 113 and the peripheral impurity region 116. Therefore, it is possible to prevent an increase in the current density on the surface of the device formation region A1, thus making it a semiconductor device with further improved resistance to damage.

[0060] Furthermore, according to the semiconductor device 100 of Embodiment 1, since the surface electrode 130 (field plate electrode 132) extends further outward than the peripheral impurity region 116 when viewed from above, it is possible to prevent the electric field from concentrating on the pn junction between the peripheral impurity region 116 and the drift layer 112 of the semiconductor substrate (especially near the surface of the semiconductor substrate 110), thereby improving the withstand voltage.

[0061] In addition, in embodiment 1, the outermost protective ring 118 is also connected to the second surface electrode 134, which also extends toward the outer periphery, and can achieve the same effect as the field plate electrode 132 described above.

[0062] Implementation Method 2

[0063] The semiconductor device 101 of Embodiment 2 has essentially the same structure as the semiconductor device 100 of Embodiment 1, but the position of the inner peripheral end of the peripheral impurity region in the surface of the semiconductor substrate differs from that of the semiconductor device 100 of Embodiment 1. Specifically, in the semiconductor device 101 of Embodiment 2, as shown in FIG4, the inner peripheral end of the peripheral impurity region 116 in the surface of the semiconductor substrate 110 is located on the inner peripheral side of the end of the opening 122. Therefore, the peripheral impurity region 116 is in contact with the surface electrode 130.

[0064] The inner peripheral end of the peripheral impurity region 116 in the surface of the semiconductor substrate 110 is located on the inner peripheral side of the end A of the opening 122, and the length L1 from the inner peripheral end of the peripheral impurity region 116 to the end A of the opening 122 is not less than 0.01 μm and less than 30 μm.

[0065] In the semiconductor device 101 of Embodiment 2, although the position of the inner peripheral end of the peripheral impurity region on the surface of the semiconductor substrate differs from that of the semiconductor device 100 of Embodiment 1, it is similar to the semiconductor device 100 of Embodiment 1. The semiconductor substrate 110 has a p-type impurity region 113 formed on the surface portion of the drift layer 112 and in contact with the surface electrode 130; and a plurality of columnar regions 114 arranged at predetermined intervals in the region where the p-type impurity region 113 is formed, having a higher impurity concentration and greater depth than the p-type impurity region 113. Therefore, under reverse bias, the area where the applied electric field is applied can extend from near the bottom of the outermost periphery of the surface portion of the drift layer 112 to the entire region where the p-type impurity region 113 is formed (element formation region A1). That is, breakdown can be intentionally performed in the larger element formation region A1 before breakdown near the bottom of the outermost periphery of the p-type impurity region 113. Therefore, compared with conventional semiconductor devices and prior art semiconductor devices, the breakdown area is larger and the breakdown current flows more easily, thus improving the PRSM tolerance.

[0066] Furthermore, according to the semiconductor device 101 of Embodiment 2, since the inner peripheral end of the peripheral impurity region 116 on the surface of the semiconductor substrate 110 is located on the inner peripheral side of the end A of the opening 122, and the length L1 from the inner peripheral end of the peripheral impurity region 116 to the end A of the opening 122 is not less than 0.01 μm and less than 30 μm, when the switch is turned on and off, holes and the like generated in the semiconductor substrate 110, including the outer peripheral region A2, are recovered by the recombination center, which can reduce the amount of current reaching the surface electrode 130 (reducing the number of holes reaching the surface electrode 130). Therefore, the current flowing into the surface electrode 130 via the p-type impurity region 113 and the current flowing into the surface electrode 130 via the peripheral impurity region 116 can be reduced, thereby reducing the current density near the confluence and suppressing temperature rise. As a result, the damage resistance can be improved. In addition, since the current density in the element formation region A1 can be reduced, the length L1 from the inner peripheral end of the peripheral impurity region 116 to the end of the opening 122 can be reduced. Therefore, it can prevent the recovery current from increasing sharply, thus enabling good recovery characteristics and suppressing the increase of recovery loss.

[0067] Furthermore, since the semiconductor device 101 of Embodiment 2 has the same structure as the semiconductor device 100 of Embodiment 1 at a point other than the inner peripheral end of the peripheral impurity region on the surface of the semiconductor substrate, it has the same effect as the semiconductor device 100 of Embodiment 1.

[0068] The present invention has been described above based on the embodiments described above, but the present invention is not limited to the embodiments described above. It can be implemented in various ways without departing from the concept, for example, the following modifications can be made.

[0069] (1) The positions, connections, numbers, etc. described in the above embodiments (including various modifications, etc.) are only examples and can be changed within the scope of not impairing the effect of the present invention.

[0070] (2) In the above embodiments, a diode is used as a semiconductor device, but the present invention is not limited thereto. The semiconductor device can be used as a MOSFET or an IGBT, or other suitable semiconductor devices.

[0071] (3) In the above embodiments, the first high-concentration region 115 is formed only in the overlapping area of ​​the p-type impurity region 113 and the surrounding impurity region 116, but the present invention is not limited thereto. The high-concentration region may also be formed in the region of the second conductivity type impurity region other than the overlapping area. However, it is not preferred from the perspective of recovery characteristics to set all the second conductivity type impurity regions as high-concentration regions, and it is preferable to have regions other than the high-concentration regions.

[0072] (4) In the above embodiments, a peripheral impurity region 116, a second high-concentration region 117, and a protective ring 118 are formed in the outer peripheral region A2, but the present invention is not limited thereto. The present invention is valid even if any or all of these constituent elements are not present.

[0073] 100, 101: Semiconductor devices 110: Semiconductor substrate 111: Low-resistance semiconductor layer 112: Drift Layer 113: p-type impurity region (second conductivity type impurity region) 114: Columnar region 115: First high concentration area 116: Surrounding impurity area 117: Second highest concentration area 118: Protective Ring 120: Insulation layer 122: Opening 130: Surface electrode 132: Field plate electrode 134: Second surface electrode 136: EQR electrode 150: Protective insulating film 900, 901: Semiconductor devices 911: n+ type low-resistance semiconductor layer 912: Drift Layer 913: p-type impurity region 916: Surrounding impurity area 918: Protective Ring 919: Ditch Blocking Area 920: Insulation layer 922: Opening 930: Surface Electrode 932: Field plate electrode 940: Back electrode 950: Surface protective film A1: Area A2: Peripheral area

Claims

1. A semiconductor device, comprising: Semiconductor substrate; An insulating layer is formed on the surface of the semiconductor substrate and has an opening that exposes the surface of the semiconductor substrate; The semiconductor substrate includes: a surface electrode, formed at least in a region overlapping with the opening and connected to the semiconductor substrate at the opening; a drift layer of a first conductivity type; an impurity region of a second conductivity type formed on the surface portion of the drift layer and in contact with the surface electrode; columnar regions of a second conductivity type, arranged at predetermined intervals in the region where the impurity regions of the second conductivity type are formed when viewed from above, having a higher impurity concentration and a deeper depth than the impurity regions of the second conductivity type; and peripheral impurity regions of a second conductivity type formed at the periphery of the impurity regions of the second conductivity type in the surface portion of the drift layer, having a portion overlapping with the impurity regions of the second conductivity type, and having a higher impurity concentration than the impurity concentration of the impurity regions of the second conductivity type. The columnar region adjacent to a certain columnar region is formed at the vertex of a regular hexagon when viewed from above, and the depth of the surrounding impurity region is the same as the depth of the columnar region.

2. The semiconductor device according to claim 1, wherein: When viewed from above, the surface electrode extends to a position further outward than the impurity region of the second conductivity type. When viewed from above, the impurity region of the second conductivity type has multiple corners and multiple edges. At the corners, the area of ​​the region where the columnar region is formed is smaller than the area of ​​the region where the columnar region is not formed.

3. The semiconductor device according to claim 2, wherein: In the region outside the corner of the impurity region of the second conductivity type, the area of ​​the region where the columnar region is formed is equal to the area of ​​the region where the columnar region is not formed.

4. The semiconductor device according to claim 1, wherein: A first high-concentration region is formed in the area where the impurity region of the second conductivity type overlaps with the columnar region, where the impurity concentration is higher than that of other regions of the impurity region of the second conductivity type.

5. The semiconductor device according to claim 1, wherein: The semiconductor substrate has a second conductivity type protective ring located on the outer side of the surface portion of the drift layer, which has a higher impurity concentration than the impurity concentration of the second conductivity type impurity region. The depth of the columnar region is the same as the depth of the protective ring.

6. The semiconductor device according to claim 5, wherein: The diameter of the protective ring is the same as the diameter of the columnar region.

7. The semiconductor device according to claim 1, wherein: The portion of the impurity region of the second conductivity type that overlaps with the surrounding impurity region has a second high concentration region where the impurity concentration is higher than that of other regions of the impurity region of the second conductivity type.

8. The semiconductor device according to claim 1, wherein: When viewed from above, the surface electrode extends to a position further outward than the surrounding impurity region.

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