Electronic device

Abstract

This disclosure provides an electronic device. The electronic device includes a first scanning transistor, a driving transistor, electronic components, and a first capacitive coupling element. The driving transistor is electrically connected to the first scanning transistor. The electronic components are electrically connected to the driving transistor. A first terminal of the first capacitive coupling element is electrically connected to a control terminal of the driving transistor.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more particularly to an electronic apparatus. Prior Technology

[0002] Generally, voltage source circuits are controlled by the data voltage transmitted through a scanning transistor. However, the scanning transistor can exhibit a clock feed-through effect, which can cause data voltage shifts and reduce control accuracy. Existing technologies address this by increasing the size of the storage capacitor to maintain the data voltage and reduce the impact of clock feed-through. However, this approach makes manufacturing and layout difficult; if the scan timing is tight, a larger scanning transistor is needed to charge the storage capacitor. Furthermore, increasing the size of the scanning transistor amplifies the clock feed-through effect, requiring an even larger storage capacitor to mitigate it. Summary of the Invention

[0003] The electronic device disclosed herein includes a first scanning transistor, a driving transistor, electronic components, and a first capacitive coupling element. The driving transistor is electrically connected to the first scanning transistor. The electronic components are electrically connected to the driving transistor. A first terminal of the first capacitive coupling element is electrically connected to a control terminal of the driving transistor.

[0004] Based on the above, according to the electronic device of this disclosure, the electronic device can effectively drive electronic components by reducing or eliminating clock feedthrough effects.

[0005] To make the foregoing easier to understand, several embodiments of the accompanying drawings are described in detail below. Simple Explanation of the Diagram

[0006] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 2A is a timing diagram of the relevant voltages and signals according to the embodiment of Figure 1 of this disclosure. Figure 2B is another timing diagram of the relevant voltages and signals according to the embodiment of Figure 1 of this disclosure. Figure 3A is a schematic diagram of a capacitive coupling element according to an embodiment of the present disclosure. Figure 3B is a schematic diagram of a capacitive coupling element according to another embodiment of the present disclosure. Figure 4 is a schematic diagram of an electronic device with threshold voltage compensation according to an embodiment of the present disclosure. Figure 5 is a schematic diagram of an electronic device without threshold voltage compensation according to an embodiment of the present disclosure. Figure 6 is a timing diagram of the relevant voltages and signals according to the embodiment of Figure 4 of this disclosure. Figure 7 is a schematic diagram of an electronic device with threshold voltage compensation according to an embodiment of the present disclosure. Figure 8 is a schematic diagram of an electronic device without threshold voltage compensation according to an embodiment of the present disclosure. Figure 9 is a timing diagram of the relevant voltages and signals according to the embodiment of Figure 7 of this disclosure. Implementation

[0007] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or similar elements.

[0008] Certain terms are used throughout this disclosure and in the appended claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising” and “including” are open-ended terms and should be interpreted as “including but not limited to…”.

[0009] The term "coupled (or electrically connected)" as used throughout the specification of this application (including the appended claims) may refer to any direct or indirect connection. For example, if the text describes a first device coupled (or electrically connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device via other devices or certain connecting members. The terms "first," "second," and similar terms used throughout the specification of this application (including the appended claims) are used only to name discrete elements or to distinguish them in different embodiments or scopes. Therefore, the terms should not be considered as upper or lower limits on the number of elements or to limit the order of arrangement of elements. Furthermore, where possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. The use of the same reference numerals or the same terms in different embodiments may refer to the related descriptions of elements / components / steps.

[0010] The electronic device disclosed herein may include, for example, an active matrix device comprising multiple data lines, multiple scan lines, and a pixel array. An electronic component may correspond to a pixel unit of the pixel array. The electronic component of this disclosure may be a voltage-controlled device, and may include, for example, a varactor, a tunable component, a liquid crystal cell, or a voltage-controlled device (or voltage-controlled circuit) that can be used to control a light-emitting diode (LED) having current. It should be noted that the electronic device of this disclosure can be manufactured using display panel processes, and the related transistors and electronic components are fabricated on a glass substrate.

[0011] It should be noted that in the following embodiments, technical features of several different embodiments may be replaced, rearranged, and combined to complete other embodiments without departing from the spirit of this disclosure. Features of each embodiment may be arbitrarily combined and used together, provided that they do not violate the spirit of this disclosure or conflict with each other.

[0012] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Referring to Figure 1, the electronic device 100 includes an electronic component 110, a capacitive coupling element 120, a scanning transistor Ts, and a data line DL. The electronic component 110 is electrically connected to the scanning transistor Ts and the capacitive coupling element 120 via node N1. A first terminal of the scanning transistor Ts is electrically connected to the data line DL. A second terminal of the scanning transistor Ts is electrically connected to the electronic component 110 and the capacitive coupling element 120 via node N1. The capacitive coupling element 120 may be further electrically connected to a compensation signal CS. A control terminal of the scanning transistor Ts is electrically connected to a scan signal SS. In embodiments of the present disclosure, the scanning transistor Ts may be an N-type transistor or a P-type transistor. Additionally, in some embodiments of the present disclosure, the electronic device 100 may further include a storage capacitor, and the storage capacitor is electrically connected to node N1.

[0013] In embodiments of this disclosure, the scanning transistor Ts transmits a data voltage to node N1 according to the data signal DS transmitted via the data line DL, in order to drive electronic component 110. During the switching of the scanning transistor Ts from on to off, a coupling capacitance Cgd may form between the control terminal and the second terminal of the scanning transistor Ts, which can cause a clock feed-through effect at node N1. In embodiments of this disclosure, the capacitive coupling element 120 can compensate for the clock feed-through effect according to the compensation signal CS.

[0014] Figure 2A is a timing diagram of the relevant voltages and signals according to the embodiment of Figure 1 of this disclosure. Referring to Figures 1 and 2A, in the embodiment of this disclosure, it is assumed that the scanning transistor Ts is an N-type transistor. The voltage of the compensation signal CS provided by the capacitive coupling element 120 can change to a low voltage level at time t0 and to a high voltage level at time t6. During the period from time t1 to time t5, the data signal DS can have a data voltage, and the control terminal of the scanning transistor Ts receives the scanning signal SS. From time t1 to time t2, the voltage of the scanning signal SS rises from a low voltage level to a high voltage level. Therefore, the node voltage Vd of node N1 changes to the data voltage during the period from time t1 to time t3. From time t4 to time t5, the scanning signal SS drops from a high voltage level to a low voltage level, and the node voltage Vd of node N1 decreases due to the clock feedthrough effect caused by the coupling capacitor Cgd.

[0015] In embodiments of this disclosure, between time t6 and time t7, the compensation signal CS provided by the capacitive coupling element 120 rises from a low voltage level to a high voltage level. Therefore, the node voltage Vd of node N1 can be compensated by the voltage rise of the compensation signal CS, thereby effectively maintaining the node voltage Vd of node N1 at the data voltage after the scanning transistor Ts is turned off.

[0016] Figure 2B is another timing diagram of the relevant voltages and signals according to the embodiment of Figure 1 of this disclosure. Referring to Figures 1 and 2B, in the embodiment of this disclosure, it is assumed that the scanning transistor Ts is a P-type transistor. The voltage of the compensation signal CS provided by the capacitive coupling element 120 can change to a high voltage level at time t0 and to a low voltage level at time t6. During the period from time t1 to time t5, the data signal DS can have a data voltage, and the control terminal of the scanning transistor Ts receives the scanning signal SS. From time t1 to time t2, the voltage of the scanning signal SS drops from a high voltage level to a low voltage level. Therefore, the node voltage Vd of node N1 changes to a data voltage during the period from time t1 to time t3. From time t4 to time t5, the scanning signal SS rises from a low voltage level to a high voltage level, and the node voltage Vd of node N1 rises due to the clock feedthrough effect caused by the coupling capacitor Cgd.

[0017] In embodiments of this disclosure, between time t6 and time t7, the compensation signal CS provided by the capacitive coupling element 120 drops from a high voltage level to a low voltage level. Therefore, the node voltage Vd of node N1 can be compensated by the voltage drop of the compensation signal CS, thereby effectively maintaining the node voltage Vd of node N1 at the data voltage after the scanning transistor is turned off.

[0018] Figure 3A is a schematic diagram of a capacitive coupling element according to an embodiment of the present disclosure. Referring to Figures 1 and 3A, the capacitive coupling element 120 of the embodiment of Figure 1 may include a capacitor C1 as shown in Figure 3A, and the capacitor C1 may be a metal-insulator-metal (MIM) capacitor. A first terminal of the capacitor C1 is electrically connected to a compensation signal CS through node P11. A second terminal of the capacitor C1 is electrically connected to node N1 through node P12. Therefore, the capacitor C1 can compensate the voltage of node N1 according to the compensation signal CS.

[0019] Figure 3B is a schematic diagram of a capacitive coupling element according to another embodiment of the present disclosure. Referring to Figures 1 and 3B, the capacitive coupling element 120 of the embodiment of Figure 1 may include a transistor T1 as shown in Figure 3B. The control terminal of the transistor T1 is electrically connected to a compensation signal CS via node P21. The second terminal of the transistor T1 is electrically connected to the first terminal of the transistor T1 and node N1 via node P22. Therefore, the transistor T1 can compensate the voltage of node N1 according to the compensation signal CS.

[0020] Figure 4 is a schematic diagram of an electronic device with threshold voltage compensation according to an embodiment of the present disclosure. Referring to Figure 4, the electronic device 400 includes an electronic component 410, a voltage source circuit 430, a scanning transistor Ts, a first capacitive coupling element, a second capacitive coupling element, and a data line DL. The electronic component 410 may include a varactor diode or other tunable components. The first capacitive coupling element is a capacitor C1 similar to the MIM capacitor shown in the embodiment of Figure 3A, and the second capacitive coupling element is a capacitor C2 also similar to the MIM capacitor shown in the embodiment of Figure 3A, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first capacitive coupling element and the second capacitive coupling element may also be implemented as the transistor T1 of the embodiment of Figure 3B, respectively.

[0021] In embodiments of this disclosure, electronic component 410 is electrically connected to a scanning transistor Ts and capacitor C2 via node N1. A first terminal of the scanning transistor Ts is electrically connected to data line DL. A second terminal of the scanning transistor Ts is electrically connected to electronic component 410 and capacitor C2 via node N1. The control terminal of the scanning transistor Ts is electrically connected to the scan signal SS. Voltage source circuit 430 is electrically connected to capacitor C1. A first terminal of capacitor C2 is electrically connected to a second terminal of the scanning transistor Ts and electronic component 410. A first terminal of capacitor C1 is electrically connected to voltage source circuit 430. A second terminal of capacitor C2 is electrically connected to a second terminal of capacitor C1 and is also electrically connected to bias signal BS. Electronic component 410 is coupled between node N1 and a second operating voltage V2.

[0022] In embodiments of this disclosure, the voltage source circuit 430 includes a driving transistor Td, a compensation transistor Tc, a bias transistor Tb, a reset transistor Tr, and a storage capacitor Cst. The first terminal of the driving transistor Td is electrically connected to the scanning transistor Ts, capacitor C2, and electronic component 410 via node N1. The second terminal of the driving transistor Td is electrically connected to the compensation transistor Tc and the bias transistor Tb. The control terminal of the driving transistor Td is electrically connected to the compensation transistor Tc, the reset transistor Tr, the storage capacitor Cst, and capacitor C1. The first terminal of the bias transistor Tb is electrically connected to a first operating voltage V1. The second terminal of the bias transistor Tb is electrically connected to the first terminal of the driving transistor Td and the first terminal of the compensation transistor Tc. The control terminal of the bias transistor Tb is electrically connected to a bias signal BS. The first terminal of the storage capacitor Cst is electrically connected to the first operating voltage V1. The second terminal of the storage capacitor Cst is electrically connected to the second terminal of the compensation transistor Tc, the control terminal of the driving transistor Td, and the first terminal of capacitor C1. The first terminal of the reset transistor Tr is electrically connected to the first operating voltage V1. The second terminal of the reset transistor Tr is electrically connected to the control terminal of the driving transistor Td and the first terminal of the capacitor C1. The control terminal of the reset transistor Tr is electrically connected to the reset signal RS. In embodiments of this disclosure, the first and second terminals of each of the above transistors can be source and drain terminals, and the control terminal of each of the above transistors can be a gate terminal. In embodiments of this disclosure, the compensation transistor Tc, the bias transistor Tb, and the reset transistor Tr can each be an N-type transistor, and the scanning transistor Ts and the driving transistor Td can each be an N-type transistor or a P-type transistor.

[0023] In embodiments of this disclosure, the scanning transistor Ts transmits the data voltage Vdata to node N1 according to the data signal DS transmitted via the data line DL, and the voltage source circuit 430 can generate a compensation current Id through node N1 based on the data voltage Vdata to compensate for the leakage current Iv of electronic component 410. In embodiments of this disclosure, during the scanning cycle, the compensation transistor Tc can compensate for the threshold voltage of the driving transistor Td at the control terminal (gate terminal) of the driving transistor Td. Furthermore, during the bias cycle, when the driving transistor Td is turned on, the node voltage of node N1 can be maintained at the voltage of the data voltage Vdata minus the incremental voltage dV to provide the compensation current Id. When the electronic device 400 is in a current balance state, the incremental voltage dV caused by the compensation current Id compensates for the leakage current Iv flowing through electronic component 410. In embodiments of this disclosure, during the switching from on to off of the scanning transistor Ts and the compensation transistor Tc, the scanning transistor Ts and the compensation transistor Tc can respectively cause clock feedthrough effects at the control terminals of node N1 and the control terminals of the driving transistor Td through the coupling capacitance between the control terminal of the scanning transistor Ts and the second terminal of the scanning transistor Ts, and the coupling capacitance between the control terminal of the compensation transistor Tc and the second terminal of the compensation transistor Tc. In embodiments of this disclosure, capacitors C1 and C2 can respectively compensate for the clock feedthrough effect according to the bias signal BS. Additionally, in some embodiments of this disclosure, capacitor C2 is selectively provided.

[0024] Figure 5 is a schematic diagram of an electronic device without threshold voltage compensation according to an embodiment of the present disclosure. Referring to Figure 5, the electronic device 500 includes an electronic component 510, a voltage source circuit 530, scanning transistors Ts1 and Ts2, a first capacitive coupling element, a second capacitive coupling element, and a data line DL. The electronic component 510 may include a varactor diode or other tunable element. The first capacitive coupling element is a capacitor C1 similar to the MIM capacitor shown in the embodiment of Figure 3A, and the second capacitive coupling element is a capacitor C2 also similar to the MIM capacitor shown in the embodiment of Figure 3A, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, the first capacitive coupling element and the second capacitive coupling element may also be implemented as the transistor T1 of the embodiment of Figure 3B, respectively.

[0025] In embodiments of this disclosure, electronic component 510 is electrically connected to scanning transistor Ts2 and capacitor C2 via node N1. A first terminal of scanning transistor Ts1 is electrically connected to data line DL. A second terminal of scanning transistor Ts1 is electrically connected to voltage source circuit 530 and capacitor C1. The control terminal of scanning transistor Ts1 is electrically connected to scan signal SS. Voltage source circuit 530 is electrically connected to capacitor C2 and scanning transistor Ts2 via node N1. A first terminal of scanning transistor Ts2 is electrically connected to data line DL. A second terminal of scanning transistor Ts2 is electrically connected to voltage source circuit 530 and capacitor C2. The control terminal of scanning transistor Ts2 is electrically connected to scan signal SS. A first terminal of capacitor C1 is electrically connected to the second terminal of scanning transistor Ts1 and voltage source circuit 530. A first terminal of capacitor C2 is electrically connected to voltage source circuit 530 and the second terminal of scanning transistor Ts2 via node N1. The second terminal of capacitor C1 is electrically connected to the second terminal of capacitor C2 and is also electrically connected to compensation signal CS. Electronic component 510 is coupled between node N1 and the second operating voltage V2.

[0026] In embodiments of this disclosure, the voltage source circuit 530 includes a driving transistor Td and a storage capacitor Cst. A first terminal of the driving transistor Td is electrically connected to a first operating voltage V1. A second terminal of the driving transistor Td is electrically connected to electronic component 510 and capacitor C2 via node N1. A control terminal of the driving transistor Td is electrically connected to a second terminal of a scanning transistor Ts1 and capacitor C1. A first terminal of the storage capacitor Cst is electrically connected to the first operating voltage V1. A second terminal of the storage capacitor Cst is electrically connected to the control terminal of the driving transistor Td. In embodiments of this disclosure, the first and second terminals of the driving transistor Td can be a source terminal and a drain terminal, and the control terminal of the driving transistor Td can be a gate terminal. In embodiments of this disclosure, the scanning transistors Ts1, Ts2, and Td can be either an N-type transistor or a P-type transistor, respectively.

[0027] In embodiments of this disclosure, scanning transistor Ts1 transmits the data voltage Vdata to the control terminal of driving transistor Td according to the data signal DS transmitted by data line DL, and scanning transistor Ts2 also transmits the data voltage Vdata to node N1 according to the data signal DS transmitted by data line DL. Voltage source circuit 530 can generate a compensation current Id through node N1 according to the data voltage Vdata to compensate for the leakage current Iv of electronic component 510. In embodiments of this disclosure, during the simultaneous switching from on to off of scanning transistors Ts1 and Ts2, scanning transistors Ts1 and Ts2 can respectively cause a clock feedthrough effect at the control terminal of driving transistor Td and node N1 through the coupling capacitance between the control terminal of scanning transistor Ts1 and the second terminal of scanning transistor Ts1 and the coupling capacitance between the control terminal of scanning transistor Ts2 and the second terminal of scanning transistor Ts2. In embodiments of this disclosure, capacitors C1 and C2 can respectively compensate for the clock feedthrough effect according to the compensation signal CS. In addition, in some embodiments of this disclosure, capacitor C1 is selectively provided.

[0028] Figure 6 is a timing diagram of the relevant voltages and signals according to the embodiment of Figure 4 of this disclosure. Referring to Figures 4 and 6, the electronic device 400 can be operated at the bias period BP, reset period RP, and scan period SP. During the period from time t0 to time t1, the bias signal BS changes to a low voltage level, and the reset signal RS and scan signal SS remain at low voltage levels, respectively. The voltages Vd, Vg, and Vs at the first terminal, second terminal, and control terminal of the driving transistor Td decrease simultaneously. During the period from time t2 to time t3, the reset signal RS rises to a high voltage level, and therefore the voltage Vg at the control terminal of the driving transistor Td rises to the first operating voltage V1. During the reset period RP from time t3 to time t4, the voltage Vg at the control terminal of the driving transistor Td remains at the first operating voltage V1. During the period from time t4 to time t5, the reset signal RS falls to a low voltage level, and therefore the voltage Vg at the control terminal of the driving transistor Td decreases simultaneously.

[0029] During the period from time t6 to time t7, the scan signal SS changes to a high voltage level, while the reset signal RS and bias signal BS remain at low voltage levels. The voltages Vd, Vg, and Vs at the first, second, and control terminals of the driving transistor Td rise simultaneously. During the period from time t8 to time t9, the voltage Vs at the second terminal of the driving transistor Td changes to the data voltage Vdata. The voltages Vd and Vg at the first and control terminals of the driving transistor Td change to the absolute value of the data voltage Vdata plus the threshold voltage Vth of the driving transistor Td.

[0030] During the period from time t9 to time t10, the scan signal SS drops to a low voltage level, therefore the voltages Vd, Vg, and Vs at the first, second, and control terminals of the driving transistor Td decrease simultaneously due to the clock feedthrough effect. During the period from time t11 to time t12, the bias signal BS rises to a high voltage level. Simultaneously, capacitors C1 and C2 compensate for the clock feedthrough effect according to the bias signal BS. Therefore, the voltage Vg at the control terminal of the driving transistor Td rises to the absolute value of the data voltage Vdata plus the threshold voltage Vth of the driving transistor Td, and the voltage Vs at the second terminal of the driving transistor recovers.

[0031] Therefore, during the period from time t12 to time t13, the voltage Vg at the control terminal of the driving transistor Td rises to the absolute value of the data voltage Vdata plus the threshold voltage Vth of the driving transistor Td. Furthermore, when the driving transistor Td is turned on, the voltage Vs at the control terminal of the driving transistor Td and the node voltage of node N1 can recover to the data voltage Vdata minus the incremental voltage dV, which is used to provide the compensation current Id. When the electronic device 400 is in a current balance state, the incremental voltage dV caused by the compensation current Id compensates for the leakage current Iv passing through the voltage source circuit 430. Additionally, the relevant voltages and signals in the above embodiment of FIG5 can also be simulated using this embodiment to achieve clock feedthrough effect compensation.

[0032] Figure 7 is a schematic diagram of an electronic device with threshold voltage compensation according to an embodiment of the present disclosure. Referring to Figure 7, the electronic device 700 includes an electronic component 710, a current sink circuit 730, a scanning transistor Ts, a capacitive coupling element, and a data line DL. The electronic component 710 may include a light-emitting diode. The capacitive coupling element is a capacitor C1 similar to the MIM capacitor shown in the embodiment of Figure 3A, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, the capacitive coupling element may also be implemented as the transistor T1 of the embodiment of Figure 3B.

[0033] In embodiments of this disclosure, electronic component 710 is electrically connected between a first operating voltage V1 and a current sink circuit 730. A first terminal of the scanning transistor Ts is electrically connected to the data line DL. A second terminal of the scanning transistor Ts is electrically connected to the current sink circuit 730 via node N1. The control terminal of the scanning transistor Ts is electrically connected to the scan signal SS. A first terminal of capacitor C1 is electrically connected to the current sink circuit 730. A second terminal of capacitor C1 is electrically connected to the transmit signal ES.

[0034] In embodiments of this disclosure, the current sinking source circuit 730 includes a driving transistor Td, a compensation transistor Tc, a transmitting transistor Te1, a transmitting transistor Te2, a reset transistor Tr, and a storage capacitor Cst. In embodiments of this disclosure, the first terminal of the transmitting transistor Te2 is electrically connected to electronic component 710. The second terminal of the transmitting transistor Te2 is electrically connected to the first terminal of the driving transistor Td and the first terminal of the compensation transistor Tc. The control terminal of the transmitting transistor Te2 is electrically connected to the transmit signal EM. The first terminal of the storage capacitor Cst is electrically connected to a first operating voltage V1. The second terminal of the compensation transistor Tc is electrically connected to the second terminal of the storage capacitor Cst, the control terminal of the driving transistor Td, and the first terminal of the capacitor C1. The control terminal of the compensation transistor Tc is electrically connected to the scan signal SS. The first terminal of the reset transistor Tr is electrically connected to the first operating voltage V1. The second terminal of the reset transistor Tr is electrically connected to the control terminal of the driving transistor Td. The control terminal of the reset transistor Tr is electrically connected to the reset signal RS. The second terminal of the driving transistor Td is electrically connected to the second terminal of the scanning transistor Ts and the first terminal of the transmitting transistor Te1 through node N1. The second terminal of the transmitting transistor Te1 is electrically connected to the second operating voltage V2. The control terminal of the transmitting transistor Te1 is electrically connected to the transmit signal ES.

[0035] In embodiments of this disclosure, the first and second terminals of each of the above transistors can be source and drain terminals, and the control terminal of each of the above transistors can be a gate terminal. In embodiments of this disclosure, the compensation transistor Tc, the transmitting transistor Te1, the transmitting transistor Te2, the reset transistor Tr, the scanning transistor Ts, and the driving transistor Td can be N-type transistors or P-type transistors, respectively.

[0036] In embodiments of this disclosure, the scanning transistor Ts transmits the data voltage Vdata to node N1 according to the data signal DS transmitted via the data line DL, and the sink current source circuit 730 can generate a drive current Id according to the data voltage Vdata to drive the electronic component 710 through node N1. In embodiments of this disclosure, during the scanning cycle, the compensation transistor Tc can compensate for the threshold voltage of the driving transistor Td at the control terminal (gate terminal). Furthermore, during the transmit cycle, the voltage at the control terminal of the driving transistor Td can be maintained at the absolute value of the data voltage Vdata plus the threshold voltage Vth of the driving transistor Td. During the switching of the compensation transistor Tc from on to off, the compensation transistor Tc can induce a clock feedthrough effect at the control terminal of the driving transistor Td through the coupling capacitance between the control terminal and the second terminal of the compensation transistor Tc. In embodiments of this disclosure, the capacitor C1 can compensate for the clock feedthrough effect according to the transmit signal ES.

[0037] Figure 8 is a schematic diagram of an electronic device without threshold voltage compensation according to an embodiment of the present disclosure. Referring to Figure 8, the electronic device 800 includes an electronic component 810, a current sinking source circuit 830, a scanning transistor Ts, a capacitive coupling element, and a data line DL. The capacitive coupling element is a capacitor C1 similar to the MIM capacitor shown in the embodiment of Figure 3A, but the present disclosure is not limited thereto. In other embodiments of the present disclosure, the capacitive coupling element may also be implemented as the transistor T1 of the embodiment of Figure 3B. The electronic component 810 may include a light-emitting diode. In an embodiment of the present disclosure, the electronic component 810 is electrically connected between a first operating voltage V1 and the current sinking source circuit 830. A first terminal of the scanning transistor Ts is electrically connected to the data line DL. A second terminal of the scanning transistor Ts is electrically connected to the current sinking source circuit 830 through node N1. A control terminal of the scanning transistor Ts is electrically connected to a scan signal SS. A first terminal of the capacitor C1 is electrically connected to a compensation signal CS. A second terminal of the capacitor C1 is electrically connected to the current sinking source circuit 830 through node N1.

[0038] In embodiments of this disclosure, the current sinking source circuit 830 includes a driving transistor Td and a storage capacitor Cst. In embodiments of this disclosure, a first terminal of the driving transistor Td is electrically connected to electronic component 810. A second terminal of the driving transistor Td is electrically connected to a second operating voltage V2. A second terminal of capacitor C1 is electrically connected via node N1 to the control terminal of the driving transistor Td, the first terminal of the storage capacitor Cst, and the second terminal of the scanning transistor Ts. The second terminal of the storage capacitor Cst is electrically connected to the second operating voltage V2. In embodiments of this disclosure, the scanning transistor Ts and the driving transistor Td can be either an N-type transistor or a P-type transistor, respectively.

[0039] In embodiments of this disclosure, the scanning transistor Ts transmits the data voltage Vdata to node N1 according to the data signal DS transmitted by the data line DL, and the current sink circuit 830 can generate a drive current Id according to the data voltage Vdata to drive the electronic component 810. In embodiments of this disclosure, during the transmit cycle, the voltage at the control terminal of the driving transistor Td can be maintained at the data voltage Vdata. In embodiments of this disclosure, during the switching of the scanning transistor Ts from on to off, the scanning transistor Ts can induce a clock feedthrough effect at the control terminal of the driving transistor (node ​​N1) through the coupling capacitance between the control terminal and the second terminal of the scanning transistor Ts. In embodiments of this disclosure, the capacitor C1 can compensate for the clock feedthrough effect according to the compensation signal CS.

[0040] Figure 9 is a timing diagram of the relevant voltages and signals according to the embodiment of Figure 7 of this disclosure. Referring to Figures 7 and 9, the electronic device 700 can operate at the transmission period EP, the reset period RP, and the scan period SP. During the period from time t0 to time t1, the transmission signal ES changes to a low voltage level, and the reset signal RS and the scan signal SS remain at low voltage levels, respectively. The voltages Vd, Vs, and Vg at the first terminal, the second terminal, and the control terminal of the driving transistor Td decrease simultaneously. During the period from time t2 to time t3, the reset signal RS rises to a high voltage level, and therefore the voltage Vg at the control terminal of the driving transistor Td rises to the first operating voltage V1. During the reset period RS from time t3 to time t4, the voltage Vg at the control terminal of the driving transistor Td remains at the first operating voltage V1. During the period from time t4 to time t5, the reset signal RS falls to a low voltage level, and therefore the voltage Vg at the control terminal of the driving transistor Td decreases simultaneously.

[0041] During the period from time t6 to time t7, the scan signal SS changes to a high voltage level, while the reset signal RS and the transmit signal ES remain at low voltage levels. The voltages Vd, Vs, and Vg at the first, second, and control terminals of the driving transistor Td rise simultaneously. During the scan period SP from time t8 to time t9, the voltage Vs at the second terminal of the driving transistor Td changes to the data voltage Vdata. The voltages Vd and Vg at the first and control terminals of the driving transistor Td change to the absolute value of the data voltage Vdata plus the threshold voltage Vth of the driving transistor Td.

[0042] During the period from time t9 to time t10, the scan signal SS drops to a low voltage level, therefore the voltages Vd, Vs, and Vg at the first, second, and control terminals of the driving transistor Td decrease simultaneously due to the clock feedthrough effect. During the period from time t11 to time t12, the transmit signal ES rises to a high voltage level. Simultaneously, capacitor C1 compensates for the clock feedthrough effect according to the transmit signal ES. Therefore, the voltage at the control terminal of the driving transistor Td returns to the absolute value of the data voltage Vdata plus the threshold voltage Vth of the driving transistor Td. Therefore, during the transmit period EP from time t12 to time t13, the voltage Vg at the control terminal of the driving transistor Td is maintained at the absolute value of the data voltage Vdata plus the threshold voltage Vth of the driving transistor Td.

[0043] In addition, the relevant voltages and signals in the above embodiment of Figure 8 can also be simulated through this embodiment in order to achieve clock feedthrough effect compensation.

[0044] In summary, the electronic device of this disclosure can effectively reduce or eliminate the clock feedthrough effect caused by scanning transistors and / or compensation transistors, so as to effectively drive electronic components. Furthermore, the electronic device of some embodiments of this disclosure may have a threshold voltage compensation function for driving transistors.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

[0046] 100, 400, 500, 700, 800: Electronic devices 110, 410, 510, 710, 810: Electronic components 120: Capacitive coupling element 430, 530: Voltage source circuit 730, 830: Current sinking source circuit BS: Bias signal BP: Bias Period C1, C2: Capacitors Cgd: Coupling capacitor CS: Compensation signal Cst: Storage capacitor DL: Data cable DS: Data signal dV: Incremental voltage ES: Transmit signal Id: Compensation Current Iv: Leakage current N1, P11, P12, P21, P22: Nodes RP: Reset Cycle RS: Reset signal SP: Scan Cycle SS: Scan signal t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13: Time T1: Transistor Tb: Bias transistor Tc: Compensating transistor Td: Driving transistor Te1, Te2: Emitter transistors Tr: Reset Transistor Ts, Ts1, Ts2: Scanning transistors V1: First operating voltage V2: Second operating voltage Vd: Node voltage Vdata: Data voltage Vg, Vs: Voltage Vth: Threshold voltage

Claims

1. An electronic device comprising: a first scanning transistor; a driving transistor electrically connected to the first scanning transistor; an electronic element electrically connected to the driving transistor at a first node; and a first capacitive coupling element, wherein a first terminal of the first capacitive coupling element is electrically connected to a control terminal of the driving transistor, wherein during a bias period after the driving transistor is reset in a reset period, after being driven in a scan period, and before the driving transistor is reset again, a signal is applied to the first capacitive coupling element to compensate for a node voltage of the first node relative to the control terminal and the first terminal of the first scanning transistor, wherein in a frame, the scan period is after the reset period, and the bias period is after the scan period.

2. The electronic device as claimed in claim 1, further comprising: A second capacitive coupling element, wherein the first end of the second capacitive coupling element is electrically connected to the first end of the driving transistor.

3. The electronic device as claimed in claim 2, wherein the second end of the first capacitive coupling element is electrically connected to the second end of the second capacitive coupling element.

4. The electronic device as claimed in claim 1, further comprising: A compensation transistor is electrically connected between the second terminal of the driving transistor and the control terminal of the driving transistor.

5. The electronic device as claimed in claim 1, further comprising: A storage capacitor is electrically connected to the control terminal of the driving transistor.

6. The electronic device as claimed in claim 1, further comprising: A reset transistor is electrically connected to the control terminal of the driving transistor.

7. The electronic device as claimed in claim 1, wherein the second terminal of the first capacitive coupling element is electrically connected to a bias signal.

8. The electronic device as claimed in claim 1, wherein the first scanning transistor is electrically connected to a data line.

9. The electronic device as claimed in claim 1, further comprising: A bias transistor is electrically connected to the second terminal of the driving transistor.

10. The electronic device as claimed in claim 1, further comprising: A first transmitting transistor is electrically connected to the first end of the driving transistor; And a second transmitting transistor, electrically connected to the second end of the driving transistor.

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