Stacked substrate structure for wafer probe testing

Abstract

A stacked substrate structure for wafer probe testing includes a multi-core unit and at least one buffer unit. The multi-core unit comprises alternating stacked core layers and adhesive layers, with the outermost layers at opposite ends of the multi-core unit along a thickness direction each composed of two adhesive layers. The buffer unit is disposed between two adhesive layers of the multi-core unit. Each buffer unit includes a support layer and two buffer layers, which are formed on opposite sides of the support layer to ensure tight adhesion between the support layer and adjacent adhesive layers. The support layer is made of metal oxide, metal nitride, ceramic glass, or a combination thereof, and its coefficient of thermal expansion is less than that of the multi-core unit.

Claims

1. A stacked substrate structure for wafer probe testing, comprising: a multi-core unit including a plurality of alternately stacked core layers and a plurality of adhesive layers, wherein the outermost layers at opposite ends of the multi-core unit along a thickness direction are respectively composed of two adhesive layers; and at least one buffer unit disposed between two adhesive layers of the multi-core unit along the thickness direction, each buffer unit including a support layer and two buffer layers, the two buffer layers being formed on opposite sides of the support layer to ensure tight adhesion between the support layer and adjacent adhesive layers, the support layer having a metal oxide, metal nitride, ceramic glass, or a combination thereof, and the coefficient of thermal expansion of the support layer being less than the coefficient of thermal expansion of the multi-core unit; wherein... The thickness of the support layer is at least 30 times the sum of the thicknesses of any core layer and the adjacent adhesive layer.

2. The stacked substrate structure for wafer probe testing as described in claim 1 further includes a plurality of connection ports disposed at the outermost layers at opposite ends of the multi-core unit.

3. The stacked substrate structure for wafer probe testing as described in claim 2 further includes at least one add-in unit disposed on the outermost layer of the multi-core unit, and includes a circuit structure electrically connected to the connection ports.

4. The stacked substrate structure for wafer probe testing as described in claim 2 further includes a plurality of vias penetrating the multi-core unit and at least one of the buffer units, and is positioned corresponding to the connection ports.

5. The stacked substrate structure for wafer probe testing as described in claim 1, wherein, The stacked substrate structure includes a buffer unit disposed in the middle region of the multi-core unit along the thickness direction.

6. The stacked substrate structure for wafer probe testing as described in claim 1, wherein, The stacked substrate structure includes two buffer units, which are respectively disposed at opposite ends of the multi-core unit along the thickness direction, and the outermost layers of the opposite ends of the multi-core unit along the thickness direction are respectively disposed outside the two buffer units.

7. The stacked substrate structure for wafer probe testing as described in claim 1, wherein, The coefficient of thermal expansion of the buffer unit is less than that of the multi-core unit, and the difference between the coefficient of thermal expansion of the buffer unit and the multi-core unit is between 1 ppm / ℃ and 15 ppm / ℃.

8. The stacked substrate structure for wafer probe testing as described in claim 1, wherein, The core layer has a resin substrate and a metal foil layer.

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